Lines Matching refs:clocks

24 	"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
60 	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
62 	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
63 	"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
65 	"allwinner,sun7i-a20-out-clk" - for the external output clocks
74 Required properties for all clocks:
76 - clocks : shall be the input parent clock(s) phandle for the clock. For
77 	multiplexed clocks, the list order must match the hardware
89 And "allwinner,*-usb-clk" clocks also require:
96 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
97 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
99 Clock consumers should specify the desired clocks they use with a
100 "clocks" phandle cell. Consumers that are using a gated clock should
103 For the other clocks with "#clock-cells" = 1, the additional ID shall
110 The "allwinner,*-mmc-clk" clocks have three different outputs: the
111 main clock, with the ID 0, and the output and sample clocks, with the
124 	clocks = <&osc24M_fixed>;
132 	clocks = <&osc24M>;
140 	clocks = <&osc24M>;
148 	clocks = <&osc24M>;
156 	clocks = <&osc32k>, <&osc24M>, <&pll1>;
164 	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
197 	clocks = <&ahb0_gates 8>;