Lines Matching refs:clocks

99 			clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
110 		clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
120 		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
166 		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
201 		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
241 		clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
251 		clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
262 		clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
273 		clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
284 		clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
295 		clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
306 		clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
317 		clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
328 		clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
337 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
347 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
357 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
367 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
377 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
387 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
397 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
407 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
417 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
427 		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
437 		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
462 		clocks = <&zb_clk>;
466 	clocks {
471 		/* External root clocks */
505 		/* Special CPG clocks */
507 			compatible = "renesas,r8a73a4-cpg-clocks";
509 			clocks = <&extal1_clk>, <&extal2_clk>;
517 		/* Variable factor clocks (DIV6) */
521 			clocks = <&pll1_div2_clk>, <0>,
529 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
537 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
545 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
553 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
561 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
569 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
578 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
587 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
596 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
605 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
614 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
622 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
630 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
638 			clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
645 			clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
653 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
659 		/* Fixed factor clocks */
662 			clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
670 			clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
678 			clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
686 			clocks = <&extal1_clk>;
693 		/* Gate clocks */
695 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
697 			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
711 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
713 			clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
734 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
736 			clocks = <&main_div2_clk>, <&main_div2_clk>,
748 			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
750 			clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;