1Device Tree Clock bindings for arch-at91 2 3This binding uses the common clock binding[1]. 4 5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6 7Required properties: 8- compatible : shall be one of the following: 9 "atmel,at91sam9x5-sckc": 10 at91 SCKC (Slow Clock Controller) 11 This node contains the slow clock definitions. 12 13 "atmel,at91sam9x5-clk-slow-osc": 14 at91 slow oscillator 15 16 "atmel,at91sam9x5-clk-slow-rc-osc": 17 at91 internal slow RC oscillator 18 19 "atmel,at91rm9200-pmc" or 20 "atmel,at91sam9g45-pmc" or 21 "atmel,at91sam9n12-pmc" or 22 "atmel,at91sam9x5-pmc" or 23 "atmel,sama5d3-pmc": 24 at91 PMC (Power Management Controller) 25 All at91 specific clocks (clocks defined below) must be child 26 node of the PMC node. 27 28 "atmel,at91sam9x5-clk-slow" (under sckc node) 29 or 30 "atmel,at91sam9260-clk-slow" (under pmc node): 31 at91 slow clk 32 33 "atmel,at91rm9200-clk-main-osc" 34 "atmel,at91sam9x5-clk-main-rc-osc" 35 at91 main clk sources 36 37 "atmel,at91sam9x5-clk-main" 38 "atmel,at91rm9200-clk-main": 39 at91 main clock 40 41 "atmel,at91rm9200-clk-master" or 42 "atmel,at91sam9x5-clk-master": 43 at91 master clock 44 45 "atmel,at91sam9x5-clk-peripheral" or 46 "atmel,at91rm9200-clk-peripheral": 47 at91 peripheral clocks 48 49 "atmel,at91rm9200-clk-pll" or 50 "atmel,at91sam9g45-clk-pll" or 51 "atmel,at91sam9g20-clk-pllb" or 52 "atmel,sama5d3-clk-pll": 53 at91 pll clocks 54 55 "atmel,at91sam9x5-clk-plldiv": 56 at91 plla divisor 57 58 "atmel,at91rm9200-clk-programmable" or 59 "atmel,at91sam9g45-clk-programmable" or 60 "atmel,at91sam9x5-clk-programmable": 61 at91 programmable clocks 62 63 "atmel,at91sam9x5-clk-smd": 64 at91 SMD (Soft Modem) clock 65 66 "atmel,at91rm9200-clk-system": 67 at91 system clocks 68 69 "atmel,at91rm9200-clk-usb" or 70 "atmel,at91sam9x5-clk-usb" or 71 "atmel,at91sam9n12-clk-usb": 72 at91 usb clock 73 74 "atmel,at91sam9x5-clk-utmi": 75 at91 utmi clock 76 77 "atmel,sama5d4-clk-h32mx": 78 at91 h32mx clock 79 80 "atmel,sama5d2-clk-generated": 81 at91 generated clock 82 83Required properties for SCKC node: 84- reg : defines the IO memory reserved for the SCKC. 85- #size-cells : shall be 0 (reg is used to encode clk id). 86- #address-cells : shall be 1 (reg is used to encode clk id). 87 88 89For example: 90 sckc: sckc@fffffe50 { 91 compatible = "atmel,sama5d3-pmc"; 92 reg = <0xfffffe50 0x4> 93 #size-cells = <0>; 94 #address-cells = <1>; 95 96 /* put at91 slow clocks here */ 97 }; 98 99 100Required properties for internal slow RC oscillator: 101- #clock-cells : from common clock binding; shall be set to 0. 102- clock-frequency : define the internal RC oscillator frequency. 103 104Optional properties: 105- clock-accuracy : define the internal RC oscillator accuracy. 106 107For example: 108 slow_rc_osc: slow_rc_osc { 109 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 110 clock-frequency = <32768>; 111 clock-accuracy = <50000000>; 112 }; 113 114Required properties for slow oscillator: 115- #clock-cells : from common clock binding; shall be set to 0. 116- clocks : shall encode the main osc source clk sources (see atmel datasheet). 117 118Optional properties: 119- atmel,osc-bypass : boolean property. Set this when a clock signal is directly 120 provided on XIN. 121 122For example: 123 slow_osc: slow_osc { 124 compatible = "atmel,at91rm9200-clk-slow-osc"; 125 #clock-cells = <0>; 126 clocks = <&slow_xtal>; 127 }; 128 129Required properties for slow clock: 130- #clock-cells : from common clock binding; shall be set to 0. 131- clocks : shall encode the slow clk sources (see atmel datasheet). 132 133For example: 134 clk32k: slck { 135 compatible = "atmel,at91sam9x5-clk-slow"; 136 #clock-cells = <0>; 137 clocks = <&slow_rc_osc &slow_osc>; 138 }; 139 140Required properties for PMC node: 141- reg : defines the IO memory reserved for the PMC. 142- #size-cells : shall be 0 (reg is used to encode clk id). 143- #address-cells : shall be 1 (reg is used to encode clk id). 144- interrupts : shall be set to PMC interrupt line. 145- interrupt-controller : tell that the PMC is an interrupt controller. 146- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id, 147 and reflect the bit position in the PMC_ER/DR/SR registers. 148 You can use the dt macros defined in dt-bindings/clock/at91.h. 149 0 (AT91_PMC_MOSCS) -> main oscillator ready 150 1 (AT91_PMC_LOCKA) -> PLL A ready 151 2 (AT91_PMC_LOCKB) -> PLL B ready 152 3 (AT91_PMC_MCKRDY) -> master clock ready 153 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready 154 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready 155 16 (AT91_PMC_MOSCSELS) -> main oscillator selected 156 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized 157 18 (AT91_PMC_CFDEV) -> clock failure detected 158 159For example: 160 pmc: pmc@fffffc00 { 161 compatible = "atmel,sama5d3-pmc"; 162 interrupts = <1 4 7>; 163 interrupt-controller; 164 #interrupt-cells = <2>; 165 #size-cells = <0>; 166 #address-cells = <1>; 167 168 /* put at91 clocks here */ 169 }; 170 171Required properties for main clock internal RC oscillator: 172- interrupt-parent : must reference the PMC node. 173- interrupts : shall be set to "<0>". 174- clock-frequency : define the internal RC oscillator frequency. 175 176Optional properties: 177- clock-accuracy : define the internal RC oscillator accuracy. 178 179For example: 180 main_rc_osc: main_rc_osc { 181 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 182 interrupt-parent = <&pmc>; 183 interrupts = <0>; 184 clock-frequency = <12000000>; 185 clock-accuracy = <50000000>; 186 }; 187 188Required properties for main clock oscillator: 189- interrupt-parent : must reference the PMC node. 190- interrupts : shall be set to "<0>". 191- #clock-cells : from common clock binding; shall be set to 0. 192- clocks : shall encode the main osc source clk sources (see atmel datasheet). 193 194Optional properties: 195- atmel,osc-bypass : boolean property. Specified if a clock signal is provided 196 on XIN. 197 198 clock signal is directly provided on XIN pin. 199 200For example: 201 main_osc: main_osc { 202 compatible = "atmel,at91rm9200-clk-main-osc"; 203 interrupt-parent = <&pmc>; 204 interrupts = <0>; 205 #clock-cells = <0>; 206 clocks = <&main_xtal>; 207 }; 208 209Required properties for main clock: 210- interrupt-parent : must reference the PMC node. 211- interrupts : shall be set to "<0>". 212- #clock-cells : from common clock binding; shall be set to 0. 213- clocks : shall encode the main clk sources (see atmel datasheet). 214 215For example: 216 main: mainck { 217 compatible = "atmel,at91sam9x5-clk-main"; 218 interrupt-parent = <&pmc>; 219 interrupts = <0>; 220 #clock-cells = <0>; 221 clocks = <&main_rc_osc &main_osc>; 222 }; 223 224Required properties for master clock: 225- interrupt-parent : must reference the PMC node. 226- interrupts : shall be set to "<3>". 227- #clock-cells : from common clock binding; shall be set to 0. 228- clocks : shall be the master clock sources (see atmel datasheet) phandles. 229 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>". 230- atmel,clk-output-range : minimum and maximum clock frequency (two u32 231 fields). 232 e.g. output = <0 133000000>; <=> 0 to 133MHz. 233- atmel,clk-divisors : master clock divisors table (four u32 fields). 234 0 <=> reserved value. 235 e.g. divisors = <1 2 4 6>; 236- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the 237 PRES field as CLOCK_DIV3 (e.g sam9x5). 238 239For example: 240 mck: mck { 241 compatible = "atmel,at91rm9200-clk-master"; 242 interrupt-parent = <&pmc>; 243 interrupts = <3>; 244 #clock-cells = <0>; 245 atmel,clk-output-range = <0 133000000>; 246 atmel,clk-divisors = <1 2 4 0>; 247 }; 248 249Required properties for peripheral clocks: 250- #size-cells : shall be 0 (reg is used to encode clk id). 251- #address-cells : shall be 1 (reg is used to encode clk id). 252- clocks : shall be the master clock phandle. 253 e.g. clocks = <&mck>; 254- name: device tree node describing a specific peripheral clock. 255 * #clock-cells : from common clock binding; shall be set to 0. 256 * reg: peripheral id. See Atmel's datasheets to get a full 257 list of peripheral ids. 258 * atmel,clk-output-range : minimum and maximum clock frequency 259 (two u32 fields). Only valid on at91sam9x5-clk-peripheral 260 compatible IPs. 261 262For example: 263 periph: periphck { 264 compatible = "atmel,at91sam9x5-clk-peripheral"; 265 #size-cells = <0>; 266 #address-cells = <1>; 267 clocks = <&mck>; 268 269 ssc0_clk { 270 #clock-cells = <0>; 271 reg = <2>; 272 atmel,clk-output-range = <0 133000000>; 273 }; 274 275 usart0_clk { 276 #clock-cells = <0>; 277 reg = <3>; 278 atmel,clk-output-range = <0 66000000>; 279 }; 280 }; 281 282 283Required properties for pll clocks: 284- interrupt-parent : must reference the PMC node. 285- interrupts : shall be set to "<1>". 286- #clock-cells : from common clock binding; shall be set to 0. 287- clocks : shall be the main clock phandle. 288- reg : pll id. 289 0 -> PLL A 290 1 -> PLL B 291- atmel,clk-input-range : minimum and maximum source clock frequency (two u32 292 fields). 293 e.g. input = <1 32000000>; <=> 1 to 32MHz. 294- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output 295 range description. Sould be set to 2, 3 296 or 4. 297 * 1st and 2nd cells represent the frequency range (min-max). 298 * 3rd cell is optional and represents the OUT field value for the given 299 range. 300 * 4th cell is optional and represents the ICPLL field (PLLICPR 301 register) 302- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter 303 depending on #atmel,pll-output-range-cells 304 property value. 305 306For example: 307 plla: pllack { 308 compatible = "atmel,at91sam9g45-clk-pll"; 309 interrupt-parent = <&pmc>; 310 interrupts = <1>; 311 #clock-cells = <0>; 312 clocks = <&main>; 313 reg = <0>; 314 atmel,clk-input-range = <2000000 32000000>; 315 #atmel,pll-clk-output-range-cells = <4>; 316 atmel,pll-clk-output-ranges = <74500000 800000000 0 0 317 69500000 750000000 1 0 318 64500000 700000000 2 0 319 59500000 650000000 3 0 320 54500000 600000000 0 1 321 49500000 550000000 1 1 322 44500000 500000000 2 1 323 40000000 450000000 3 1>; 324 }; 325 326Required properties for plldiv clocks (plldiv = pll / 2): 327- #clock-cells : from common clock binding; shall be set to 0. 328- clocks : shall be the plla clock phandle. 329 330The pll divisor is equal to 2 and cannot be changed. 331 332For example: 333 plladiv: plladivck { 334 compatible = "atmel,at91sam9x5-clk-plldiv"; 335 #clock-cells = <0>; 336 clocks = <&plla>; 337 }; 338 339Required properties for programmable clocks: 340- interrupt-parent : must reference the PMC node. 341- #size-cells : shall be 0 (reg is used to encode clk id). 342- #address-cells : shall be 1 (reg is used to encode clk id). 343- clocks : shall be the programmable clock source phandles. 344 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 345- name: device tree node describing a specific prog clock. 346 * #clock-cells : from common clock binding; shall be set to 0. 347 * reg : programmable clock id (register offset from PCKx 348 register). 349 * interrupts : shall be set to "<(8 + id)>". 350 351For example: 352 prog: progck { 353 compatible = "atmel,at91sam9g45-clk-programmable"; 354 #size-cells = <0>; 355 #address-cells = <1>; 356 interrupt-parent = <&pmc>; 357 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 358 359 prog0 { 360 #clock-cells = <0>; 361 reg = <0>; 362 interrupts = <8>; 363 }; 364 365 prog1 { 366 #clock-cells = <0>; 367 reg = <1>; 368 interrupts = <9>; 369 }; 370 }; 371 372 373Required properties for smd clock: 374- #clock-cells : from common clock binding; shall be set to 0. 375- clocks : shall be the smd clock source phandles. 376 e.g. clocks = <&plladiv>, <&utmi>; 377 378For example: 379 smd: smdck { 380 compatible = "atmel,at91sam9x5-clk-smd"; 381 #clock-cells = <0>; 382 clocks = <&plladiv>, <&utmi>; 383 }; 384 385Required properties for system clocks: 386- #size-cells : shall be 0 (reg is used to encode clk id). 387- #address-cells : shall be 1 (reg is used to encode clk id). 388- name: device tree node describing a specific system clock. 389 * #clock-cells : from common clock binding; shall be set to 0. 390 * reg: system clock id (bit position in SCER/SCDR/SCSR registers). 391 See Atmel's datasheet to get a full list of system clock ids. 392 393For example: 394 system: systemck { 395 compatible = "atmel,at91rm9200-clk-system"; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 399 ddrck { 400 #clock-cells = <0>; 401 reg = <2>; 402 clocks = <&mck>; 403 }; 404 405 uhpck { 406 #clock-cells = <0>; 407 reg = <6>; 408 clocks = <&usb>; 409 }; 410 411 udpck { 412 #clock-cells = <0>; 413 reg = <7>; 414 clocks = <&usb>; 415 }; 416 }; 417 418 419Required properties for usb clock: 420- #clock-cells : from common clock binding; shall be set to 0. 421- clocks : shall be the smd clock source phandles. 422 e.g. clocks = <&pllb>; 423- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"): 424 usb clock divisor table. 425 e.g. divisors = <1 2 4 0>; 426 427For example: 428 usb: usbck { 429 compatible = "atmel,at91sam9x5-clk-usb"; 430 #clock-cells = <0>; 431 clocks = <&plladiv>, <&utmi>; 432 }; 433 434 usb: usbck { 435 compatible = "atmel,at91rm9200-clk-usb"; 436 #clock-cells = <0>; 437 clocks = <&pllb>; 438 atmel,clk-divisors = <1 2 4 0>; 439 }; 440 441 442Required properties for utmi clock: 443- interrupt-parent : must reference the PMC node. 444- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>". 445- #clock-cells : from common clock binding; shall be set to 0. 446- clocks : shall be the main clock source phandle. 447 448For example: 449 utmi: utmick { 450 compatible = "atmel,at91sam9x5-clk-utmi"; 451 interrupt-parent = <&pmc>; 452 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>; 453 #clock-cells = <0>; 454 clocks = <&main>; 455 }; 456 457Required properties for 32 bits bus Matrix clock (h32mx clock): 458- #clock-cells : from common clock binding; shall be set to 0. 459- clocks : shall be the master clock source phandle. 460 461For example: 462 h32ck: h32mxck { 463 #clock-cells = <0>; 464 compatible = "atmel,sama5d4-clk-h32mx"; 465 clocks = <&mck>; 466 }; 467 468Required properties for generated clocks: 469- #size-cells : shall be 0 (reg is used to encode clk id). 470- #address-cells : shall be 1 (reg is used to encode clk id). 471- clocks : shall be the generated clock source phandles. 472 e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; 473- name: device tree node describing a specific generated clock. 474 * #clock-cells : from common clock binding; shall be set to 0. 475 * reg: peripheral id. See Atmel's datasheets to get a full 476 list of peripheral ids. 477 * atmel,clk-output-range : minimum and maximum clock frequency 478 (two u32 fields). 479 480For example: 481 gck { 482 compatible = "atmel,sama5d2-clk-generated"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; 486 487 tcb0_gclk: tcb0_gclk { 488 #clock-cells = <0>; 489 reg = <35>; 490 atmel,clk-output-range = <0 83000000>; 491 }; 492 493 pwm_gclk: pwm_gclk { 494 #clock-cells = <0>; 495 reg = <38>; 496 atmel,clk-output-range = <0 83000000>; 497 }; 498 }; 499