Lines Matching refs:clocks
54 clocks = <&clks IMX5_CLK_ARM>;
80 clocks {
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
205 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
217 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
229 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
242 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
256 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
268 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
284 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
291 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
300 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
310 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
321 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
331 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
341 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
388 clocks = <&clks IMX5_CLK_DUMMY>;
396 clocks = <&clks IMX5_CLK_DUMMY>;
403 clocks = <&clks IMX5_CLK_DUMMY>;
411 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
432 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
478 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
488 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
498 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
508 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
518 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
528 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
583 clocks = <&clks IMX5_CLK_I2C3_GATE>;
591 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
614 clocks = <&clks IMX5_CLK_IIM_GATE>;
621 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
630 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
640 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
650 clocks = <&clks IMX5_CLK_SDMA_GATE>,
663 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
675 clocks = <&clks IMX5_CLK_I2C2_GATE>;
685 clocks = <&clks IMX5_CLK_I2C1_GATE>;
695 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
715 clocks = <&clks IMX5_CLK_NFC_GATE>;
725 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
739 clocks = <&clks IMX5_CLK_FEC_GATE>,
750 clocks = <&clks IMX5_CLK_TVE_GATE>,
766 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
777 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
786 clocks = <&clks IMX5_CLK_OCRAM>;