1/* 2 * Device Tree Source for the r8a7740 SoC 3 * 4 * Copyright (C) 2012 Renesas Solutions Corp. 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11/include/ "skeleton.dtsi" 12 13#include <dt-bindings/clock/r8a7740-clock.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15 16/ { 17 compatible = "renesas,r8a7740"; 18 interrupt-parent = <&gic>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 cpu@0 { 24 compatible = "arm,cortex-a9"; 25 device_type = "cpu"; 26 reg = <0x0>; 27 clock-frequency = <800000000>; 28 power-domains = <&pd_a3sm>; 29 }; 30 }; 31 32 gic: interrupt-controller@c2800000 { 33 compatible = "arm,cortex-a9-gic"; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0xc2800000 0x1000>, 37 <0xc2000000 0x1000>; 38 }; 39 40 dbsc3: memory-controller@fe400000 { 41 compatible = "renesas,dbsc3-r8a7740"; 42 reg = <0xfe400000 0x400>; 43 power-domains = <&pd_a4s>; 44 }; 45 46 pmu { 47 compatible = "arm,cortex-a9-pmu"; 48 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 49 }; 50 51 ptm { 52 compatible = "arm,coresight-etm3x"; 53 power-domains = <&pd_d4>; 54 }; 55 56 cmt1: timer@e6138000 { 57 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; 58 reg = <0xe6138000 0x170>; 59 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; 60 clocks = <&mstp3_clks R8A7740_CLK_CMT1>; 61 clock-names = "fck"; 62 power-domains = <&pd_c5>; 63 64 renesas,channels-mask = <0x3f>; 65 66 status = "disabled"; 67 }; 68 69 /* irqpin0: IRQ0 - IRQ7 */ 70 irqpin0: interrupt-controller@e6900000 { 71 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 72 #interrupt-cells = <2>; 73 interrupt-controller; 74 reg = <0xe6900000 4>, 75 <0xe6900010 4>, 76 <0xe6900020 1>, 77 <0xe6900040 1>, 78 <0xe6900060 1>; 79 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 80 0 149 IRQ_TYPE_LEVEL_HIGH 81 0 149 IRQ_TYPE_LEVEL_HIGH 82 0 149 IRQ_TYPE_LEVEL_HIGH 83 0 149 IRQ_TYPE_LEVEL_HIGH 84 0 149 IRQ_TYPE_LEVEL_HIGH 85 0 149 IRQ_TYPE_LEVEL_HIGH 86 0 149 IRQ_TYPE_LEVEL_HIGH>; 87 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 88 power-domains = <&pd_a4s>; 89 }; 90 91 /* irqpin1: IRQ8 - IRQ15 */ 92 irqpin1: interrupt-controller@e6900004 { 93 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 94 #interrupt-cells = <2>; 95 interrupt-controller; 96 reg = <0xe6900004 4>, 97 <0xe6900014 4>, 98 <0xe6900024 1>, 99 <0xe6900044 1>, 100 <0xe6900064 1>; 101 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 102 0 149 IRQ_TYPE_LEVEL_HIGH 103 0 149 IRQ_TYPE_LEVEL_HIGH 104 0 149 IRQ_TYPE_LEVEL_HIGH 105 0 149 IRQ_TYPE_LEVEL_HIGH 106 0 149 IRQ_TYPE_LEVEL_HIGH 107 0 149 IRQ_TYPE_LEVEL_HIGH 108 0 149 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 110 power-domains = <&pd_a4s>; 111 }; 112 113 /* irqpin2: IRQ16 - IRQ23 */ 114 irqpin2: interrupt-controller@e6900008 { 115 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 116 #interrupt-cells = <2>; 117 interrupt-controller; 118 reg = <0xe6900008 4>, 119 <0xe6900018 4>, 120 <0xe6900028 1>, 121 <0xe6900048 1>, 122 <0xe6900068 1>; 123 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 124 0 149 IRQ_TYPE_LEVEL_HIGH 125 0 149 IRQ_TYPE_LEVEL_HIGH 126 0 149 IRQ_TYPE_LEVEL_HIGH 127 0 149 IRQ_TYPE_LEVEL_HIGH 128 0 149 IRQ_TYPE_LEVEL_HIGH 129 0 149 IRQ_TYPE_LEVEL_HIGH 130 0 149 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 132 power-domains = <&pd_a4s>; 133 }; 134 135 /* irqpin3: IRQ24 - IRQ31 */ 136 irqpin3: interrupt-controller@e690000c { 137 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 138 #interrupt-cells = <2>; 139 interrupt-controller; 140 reg = <0xe690000c 4>, 141 <0xe690001c 4>, 142 <0xe690002c 1>, 143 <0xe690004c 1>, 144 <0xe690006c 1>; 145 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 146 0 149 IRQ_TYPE_LEVEL_HIGH 147 0 149 IRQ_TYPE_LEVEL_HIGH 148 0 149 IRQ_TYPE_LEVEL_HIGH 149 0 149 IRQ_TYPE_LEVEL_HIGH 150 0 149 IRQ_TYPE_LEVEL_HIGH 151 0 149 IRQ_TYPE_LEVEL_HIGH 152 0 149 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 154 power-domains = <&pd_a4s>; 155 }; 156 157 ether: ethernet@e9a00000 { 158 compatible = "renesas,gether-r8a7740"; 159 reg = <0xe9a00000 0x800>, 160 <0xe9a01800 0x800>; 161 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&mstp3_clks R8A7740_CLK_GETHER>; 163 power-domains = <&pd_a4s>; 164 phy-mode = "mii"; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 status = "disabled"; 168 }; 169 170 i2c0: i2c@fff20000 { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 174 reg = <0xfff20000 0x425>; 175 interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH 176 0 202 IRQ_TYPE_LEVEL_HIGH 177 0 203 IRQ_TYPE_LEVEL_HIGH 178 0 204 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&mstp1_clks R8A7740_CLK_IIC0>; 180 power-domains = <&pd_a4r>; 181 status = "disabled"; 182 }; 183 184 i2c1: i2c@e6c20000 { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 188 reg = <0xe6c20000 0x425>; 189 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH 190 0 71 IRQ_TYPE_LEVEL_HIGH 191 0 72 IRQ_TYPE_LEVEL_HIGH 192 0 73 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&mstp3_clks R8A7740_CLK_IIC1>; 194 power-domains = <&pd_a3sp>; 195 status = "disabled"; 196 }; 197 198 scifa0: serial@e6c40000 { 199 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 200 reg = <0xe6c40000 0x100>; 201 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; 203 clock-names = "sci_ick"; 204 power-domains = <&pd_a3sp>; 205 status = "disabled"; 206 }; 207 208 scifa1: serial@e6c50000 { 209 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 210 reg = <0xe6c50000 0x100>; 211 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; 213 clock-names = "sci_ick"; 214 power-domains = <&pd_a3sp>; 215 status = "disabled"; 216 }; 217 218 scifa2: serial@e6c60000 { 219 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 220 reg = <0xe6c60000 0x100>; 221 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; 223 clock-names = "sci_ick"; 224 power-domains = <&pd_a3sp>; 225 status = "disabled"; 226 }; 227 228 scifa3: serial@e6c70000 { 229 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 230 reg = <0xe6c70000 0x100>; 231 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; 233 clock-names = "sci_ick"; 234 power-domains = <&pd_a3sp>; 235 status = "disabled"; 236 }; 237 238 scifa4: serial@e6c80000 { 239 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 240 reg = <0xe6c80000 0x100>; 241 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; 243 clock-names = "sci_ick"; 244 power-domains = <&pd_a3sp>; 245 status = "disabled"; 246 }; 247 248 scifa5: serial@e6cb0000 { 249 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 250 reg = <0xe6cb0000 0x100>; 251 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; 253 clock-names = "sci_ick"; 254 power-domains = <&pd_a3sp>; 255 status = "disabled"; 256 }; 257 258 scifa6: serial@e6cc0000 { 259 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 260 reg = <0xe6cc0000 0x100>; 261 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; 263 clock-names = "sci_ick"; 264 power-domains = <&pd_a3sp>; 265 status = "disabled"; 266 }; 267 268 scifa7: serial@e6cd0000 { 269 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 270 reg = <0xe6cd0000 0x100>; 271 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; 273 clock-names = "sci_ick"; 274 power-domains = <&pd_a3sp>; 275 status = "disabled"; 276 }; 277 278 scifb: serial@e6c30000 { 279 compatible = "renesas,scifb-r8a7740", "renesas,scifb"; 280 reg = <0xe6c30000 0x100>; 281 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; 283 clock-names = "sci_ick"; 284 power-domains = <&pd_a3sp>; 285 status = "disabled"; 286 }; 287 288 pfc: pfc@e6050000 { 289 compatible = "renesas,pfc-r8a7740"; 290 reg = <0xe6050000 0x8000>, 291 <0xe605800c 0x20>; 292 gpio-controller; 293 #gpio-cells = <2>; 294 gpio-ranges = <&pfc 0 0 212>; 295 interrupts-extended = 296 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, 297 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, 298 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, 299 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, 300 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, 301 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 302 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 303 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 304 power-domains = <&pd_c5>; 305 }; 306 307 tpu: pwm@e6600000 { 308 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 309 reg = <0xe6600000 0x100>; 310 clocks = <&mstp3_clks R8A7740_CLK_TPU0>; 311 power-domains = <&pd_a3sp>; 312 status = "disabled"; 313 #pwm-cells = <3>; 314 }; 315 316 mmcif0: mmc@e6bd0000 { 317 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; 318 reg = <0xe6bd0000 0x100>; 319 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 320 0 57 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&mstp3_clks R8A7740_CLK_MMC>; 322 power-domains = <&pd_a3sp>; 323 status = "disabled"; 324 }; 325 326 sdhi0: sd@e6850000 { 327 compatible = "renesas,sdhi-r8a7740"; 328 reg = <0xe6850000 0x100>; 329 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH 330 0 118 IRQ_TYPE_LEVEL_HIGH 331 0 119 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; 333 power-domains = <&pd_a3sp>; 334 cap-sd-highspeed; 335 cap-sdio-irq; 336 status = "disabled"; 337 }; 338 339 sdhi1: sd@e6860000 { 340 compatible = "renesas,sdhi-r8a7740"; 341 reg = <0xe6860000 0x100>; 342 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH 343 0 122 IRQ_TYPE_LEVEL_HIGH 344 0 123 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; 346 power-domains = <&pd_a3sp>; 347 cap-sd-highspeed; 348 cap-sdio-irq; 349 status = "disabled"; 350 }; 351 352 sdhi2: sd@e6870000 { 353 compatible = "renesas,sdhi-r8a7740"; 354 reg = <0xe6870000 0x100>; 355 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH 356 0 126 IRQ_TYPE_LEVEL_HIGH 357 0 127 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; 359 power-domains = <&pd_a3sp>; 360 cap-sd-highspeed; 361 cap-sdio-irq; 362 status = "disabled"; 363 }; 364 365 sh_fsi2: sound@fe1f0000 { 366 #sound-dai-cells = <1>; 367 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; 368 reg = <0xfe1f0000 0x400>; 369 interrupts = <0 9 0x4>; 370 clocks = <&mstp3_clks R8A7740_CLK_FSI>; 371 power-domains = <&pd_a4mp>; 372 status = "disabled"; 373 }; 374 375 tmu0: timer@fff80000 { 376 compatible = "renesas,tmu-r8a7740", "renesas,tmu"; 377 reg = <0xfff80000 0x2c>; 378 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, 379 <0 199 IRQ_TYPE_LEVEL_HIGH>, 380 <0 200 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&mstp1_clks R8A7740_CLK_TMU0>; 382 clock-names = "fck"; 383 power-domains = <&pd_a4r>; 384 385 #renesas,channels = <3>; 386 387 status = "disabled"; 388 }; 389 390 tmu1: timer@fff90000 { 391 compatible = "renesas,tmu-r8a7740", "renesas,tmu"; 392 reg = <0xfff90000 0x2c>; 393 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>, 394 <0 171 IRQ_TYPE_LEVEL_HIGH>, 395 <0 172 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&mstp1_clks R8A7740_CLK_TMU1>; 397 clock-names = "fck"; 398 power-domains = <&pd_a4r>; 399 400 #renesas,channels = <3>; 401 402 status = "disabled"; 403 }; 404 405 clocks { 406 #address-cells = <1>; 407 #size-cells = <1>; 408 ranges; 409 410 /* External root clock */ 411 extalr_clk: extalr_clk { 412 compatible = "fixed-clock"; 413 #clock-cells = <0>; 414 clock-frequency = <32768>; 415 clock-output-names = "extalr"; 416 }; 417 extal1_clk: extal1_clk { 418 compatible = "fixed-clock"; 419 #clock-cells = <0>; 420 clock-frequency = <0>; 421 clock-output-names = "extal1"; 422 }; 423 extal2_clk: extal2_clk { 424 compatible = "fixed-clock"; 425 #clock-cells = <0>; 426 clock-frequency = <0>; 427 clock-output-names = "extal2"; 428 }; 429 dv_clk: dv_clk { 430 compatible = "fixed-clock"; 431 #clock-cells = <0>; 432 clock-frequency = <27000000>; 433 clock-output-names = "dv"; 434 }; 435 fmsick_clk: fmsick_clk { 436 compatible = "fixed-clock"; 437 #clock-cells = <0>; 438 clock-frequency = <0>; 439 clock-output-names = "fmsick"; 440 }; 441 fmsock_clk: fmsock_clk { 442 compatible = "fixed-clock"; 443 #clock-cells = <0>; 444 clock-frequency = <0>; 445 clock-output-names = "fmsock"; 446 }; 447 fsiack_clk: fsiack_clk { 448 compatible = "fixed-clock"; 449 #clock-cells = <0>; 450 clock-frequency = <0>; 451 clock-output-names = "fsiack"; 452 }; 453 fsibck_clk: fsibck_clk { 454 compatible = "fixed-clock"; 455 #clock-cells = <0>; 456 clock-frequency = <0>; 457 clock-output-names = "fsibck"; 458 }; 459 460 /* Special CPG clocks */ 461 cpg_clocks: cpg_clocks@e6150000 { 462 compatible = "renesas,r8a7740-cpg-clocks"; 463 reg = <0xe6150000 0x10000>; 464 clocks = <&extal1_clk>, <&extalr_clk>; 465 #clock-cells = <1>; 466 clock-output-names = "system", "pllc0", "pllc1", 467 "pllc2", "r", 468 "usb24s", 469 "i", "zg", "b", "m1", "hp", 470 "hpp", "usbp", "s", "zb", "m3", 471 "cp"; 472 }; 473 474 /* Variable factor clocks (DIV6) */ 475 vclk1_clk: vclk1_clk@e6150008 { 476 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 477 reg = <0xe6150008 4>; 478 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, 479 <&cpg_clocks R8A7740_CLK_USB24S>, 480 <&extal1_div2_clk>, <&extalr_clk>, <0>, 481 <0>; 482 #clock-cells = <0>; 483 clock-output-names = "vclk1"; 484 }; 485 vclk2_clk: vclk2_clk@e615000c { 486 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 487 reg = <0xe615000c 4>; 488 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, 489 <&cpg_clocks R8A7740_CLK_USB24S>, 490 <&extal1_div2_clk>, <&extalr_clk>, <0>, 491 <0>; 492 #clock-cells = <0>; 493 clock-output-names = "vclk2"; 494 }; 495 fmsi_clk: fmsi_clk@e6150010 { 496 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 497 reg = <0xe6150010 4>; 498 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; 499 #clock-cells = <0>; 500 clock-output-names = "fmsi"; 501 }; 502 fmso_clk: fmso_clk@e6150014 { 503 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 504 reg = <0xe6150014 4>; 505 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; 506 #clock-cells = <0>; 507 clock-output-names = "fmso"; 508 }; 509 fsia_clk: fsia_clk@e6150018 { 510 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 511 reg = <0xe6150018 4>; 512 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; 513 #clock-cells = <0>; 514 clock-output-names = "fsia"; 515 }; 516 sub_clk: sub_clk@e6150080 { 517 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 518 reg = <0xe6150080 4>; 519 clocks = <&pllc1_div2_clk>, 520 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; 521 #clock-cells = <0>; 522 clock-output-names = "sub"; 523 }; 524 spu_clk: spu_clk@e6150084 { 525 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 526 reg = <0xe6150084 4>; 527 clocks = <&pllc1_div2_clk>, 528 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; 529 #clock-cells = <0>; 530 clock-output-names = "spu"; 531 }; 532 vou_clk: vou_clk@e6150088 { 533 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 534 reg = <0xe6150088 4>; 535 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, 536 <0>; 537 #clock-cells = <0>; 538 clock-output-names = "vou"; 539 }; 540 stpro_clk: stpro_clk@e615009c { 541 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 542 reg = <0xe615009c 4>; 543 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; 544 #clock-cells = <0>; 545 clock-output-names = "stpro"; 546 }; 547 548 /* Fixed factor clocks */ 549 pllc1_div2_clk: pllc1_div2_clk { 550 compatible = "fixed-factor-clock"; 551 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; 552 #clock-cells = <0>; 553 clock-div = <2>; 554 clock-mult = <1>; 555 clock-output-names = "pllc1_div2"; 556 }; 557 extal1_div2_clk: extal1_div2_clk { 558 compatible = "fixed-factor-clock"; 559 clocks = <&extal1_clk>; 560 #clock-cells = <0>; 561 clock-div = <2>; 562 clock-mult = <1>; 563 clock-output-names = "extal1_div2"; 564 }; 565 566 /* Gate clocks */ 567 subck_clks: subck_clks@e6150080 { 568 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 569 reg = <0xe6150080 4>; 570 clocks = <&sub_clk>, <&sub_clk>; 571 #clock-cells = <1>; 572 clock-indices = < 573 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 574 >; 575 clock-output-names = 576 "subck", "subck2"; 577 }; 578 mstp1_clks: mstp1_clks@e6150134 { 579 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 580 reg = <0xe6150134 4>, <0xe6150038 4>; 581 clocks = <&cpg_clocks R8A7740_CLK_S>, 582 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, 583 <&cpg_clocks R8A7740_CLK_B>, 584 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, 585 <&cpg_clocks R8A7740_CLK_B>; 586 #clock-cells = <1>; 587 clock-indices = < 588 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 589 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 590 R8A7740_CLK_LCDC0 591 >; 592 clock-output-names = 593 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", 594 "tmu1", "lcdc0"; 595 }; 596 mstp2_clks: mstp2_clks@e6150138 { 597 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 598 reg = <0xe6150138 4>, <0xe6150040 4>; 599 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, 600 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, 601 <&cpg_clocks R8A7740_CLK_HP>, 602 <&cpg_clocks R8A7740_CLK_HP>, 603 <&cpg_clocks R8A7740_CLK_HP>, 604 <&sub_clk>, <&sub_clk>, <&sub_clk>, 605 <&sub_clk>, <&sub_clk>, <&sub_clk>, 606 <&sub_clk>; 607 #clock-cells = <1>; 608 clock-indices = < 609 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA 610 R8A7740_CLK_SCIFA7 611 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 612 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC 613 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB 614 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 615 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 616 R8A7740_CLK_SCIFA4 617 >; 618 clock-output-names = 619 "scifa6", "intca", 620 "scifa7", "dmac1", "dmac2", "dmac3", 621 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", 622 "scifa2", "scifa3", "scifa4"; 623 }; 624 mstp3_clks: mstp3_clks@e615013c { 625 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 626 reg = <0xe615013c 4>, <0xe6150048 4>; 627 clocks = <&cpg_clocks R8A7740_CLK_R>, 628 <&cpg_clocks R8A7740_CLK_HP>, 629 <&sub_clk>, 630 <&cpg_clocks R8A7740_CLK_HP>, 631 <&cpg_clocks R8A7740_CLK_HP>, 632 <&cpg_clocks R8A7740_CLK_HP>, 633 <&cpg_clocks R8A7740_CLK_HP>, 634 <&cpg_clocks R8A7740_CLK_HP>, 635 <&cpg_clocks R8A7740_CLK_HP>; 636 #clock-cells = <1>; 637 clock-indices = < 638 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 639 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 640 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 641 >; 642 clock-output-names = 643 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", 644 "mmc", "gether", "tpu0"; 645 }; 646 mstp4_clks: mstp4_clks@e6150140 { 647 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 648 reg = <0xe6150140 4>, <0xe615004c 4>; 649 clocks = <&cpg_clocks R8A7740_CLK_HP>, 650 <&cpg_clocks R8A7740_CLK_HP>, 651 <&cpg_clocks R8A7740_CLK_HP>, 652 <&cpg_clocks R8A7740_CLK_HP>; 653 #clock-cells = <1>; 654 clock-indices = < 655 R8A7740_CLK_USBH R8A7740_CLK_SDHI2 656 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY 657 >; 658 clock-output-names = 659 "usbhost", "sdhi2", "usbfunc", "usphy"; 660 }; 661 }; 662 663 sysc: system-controller@e6180000 { 664 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; 665 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; 666 667 pm-domains { 668 pd_c5: c5 { 669 #address-cells = <1>; 670 #size-cells = <0>; 671 #power-domain-cells = <0>; 672 673 pd_a4lc: a4lc@1 { 674 reg = <1>; 675 #power-domain-cells = <0>; 676 }; 677 678 pd_a4mp: a4mp@2 { 679 reg = <2>; 680 #power-domain-cells = <0>; 681 }; 682 683 pd_d4: d4@3 { 684 reg = <3>; 685 #power-domain-cells = <0>; 686 }; 687 688 pd_a4r: a4r@5 { 689 reg = <5>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 #power-domain-cells = <0>; 693 694 pd_a3rv: a3rv@6 { 695 reg = <6>; 696 #power-domain-cells = <0>; 697 }; 698 }; 699 700 pd_a4s: a4s@10 { 701 reg = <10>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 #power-domain-cells = <0>; 705 706 pd_a3sp: a3sp@11 { 707 reg = <11>; 708 #power-domain-cells = <0>; 709 }; 710 711 pd_a3sm: a3sm@12 { 712 reg = <12>; 713 #power-domain-cells = <0>; 714 }; 715 716 pd_a3sg: a3sg@13 { 717 reg = <13>; 718 #power-domain-cells = <0>; 719 }; 720 }; 721 722 pd_a4su: a4su@20 { 723 reg = <20>; 724 #power-domain-cells = <0>; 725 }; 726 }; 727 }; 728 }; 729}; 730