1/* 2 * Samsung's Exynos3250 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 8 * based board files can include this file and provide values for board specfic 9 * bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional 13 * nodes can be added to this file. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20#include "skeleton.dtsi" 21#include "exynos4-cpu-thermal.dtsi" 22#include <dt-bindings/clock/exynos3250.h> 23 24/ { 25 compatible = "samsung,exynos3250"; 26 interrupt-parent = <&gic>; 27 28 aliases { 29 pinctrl0 = &pinctrl_0; 30 pinctrl1 = &pinctrl_1; 31 mshc0 = &mshc_0; 32 mshc1 = &mshc_1; 33 spi0 = &spi_0; 34 spi1 = &spi_1; 35 i2c0 = &i2c_0; 36 i2c1 = &i2c_1; 37 i2c2 = &i2c_2; 38 i2c3 = &i2c_3; 39 i2c4 = &i2c_4; 40 i2c5 = &i2c_5; 41 i2c6 = &i2c_6; 42 i2c7 = &i2c_7; 43 serial0 = &serial_0; 44 serial1 = &serial_1; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0>; 55 clock-frequency = <1000000000>; 56 clocks = <&cmu CLK_ARM_CLK>; 57 clock-names = "cpu"; 58 #cooling-cells = <2>; 59 60 operating-points = < 61 1000000 1150000 62 900000 1112500 63 800000 1075000 64 700000 1037500 65 600000 1000000 66 500000 962500 67 400000 925000 68 300000 887500 69 200000 850000 70 100000 850000 71 >; 72 }; 73 74 cpu1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 reg = <1>; 78 clock-frequency = <1000000000>; 79 }; 80 }; 81 82 soc: soc { 83 compatible = "simple-bus"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 88 fixed-rate-clocks { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 92 xusbxti: clock@0 { 93 compatible = "fixed-clock"; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 reg = <0>; 97 clock-frequency = <0>; 98 #clock-cells = <0>; 99 clock-output-names = "xusbxti"; 100 }; 101 102 xxti: clock@1 { 103 compatible = "fixed-clock"; 104 reg = <1>; 105 clock-frequency = <0>; 106 #clock-cells = <0>; 107 clock-output-names = "xxti"; 108 }; 109 110 xtcxo: clock@2 { 111 compatible = "fixed-clock"; 112 reg = <2>; 113 clock-frequency = <0>; 114 #clock-cells = <0>; 115 clock-output-names = "xtcxo"; 116 }; 117 }; 118 119 sysram@02020000 { 120 compatible = "mmio-sram"; 121 reg = <0x02020000 0x40000>; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0 0x02020000 0x40000>; 125 126 smp-sysram@0 { 127 compatible = "samsung,exynos4210-sysram"; 128 reg = <0x0 0x1000>; 129 }; 130 131 smp-sysram@3f000 { 132 compatible = "samsung,exynos4210-sysram-ns"; 133 reg = <0x3f000 0x1000>; 134 }; 135 }; 136 137 chipid@10000000 { 138 compatible = "samsung,exynos4210-chipid"; 139 reg = <0x10000000 0x100>; 140 }; 141 142 sys_reg: syscon@10010000 { 143 compatible = "samsung,exynos3-sysreg", "syscon"; 144 reg = <0x10010000 0x400>; 145 }; 146 147 pmu_system_controller: system-controller@10020000 { 148 compatible = "samsung,exynos3250-pmu", "syscon"; 149 reg = <0x10020000 0x4000>; 150 interrupt-controller; 151 #interrupt-cells = <3>; 152 interrupt-parent = <&gic>; 153 }; 154 155 mipi_phy: video-phy@10020710 { 156 compatible = "samsung,s5pv210-mipi-video-phy"; 157 #phy-cells = <1>; 158 syscon = <&pmu_system_controller>; 159 }; 160 161 pd_cam: cam-power-domain@10023C00 { 162 compatible = "samsung,exynos4210-pd"; 163 reg = <0x10023C00 0x20>; 164 #power-domain-cells = <0>; 165 }; 166 167 pd_mfc: mfc-power-domain@10023C40 { 168 compatible = "samsung,exynos4210-pd"; 169 reg = <0x10023C40 0x20>; 170 #power-domain-cells = <0>; 171 }; 172 173 pd_g3d: g3d-power-domain@10023C60 { 174 compatible = "samsung,exynos4210-pd"; 175 reg = <0x10023C60 0x20>; 176 #power-domain-cells = <0>; 177 }; 178 179 pd_lcd0: lcd0-power-domain@10023C80 { 180 compatible = "samsung,exynos4210-pd"; 181 reg = <0x10023C80 0x20>; 182 #power-domain-cells = <0>; 183 }; 184 185 pd_isp: isp-power-domain@10023CA0 { 186 compatible = "samsung,exynos4210-pd"; 187 reg = <0x10023CA0 0x20>; 188 #power-domain-cells = <0>; 189 }; 190 191 cmu: clock-controller@10030000 { 192 compatible = "samsung,exynos3250-cmu"; 193 reg = <0x10030000 0x20000>; 194 #clock-cells = <1>; 195 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, 196 <&cmu CLK_MOUT_ACLK_266_SUB>; 197 assigned-clock-parents = <&cmu CLK_FIN_PLL>, 198 <&cmu CLK_FIN_PLL>; 199 }; 200 201 cmu_dmc: clock-controller@105C0000 { 202 compatible = "samsung,exynos3250-cmu-dmc"; 203 reg = <0x105C0000 0x2000>; 204 #clock-cells = <1>; 205 }; 206 207 rtc: rtc@10070000 { 208 compatible = "samsung,s3c6410-rtc"; 209 reg = <0x10070000 0x100>; 210 interrupts = <0 73 0>, <0 74 0>; 211 interrupt-parent = <&pmu_system_controller>; 212 status = "disabled"; 213 }; 214 215 tmu: tmu@100C0000 { 216 compatible = "samsung,exynos3250-tmu"; 217 reg = <0x100C0000 0x100>; 218 interrupts = <0 216 0>; 219 clocks = <&cmu CLK_TMU_APBIF>; 220 clock-names = "tmu_apbif"; 221 #include "exynos4412-tmu-sensor-conf.dtsi" 222 status = "disabled"; 223 }; 224 225 gic: interrupt-controller@10481000 { 226 compatible = "arm,cortex-a15-gic"; 227 #interrupt-cells = <3>; 228 interrupt-controller; 229 reg = <0x10481000 0x1000>, 230 <0x10482000 0x1000>, 231 <0x10484000 0x2000>, 232 <0x10486000 0x2000>; 233 interrupts = <1 9 0xf04>; 234 }; 235 236 mct@10050000 { 237 compatible = "samsung,exynos4210-mct"; 238 reg = <0x10050000 0x800>; 239 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, 240 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; 241 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 242 clock-names = "fin_pll", "mct"; 243 }; 244 245 pinctrl_1: pinctrl@11000000 { 246 compatible = "samsung,exynos3250-pinctrl"; 247 reg = <0x11000000 0x1000>; 248 interrupts = <0 225 0>; 249 250 wakeup-interrupt-controller { 251 compatible = "samsung,exynos4210-wakeup-eint"; 252 interrupts = <0 48 0>; 253 }; 254 }; 255 256 pinctrl_0: pinctrl@11400000 { 257 compatible = "samsung,exynos3250-pinctrl"; 258 reg = <0x11400000 0x1000>; 259 interrupts = <0 240 0>; 260 }; 261 262 jpeg: codec@11830000 { 263 compatible = "samsung,exynos3250-jpeg"; 264 reg = <0x11830000 0x1000>; 265 interrupts = <0 171 0>; 266 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; 267 clock-names = "jpeg", "sclk"; 268 power-domains = <&pd_cam>; 269 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; 270 assigned-clock-rates = <0>, <150000000>; 271 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; 272 iommus = <&sysmmu_jpeg>; 273 status = "disabled"; 274 }; 275 276 sysmmu_jpeg: sysmmu@11A60000 { 277 compatible = "samsung,exynos-sysmmu"; 278 reg = <0x11a60000 0x1000>; 279 interrupts = <0 156 0>, <0 161 0>; 280 clock-names = "sysmmu", "master"; 281 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; 282 power-domains = <&pd_cam>; 283 #iommu-cells = <0>; 284 }; 285 286 fimd: fimd@11c00000 { 287 compatible = "samsung,exynos3250-fimd"; 288 reg = <0x11c00000 0x30000>; 289 interrupt-names = "fifo", "vsync", "lcd_sys"; 290 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 291 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 292 clock-names = "sclk_fimd", "fimd"; 293 power-domains = <&pd_lcd0>; 294 iommus = <&sysmmu_fimd0>; 295 samsung,sysreg = <&sys_reg>; 296 status = "disabled"; 297 }; 298 299 dsi_0: dsi@11C80000 { 300 compatible = "samsung,exynos3250-mipi-dsi"; 301 reg = <0x11C80000 0x10000>; 302 interrupts = <0 83 0>; 303 samsung,phy-type = <0>; 304 power-domains = <&pd_lcd0>; 305 phys = <&mipi_phy 1>; 306 phy-names = "dsim"; 307 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 308 clock-names = "bus_clk", "pll_clk"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 status = "disabled"; 312 }; 313 314 sysmmu_fimd0: sysmmu@11E20000 { 315 compatible = "samsung,exynos-sysmmu"; 316 reg = <0x11e20000 0x1000>; 317 interrupts = <0 80 0>, <0 81 0>; 318 clock-names = "sysmmu", "master"; 319 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 320 power-domains = <&pd_lcd0>; 321 #iommu-cells = <0>; 322 }; 323 324 hsotg: hsotg@12480000 { 325 compatible = "snps,dwc2"; 326 reg = <0x12480000 0x20000>; 327 interrupts = <0 141 0>; 328 clocks = <&cmu CLK_USBOTG>; 329 clock-names = "otg"; 330 phys = <&exynos_usbphy 0>; 331 phy-names = "usb2-phy"; 332 status = "disabled"; 333 }; 334 335 mshc_0: mshc@12510000 { 336 compatible = "samsung,exynos5420-dw-mshc"; 337 reg = <0x12510000 0x1000>; 338 interrupts = <0 142 0>; 339 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 340 clock-names = "biu", "ciu"; 341 fifo-depth = <0x80>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 status = "disabled"; 345 }; 346 347 mshc_1: mshc@12520000 { 348 compatible = "samsung,exynos5420-dw-mshc"; 349 reg = <0x12520000 0x1000>; 350 interrupts = <0 143 0>; 351 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 352 clock-names = "biu", "ciu"; 353 fifo-depth = <0x80>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 359 exynos_usbphy: exynos-usbphy@125B0000 { 360 compatible = "samsung,exynos3250-usb2-phy"; 361 reg = <0x125B0000 0x100>; 362 samsung,pmureg-phandle = <&pmu_system_controller>; 363 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; 364 clock-names = "phy", "ref"; 365 #phy-cells = <1>; 366 status = "disabled"; 367 }; 368 369 amba { 370 compatible = "arm,amba-bus"; 371 #address-cells = <1>; 372 #size-cells = <1>; 373 ranges; 374 375 pdma0: pdma@12680000 { 376 compatible = "arm,pl330", "arm,primecell"; 377 reg = <0x12680000 0x1000>; 378 interrupts = <0 138 0>; 379 clocks = <&cmu CLK_PDMA0>; 380 clock-names = "apb_pclk"; 381 #dma-cells = <1>; 382 #dma-channels = <8>; 383 #dma-requests = <32>; 384 }; 385 386 pdma1: pdma@12690000 { 387 compatible = "arm,pl330", "arm,primecell"; 388 reg = <0x12690000 0x1000>; 389 interrupts = <0 139 0>; 390 clocks = <&cmu CLK_PDMA1>; 391 clock-names = "apb_pclk"; 392 #dma-cells = <1>; 393 #dma-channels = <8>; 394 #dma-requests = <32>; 395 }; 396 }; 397 398 adc: adc@126C0000 { 399 compatible = "samsung,exynos3250-adc", 400 "samsung,exynos-adc-v2"; 401 reg = <0x126C0000 0x100>; 402 interrupts = <0 137 0>; 403 clock-names = "adc", "sclk"; 404 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 405 #io-channel-cells = <1>; 406 io-channel-ranges; 407 samsung,syscon-phandle = <&pmu_system_controller>; 408 status = "disabled"; 409 }; 410 411 mfc: codec@13400000 { 412 compatible = "samsung,mfc-v7"; 413 reg = <0x13400000 0x10000>; 414 interrupts = <0 102 0>; 415 clock-names = "mfc", "sclk_mfc"; 416 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 417 power-domains = <&pd_mfc>; 418 iommus = <&sysmmu_mfc>; 419 status = "disabled"; 420 }; 421 422 sysmmu_mfc: sysmmu@13620000 { 423 compatible = "samsung,exynos-sysmmu"; 424 reg = <0x13620000 0x1000>; 425 interrupts = <0 96 0>, <0 98 0>; 426 clock-names = "sysmmu", "master"; 427 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; 428 power-domains = <&pd_mfc>; 429 #iommu-cells = <0>; 430 }; 431 432 serial_0: serial@13800000 { 433 compatible = "samsung,exynos4210-uart"; 434 reg = <0x13800000 0x100>; 435 interrupts = <0 109 0>; 436 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 437 clock-names = "uart", "clk_uart_baud0"; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&uart0_data &uart0_fctl>; 440 status = "disabled"; 441 }; 442 443 serial_1: serial@13810000 { 444 compatible = "samsung,exynos4210-uart"; 445 reg = <0x13810000 0x100>; 446 interrupts = <0 110 0>; 447 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 448 clock-names = "uart", "clk_uart_baud0"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&uart1_data>; 451 status = "disabled"; 452 }; 453 454 i2c_0: i2c@13860000 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 compatible = "samsung,s3c2440-i2c"; 458 reg = <0x13860000 0x100>; 459 interrupts = <0 113 0>; 460 clocks = <&cmu CLK_I2C0>; 461 clock-names = "i2c"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&i2c0_bus>; 464 status = "disabled"; 465 }; 466 467 i2c_1: i2c@13870000 { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 compatible = "samsung,s3c2440-i2c"; 471 reg = <0x13870000 0x100>; 472 interrupts = <0 114 0>; 473 clocks = <&cmu CLK_I2C1>; 474 clock-names = "i2c"; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&i2c1_bus>; 477 status = "disabled"; 478 }; 479 480 i2c_2: i2c@13880000 { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 compatible = "samsung,s3c2440-i2c"; 484 reg = <0x13880000 0x100>; 485 interrupts = <0 115 0>; 486 clocks = <&cmu CLK_I2C2>; 487 clock-names = "i2c"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&i2c2_bus>; 490 status = "disabled"; 491 }; 492 493 i2c_3: i2c@13890000 { 494 #address-cells = <1>; 495 #size-cells = <0>; 496 compatible = "samsung,s3c2440-i2c"; 497 reg = <0x13890000 0x100>; 498 interrupts = <0 116 0>; 499 clocks = <&cmu CLK_I2C3>; 500 clock-names = "i2c"; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&i2c3_bus>; 503 status = "disabled"; 504 }; 505 506 i2c_4: i2c@138A0000 { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 compatible = "samsung,s3c2440-i2c"; 510 reg = <0x138A0000 0x100>; 511 interrupts = <0 117 0>; 512 clocks = <&cmu CLK_I2C4>; 513 clock-names = "i2c"; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&i2c4_bus>; 516 status = "disabled"; 517 }; 518 519 i2c_5: i2c@138B0000 { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 compatible = "samsung,s3c2440-i2c"; 523 reg = <0x138B0000 0x100>; 524 interrupts = <0 118 0>; 525 clocks = <&cmu CLK_I2C5>; 526 clock-names = "i2c"; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&i2c5_bus>; 529 status = "disabled"; 530 }; 531 532 i2c_6: i2c@138C0000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "samsung,s3c2440-i2c"; 536 reg = <0x138C0000 0x100>; 537 interrupts = <0 119 0>; 538 clocks = <&cmu CLK_I2C6>; 539 clock-names = "i2c"; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&i2c6_bus>; 542 status = "disabled"; 543 }; 544 545 i2c_7: i2c@138D0000 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 compatible = "samsung,s3c2440-i2c"; 549 reg = <0x138D0000 0x100>; 550 interrupts = <0 120 0>; 551 clocks = <&cmu CLK_I2C7>; 552 clock-names = "i2c"; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&i2c7_bus>; 555 status = "disabled"; 556 }; 557 558 spi_0: spi@13920000 { 559 compatible = "samsung,exynos4210-spi"; 560 reg = <0x13920000 0x100>; 561 interrupts = <0 121 0>; 562 dmas = <&pdma0 7>, <&pdma0 6>; 563 dma-names = "tx", "rx"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 567 clock-names = "spi", "spi_busclk0"; 568 samsung,spi-src-clk = <0>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&spi0_bus>; 571 status = "disabled"; 572 }; 573 574 spi_1: spi@13930000 { 575 compatible = "samsung,exynos4210-spi"; 576 reg = <0x13930000 0x100>; 577 interrupts = <0 122 0>; 578 dmas = <&pdma1 7>, <&pdma1 6>; 579 dma-names = "tx", "rx"; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 583 clock-names = "spi", "spi_busclk0"; 584 samsung,spi-src-clk = <0>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&spi1_bus>; 587 status = "disabled"; 588 }; 589 590 i2s2: i2s@13970000 { 591 compatible = "samsung,s3c6410-i2s"; 592 reg = <0x13970000 0x100>; 593 interrupts = <0 126 0>; 594 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; 595 clock-names = "iis", "i2s_opclk0"; 596 dmas = <&pdma0 14>, <&pdma0 13>; 597 dma-names = "tx", "rx"; 598 pinctrl-0 = <&i2s2_bus>; 599 pinctrl-names = "default"; 600 status = "disabled"; 601 }; 602 603 pwm: pwm@139D0000 { 604 compatible = "samsung,exynos4210-pwm"; 605 reg = <0x139D0000 0x1000>; 606 interrupts = <0 104 0>, <0 105 0>, <0 106 0>, 607 <0 107 0>, <0 108 0>; 608 #pwm-cells = <3>; 609 status = "disabled"; 610 }; 611 612 pmu { 613 compatible = "arm,cortex-a7-pmu"; 614 interrupts = <0 18 0>, <0 19 0>; 615 }; 616 617 ppmu_dmc0: ppmu_dmc0@106a0000 { 618 compatible = "samsung,exynos-ppmu"; 619 reg = <0x106a0000 0x2000>; 620 status = "disabled"; 621 }; 622 623 ppmu_dmc1: ppmu_dmc1@106b0000 { 624 compatible = "samsung,exynos-ppmu"; 625 reg = <0x106b0000 0x2000>; 626 status = "disabled"; 627 }; 628 629 ppmu_cpu: ppmu_cpu@106c0000 { 630 compatible = "samsung,exynos-ppmu"; 631 reg = <0x106c0000 0x2000>; 632 status = "disabled"; 633 }; 634 635 ppmu_rightbus: ppmu_rightbus@112a0000 { 636 compatible = "samsung,exynos-ppmu"; 637 reg = <0x112a0000 0x2000>; 638 clocks = <&cmu CLK_PPMURIGHT>; 639 clock-names = "ppmu"; 640 status = "disabled"; 641 }; 642 643 ppmu_leftbus: ppmu_leftbus0@116a0000 { 644 compatible = "samsung,exynos-ppmu"; 645 reg = <0x116a0000 0x2000>; 646 clocks = <&cmu CLK_PPMULEFT>; 647 clock-names = "ppmu"; 648 status = "disabled"; 649 }; 650 651 ppmu_camif: ppmu_camif@11ac0000 { 652 compatible = "samsung,exynos-ppmu"; 653 reg = <0x11ac0000 0x2000>; 654 clocks = <&cmu CLK_PPMUCAMIF>; 655 clock-names = "ppmu"; 656 status = "disabled"; 657 }; 658 659 ppmu_lcd0: ppmu_lcd0@11e40000 { 660 compatible = "samsung,exynos-ppmu"; 661 reg = <0x11e40000 0x2000>; 662 clocks = <&cmu CLK_PPMULCD0>; 663 clock-names = "ppmu"; 664 status = "disabled"; 665 }; 666 667 ppmu_fsys: ppmu_fsys@12630000 { 668 compatible = "samsung,exynos-ppmu"; 669 reg = <0x12630000 0x2000>; 670 clocks = <&cmu CLK_PPMUFILE>; 671 clock-names = "ppmu"; 672 status = "disabled"; 673 }; 674 675 ppmu_g3d: ppmu_g3d@13220000 { 676 compatible = "samsung,exynos-ppmu"; 677 reg = <0x13220000 0x2000>; 678 clocks = <&cmu CLK_PPMUG3D>; 679 clock-names = "ppmu"; 680 status = "disabled"; 681 }; 682 683 ppmu_mfc: ppmu_mfc@13660000 { 684 compatible = "samsung,exynos-ppmu"; 685 reg = <0x13660000 0x2000>; 686 clocks = <&cmu CLK_PPMUMFC_L>; 687 clock-names = "ppmu"; 688 status = "disabled"; 689 }; 690 }; 691}; 692 693#include "exynos3250-pinctrl.dtsi" 694