1Broadcom iProc Family Clocks
2
3This binding uses the common clock binding:
4    Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The iProc clock controller manages clocks that are common to the iProc family.
7An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
8LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
9comprises of several leaf clocks
10
11Required properties for a PLL and its leaf clocks:
12
13- compatible:
14    Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
15Cygnus has a compatible string of "brcm,cygnus-genpll"
16
17- #clock-cells:
18    Have a value of <1> since there are more than 1 leaf clock of a given PLL
19
20- reg:
21    Define the base and range of the I/O address space that contain the iProc
22clock control registers required for the PLL
23
24- clocks:
25    The input parent clock phandle for the PLL. For most iProc PLLs, this is an
26onboard crystal with a fixed rate
27
28- clock-output-names:
29    An ordered list of strings defining the names of the clocks
30
31Example:
32
33	osc: oscillator {
34		#clock-cells = <0>;
35		compatible = "fixed-clock";
36		clock-frequency = <25000000>;
37	};
38
39	genpll: genpll {
40		#clock-cells = <1>;
41		compatible = "brcm,cygnus-genpll";
42		reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
43		clocks = <&osc>;
44		clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
45				     "enet_sw", "audio_125", "can";
46	};
47
48Required properties for ASIU clocks:
49
50ASIU clocks are a special case. These clocks are derived directly from the
51reference clock of the onboard crystal
52
53- compatible:
54    Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
55clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
56
57- #clock-cells:
58    Have a value of <1> since there are more than 1 ASIU clocks
59
60- reg:
61    Define the base and range of the I/O address space that contain the iProc
62clock control registers required for ASIU clocks
63
64- clocks:
65    The input parent clock phandle for the ASIU clock, i.e., the onboard
66crystal
67
68- clock-output-names:
69    An ordered list of strings defining the names of the ASIU clocks
70
71Example:
72
73	osc: oscillator {
74		#clock-cells = <0>;
75		compatible = "fixed-clock";
76		clock-frequency = <25000000>;
77	};
78
79	asiu_clks: asiu_clks {
80		#clock-cells = <1>;
81		compatible = "brcm,cygnus-asiu-clk";
82		reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
83		clocks = <&osc>;
84		clock-output-names = "keypad", "adc/touch", "pwm";
85	};
86
87Cygnus
88------
89PLL and leaf clock compatible strings for Cygnus are:
90    "brcm,cygnus-armpll"
91    "brcm,cygnus-genpll"
92    "brcm,cygnus-lcpll0"
93    "brcm,cygnus-mipipll"
94    "brcm,cygnus-asiu-clk"
95
96The following table defines the set of PLL/clock index and ID for Cygnus.
97These clock IDs are defined in:
98    "include/dt-bindings/clock/bcm-cygnus.h"
99
100    Clock      Source (Parent)  Index   ID
101    ---        -----            -----   ---------
102    crystal    N/A              N/A     N/A
103
104    armpll     crystal          N/A     N/A
105
106    keypad     crystal (ASIU)   0       BCM_CYGNUS_ASIU_KEYPAD_CLK
107    adc/tsc    crystal (ASIU)   1       BCM_CYGNUS_ASIU_ADC_CLK
108    pwm        crystal (ASIU)   2       BCM_CYGNUS_ASIU_PWM_CLK
109
110    genpll     crystal          0       BCM_CYGNUS_GENPLL
111    axi21      genpll           1       BCM_CYGNUS_GENPLL_AXI21_CLK
112    250mhz     genpll           2       BCM_CYGNUS_GENPLL_250MHZ_CLK
113    ihost_sys  genpll           3       BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
114    enet_sw    genpll           4       BCM_CYGNUS_GENPLL_ENET_SW_CLK
115    audio_125  genpll           5       BCM_CYGNUS_GENPLL_AUDIO_125_CLK
116    can        genpll           6       BCM_CYGNUS_GENPLL_CAN_CLK
117
118    lcpll0     crystal          0       BCM_CYGNUS_LCPLL0
119    pcie_phy   lcpll0           1       BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
120    ddr_phy    lcpll0           2       BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
121    sdio       lcpll0           3       BCM_CYGNUS_LCPLL0_SDIO_CLK
122    usb_phy    lcpll0           4       BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
123    smart_card lcpll0           5       BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
124    ch5_unused lcpll0           6       BCM_CYGNUS_LCPLL0_CH5_UNUSED
125
126    mipipll    crystal          0       BCM_CYGNUS_MIPIPLL
127    ch0_unused mipipll          1       BCM_CYGNUS_MIPIPLL_CH0_UNUSED
128    ch1_lcd    mipipll          2       BCM_CYGNUS_MIPIPLL_CH1_LCD
129    ch2_v3d    mipipll          3       BCM_CYGNUS_MIPIPLL_CH2_V3D
130    ch3_unused mipipll          4       BCM_CYGNUS_MIPIPLL_CH3_UNUSED
131    ch4_unused mipipll          5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED
132    ch5_unused mipipll          6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED
133
134Northstar and Northstar Plus
135------
136PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
137 "brcm,nsp-armpll"
138 "brcm,nsp-genpll"
139 "brcm,nsp-lcpll0"
140
141The following table defines the set of PLL/clock index and ID for Northstar and
142Northstar Plus.  These clock IDs are defined in:
143    "include/dt-bindings/clock/bcm-nsp.h"
144
145    Clock	Source		Index	ID
146    ---		-----		-----	---------
147    crystal	N/A		N/A	N/A
148
149    armpll	crystal		N/A	N/A
150
151    genpll	crystal		0	BCM_NSP_GENPLL
152    phy		genpll		1	BCM_NSP_GENPLL_PHY_CLK
153    ethernetclk	genpll		2	BCM_NSP_GENPLL_ENET_SW_CLK
154    usbclk	genpll		3	BCM_NSP_GENPLL_USB_PHY_REF_CLK
155    iprocfast	genpll		4	BCM_NSP_GENPLL_IPROCFAST_CLK
156    sata1	genpll		5	BCM_NSP_GENPLL_SATA1_CLK
157    sata2	genpll		6	BCM_NSP_GENPLL_SATA2_CLK
158
159    lcpll0	crystal		0	BCM_NSP_LCPLL0
160    pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
161    sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
162    ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
163
164Northstar 2
165-----------
166PLL and leaf clock compatible strings for Northstar 2 are:
167    "brcm,ns2-genpll-scr"
168    "brcm,ns2-genpll-sw"
169    "brcm,ns2-lcpll-ddr"
170    "brcm,ns2-lcpll-ports"
171
172The following table defines the set of PLL/clock index and ID for Northstar 2.
173These clock IDs are defined in:
174    "include/dt-bindings/clock/bcm-ns2.h"
175
176    Clock	Source		Index	ID
177    ---		-----		-----	---------
178    crystal	N/A		N/A	N/A
179
180    genpll_scr	crystal		0	BCM_NS2_GENPLL_SCR
181    scr		genpll_scr	1	BCM_NS2_GENPLL_SCR_SCR_CLK
182    fs		genpll_scr	2	BCM_NS2_GENPLL_SCR_FS_CLK
183    audio_ref	genpll_scr	3	BCM_NS2_GENPLL_SCR_AUDIO_CLK
184    ch3_unused	genpll_scr	4	BCM_NS2_GENPLL_SCR_CH3_UNUSED
185    ch4_unused	genpll_scr	5	BCM_NS2_GENPLL_SCR_CH4_UNUSED
186    ch5_unused	genpll_scr	6	BCM_NS2_GENPLL_SCR_CH5_UNUSED
187
188    genpll_sw	crystal		0	BCM_NS2_GENPLL_SW
189    rpe		genpll_sw	1	BCM_NS2_GENPLL_SW_RPE_CLK
190    250		genpll_sw	2	BCM_NS2_GENPLL_SW_250_CLK
191    nic		genpll_sw	3	BCM_NS2_GENPLL_SW_NIC_CLK
192    chimp	genpll_sw	4	BCM_NS2_GENPLL_SW_CHIMP_CLK
193    port	genpll_sw	5	BCM_NS2_GENPLL_SW_PORT_CLK
194    sdio	genpll_sw	6	BCM_NS2_GENPLL_SW_SDIO_CLK
195
196    lcpll_ddr	crystal		0	BCM_NS2_LCPLL_DDR
197    pcie_sata_usb lcpll_ddr	1	BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
198    ddr		lcpll_ddr	2	BCM_NS2_LCPLL_DDR_DDR_CLK
199    ch2_unused	lcpll_ddr	3	BCM_NS2_LCPLL_DDR_CH2_UNUSED
200    ch3_unused	lcpll_ddr	4	BCM_NS2_LCPLL_DDR_CH3_UNUSED
201    ch4_unused	lcpll_ddr	5	BCM_NS2_LCPLL_DDR_CH4_UNUSED
202    ch5_unused	lcpll_ddr	6	BCM_NS2_LCPLL_DDR_CH5_UNUSED
203
204    lcpll_ports	crystal		0	BCM_NS2_LCPLL_PORTS
205    wan		lcpll_ports	1	BCM_NS2_LCPLL_PORTS_WAN_CLK
206    rgmii	lcpll_ports	2	BCM_NS2_LCPLL_PORTS_RGMII_CLK
207    ch2_unused	lcpll_ports	3	BCM_NS2_LCPLL_PORTS_CH2_UNUSED
208    ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED
209    ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED
210    ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED
211