1/* 2 * Common base for NXP LPC18xx and LPC43xx devices. 3 * 4 * Copyright 2015 Joachim Eastwood <manabian@gmail.com> 5 * 6 * This code is released using a dual license strategy: BSD/GPL 7 * You can choose the licence that better fits your requirements. 8 * 9 * Released under the terms of 3-clause BSD License 10 * Released under the terms of GNU General Public License Version 2.0 11 * 12 */ 13 14#include "armv7-m.dtsi" 15 16#include "dt-bindings/clock/lpc18xx-cgu.h" 17#include "dt-bindings/clock/lpc18xx-ccu.h" 18 19#define LPC_PIN(port, pin) (0x##port * 32 + pin) 20#define LPC_GPIO(port, pin) (port * 32 + pin) 21 22/ { 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu@0 { 28 compatible = "arm,cortex-m3"; 29 device_type = "cpu"; 30 reg = <0x0>; 31 clocks = <&ccu1 CLK_CPU_CORE>; 32 }; 33 }; 34 35 clocks { 36 xtal: xtal { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <12000000>; 40 }; 41 42 xtal32: xtal32 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <32768>; 46 }; 47 48 enet_rx_clk: enet_rx_clk { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 clock-output-names = "enet_rx_clk"; 53 }; 54 55 enet_tx_clk: enet_tx_clk { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 clock-output-names = "enet_tx_clk"; 60 }; 61 62 gp_clkin: gp_clkin { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 clock-output-names = "gp_clkin"; 67 }; 68 }; 69 70 soc { 71 sct_pwm: pwm@40000000 { 72 compatible = "nxp,lpc1850-sct-pwm"; 73 reg = <0x40000000 0x1000>; 74 clocks =<&ccu1 CLK_CPU_SCT>; 75 clock-names = "pwm"; 76 resets = <&rgu 37>; 77 #pwm-cells = <3>; 78 status = "disabled"; 79 }; 80 81 dmac: dma-controller@40002000 { 82 compatible = "arm,pl080", "arm,primecell"; 83 arm,primecell-periphid = <0x00041080>; 84 reg = <0x40002000 0x1000>; 85 interrupts = <2>; 86 clocks = <&ccu1 CLK_CPU_DMA>; 87 clock-names = "apb_pclk"; 88 resets = <&rgu 19>; 89 #dma-cells = <2>; 90 dma-channels = <8>; 91 dma-requests = <16>; 92 lli-bus-interface-ahb1; 93 lli-bus-interface-ahb2; 94 mem-bus-interface-ahb1; 95 mem-bus-interface-ahb2; 96 memcpy-burst-size = <256>; 97 memcpy-bus-width = <32>; 98 }; 99 100 spifi: flash-controller@40003000 { 101 compatible = "nxp,lpc1773-spifi"; 102 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; 103 reg-names = "spifi", "flash"; 104 interrupts = <30>; 105 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; 106 clock-names = "spifi", "reg"; 107 resets = <&rgu 53>; 108 status = "disabled"; 109 }; 110 111 mmcsd: mmcsd@40004000 { 112 compatible = "snps,dw-mshc"; 113 reg = <0x40004000 0x1000>; 114 interrupts = <6>; 115 num-slots = <1>; 116 clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; 117 clock-names = "ciu", "biu"; 118 resets = <&rgu 20>; 119 status = "disabled"; 120 }; 121 122 usb0: ehci@40006100 { 123 compatible = "nxp,lpc1850-ehci", "generic-ehci"; 124 reg = <0x40006100 0x100>; 125 interrupts = <8>; 126 clocks = <&ccu1 CLK_CPU_USB0>; 127 resets = <&rgu 17>; 128 phys = <&usb0_otg_phy>; 129 phy-names = "usb"; 130 has-transaction-translator; 131 status = "disabled"; 132 }; 133 134 usb1: ehci@40007100 { 135 compatible = "nxp,lpc1850-ehci", "generic-ehci"; 136 reg = <0x40007100 0x100>; 137 interrupts = <9>; 138 clocks = <&ccu1 CLK_CPU_USB1>; 139 resets = <&rgu 18>; 140 status = "disabled"; 141 }; 142 143 emc: memory-controller@40005000 { 144 compatible = "arm,pl172", "arm,primecell"; 145 reg = <0x40005000 0x1000>; 146 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; 147 clock-names = "mpmcclk", "apb_pclk"; 148 resets = <&rgu 21>; 149 #address-cells = <2>; 150 #size-cells = <1>; 151 ranges = <0 0 0x1c000000 0x1000000 152 1 0 0x1d000000 0x1000000 153 2 0 0x1e000000 0x1000000 154 3 0 0x1f000000 0x1000000>; 155 status = "disabled"; 156 }; 157 158 lcdc: lcd-controller@40008000 { 159 compatible = "arm,pl111", "arm,primecell"; 160 reg = <0x40008000 0x1000>; 161 interrupts = <7>; 162 interrupt-names = "combined"; 163 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; 164 clock-names = "clcdclk", "apb_pclk"; 165 resets = <&rgu 16>; 166 status = "disabled"; 167 }; 168 169 mac: ethernet@40010000 { 170 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 171 reg = <0x40010000 0x2000>; 172 interrupts = <5>; 173 interrupt-names = "macirq"; 174 clocks = <&ccu1 CLK_CPU_ETHERNET>; 175 clock-names = "stmmaceth"; 176 resets = <&rgu 22>; 177 reset-names = "stmmaceth"; 178 status = "disabled"; 179 }; 180 181 creg: syscon@40043000 { 182 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; 183 reg = <0x40043000 0x1000>; 184 clocks = <&ccu1 CLK_CPU_CREG>; 185 resets = <&rgu 5>; 186 187 usb0_otg_phy: phy@004 { 188 compatible = "nxp,lpc1850-usb-otg-phy"; 189 clocks = <&ccu1 CLK_USB0>; 190 #phy-cells = <0>; 191 }; 192 193 dmamux: dma-mux@11c { 194 compatible = "nxp,lpc1850-dmamux"; 195 #dma-cells = <3>; 196 dma-requests = <64>; 197 dma-masters = <&dmac>; 198 }; 199 }; 200 201 cgu: clock-controller@40050000 { 202 compatible = "nxp,lpc1850-cgu"; 203 reg = <0x40050000 0x1000>; 204 #clock-cells = <1>; 205 clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; 206 }; 207 208 ccu1: clock-controller@40051000 { 209 compatible = "nxp,lpc1850-ccu"; 210 reg = <0x40051000 0x1000>; 211 #clock-cells = <1>; 212 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, 213 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, 214 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, 215 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; 216 clock-names = "base_apb3_clk", "base_apb1_clk", 217 "base_spifi_clk", "base_cpu_clk", 218 "base_periph_clk", "base_usb0_clk", 219 "base_usb1_clk", "base_spi_clk"; 220 }; 221 222 ccu2: clock-controller@40052000 { 223 compatible = "nxp,lpc1850-ccu"; 224 reg = <0x40052000 0x1000>; 225 #clock-cells = <1>; 226 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, 227 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, 228 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, 229 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; 230 clock-names = "base_audio_clk", "base_uart3_clk", 231 "base_uart2_clk", "base_uart1_clk", 232 "base_uart0_clk", "base_ssp1_clk", 233 "base_ssp0_clk", "base_sdio_clk"; 234 }; 235 236 rgu: reset-controller@40053000 { 237 compatible = "nxp,lpc1850-rgu"; 238 reg = <0x40053000 0x1000>; 239 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 240 clock-names = "delay", "reg"; 241 #reset-cells = <1>; 242 }; 243 244 watchdog@40080000 { 245 compatible = "nxp,lpc1850-wwdt"; 246 reg = <0x40080000 0x24>; 247 interrupts = <49>; 248 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; 249 clock-names = "wdtclk", "reg"; 250 }; 251 252 uart0: serial@40081000 { 253 compatible = "nxp,lpc1850-uart", "ns16550a"; 254 reg = <0x40081000 0x1000>; 255 reg-shift = <2>; 256 interrupts = <24>; 257 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 258 clock-names = "uartclk", "reg"; 259 resets = <&rgu 44>; 260 dmas = <&dmamux 1 1 2 261 &dmamux 2 1 2 262 &dmamux 11 2 2 263 &dmamux 12 2 2>; 264 dma-names = "tx", "rx", "tx", "rx"; 265 status = "disabled"; 266 }; 267 268 uart1: serial@40082000 { 269 compatible = "nxp,lpc1850-uart", "ns16550a"; 270 reg = <0x40082000 0x1000>; 271 reg-shift = <2>; 272 interrupts = <25>; 273 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; 274 clock-names = "uartclk", "reg"; 275 resets = <&rgu 45>; 276 dmas = <&dmamux 3 1 2 277 &dmamux 4 1 2>; 278 dma-names = "tx", "rx"; 279 status = "disabled"; 280 }; 281 282 ssp0: spi@40083000 { 283 compatible = "arm,pl022", "arm,primecell"; 284 reg = <0x40083000 0x1000>; 285 interrupts = <22>; 286 clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; 287 clock-names = "sspclk", "apb_pclk"; 288 resets = <&rgu 50>; 289 dmas = <&dmamux 9 0 2 290 &dmamux 10 0 2>; 291 dma-names = "rx", "tx"; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 timer0: timer@40084000 { 298 compatible = "nxp,lpc3220-timer"; 299 reg = <0x40084000 0x1000>; 300 interrupts = <12>; 301 clocks = <&ccu1 CLK_CPU_TIMER0>; 302 clock-names = "timerclk"; 303 resets = <&rgu 32>; 304 }; 305 306 timer1: timer@40085000 { 307 compatible = "nxp,lpc3220-timer"; 308 reg = <0x40085000 0x1000>; 309 interrupts = <13>; 310 clocks = <&ccu1 CLK_CPU_TIMER1>; 311 clock-names = "timerclk"; 312 resets = <&rgu 33>; 313 }; 314 315 pinctrl: pinctrl@40086000 { 316 compatible = "nxp,lpc1850-scu"; 317 reg = <0x40086000 0x1000>; 318 clocks = <&ccu1 CLK_CPU_SCU>; 319 }; 320 321 i2c0: i2c@400a1000 { 322 compatible = "nxp,lpc1788-i2c"; 323 reg = <0x400a1000 0x1000>; 324 interrupts = <18>; 325 clocks = <&ccu1 CLK_APB1_I2C0>; 326 resets = <&rgu 48>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 status = "disabled"; 330 }; 331 332 can1: can@400a4000 { 333 compatible = "bosch,c_can"; 334 reg = <0x400a4000 0x1000>; 335 interrupts = <43>; 336 clocks = <&ccu1 CLK_APB1_CAN1>; 337 resets = <&rgu 54>; 338 status = "disabled"; 339 }; 340 341 uart2: serial@400c1000 { 342 compatible = "nxp,lpc1850-uart", "ns16550a"; 343 reg = <0x400c1000 0x1000>; 344 reg-shift = <2>; 345 interrupts = <26>; 346 clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; 347 clock-names = "uartclk", "reg"; 348 resets = <&rgu 46>; 349 dmas = <&dmamux 5 1 2 350 &dmamux 6 1 2>; 351 dma-names = "tx", "rx"; 352 status = "disabled"; 353 }; 354 355 uart3: serial@400c2000 { 356 compatible = "nxp,lpc1850-uart", "ns16550a"; 357 reg = <0x400c2000 0x1000>; 358 reg-shift = <2>; 359 interrupts = <27>; 360 clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; 361 clock-names = "uartclk", "reg"; 362 resets = <&rgu 47>; 363 dmas = <&dmamux 7 1 2 364 &dmamux 8 1 2 365 &dmamux 13 3 2 366 &dmamux 14 3 2>; 367 dma-names = "tx", "rx", "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 timer2: timer@400c3000 { 372 compatible = "nxp,lpc3220-timer"; 373 reg = <0x400c3000 0x1000>; 374 interrupts = <14>; 375 clocks = <&ccu1 CLK_CPU_TIMER2>; 376 clock-names = "timerclk"; 377 resets = <&rgu 34>; 378 }; 379 380 timer3: timer@400c4000 { 381 compatible = "nxp,lpc3220-timer"; 382 reg = <0x400c4000 0x1000>; 383 interrupts = <15>; 384 clocks = <&ccu1 CLK_CPU_TIMER3>; 385 clock-names = "timerclk"; 386 resets = <&rgu 35>; 387 }; 388 389 ssp1: spi@400c5000 { 390 compatible = "arm,pl022", "arm,primecell"; 391 reg = <0x400c5000 0x1000>; 392 interrupts = <23>; 393 clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; 394 clock-names = "sspclk", "apb_pclk"; 395 resets = <&rgu 51>; 396 dmas = <&dmamux 11 2 2 397 &dmamux 12 2 2 398 &dmamux 3 3 2 399 &dmamux 4 3 2 400 &dmamux 5 2 2 401 &dmamux 6 2 2 402 &dmamux 13 2 2 403 &dmamux 14 2 2>; 404 dma-names = "rx", "tx", "tx", "rx", 405 "tx", "rx", "rx", "tx"; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 status = "disabled"; 409 }; 410 411 i2c1: i2c@400e0000 { 412 compatible = "nxp,lpc1788-i2c"; 413 reg = <0x400e0000 0x1000>; 414 interrupts = <19>; 415 clocks = <&ccu1 CLK_APB3_I2C1>; 416 resets = <&rgu 49>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 can0: can@400e2000 { 423 compatible = "bosch,c_can"; 424 reg = <0x400e2000 0x1000>; 425 interrupts = <51>; 426 clocks = <&ccu1 CLK_APB3_CAN0>; 427 resets = <&rgu 55>; 428 status = "disabled"; 429 }; 430 431 gpio: gpio@400f4000 { 432 compatible = "nxp,lpc1850-gpio"; 433 reg = <0x400f4000 0x4000>; 434 clocks = <&ccu1 CLK_CPU_GPIO>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, 438 <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, 439 <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, 440 <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, 441 <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, 442 <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, 443 <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, 444 <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, 445 <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, 446 <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, 447 <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, 448 <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, 449 <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, 450 <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, 451 <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, 452 <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, 453 <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, 454 <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, 455 <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, 456 <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, 457 <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, 458 <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, 459 <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, 460 <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, 461 <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, 462 <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, 463 <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, 464 <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, 465 <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, 466 <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, 467 <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, 468 <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, 469 <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, 470 <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, 471 <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, 472 <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, 473 <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, 474 <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, 475 <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, 476 <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; 477 }; 478 }; 479}; 480