Lines Matching refs:clocks
45 clocks = <&twd_clk>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
246 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
256 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
268 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
280 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
292 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
303 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
313 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
323 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
333 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
343 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
353 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
363 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
373 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
383 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
537 clocks = <&zb_clk>;
541 clocks {
546 /* External root clocks */
582 /* Special CPG clocks */
584 compatible = "renesas,sh73a0-cpg-clocks";
586 clocks = <&extal1_clk>, <&extal2_clk>;
594 /* Variable factor clocks (DIV6) */
598 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
608 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
618 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
628 clocks = <&pll1_div2_clk>, <0>,
636 clocks = <&pll1_div2_clk>, <0>,
644 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
652 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
660 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
668 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
676 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
684 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
692 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
700 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
708 clocks = <&pll1_div2_clk>, <0>,
716 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
724 clocks = <&pll1_div2_clk>, <0>,
732 clocks = <&pll1_div2_clk>, <0>,
740 clocks = <&pll1_div2_clk>, <0>,
748 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
755 /* Fixed factor clocks */
758 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
766 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
774 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
782 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
790 clocks = <&cpg_clocks SH73A0_CLK_Z>;
797 /* Gate clocks */
799 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
801 clocks = <&cpg_clocks SH73A0_CLK_HP>;
810 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
812 clocks = <&cpg_clocks SH73A0_CLK_B>,
833 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
835 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
853 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
855 clocks = <&sub_clk>, <&extalr_clk>,
881 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
883 clocks = <&cpg_clocks SH73A0_CLK_HP>,
894 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
896 clocks = <&cpg_clocks SH73A0_CLK_HP>;