1/* 2 * Copyright Altera Corporation (C) 2014. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include "skeleton.dtsi" 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/reset/altr,rst-mgr-a10.h> 20 21/ { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 aliases { 26 serial0 = &uart0; 27 serial1 = &uart1; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 enable-method = "altr,socfpga-a10-smp"; 34 35 cpu@0 { 36 compatible = "arm,cortex-a9"; 37 device_type = "cpu"; 38 reg = <0>; 39 next-level-cache = <&L2>; 40 }; 41 cpu@1 { 42 compatible = "arm,cortex-a9"; 43 device_type = "cpu"; 44 reg = <1>; 45 next-level-cache = <&L2>; 46 }; 47 }; 48 49 intc: intc@ffffd000 { 50 compatible = "arm,cortex-a9-gic"; 51 #interrupt-cells = <3>; 52 interrupt-controller; 53 reg = <0xffffd000 0x1000>, 54 <0xffffc100 0x100>; 55 }; 56 57 soc { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 device_type = "soc"; 62 interrupt-parent = <&intc>; 63 ranges; 64 65 amba { 66 compatible = "arm,amba-bus"; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 pdma: pdma@ffda1000 { 72 compatible = "arm,pl330", "arm,primecell"; 73 reg = <0xffda1000 0x1000>; 74 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, 75 <0 84 IRQ_TYPE_LEVEL_HIGH>, 76 <0 85 IRQ_TYPE_LEVEL_HIGH>, 77 <0 86 IRQ_TYPE_LEVEL_HIGH>, 78 <0 87 IRQ_TYPE_LEVEL_HIGH>, 79 <0 88 IRQ_TYPE_LEVEL_HIGH>, 80 <0 89 IRQ_TYPE_LEVEL_HIGH>, 81 <0 90 IRQ_TYPE_LEVEL_HIGH>; 82 #dma-cells = <1>; 83 #dma-channels = <8>; 84 #dma-requests = <32>; 85 }; 86 }; 87 88 clkmgr@ffd04000 { 89 compatible = "altr,clk-mgr"; 90 reg = <0xffd04000 0x1000>; 91 92 clocks { 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 }; 100 101 cb_intosc_ls_clk: cb_intosc_ls_clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 }; 105 106 f2s_free_clk: f2s_free_clk { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 }; 110 111 osc1: osc1 { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 }; 115 116 main_pll: main_pll { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 #clock-cells = <0>; 120 compatible = "altr,socfpga-a10-pll-clock"; 121 clocks = <&osc1>, <&cb_intosc_ls_clk>, 122 <&f2s_free_clk>; 123 reg = <0x40>; 124 125 main_mpu_base_clk: main_mpu_base_clk { 126 #clock-cells = <0>; 127 compatible = "altr,socfpga-a10-perip-clk"; 128 clocks = <&main_pll>; 129 div-reg = <0x140 0 11>; 130 }; 131 132 main_noc_base_clk: main_noc_base_clk { 133 #clock-cells = <0>; 134 compatible = "altr,socfpga-a10-perip-clk"; 135 clocks = <&main_pll>; 136 div-reg = <0x144 0 11>; 137 }; 138 139 main_emaca_clk: main_emaca_clk { 140 #clock-cells = <0>; 141 compatible = "altr,socfpga-a10-perip-clk"; 142 clocks = <&main_pll>; 143 reg = <0x68>; 144 }; 145 146 main_emacb_clk: main_emacb_clk { 147 #clock-cells = <0>; 148 compatible = "altr,socfpga-a10-perip-clk"; 149 clocks = <&main_pll>; 150 reg = <0x6C>; 151 }; 152 153 main_emac_ptp_clk: main_emac_ptp_clk { 154 #clock-cells = <0>; 155 compatible = "altr,socfpga-a10-perip-clk"; 156 clocks = <&main_pll>; 157 reg = <0x70>; 158 }; 159 160 main_gpio_db_clk: main_gpio_db_clk { 161 #clock-cells = <0>; 162 compatible = "altr,socfpga-a10-perip-clk"; 163 clocks = <&main_pll>; 164 reg = <0x74>; 165 }; 166 167 main_sdmmc_clk: main_sdmmc_clk { 168 #clock-cells = <0>; 169 compatible = "altr,socfpga-a10-perip-clk" 170; 171 clocks = <&main_pll>; 172 reg = <0x78>; 173 }; 174 175 main_s2f_usr0_clk: main_s2f_usr0_clk { 176 #clock-cells = <0>; 177 compatible = "altr,socfpga-a10-perip-clk"; 178 clocks = <&main_pll>; 179 reg = <0x7C>; 180 }; 181 182 main_s2f_usr1_clk: main_s2f_usr1_clk { 183 #clock-cells = <0>; 184 compatible = "altr,socfpga-a10-perip-clk"; 185 clocks = <&main_pll>; 186 reg = <0x80>; 187 }; 188 189 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { 190 #clock-cells = <0>; 191 compatible = "altr,socfpga-a10-perip-clk"; 192 clocks = <&main_pll>; 193 reg = <0x84>; 194 }; 195 196 main_periph_ref_clk: main_periph_ref_clk { 197 #clock-cells = <0>; 198 compatible = "altr,socfpga-a10-perip-clk"; 199 clocks = <&main_pll>; 200 reg = <0x9C>; 201 }; 202 }; 203 204 periph_pll: periph_pll { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 #clock-cells = <0>; 208 compatible = "altr,socfpga-a10-pll-clock"; 209 clocks = <&osc1>, <&cb_intosc_ls_clk>, 210 <&f2s_free_clk>, <&main_periph_ref_clk>; 211 reg = <0xC0>; 212 213 peri_mpu_base_clk: peri_mpu_base_clk { 214 #clock-cells = <0>; 215 compatible = "altr,socfpga-a10-perip-clk"; 216 clocks = <&periph_pll>; 217 div-reg = <0x140 16 11>; 218 }; 219 220 peri_noc_base_clk: peri_noc_base_clk { 221 #clock-cells = <0>; 222 compatible = "altr,socfpga-a10-perip-clk"; 223 clocks = <&periph_pll>; 224 div-reg = <0x144 16 11>; 225 }; 226 227 peri_emaca_clk: peri_emaca_clk { 228 #clock-cells = <0>; 229 compatible = "altr,socfpga-a10-perip-clk"; 230 clocks = <&periph_pll>; 231 reg = <0xE8>; 232 }; 233 234 peri_emacb_clk: peri_emacb_clk { 235 #clock-cells = <0>; 236 compatible = "altr,socfpga-a10-perip-clk"; 237 clocks = <&periph_pll>; 238 reg = <0xEC>; 239 }; 240 241 peri_emac_ptp_clk: peri_emac_ptp_clk { 242 #clock-cells = <0>; 243 compatible = "altr,socfpga-a10-perip-clk"; 244 clocks = <&periph_pll>; 245 reg = <0xF0>; 246 }; 247 248 peri_gpio_db_clk: peri_gpio_db_clk { 249 #clock-cells = <0>; 250 compatible = "altr,socfpga-a10-perip-clk"; 251 clocks = <&periph_pll>; 252 reg = <0xF4>; 253 }; 254 255 peri_sdmmc_clk: peri_sdmmc_clk { 256 #clock-cells = <0>; 257 compatible = "altr,socfpga-a10-perip-clk"; 258 clocks = <&periph_pll>; 259 reg = <0xF8>; 260 }; 261 262 peri_s2f_usr0_clk: peri_s2f_usr0_clk { 263 #clock-cells = <0>; 264 compatible = "altr,socfpga-a10-perip-clk"; 265 clocks = <&periph_pll>; 266 reg = <0xFC>; 267 }; 268 269 peri_s2f_usr1_clk: peri_s2f_usr1_clk { 270 #clock-cells = <0>; 271 compatible = "altr,socfpga-a10-perip-clk"; 272 clocks = <&periph_pll>; 273 reg = <0x100>; 274 }; 275 276 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { 277 #clock-cells = <0>; 278 compatible = "altr,socfpga-a10-perip-clk"; 279 clocks = <&periph_pll>; 280 reg = <0x104>; 281 }; 282 }; 283 284 mpu_free_clk: mpu_free_clk { 285 #clock-cells = <0>; 286 compatible = "altr,socfpga-a10-perip-clk"; 287 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, 288 <&osc1>, <&cb_intosc_hs_div2_clk>, 289 <&f2s_free_clk>; 290 reg = <0x60>; 291 }; 292 293 noc_free_clk: noc_free_clk { 294 #clock-cells = <0>; 295 compatible = "altr,socfpga-a10-perip-clk"; 296 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, 297 <&osc1>, <&cb_intosc_hs_div2_clk>, 298 <&f2s_free_clk>; 299 reg = <0x64>; 300 }; 301 302 s2f_user1_free_clk: s2f_user1_free_clk { 303 #clock-cells = <0>; 304 compatible = "altr,socfpga-a10-perip-clk"; 305 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, 306 <&osc1>, <&cb_intosc_hs_div2_clk>, 307 <&f2s_free_clk>; 308 reg = <0x104>; 309 }; 310 311 sdmmc_free_clk: sdmmc_free_clk { 312 #clock-cells = <0>; 313 compatible = "altr,socfpga-a10-perip-clk"; 314 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, 315 <&osc1>, <&cb_intosc_hs_div2_clk>, 316 <&f2s_free_clk>; 317 fixed-divider = <4>; 318 reg = <0xF8>; 319 }; 320 321 l4_sys_free_clk: l4_sys_free_clk { 322 #clock-cells = <0>; 323 compatible = "altr,socfpga-a10-perip-clk"; 324 clocks = <&noc_free_clk>; 325 fixed-divider = <4>; 326 }; 327 328 l4_main_clk: l4_main_clk { 329 #clock-cells = <0>; 330 compatible = "altr,socfpga-a10-gate-clk"; 331 clocks = <&noc_free_clk>; 332 div-reg = <0xA8 0 2>; 333 clk-gate = <0x48 1>; 334 }; 335 336 l4_mp_clk: l4_mp_clk { 337 #clock-cells = <0>; 338 compatible = "altr,socfpga-a10-gate-clk"; 339 clocks = <&noc_free_clk>; 340 div-reg = <0xA8 8 2>; 341 clk-gate = <0x48 2>; 342 }; 343 344 l4_sp_clk: l4_sp_clk { 345 #clock-cells = <0>; 346 compatible = "altr,socfpga-a10-gate-clk"; 347 clocks = <&noc_free_clk>; 348 div-reg = <0xA8 16 2>; 349 clk-gate = <0x48 3>; 350 }; 351 352 mpu_periph_clk: mpu_periph_clk { 353 #clock-cells = <0>; 354 compatible = "altr,socfpga-a10-gate-clk"; 355 clocks = <&mpu_free_clk>; 356 fixed-divider = <4>; 357 clk-gate = <0x48 0>; 358 }; 359 360 sdmmc_clk: sdmmc_clk { 361 #clock-cells = <0>; 362 compatible = "altr,socfpga-a10-gate-clk"; 363 clocks = <&sdmmc_free_clk>; 364 clk-gate = <0xC8 5>; 365 }; 366 367 qspi_clk: qspi_clk { 368 #clock-cells = <0>; 369 compatible = "altr,socfpga-a10-gate-clk"; 370 clocks = <&l4_main_clk>; 371 clk-gate = <0xC8 11>; 372 }; 373 374 nand_clk: nand_clk { 375 #clock-cells = <0>; 376 compatible = "altr,socfpga-a10-gate-clk"; 377 clocks = <&l4_mp_clk>; 378 clk-gate = <0xC8 10>; 379 }; 380 381 spi_m_clk: spi_m_clk { 382 #clock-cells = <0>; 383 compatible = "altr,socfpga-a10-gate-clk"; 384 clocks = <&l4_main_clk>; 385 clk-gate = <0xC8 9>; 386 }; 387 388 usb_clk: usb_clk { 389 #clock-cells = <0>; 390 compatible = "altr,socfpga-a10-gate-clk"; 391 clocks = <&l4_mp_clk>; 392 clk-gate = <0xC8 8>; 393 }; 394 395 s2f_usr1_clk: s2f_usr1_clk { 396 #clock-cells = <0>; 397 compatible = "altr,socfpga-a10-gate-clk"; 398 clocks = <&peri_s2f_usr1_clk>; 399 clk-gate = <0xC8 6>; 400 }; 401 }; 402 }; 403 404 gmac0: ethernet@ff800000 { 405 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 406 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 407 reg = <0xff800000 0x2000>; 408 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-names = "macirq"; 410 /* Filled in by bootloader */ 411 mac-address = [00 00 00 00 00 00]; 412 snps,multicast-filter-bins = <256>; 413 snps,perfect-filter-entries = <128>; 414 tx-fifo-depth = <4096>; 415 rx-fifo-depth = <16384>; 416 clocks = <&l4_mp_clk>; 417 clock-names = "stmmaceth"; 418 resets = <&rst EMAC0_RESET>; 419 reset-names = "stmmaceth"; 420 status = "disabled"; 421 }; 422 423 gmac1: ethernet@ff802000 { 424 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 425 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 426 reg = <0xff802000 0x2000>; 427 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "macirq"; 429 /* Filled in by bootloader */ 430 mac-address = [00 00 00 00 00 00]; 431 snps,multicast-filter-bins = <256>; 432 snps,perfect-filter-entries = <128>; 433 tx-fifo-depth = <4096>; 434 rx-fifo-depth = <16384>; 435 clocks = <&l4_mp_clk>; 436 clock-names = "stmmaceth"; 437 resets = <&rst EMAC1_RESET>; 438 reset-names = "stmmaceth"; 439 status = "disabled"; 440 }; 441 442 gmac2: ethernet@ff804000 { 443 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 444 altr,sysmgr-syscon = <&sysmgr 0x4C 0>; 445 reg = <0xff804000 0x2000>; 446 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "macirq"; 448 /* Filled in by bootloader */ 449 mac-address = [00 00 00 00 00 00]; 450 snps,multicast-filter-bins = <256>; 451 snps,perfect-filter-entries = <128>; 452 tx-fifo-depth = <4096>; 453 rx-fifo-depth = <16384>; 454 clocks = <&l4_mp_clk>; 455 clock-names = "stmmaceth"; 456 status = "disabled"; 457 }; 458 459 gpio0: gpio@ffc02900 { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 compatible = "snps,dw-apb-gpio"; 463 reg = <0xffc02900 0x100>; 464 status = "disabled"; 465 466 porta: gpio-controller@0 { 467 compatible = "snps,dw-apb-gpio-port"; 468 gpio-controller; 469 #gpio-cells = <2>; 470 snps,nr-gpios = <29>; 471 reg = <0>; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; 475 }; 476 }; 477 478 gpio1: gpio@ffc02a00 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 compatible = "snps,dw-apb-gpio"; 482 reg = <0xffc02a00 0x100>; 483 status = "disabled"; 484 485 portb: gpio-controller@0 { 486 compatible = "snps,dw-apb-gpio-port"; 487 gpio-controller; 488 #gpio-cells = <2>; 489 snps,nr-gpios = <29>; 490 reg = <0>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; 494 }; 495 }; 496 497 gpio2: gpio@ffc02b00 { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 compatible = "snps,dw-apb-gpio"; 501 reg = <0xffc02b00 0x100>; 502 status = "disabled"; 503 504 portc: gpio-controller@0 { 505 compatible = "snps,dw-apb-gpio-port"; 506 gpio-controller; 507 #gpio-cells = <2>; 508 snps,nr-gpios = <27>; 509 reg = <0>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 513 }; 514 }; 515 516 i2c0: i2c@ffc02200 { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 compatible = "snps,designware-i2c"; 520 reg = <0xffc02200 0x100>; 521 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&l4_sp_clk>; 523 status = "disabled"; 524 }; 525 526 i2c1: i2c@ffc02300 { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 compatible = "snps,designware-i2c"; 530 reg = <0xffc02300 0x100>; 531 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&l4_sp_clk>; 533 status = "disabled"; 534 }; 535 536 i2c2: i2c@ffc02400 { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 compatible = "snps,designware-i2c"; 540 reg = <0xffc02400 0x100>; 541 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&l4_sp_clk>; 543 status = "disabled"; 544 }; 545 546 i2c3: i2c@ffc02500 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 compatible = "snps,designware-i2c"; 550 reg = <0xffc02500 0x100>; 551 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&l4_sp_clk>; 553 status = "disabled"; 554 }; 555 556 i2c4: i2c@ffc02600 { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 compatible = "snps,designware-i2c"; 560 reg = <0xffc02600 0x100>; 561 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&l4_sp_clk>; 563 status = "disabled"; 564 }; 565 566 sdr: sdr@ffc25000 { 567 compatible = "syscon"; 568 reg = <0xffcfb100 0x80>; 569 }; 570 571 sdramedac { 572 compatible = "altr,sdram-edac-a10"; 573 altr,sdr-syscon = <&sdr>; 574 interrupts = <0 2 4>, <0 0 4>; 575 }; 576 577 L2: l2-cache@fffff000 { 578 compatible = "arm,pl310-cache"; 579 reg = <0xfffff000 0x1000>; 580 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 581 cache-unified; 582 cache-level = <2>; 583 }; 584 585 mmc: dwmmc0@ff808000 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 compatible = "altr,socfpga-dw-mshc"; 589 reg = <0xff808000 0x1000>; 590 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 591 fifo-depth = <0x400>; 592 clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; 593 clock-names = "biu", "ciu"; 594 status = "disabled"; 595 }; 596 597 ocram: sram@ffe00000 { 598 compatible = "mmio-sram"; 599 reg = <0xffe00000 0x40000>; 600 }; 601 602 rst: rstmgr@ffd05000 { 603 #reset-cells = <1>; 604 compatible = "altr,rst-mgr"; 605 reg = <0xffd05000 0x100>; 606 altr,modrst-offset = <0x20>; 607 }; 608 609 scu: snoop-control-unit@ffffc000 { 610 compatible = "arm,cortex-a9-scu"; 611 reg = <0xffffc000 0x100>; 612 }; 613 614 sysmgr: sysmgr@ffd06000 { 615 compatible = "altr,sys-mgr", "syscon"; 616 reg = <0xffd06000 0x300>; 617 cpu1-start-addr = <0xffd06230>; 618 }; 619 620 /* Local timer */ 621 timer@ffffc600 { 622 compatible = "arm,cortex-a9-twd-timer"; 623 reg = <0xffffc600 0x100>; 624 interrupts = <1 13 0xf04>; 625 clocks = <&mpu_periph_clk>; 626 }; 627 628 timer0: timer0@ffc02700 { 629 compatible = "snps,dw-apb-timer"; 630 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; 631 reg = <0xffc02700 0x100>; 632 clocks = <&l4_sp_clk>; 633 clock-names = "timer"; 634 }; 635 636 timer1: timer1@ffc02800 { 637 compatible = "snps,dw-apb-timer"; 638 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; 639 reg = <0xffc02800 0x100>; 640 clocks = <&l4_sp_clk>; 641 clock-names = "timer"; 642 }; 643 644 timer2: timer2@ffd00000 { 645 compatible = "snps,dw-apb-timer"; 646 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; 647 reg = <0xffd00000 0x100>; 648 clocks = <&l4_sys_free_clk>; 649 clock-names = "timer"; 650 }; 651 652 timer3: timer3@ffd00100 { 653 compatible = "snps,dw-apb-timer"; 654 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; 655 reg = <0xffd01000 0x100>; 656 clocks = <&l4_sys_free_clk>; 657 clock-names = "timer"; 658 }; 659 660 uart0: serial0@ffc02000 { 661 compatible = "snps,dw-apb-uart"; 662 reg = <0xffc02000 0x100>; 663 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 664 reg-shift = <2>; 665 reg-io-width = <4>; 666 clocks = <&l4_sp_clk>; 667 status = "disabled"; 668 }; 669 670 uart1: serial1@ffc02100 { 671 compatible = "snps,dw-apb-uart"; 672 reg = <0xffc02100 0x100>; 673 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 674 reg-shift = <2>; 675 reg-io-width = <4>; 676 clocks = <&l4_sp_clk>; 677 status = "disabled"; 678 }; 679 680 usbphy0: usbphy@0 { 681 #phy-cells = <0>; 682 compatible = "usb-nop-xceiv"; 683 status = "okay"; 684 }; 685 686 usb0: usb@ffb00000 { 687 compatible = "snps,dwc2"; 688 reg = <0xffb00000 0xffff>; 689 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&usb_clk>; 691 clock-names = "otg"; 692 phys = <&usbphy0>; 693 phy-names = "usb2-phy"; 694 status = "disabled"; 695 }; 696 697 usb1: usb@ffb40000 { 698 compatible = "snps,dwc2"; 699 reg = <0xffb40000 0xffff>; 700 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&usb_clk>; 702 clock-names = "otg"; 703 phys = <&usbphy0>; 704 phy-names = "usb2-phy"; 705 status = "disabled"; 706 }; 707 708 watchdog0: watchdog@ffd00200 { 709 compatible = "snps,dw-wdt"; 710 reg = <0xffd00200 0x100>; 711 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&l4_sys_free_clk>; 713 status = "disabled"; 714 }; 715 716 watchdog1: watchdog@ffd00300 { 717 compatible = "snps,dw-wdt"; 718 reg = <0xffd00300 0x100>; 719 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&l4_sys_free_clk>; 721 status = "disabled"; 722 }; 723 }; 724}; 725