Lines Matching refs:clocks

48 	clocks {
85 			clocks = <&clks IMX5_CLK_CPU_PODF>;
104 			clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 			clocks = <&clks IMX5_CLK_IPU_GATE>,
171 					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
217 					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
231 					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
243 					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
256 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
266 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
276 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
286 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
296 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
343 				clocks = <&clks IMX5_CLK_DUMMY>;
351 				clocks = <&clks IMX5_CLK_DUMMY>;
358 				clocks = <&clks IMX5_CLK_DUMMY>;
366 				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
380 				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
390 				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
400 				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
410 				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
441 				clocks = <&clks IMX5_CLK_IIM_GATE>;
448 				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
458 				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
468 				clocks = <&clks IMX5_CLK_SDMA_GATE>,
481 				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
493 				clocks = <&clks IMX5_CLK_I2C2_GATE>;
503 				clocks = <&clks IMX5_CLK_I2C1_GATE>;
512 				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
525 				clocks = <&clks IMX5_CLK_DUMMY>;
535 				clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
553 				clocks = <&clks IMX5_CLK_NFC_GATE>;
561 				clocks = <&clks IMX5_CLK_PATA_GATE>;
570 				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
584 				clocks = <&clks IMX5_CLK_FEC_GATE>,