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/linux-4.1.27/arch/score/include/asm/
Dasmmacro.h10 mv r31, r0
18 mv r30, r0
19 addri r0, r31, -PT_SIZE
21 sw r30, [r0, PT_R0]
23 sw r1, [r0, PT_R1]
25 sw r2, [r0, PT_R2]
26 sw r3, [r0, PT_R3]
27 sw r4, [r0, PT_R4]
28 sw r5, [r0, PT_R5]
29 sw r6, [r0, PT_R6]
[all …]
/linux-4.1.27/arch/sh/lib/
Dchecksum.S51 mov r4, r0
52 tst #3, r0 ! Check alignment.
56 tst #1, r0 ! Check alignment.
63 mov.b @r4+, r0
64 extu.b r0, r0
65 addc r0, r6 ! t=0 from previous tst
66 mov r6, r0
68 shlr16 r0
69 shlr8 r0
70 or r0, r6
[all …]
Dashrsi3.S51 ! r0: Result
62 mov #31,r0
63 and r0,r5
64 mova ashrsi3_table,r0
65 mov.b @(r0,r5),r5
67 add r5,r0
68 jmp @r0
72 mov r4,r0
110 rotcl r0
112 subc r0,r0
[all …]
Dlshrsi3.S51 ! r0: Result
61 mov #31,r0
62 and r0,r5
63 mova lshrsi3_table,r0
64 mov.b @(r0,r5),r5
66 add r5,r0
67 jmp @r0
71 mov r4,r0
109 shlr2 r0
111 shlr2 r0
[all …]
Dashlsi3.S51 ! r0: Result
61 mov #31,r0
62 and r0,r5
63 mova ashlsi3_table,r0
64 mov.b @(r0,r5),r5
66 add r5,r0
67 jmp @r0
71 mov r4,r0
109 shll2 r0
111 shll2 r0
[all …]
Dudivsi3_i4i.S65 mov r4,r0
66 shlr8 r0
72 shlr r0
76 div1 r5,r0
78 div1 r5,r0
79 div1 r5,r0
81 div1 r5,r0
84 mova div_table_ix,r0
86 mov.b @(r0,r5),r1
89 mova div_table_ix,r0
[all …]
Dcopy_page.S33 mov #(PAGE_SIZE >> 10), r0
34 shll8 r0
35 shll2 r0
36 add r0,r8
38 1: mov.l @r11+,r0
47 movca.l r0,@r10
49 mov.l r0,@r10
85 mov #11,r0
87 cmp/gt r0,r6 ! r6 (len) > r0 (11)
93 neg r5,r0
[all …]
Dmovmem.S52 mov.l @(48,r5),r0
55 mov.l @(60,r5),r0
57 mov.l r0,@(60,r4)
59 mov.l @(56,r5),r0
61 mov.l r0,@(56,r4)
63 mov.l @(52,r5),r0
65 mov.l r0,@(52,r4)
70 mova __movmemSI4+4,r0
71 add r6,r0
72 jmp @r0
[all …]
Dudivsi3.S43 div1 r5,r4; rotcl r0
44 div1 r5,r4; rotcl r0
45 div1 r5,r4; rotcl r0
50 extu.w r5,r0
51 cmp/eq r5,r0
54 swap.w r4,r0
60 xtrct r4,r0
61 xtrct r0,r4
67 xtrct r4,r0
68 swap.w r0,r0
[all …]
Dmemset-sh4.S16 mov #12,r0
18 cmp/gt r6,r0
24 sub r0,r6
26 dt r0
31 swap.b r5,r0 ! V0
32 or r0,r5 ! VV
33 swap.w r5,r0 ! VV00
34 or r0,r5 ! VVVV
37 mov #0x40, r0 ! (MT)
38 cmp/gt r6,r0 ! (MT) 64 > len => slow loop
[all …]
Dstrlen.S13 mov r4,r0
14 and #3,r0
15 tst r0,r0
19 add #-1,r0
20 shll2 r0
21 shll r0
22 braf r0
54 extu.b r1,r0
55 tst r0,r0
59 extu.b r1,r0
[all …]
Dmemcpy-sh4.S32 mov.l @(r0,r5),r7 ! 21 LS (2 cycles latency)
39 3: mov.l @(r0,r5),r1 ! 21 LS (latency=2) ! NMLK
42 cmp/hi r2,r0 ! 57 MT
54 mov.l r3,@-r0 ! 30 LS
56 3: mov.l @(r0,r5),r1 ! 21 LS (latency=2) ! KLMN
59 cmp/hi r2,r0 ! 57 MT
71 mov.l r3,@-r0 ! 30 LS
76 cmp/eq r4,r0 ! 54 MT
81 8: cmp/hi r2,r0 ! 57 MT
82 mov.b @(r0,r5),r1 ! 20 LS (latency=2)
[all …]
Dudivsi3_i4i-Os.S50 extu.w r5,r0
51 cmp/eq r5,r0
52 swap.w r4,r0
65 xtrct r4,r0
66 xtrct r0,r4
72 xtrct r4,r0
74 swap.w r0,r0
77 rotcl r0
85 rotcl r0
87 rotcl r0
[all …]
Dmemset.S19 mov #12,r0
20 cmp/gt r6,r0
26 sub r0,r6
28 dt r0
33 swap.b r5,r0 ! V0
34 or r0,r5 ! VV
35 swap.w r5,r0 ! VV00
36 or r0,r5 ! VVVV
38 mov r6,r0
39 shlr2 r0
[all …]
Dudiv_qrnnd.S47 cmp/hi r6,r0
50 div1 r6,r0
52 extu.w r0,r1
54 add r6,r0
57 xtrct r4,r0
58 swap.w r0,r0
60 cmp/hs r2,r0
61 sub r2,r0
63 addc r5,r0
68 add r5,r0
[all …]
Dmcount.S45 mov #(THREAD_SIZE >> 10), r0; \
46 shll8 r0; \
47 shll2 r0; \
51 add r0, r1; \
74 add r0, r1; \
118 mov.l .Lftrace_graph_caller, r0
119 jmp @r0
128 mov.l .Lftrace_graph_caller, r0
129 jmp @r0
159 mov.l .Lskip_trace, r0
[all …]
D__clear_user.S13 mov #0, r0
36 0: mov.b r0, @r2
51 1: movca.l r0, @r2
53 1: mov.l r0, @r2
56 2: mov.l r0, @r2
58 3: mov.l r0, @r2
60 4: mov.l r0, @r2
62 5: mov.l r0, @r2
64 6: mov.l r0, @r2
66 7: mov.l r0, @r2
[all …]
/linux-4.1.27/arch/arm/mm/
Dproc-arm946.S47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
48 bic r0, r0, #0x00001000 @ i-cache
49 bic r0, r0, #0x00000004 @ d-cache
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 ret r0
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
86 mov r0, #0
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 sub r3, r1, r0 @ calculate total size
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
Dcache-v6.S39 mov r0, #0
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
65 mov r0, #0
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
[all …]
Dcache-fa.S47 mov r0, #0
48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
89 sub r3, r1, r0 @ calculate total size
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
96 add r0, r0, #CACHE_DLINESIZE
97 cmp r0, r1
129 bic r0, r0, #CACHE_DLINESIZE - 1
130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm925.S95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
132 ret r0
141 mov r0, #0
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
156 mov r0, #0
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-arm926.S64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
65 bic r0, r0, #0x1000 @ ...i............
66 bic r0, r0, #0x000e @ ............wca.
67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 ret r0
103 mov r0, #0
105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-mohawk.S54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 bic r0, r0, #0x1800 @ ...iz...........
56 bic r0, r0, #0x0006 @ .............ca.
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 ret r0
93 mov r0, #0
94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
104 mov r0, #0
105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-arm740.S41 mrc p15, 0, r0, c1, c0, 0
42 bic r0, r0, #0x3f000000 @ bank/f/lock/s
43 bic r0, r0, #0x0000000c @ w-buffer/cache
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 ret r0
65 mov r0, #0
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
68 mcr p15, 0, r0, c6, c3 @ disable area 3~7
69 mcr p15, 0, r0, c6, c4
70 mcr p15, 0, r0, c6, c5
[all …]
Dproc-arm922.S74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
75 bic r0, r0, #0x1000 @ ...i............
76 bic r0, r0, #0x000e @ ............wca.
77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
102 ret r0
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mov r0, #0
124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
170 sub r3, r1, r0 @ calculate total size
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
Dproc-arm920.S72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
73 bic r0, r0, #0x1000 @ ...i............
74 bic r0, r0, #0x000e @ ............wca.
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 ret r0
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 mov r0, #0
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 sub r3, r1, r0 @ calculate total size
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
Dproc-feroceon.S60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
66 and r0, r0, #0xf
68 mov r2, r2, lsl r0 @ actual cache size
80 mov r0, #0
81 mcr p15, 1, r0, c15, c9, 0 @ clean L2
82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
86 bic r0, r0, #0x1000 @ ...i............
[all …]
Dproc-arm1026.S71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0, #0x1000 @ ...i............
73 bic r0, r0, #0x000e @ ............wca.
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 ret r0
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 sub r3, r1, r0 @ calculate total size
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
Dproc-arm1020e.S80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 ret r0
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 mov r0, #0
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
183 sub r3, r1, r0 @ calculate total size
188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
Dproc-arm1022.S71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0, #0x1000 @ ...i............
73 bic r0, r0, #0x000e @ ............wca.
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 ret r0
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 sub r3, r1, r0 @ calculate total size
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
Dcache-v4wb.S60 mov r0, #0
61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
112 sub r3, r1, r0 @ calculate total size
119 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
120 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
121 add r0, r0, #CACHE_DLINESIZE
122 cmp r0, r1
138 add r1, r0, r1
165 bic r0, r0, #CACHE_DLINESIZE - 1
166 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
Dproc-sa110.S39 mov r0, #0
40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
47 mov r0, #0
48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
50 bic r0, r0, #0x1000 @ ...i............
51 bic r0, r0, #0x000e @ ............wca.
52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 ret r0
98 mov r0, r0 @ safety
[all …]
Dproc-arm1020.S80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 ret r0
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 mov r0, #0
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
184 sub r3, r1, r0 @ calculate total size
190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
Dproc-sa1100.S43 mov r0, #0
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
57 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
58 bic r0, r0, #0x1000 @ ...i............
59 bic r0, r0, #0x000e @ ............wca.
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 ret r0
102 mov r0, r0 @ 4 nop padding
103 mov r0, r0
[all …]
Dproc-xsc3.S92 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
93 bic r0, r0, #0x1800 @ ...IZ...........
94 bic r0, r0, #0x0006 @ .............CA.
95 mcr p15, 0, r0, c1, c0, 0 @ disable caches
122 ret r0
139 mov r0, #1
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
151 mov r0, #0
152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
174 clean_d_cache r0, r1
[all …]
Dproc-arm940.S40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
41 bic r0, r0, #0x00001000 @ i-cache
42 bic r0, r0, #0x00000004 @ d-cache
43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 ret r0
70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
79 mov r0, #0
80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
163 mov r0, #0
171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-xscale.S127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 bic r0, r0, #0x1800 @ ...IZ...........
129 bic r0, r0, #0x0006 @ .............CA.
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
163 ret r0
180 mov r0, #1
181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
192 mov r0, #0
193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
215 clean_d_cache r0, r1
[all …]
Dcache-v4wt.S50 mov r0, #0
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
88 sub r3, r1, r0 @ calculate total size
92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
95 add r0, r0, #CACHE_DLINESIZE
96 cmp r0, r1
124 bic r0, r0, #CACHE_DLINESIZE - 1
125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
126 add r0, r0, #CACHE_DLINESIZE
[all …]
Dproc-fa526.S41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 bic r0, r0, #0x1000 @ ...i............
43 bic r0, r0, #0x000e @ ............wca.
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 ret r0
88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 add r0, r0, #CACHE_DLINESIZE
92 mcr p15, 0, r0, c7, c10, 4 @ drain WB
117 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
131 mov r0, r0
[all …]
Dtlb-v4wbi.S40 bic r0, r0, #0x0ff
41 bic r0, r0, #0xf00
43 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
44 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
45 add r0, r0, #PAGE_SZ
46 cmp r0, r1
53 bic r0, r0, #0x0ff
54 bic r0, r0, #0xf00
55 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
56 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
[all …]
Dtlb-v7.S39 mov r0, r0, lsr #PAGE_SHIFT @ align address
46 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
56 add r0, r0, #PAGE_SZ
57 cmp r0, r1
73 mov r0, r0, lsr #PAGE_SHIFT @ align address
75 mov r0, r0, lsl #PAGE_SHIFT
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
[all …]
Dtlb-v4wb.S42 bic r0, r0, #0x0ff
43 bic r0, r0, #0xf00
44 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
45 add r0, r0, #PAGE_SZ
46 cmp r0, r1
62 bic r0, r0, #0x0ff
63 bic r0, r0, #0xf00
65 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
66 add r0, r0, #PAGE_SZ
67 cmp r0, r1
Dtlb-fa.S44 bic r0, r0, #0x0ff
45 bic r0, r0, #0xf00
46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
47 add r0, r0, #PAGE_SZ
48 cmp r0, r1
57 bic r0, r0, #0x0ff
58 bic r0, r0, #0xf00
59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
60 add r0, r0, #PAGE_SZ
61 cmp r0, r1
Dtlb-v6.S41 mov r0, r0, lsr #PAGE_SHIFT @ align address
44 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
55 add r0, r0, #PAGE_SZ
56 cmp r0, r1
72 mov r0, r0, lsr #PAGE_SHIFT @ align address
74 mov r0, r0, lsl #PAGE_SHIFT
78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
[all …]
Dcache-v7.S35 mov r0, #0
36 mcr p15, 2, r0, c0, c0, 0
37 mrc p15, 1, r0, c0, c0, 0
40 and r2, r1, r0, lsr #13
44 and r3, r1, r0, lsr #3 @ NumWays - 1
47 and r0, r0, #0x7
48 add r0, r0, #4 @ SetShift
56 mov r6, r2, lsl r0
76 mov r0, #0
77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
[all …]
Dproc-v7.S33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 bx r0
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, r2
101 stmia r0!, {r4 - r5}
114 stmia r0, {r5 - r11}
122 ldmia r0!, {r4 - r5}
[all …]
Dproc-arm720.S57 mrc p15, 0, r0, c1, c0, 0
58 bic r0, r0, #0x1000 @ ...i............
59 bic r0, r0, #0x000e @ ............wca.
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
115 ret r0
121 mov r0, #0
122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
126 mrc p15, 0, r0, c1, c0 @ get control register
[all …]
Dproc-v6.S42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
43 bic r0, r0, #0x1000 @ ...i............
44 bic r0, r0, #0x0006 @ .............ca.
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 ret r0
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
84 add r0, r0, #D_CACHE_LINE_SIZE
103 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
104 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
[all …]
Dl2c-l2x0-resume.S15 adr r0, 1f
16 ldr r2, [r0]
17 add r0, r2, r0
19 ldmia r0, {r1, r2, r3, r4, r5, r6, r7, r8}
35 ldr r0, [r1, #L2X0_CACHE_ID]
36 and r0, r0, #L2X0_CACHE_ID_RTL_MASK
37 cmp r0, #L310_CACHE_ID_RTL_R2P0
39 cmp r0, #L310_CACHE_ID_RTL_R3P0
/linux-4.1.27/arch/powerpc/lib/
Dchecksum_64.S28 lwz r0,0(r3)
31 addc r0,r0,r5
35 adde r0,r0,r4
37 addze r0,r0 /* add in final carry */
38 rldicl r4,r0,32,0 /* fold two 32-bit halves together */
39 add r0,r0,r4
40 srdi r0,r0,32
41 rlwinm r3,r0,16,0,31 /* fold two halves together */
42 add r3,r0,r3
56 addc r0,r3,r4 /* add 4 32-bit words together */
[all …]
Dchecksum_32.S27 lwz r0,0(r3)
30 addc r0,r0,r5
34 adde r0,r0,r4
36 addze r0,r0 /* add in final carry */
37 rlwinm r3,r0,16,0,31 /* fold two halves together */
38 add r3,r0,r3
49 addc r0,r3,r4 /* add 4 32-bit words together */
50 adde r0,r0,r5
51 adde r0,r0,r7
52 addze r0,r0 /* add in final carry */
[all …]
Dcopy_32.S80 andi. r0,r6,3
81 add r5,r0,r5
82 subf r6,r0,r6
83 srwi r0,r5,2
84 mtctr r0
107 andi. r0,r6,3 /* get dest word aligned */
118 lwzu r0,4(r4)
120 stwu r0,4(r6)
126 4: lbzu r0,1(r4)
127 stbu r0,1(r6)
[all …]
Dstring.S22 1: lbzu r0,1(r4)
23 cmpwi 0,r0,0
24 stbu r0,1(r5)
36 1: lbzu r0,1(r4)
37 cmpwi 0,r0,0
38 stbu r0,1(r6)
44 2: stbu r0,1(r6) /* clear it out if so */
51 1: lbzu r0,1(r5)
52 cmpwi 0,r0,0
55 1: lbzu r0,1(r4)
[all …]
Dmemcpy_power7.S55 lbz r0,0(r4)
57 stb r0,0(r3)
61 lhz r0,0(r4)
63 sth r0,0(r3)
67 lwz r0,0(r4)
69 stw r0,0(r3)
76 mflr r0
87 std r0,STACKFRAMESIZE+16(r1)
95 ld r0,0(r4)
112 std r0,0(r3)
[all …]
Dcrtsavres.S239 stvx v20,r11,r0
242 stvx v21,r11,r0
245 stvx v22,r11,r0
248 stvx v23,r11,r0
251 stvx v24,r11,r0
254 stvx v25,r11,r0
257 stvx v26,r11,r0
260 stvx v27,r11,r0
263 stvx v28,r11,r0
266 stvx v29,r11,r0
[all …]
Dcopyuser_power7.S70 ld r0,STACKFRAMESIZE+16(r1)
71 mtlr r0
122 err1; lbz r0,0(r4)
124 err1; stb r0,0(r3)
128 err1; lhz r0,0(r4)
130 err1; sth r0,0(r3)
134 err1; lwz r0,0(r4)
136 err1; stw r0,0(r3)
143 mflr r0
154 std r0,STACKFRAMESIZE+16(r1)
[all …]
Dldstfp.S42 mflr r0
56 mtlr r0
61 mflr r0
75 mtlr r0
81 mflr r0
82 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
96 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
97 mtlr r0
108 mflr r0
109 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
[all …]
Dmemcpy_64.S56 andi. r0,r4,7
97 subf r4,r0,r4
99 sldi r10,r0,3
104 add r5,r5,r0
109 ld r0,8(r4)
112 srd r7,r0,r11
113 sld r8,r0,r10
116 ld r0,8(r4)
117 # s1<< in r8, d0=(s0<<|s1>>) in r7, s3 in r0, s2 in r9, nix in r6 & r12
120 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
[all …]
Dstring_64.S71 err3; stb r0,0(r3)
83 li r0,0
91 err1; stb r0,0(r3)
95 err1; sth r0,0(r3)
99 err1; stw r0,0(r3)
115 err2; std r0,0(r3)
116 err2; std r0,8(r3)
117 err2; std r0,16(r3)
118 err2; std r0,24(r3)
127 err2; std r0,0(r3)
[all …]
Dmem_64.S16 neg r0,r3
18 andi. r0,r0,7 /* # bytes to be 8-byte aligned */
20 cmplw cr1,r5,r0 /* do we get that far? */
22 PPC_MTOCRF(1,r0)
26 subf r5,r0,r5
36 3: srdi. r0,r5,6
38 mtctr r0
50 5: srwi. r0,r5,3
52 PPC_MTOCRF(1,r0)
90 andi. r0,r6,3
[all …]
/linux-4.1.27/arch/sh/kernel/cpu/shmobile/
Dsleep.S24 #define k0 r0
37 stc vbr, r0
38 mov.l r0, @(SH_SLEEP_VBR, r5)
44 sts pr, r0
45 mov.l r0, @(SH_SLEEP_SPC, r5)
48 stc sr, r0
49 mov.l r0, @(SH_SLEEP_SR, r5)
52 mov.l @(SH_SLEEP_MODE, r5), r0
53 tst #SUSP_SH_REGS, r0
96 mov #SH_SLEEP_REG_STBCR, r0
[all …]
/linux-4.1.27/arch/m32r/lib/
Dchecksum.S55 ; r0: unsigned char *buff
60 and3 r7, r0, #1 ; Check alignment.
63 ldub r4, @r0 || addi r0, #1
65 cmp r0, r0 || addi r1, #-1
70 and3 r4, r0, #2 ; Check alignment.
73 cmp r0, r0 || addi r1, #-2
79 lduh r4, @r0 || ldi r3, #0
80 addx r2, r4 || addi r0, #2
85 cmp r0, r0 ; clear c-bit
90 1: ld r3, @r0+
[all …]
Dashxdi3.S9 ; input (r0,r1) src
12 ; output (r0,r1)
27 mv r1, r0 || srai r0, #31
33 mv r3, r0 || srl r1, r2
34 sra r0, r2 || neg r2, r2
47 mv r0, r1 || addi r2, #-32
48 sll r0, r2 || ldi r1, #0
52 mv r3, r1 || sll r0, r2
55 or r0, r3 || jmp r14
64 mv r1, r0 || addi r2, #-32
[all …]
Dstrlen.S17 mv r6, r0 || ldi r2, #0
18 and3 r0, r0, #3
19 bnez r0, strlen_byte
22 ld r0, @r6+
28 ld r1, @r6+ || not r4, r0
29 sub r0, r5 || and r4, r7
30 and r4, r0
32 ld r0, @r6+ || not r4, r1
48 ldi r0, #4 || addi r6, #-8
52 addi r0, #-1 || cmpz r1
[all …]
/linux-4.1.27/arch/tile/kernel/
Drelocate_kernel_32.S27 move r30, r0 /* page list */
41 moveli r0, 'r'
44 moveli r0, '_'
47 moveli r0, 'n'
50 moveli r0, '_'
53 moveli r0, 'k'
56 moveli r0, '\n'
90 move r0, zero /* cache_pa */
125 seqi r0, r9, 0x1 /* IND_DESTINATION */
126 bzt r0, .Ltry2
[all …]
Drelocate_kernel_64.S27 move r30, r0 /* page list */
42 moveli r0, 'r'
45 moveli r0, '_'
48 moveli r0, 'n'
51 moveli r0, '_'
54 moveli r0, 'k'
57 moveli r0, '\n'
91 move r0, zero /* cache_pa */
128 cmpeqi r0, r9, 0x1 /* IND_DESTINATION */
129 beqzt r0, .Ltry2
[all …]
Dhead_64.S48 movei r0, _HV_VERSION_OLD_HV_INIT
50 movei r0, _HV_VERSION
61 move r0, zero
73 GET_FIRST_INT(r2, r0) /* ASID for hv_install_context */
83 moveli r0, hw1_last(.Lsv_data_pmd - PAGE_OFFSET)
93 shl16insli r0, r0, hw0(.Lsv_data_pmd - PAGE_OFFSET)
109 st r0, r5
114 addli r0, r0, .Lsv_code_pmd - .Lsv_data_pmd
119 st r0, r5
125 moveli r0, hw1_last(swapper_pg_dir - PAGE_OFFSET)
[all …]
Dregs_64.S72 addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
75 addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
100 lnk r0
102 addli r0, r0, .L__switch_to_pc - .
108 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
116 st r0, \reg
117 addi r0, r0, 8
121 st r0, lr
122 addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
126 st r0, r1
[all …]
Dregs_32.S70 addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
75 addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
100 lnk r0
102 addli r0, r0, .L__switch_to_pc - .
108 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
116 sw r0, \reg
117 addi r0, r0, 4
121 sw r0, lr
122 addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
126 sw r0, r1
[all …]
Dintvec_64.S98 moveli r0, hw2_last(1b)
101 shl16insli r0, r0, hw1(1b)
104 shl16insli r0, r0, hw0(1b)
153 st_add r3, r0, 8
180 addli r0, r3, THREAD_INFO_UNALIGN_JIT_BASE_OFFSET - \
187 ld r0, r0
196 beqz r0, hand_unalign_slow
197 add r2, r0, r2
210 ld_add r0, r2, 8
217 cmpeq r0, r0, r1
[all …]
Dhead_32.S41 moveli r0, _HV_VERSION_OLD_HV_INIT
46 move r0, zero
52 move r4, r0 /* use starting ASID of range for this page table */
55 moveli r0, lo16(swapper_pg_dir - PAGE_OFFSET)
64 auli r0, r0, ha16(swapper_pg_dir - PAGE_OFFSET)
83 add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */
104 moveli r0, lo16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
105 auli r0, r0, ha16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
107 sw r0, r2
108 addi r0, r0, (HV_TOPOLOGY_HEIGHT_OFFSET - HV_TOPOLOGY_WIDTH_OFFSET)
[all …]
Dintvec_32.S85 moveli r0, lo16(1b)
88 auli r0, r0, ha16(1b)
121 mtspr SPR_SYSTEM_SAVE_K_1, r0
122 mfspr r0, SPR_EX_CONTEXT_K_1
127 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
137 bz r0, 1f
146 bnz r0, 0f
147 move r0, sp
167 mfspr r0, SPR_SYSTEM_SAVE_K_2
169 blz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
[all …]
/linux-4.1.27/arch/sh/kernel/cpu/sh5/
Dswitchto.S45 movi FRAME_SIZE, r0
46 sub.l r15, r0, r15
56 addi.l r1, 24, r0 ! base of pt_regs.regs
57 addi.l r0, (63*8), r8 ! base of pt_regs.trregs
66 st.q r0, ( 9*8), r9
67 st.q r0, (10*8), r10
68 st.q r0, (11*8), r11
69 st.q r0, (12*8), r12
70 st.q r0, (13*8), r13
71 st.q r0, (14*8), r14 ! for unwind, want to look as though we took a trap at
[all …]
Dentry.S302 st.q SP, TLB_SAVED_R0 , r0
354 ld.q SP, TLB_SAVED_R0, r0
383 ld.q SP, TLB_SAVED_R0, r0
458 st.q SP, 0, r0
460 gettr tr0, r0
461 st.q SP, 32, r0
464 getcon EXPEVT, r0
466 sub r1, r0, r1 /* r1=0 if reset */
467 movi _stext-CONFIG_PAGE_OFFSET, r0
468 ori r0, 1, r0
[all …]
/linux-4.1.27/arch/arm/mach-pxa/
Dstandby.S22 ldr r0, =PSSR
31 str r1, [r0] @ make sure PSSR_PH/STS are clear
64 mcr p14, 0, r0, c7, c0, 0
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
70 bic r0, r0, #PXA3_DDR_HCAL_HCEN
71 str r0, [r1, #PXA3_DDR_HCAL]
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
73 tst r0, #PXA3_DDR_HCAL_HCEN
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
77 orr r0, r0, #PXA3_RCOMP_SWEVAL
[all …]
/linux-4.1.27/arch/arm/lib/
Ddelay-loop.S26 mul r0, r2, r0
27 ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0x7fffff06
31 add r0, r0, r1, lsr #32-14
32 mov r0, r0, lsr #14 @ max = 0x0001ffff
35 mul r0, r2, r0 @ max = 2^32-1
36 add r0, r0, r1, lsr #32-6
37 movs r0, r0, lsr #6
47 subs r0, r0, #1
50 subs r0, r0, #1
52 subs r0, r0, #1
[all …]
Dgetuser.S36 check_uaccess r0, 1, r1, r2, __get_user_bad
37 1: TUSER(ldrb) r2, [r0]
38 mov r0, #0
43 check_uaccess r0, 2, r1, r2, __get_user_bad
46 2: ldrbt r2, [r0], #1
47 3: ldrbt rb, [r0], #0
49 rb .req r0
50 2: ldrb r2, [r0]
51 3: ldrb rb, [r0, #1]
58 mov r0, #0
[all …]
Dputuser.S36 check_uaccess r0, 1, r1, ip, __put_user_bad
37 1: TUSER(strb) r2, [r0]
38 mov r0, #0
43 check_uaccess r0, 2, r1, ip, __put_user_bad
47 2: TUSER(strb) r2, [r0]
48 3: TUSER(strb) ip, [r0, #1]
50 2: TUSER(strb) ip, [r0]
51 3: TUSER(strb) r2, [r0, #1]
55 2: TUSER(strb) r2, [r0], #1
56 3: TUSER(strb) ip, [r0]
[all …]
Dio-readsb.S17 ldrb r3, [r0]
19 ldrgeb r3, [r0]
21 ldrgtb r3, [r0]
37 .Linsb_16_lp: ldrb r3, [r0]
38 ldrb r4, [r0]
39 ldrb r5, [r0]
41 ldrb r6, [r0]
43 ldrb r4, [r0]
45 ldrb r5, [r0]
47 ldrb r6, [r0]
[all …]
Dbitops.h11 and r3, r0, #31 @ Get bit offset
12 mov r0, r0, lsr #5
13 add r1, r1, r0, lsl #2 @ Get word offset
22 strex r0, r2, [r1]
23 cmp r0, #0
36 and r3, r0, #31 @ Get bit offset
37 mov r0, r0, lsr #5
38 add r1, r1, r0, lsl #2 @ Get word offset
47 ands r0, r2, r3 @ save old value of bit
53 cmp r0, #0
[all …]
Dcsumipv6.S23 ldmia r0, {r0 - r3}
24 adcs r0, ip, r0
25 adcs r0, r0, r1
26 adcs r0, r0, r2
28 adcs r0, r0, r3
29 adcs r0, r0, r2
30 adcs r0, r0, #0
Dmemzero.S26 strltb r2, [r0], #1 @ 1
27 strleb r2, [r0], #1 @ 1
28 strb r2, [r0], #1 @ 1
37 ands r3, r0, #3 @ 1 unaligned?
59 stmgeia r0!, {r2, r3, ip, lr} @ 4
60 stmgeia r0!, {r2, r3, ip, lr} @ 4
61 stmgeia r0!, {r2, r3, ip, lr} @ 4
62 stmgeia r0!, {r2, r3, ip, lr} @ 4
69 stmneia r0!, {r2, r3, ip, lr} @ 4
70 stmneia r0!, {r2, r3, ip, lr} @ 4
[all …]
Dlib1funcs.S215 cmp r0, r1
220 ARM_DIV_BODY r0, r1, r2, r3
222 mov r0, r2
225 11: moveq r0, #1
226 movne r0, #0
231 mov r0, r0, lsr r2
243 cmpne r0, r1 @ compare dividend with divisor
244 moveq r0, #0
246 andeq r0, r0, r2
249 ARM_MOD_BODY r0, r1, r2, r3
[all …]
Dbswapsdi2.S6 rev r0, r0
11 rev r3, r0
12 rev r0, r1
18 eor r3, r0, r0, ror #16
21 eor r0, r3, r0, ror #8
28 eor r1, r0, r0, ror #16
33 eor r1, r1, r0, ror #8
34 eor r0, r3, ip, ror #8
Dio-readsw-armv4.S23 ldrh ip, [r0]
38 .Linsw_8_lp: ldrh r3, [r0]
39 ldrh r4, [r0]
42 ldrh r4, [r0]
43 ldrh r5, [r0]
46 ldrh r5, [r0]
47 ldrh ip, [r0]
50 ldrh ip, [r0]
51 ldrh lr, [r0]
61 ldrh r3, [r0]
[all …]
Dio-readsw-armv3.S14 adr r0, .Linsw_bad_align_msg
24 ldr r3, [r0]
45 .Linsw_8_lp: ldr r3, [r0]
47 ldr r4, [r0]
50 ldr r4, [r0]
52 ldr r5, [r0]
55 ldr r5, [r0]
57 ldr r6, [r0]
60 ldr r6, [r0]
62 ldr lr, [r0]
[all …]
Dcsumpartialcopyuser.S29 ldrusr \reg1, r0, 1
33 ldrusr \reg1, r0, 1
34 ldrusr \reg2, r0, 1
38 ldrusr \reg1, r0, 4
42 ldrusr \reg1, r0, 4
43 ldrusr \reg2, r0, 4
47 ldrusr \reg1, r0, 4
48 ldrusr \reg2, r0, 4
49 ldrusr \reg3, r0, 4
50 ldrusr \reg4, r0, 4
[all …]
Dmemmove.S33 subs ip, r0, r1
37 stmfd sp!, {r0, r4, lr}
41 UNWIND( .save {r0, r4, lr} ) @ in first stmfd block
43 add r0, r0, r2
46 ands ip, r0, #3
57 UNWIND( .save {r0, r4, lr} )
61 CALGN( ands ip, r0, #31 )
79 stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
100 W(str) r3, [r0, #-4]!
101 W(str) r4, [r0, #-4]!
[all …]
Dio-writesw-armv3.S14 adr r0, .Loutsw_bad_align_msg
29 str r3, [r0]
48 str ip, [r0]
52 str ip, [r0]
56 str ip, [r0]
60 str ip, [r0]
64 str ip, [r0]
68 str ip, [r0]
72 str ip, [r0]
76 str ip, [r0]
[all …]
Dfindbit.S29 ARM( ldrb r3, [r0, r2, lsr #3] )
31 THUMB( ldrb r3, [r0, r3] )
37 3: mov r0, r1 @ no free bits
50 ARM( ldrb r3, [r0, r2, lsr #3] )
52 THUMB( ldrb r3, [r0, r3] )
70 ARM( ldrb r3, [r0, r2, lsr #3] )
72 THUMB( ldrb r3, [r0, r3] )
78 3: mov r0, r1 @ no free bits
91 ARM( ldrb r3, [r0, r2, lsr #3] )
93 THUMB( ldrb r3, [r0, r3] )
[all …]
Dio-writesb.S15 strb \rd, [r0]
17 strb \rd, [r0]
19 strb \rd, [r0]
21 strb \rd, [r0]
24 strb lr, [r0]
26 strb lr, [r0]
28 strb lr, [r0]
29 strb \rd, [r0]
38 strb r3, [r0]
40 strgeb r3, [r0]
[all …]
/linux-4.1.27/arch/arm/mach-exynos/
Dsleep.S45 mrc p15, 0, r0, c0, c0, 0
47 and r0, r0, r1
49 cmp r0, r1
58 mrc p15, 0, r0, c0, c0, 0
60 and r0, r0, r1
62 cmp r0, r1
65 adr r0, _cp15_save_power
66 ldr r1, [r0]
67 ldr r1, [r0, r1]
68 adr r0, _cp15_save_diag
[all …]
/linux-4.1.27/arch/tile/lib/
Dusercopy_32.S28 { bz r1, 2f; addi r3, r0, -1 } /* bias down to include NUL */
29 1: { lb_u r4, r0; addi r1, r1, -1 }
31 { bnzt r1, 1b; addi r0, r0, 1 }
32 2: { sub r0, r0, r3; jrp lr }
36 { move r0, zero; jrp lr }
50 { bz r2, 2f; move r3, r0 }
52 { sb r0, r4; addi r0, r0, 1 }
55 { sub r0, r0, r3; jrp lr }
56 2: addi r0, r0, -1 /* don't count the trailing NUL */
57 { sub r0, r0, r3; jrp lr }
[all …]
Dusercopy_64.S28 { beqz r1, 2f; addi r3, r0, -1 } /* bias down to include NUL */
29 1: { ld1u r4, r0; addi r1, r1, -1 }
31 { bnezt r1, 1b; addi r0, r0, 1 }
32 2: { sub r0, r0, r3; jrp lr }
36 { move r0, zero; jrp lr }
50 { beqz r2, 2f; move r3, r0 }
52 { st1 r0, r4; addi r0, r0, 1 }
55 { sub r0, r0, r3; jrp lr }
56 2: addi r0, r0, -1 /* don't count the trailing NUL */
57 { sub r0, r0, r3; jrp lr }
[all …]
Dmemcpy_32.S91 { sw sp, lr; move r23, r0; or r4, r0, r1 }
120 EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
121 EX: { sw r0, r4; addi r0, r0, 4; addi r2, r2, -4 }
128 EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
135 { mz r0, r29, r23; jrp lr }
148 EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
150 { bnzt r6, .Lalign_loop; addi r9, r0, 63 }
280 EX: { lw r15, r1; addi r1, r1, 8; addi r10, r0, 60 } /* r15 = WORD_3 */
300 EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */
301 EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */
[all …]
/linux-4.1.27/crypto/
Dserpent_generic.c237 u32 r0, r1, r2, r3, r4; in __serpent_setkey() local
251 r0 = le32_to_cpu(k[3]); in __serpent_setkey()
257 keyiter(le32_to_cpu(k[0]), r0, r4, r2, 0, 0); in __serpent_setkey()
258 keyiter(le32_to_cpu(k[1]), r1, r0, r3, 1, 1); in __serpent_setkey()
260 keyiter(le32_to_cpu(k[3]), r3, r2, r0, 3, 3); in __serpent_setkey()
262 keyiter(le32_to_cpu(k[5]), r0, r4, r2, 5, 5); in __serpent_setkey()
263 keyiter(le32_to_cpu(k[6]), r1, r0, r3, 6, 6); in __serpent_setkey()
266 keyiter(k[0], r3, r2, r0, 8, 8); in __serpent_setkey()
268 keyiter(k[2], r0, r4, r2, 10, 10); in __serpent_setkey()
269 keyiter(k[3], r1, r0, r3, 11, 11); in __serpent_setkey()
[all …]
/linux-4.1.27/arch/arc/lib/
Dstrcmp.S19 or r2,r0,r1
25 ld.ab r2,[r0,4]
34 xor r0,r2,r3 ; mask for difference
35 sub_s r1,r0,1
36 bic_s r0,r0,r1 ; mask for least significant difference bit
37 sub r1,r5,r0
38 xor r0,r5,r1 ; mask for least significant difference byte
39 and_s r2,r2,r0
40 and_s r3,r3,r0
43 mov_s r0,1
[all …]
Dmemcmp.S20 or r12,r0,r1
24 ld r4,[r0,0]
28 ld_s WORD2,[r0,4]
31 ld.a r4,[r0,8]
38 ld r4,[r0,4]
44 xor r0,r4,r5
45 bset r0,r0,SHIFT
46 sub_s r1,r0,1
47 bic_s r1,r1,r0
52 xor r0,r4,r5
[all …]
Dstrchr-700.S19 bmsk r2,r0,1
22 breq.d r2,r0,.Laligned
24 sub_s r0,r0,r2
26 ld_s r2,[r0]
39 ld.a r2,[r0,4]
56 ld_s r2,[r0]
66 ld.a r2,[r0,4]
71 ; Found searched-for character. r0 has already advanced to next word.
80 sub_s r0,r0,1
83 sub_s r0,r0,r2
[all …]
Dstrlen.S12 or r3,r0,7
18 asl_s r1,r0,3
19 btst_s r0,2
32 btst_s r0,2
34 sub3 r7,r1,r0
65 sub_s r0,r0,3
67 sub r0,r3,r0
69 sub r0,r0,r1
75 sub r0,r3,r0
78 add r0,r0,r1
/linux-4.1.27/arch/arm/mach-omap2/
Dsleep44xx.S63 cmp r0, #0x0
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
74 mov r0, #SCU_PM_NORMAL
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
109 mov r8, r0
113 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
114 ands r0, r0, #0x0f
115 ldreq r0, [r8, #SCU_OFFSET0]
[all …]
Domap-headsmp.S36 ldr r0, [r2]
37 mov r0, r0, lsr #5
40 cmp r0, r4
52 ldr r0, [r2]
53 mov r0, r0, lsr #5
56 cmp r0, r4
59 adr r0, hyp_boot
75 mov r0, r0, lsr #9
78 cmp r0, r4
92 mov r0, r0, lsr #9
[all …]
/linux-4.1.27/arch/powerpc/kernel/
Dcpu_setup_ppc970.S21 mfmsr r0
22 rldicl. r0,r0,4,63
29 li r0,0
31 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
32 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
38 rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
45 mfspr r0,SPRN_HID1
48 or r0,r0,r3
49 mtspr SPRN_HID1,r0
50 mtspr SPRN_HID1,r0
[all …]
Dreloc_32.S36 mflr r0 /* Save our LR */
39 mtlr r0
137 lwz r0, 8(r9) /* r_addend */
138 add r0, r0, r3 /* final addend */
139 stwx r0, r4, r7 /* memory[r4+r7]) = (u32)r0 */
147 lwz r0, 8(r9) /* r_addend */
148 add r0, r0, r3
149 add r0, r0, r5 /* r0 = (S+A+Offset) */
150 extrwi r0, r0, 16, 0 /* r0 = (r0 >> 16) */
158 lwz r0, 8(r9) /* r_addend */
[all …]
Dentry_32.S48 mfspr r0,SPRN_DSRR0
49 stw r0,_DSRR0(r11)
50 mfspr r0,SPRN_DSRR1
51 stw r0,_DSRR1(r11)
56 mfspr r0,SPRN_CSRR0
57 stw r0,_CSRR0(r11)
58 mfspr r0,SPRN_CSRR1
59 stw r0,_CSRR1(r11)
65 mfspr r0,SPRN_MAS0
66 stw r0,MAS0(r11)
[all …]
Dcpu_setup_pa6t.S32 mfmsr r0
33 rldicl. r0,r0,4,63
36 mfspr r0,SPRN_HID5
37 ori r0,r0,0x38
38 mtspr SPRN_HID5,r0
40 mfspr r0,SPRN_LPCR
41 ori r0,r0,0x7000
42 mtspr SPRN_LPCR,r0
Dentry_64.S62 std r0,GPR0(r1)
148 cmpldi 0,r0,NR_syscalls
167 slwi r0,r0,4
168 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
204 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
212 stdcx. r0,0,r1 /* to clear the reservation */
246 mr r0,r3
269 andi. r0,r9,_TIF_RESTOREALL
275 andi. r0,r9,_TIF_NOERROR
282 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
[all …]
Dswsusp_asm64.S57 mfspr r0, SPRN_##register ;\
58 std r0, SL_##register(r11)
60 ld r0, SL_##register(r11) ;\
61 mtspr SPRN_##register, r0
63 mf##special r0 ;\
64 std r0, SL_##special(r11)
66 ld r0, SL_##special(r11) ;\
67 mt##special r0
162 ldx r0,r10,r13
163 stdx r0,r10,r14
[all …]
Didle_power4.S35 rldicl r0,r7,48,1
36 rotldi r0,r0,16
37 mtmsrd r0,1
40 lbz r0,PACAIRQHAPPENED(r13)
41 cmpwi cr0,r0,0
46 mflr r0
47 std r0,16(r1)
51 ld r0,16(r1)
52 mtlr r0
56 li r0,1
[all …]
Dmisc_64.S33 mflr r0
34 std r0,16(r1)
39 ld r0,16(r1)
40 mtlr r0
44 mflr r0
45 std r0,16(r1)
50 ld r0,16(r1)
51 mtlr r0
163 ori r0,r5,MSR_DR
164 xori r0,r0,MSR_DR
[all …]
Dhead_32.S205 mfmsr r0
206 ori r0,r0,MSR_DR|MSR_IR
207 mtspr SPRN_SRR1,r0
208 lis r0,start_here@h
209 ori r0,r0,start_here@l
210 mtspr SPRN_SRR0,r0
286 stw r0,GPR0(r11); \
391 andis. r0,r10,0xa470 /* weird error? */
406 andis. r0,r9,0x4000 /* no pte found? */
514 lwz r0,0(r2) /* get linux-style pte */
[all …]
Dppc_save_regs.S27 PPC_STL r0,0*SZL(r3)
62 PPC_LL r0,LRSAVE(r4)
63 PPC_STL r0,_NIP-STACK_FRAME_OVERHEAD(r3)
64 PPC_STL r0,_LINK-STACK_FRAME_OVERHEAD(r3)
65 mfmsr r0
66 PPC_STL r0,_MSR-STACK_FRAME_OVERHEAD(r3)
67 mfctr r0
68 PPC_STL r0,_CTR-STACK_FRAME_OVERHEAD(r3)
69 mfxer r0
70 PPC_STL r0,_XER-STACK_FRAME_OVERHEAD(r3)
[all …]
Didle_power7.S44 std r0,0(r1); \
46 ld r0,0(r1); \
47 1: cmp cr0,r0,r0; \
86 mflr r0
87 std r0,16(r1)
89 std r0,_LINK(r1)
90 std r0,_NIP(r1)
106 lbz r0,PACAIRQHAPPENED(r13)
107 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
112 ld r0,16(r1)
[all …]
Dcpu_setup_fsl_booke.S23 mfspr r0, SPRN_L1CSR1
24 andi. r3, r0, L1CSR1_ICE
26 oris r0, r0, L1CSR1_CPE@h
27 ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
28 mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
33 mfspr r0, SPRN_L1CSR0
34 andi. r3, r0, L1CSR0_DCE
38 li r0, 0
39 mtspr SPRN_L1CSR0, r0 /* Disable */
42 li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
[all …]
Dtm.S52 and. r0, r4, r3
59 mfspr r0, SPRN_TFHAR
60 std r0, THREAD_TM_TFHAR(r3)
61 mfspr r0, SPRN_TEXASR
62 std r0, THREAD_TM_TEXASR(r3)
63 mfspr r0, SPRN_TFIAR
64 std r0, THREAD_TM_TFIAR(r3)
68 ld r0, THREAD_TM_TFHAR(r3)
69 mtspr SPRN_TFHAR, r0
70 ld r0, THREAD_TM_TEXASR(r3)
[all …]
/linux-4.1.27/arch/arm/mach-tegra/
Dsleep-tegra30.S144 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
198 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
214 ldr r0, [r2]
262 add r3, r3, r0
264 mov32 r0, tegra30_tear_down_core
266 sub r0, r0, r1
268 add r0, r0, r1
282 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
286 mov r0, #0 @ power mode flags (!hotplug)
288 mov r0, #1 @ never return here
[all …]
Dsleep.S49 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
59 cmp r0, #TEGRA_FLUSH_CACHE_ALL
66 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
77 mrc p15, 0, r0, c0, c0, 5
78 ubfx r0, r0, #8, #4
79 tst r0, #1 @ only need for cluster 0
82 mrc p15, 0x1, r0, c9, c0, 2
83 and r0, r0, #7
84 cmp r0, #2
85 bicne r0, r0, #7
[all …]
Dsleep-tegra20.S79 cpu_id r0
98 cmp r0, #0
105 cpu_to_halt_reg r1, r0
113 mov r1, r1, lsl r0
119 cmp r3, r0
149 cpu_id r0
151 cmp r0, #0
165 cmpeq r12, r0 @ !turn == cpu?
174 cpu_id r0
175 cmp r0, #0
[all …]
Dreset-handler.S49 cpu_id r0
50 cmp r0, #0 @ CPU0?
59 cpu_to_csr_reg r1, r0
65 movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
67 bic r1, r1, r0
76 mov32 r0, TEGRA_ARM_PERIF_BASE
77 ldr r1, [r0]
79 str r1, [r0]
130 mrc p15, 0, r0, c1, c0, 0 @ read system control register
131 orr r0, r0, #1 << 14 @ erratum 716044
[all …]
/linux-4.1.27/arch/microblaze/kernel/
Dhead.S66 mts rmsr, r0
68 mts rslr, r0
69 addi r8, r0, 0xFFFFFFFF
90 lbui r11, r0, TOPHYS(endian_check)
92 lw r11, r0, r7 /* Big endian load in delay slot */
93 lwr r11, r0, r7 /* Little endian load */
97 or r7, r0, r0 /* clear R7 when not valid DTB */
100 or r11, r0, r0 /* incremment */
101 ori r4, r0, TOPHYS(_fdt_start)
102 ori r3, r0, (0x8000 - 4)
[all …]
Dentry.S54 msrclr r0, MSR_BIP
58 msrset r0, MSR_BIP
62 msrclr r0, MSR_EIP
66 msrset r0, MSR_EE
70 msrclr r0, MSR_IE
74 msrset r0, MSR_IE
78 msrset r0, MSR_UMS
79 msrclr r0, MSR_VMS
83 msrclr r0, MSR_UMS
84 msrset r0, MSR_VMS
[all …]
Dentry-nommu.S23 msrclr r0, MSR_IE
27 msrset r0, MSR_IE
31 msrclr r0, MSR_BIP
54 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
55 swi r11, r0, PER_CPU(R11_SAVE) /* temporarily save r11 */
56 lwi r11, r0, PER_CPU(KM) /* load mode indicator */
62 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
68 lwi r11, r0, PER_CPU(R11_SAVE) /* reload r11 */
110 lwi r11, r0, PER_CPU(ENTRY_SP)
113 addik r11, r0, 1
[all …]
/linux-4.1.27/arch/powerpc/mm/
Dhash_low_32.S56 lis r0,0x0fff
64 stwcx. r0,0,r8
69 lis r0,KERNELBASE@h /* check if kernel address */
70 cmplw 0,r4,r0
102 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
103 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
125 or r5,r0,r6 /* set accessed/dirty bits */
139 mfctr r0
140 stw r0,_CTR(r11)
146 li r0,0
[all …]
Dhash_low_64.S56 mflr r0
57 std r0,16(r1)
85 andc. r0,r4,r31
88 andi. r0,r31,_PAGE_BUSY
124 rldicl r0,r3,64-12,48
125 xor r28,r5,r0 /* hash */
140 rldicl r0,r3,64-12,36
142 xor r28,r28,r0 /* hash */
147 rlwinm r0,r30,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
149 and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
[all …]
/linux-4.1.27/arch/unicore32/kernel/
Dhead.S63 mov r0, #PRIV_MODE @ ensure priv mode
64 or r0, #PSR_R_BIT | PSR_I_BIT @ disable irqs
65 mov.a asr, r0
68 movc r0, p0.c0, #0 @ cpuid
71 and r0, r1, r0
72 cxor.a r0, r2
78 movl r0, #KERNEL_PGD_PADDR @ page table address
80 add r2, r0, #0x1000
81 101: stw.w r1, [r0]+, #4
82 stw.w r1, [r0]+, #4
[all …]
Dentry.S66 ldm.w (r0 - r15), [sp]+
67 ldm.b (r16 - pc), [sp]+ @ load r0 - pc, asr
75 add sp, sp, #\offset + S_R1 @ r0 is syscall return value
79 ldm.w (r0 - r15), [sp]+ @ get calling r0 - r15
107 stm (r0-r3), [\temp]+
109 mov r0, \reg
111 mov r0, #':'
113 mov r0, pc
115 adr r0, 902f
118 ldm (r0-r3), [\temp]+
[all …]
/linux-4.1.27/arch/powerpc/platforms/ps3/
Dhvcall.S30 mflr r0; \
31 std r0, 16(r1); \
36 ld r0, 16(r1); \
37 mtlr r0; \
52 mflr r0; \
53 std r0, 16(r1); \
64 ld r0, 16(r1); \
65 mtlr r0; \
71 mflr r0; \
72 std r0, 16(r1); \
[all …]
/linux-4.1.27/arch/unicore32/mm/
Dtlb-ucv2.S30 mov r0, r0 >> #PAGE_SHIFT @ align address
31 mov r0, r0 << #PAGE_SHIFT
34 movc p0.c6, r0, #3
40 movc p0.c6, r0, #5
43 add r0, r0, #PAGE_SZ
44 csub.a r0, r1
47 movc p0.c6, r0, #2
53 movc p0.c6, r0, #4
69 mov r0, r0 >> #PAGE_SHIFT @ align address
70 mov r0, r0 << #PAGE_SHIFT
[all …]
Dcache-ucv2.S33 mov r0, #0
34 movc p0.c5, r0, #14 @ Dcache flush all
37 mov r0, #0
38 movc p0.c5, r0, #20 @ Icache invalidate all
57 andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
58 sub r1, r1, r0
65 101: dcacheline_flush r0, r11, r12
67 add r0, r0, #CACHE_LINESIZE
97 andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
98 sub r1, r1, r0
[all …]
/linux-4.1.27/arch/cris/arch-v32/kernel/
Dkgdb_asm.S326 move.d [$acr], $r0
327 move $r0, $s0
329 move.d [$acr], $r0
330 move $r0, $s1
332 move.d [$acr], $r0
333 move $r0, $s2
335 move.d [$acr], $r0
336 move $r0, $s3
338 move.d [$acr], $r0
339 move $r0, $s4
[all …]
/linux-4.1.27/arch/powerpc/boot/
Dstring.S19 1: lbzu r0,1(r4)
20 cmpwi 0,r0,0
21 stbu r0,1(r5)
32 1: lbzu r0,1(r4)
33 cmpwi 0,r0,0
34 stbu r0,1(r6)
42 1: lbzu r0,1(r5)
43 cmpwi 0,r0,0
46 1: lbzu r0,1(r4)
47 cmpwi 0,r0,0
[all …]
Dcrt0.S74 li r0,0
85 lwz r0,4(r12) /* get RELACOUNT value in r0 */
95 cmpwi r0,0
101 mtctr r0
102 2: lbz r0,4+3(r9) /* ELF32_R_INFO(reloc->r_info) */
103 cmpwi r0,22 /* R_PPC_RELATIVE */
106 lwz r0,8(r9) /* reloc->r_addend */
107 add r0,r0,r11
108 stwx r0,r11,r12
115 4: dcbf r0,r9
[all …]
/linux-4.1.27/arch/m32r/mm/
Dpage.S27 ld r3, @r0 /* cache line allocate */
34 st r4, @r0
35 st r5, @+r0
36 st r6, @+r0
37 st r7, @+r0
39 addi r0, #4
43 ld r3, @r0 /* cache line allocate */
47 st r4, @r0
48 st r5, @+r0
49 st r6, @+r0
[all …]
Dmmu.S30 st r0, @-sp
37 ld r0, @(MDEVP_offset, r3) ; r0: PFN + ASID (MDEVP reg.)
44 ;; r0: PFN + ASID (MDEVP reg.)
47 ;; r0: PFN + ASID
73 ;; r0: MDEVP reg. (included ASID)
76 ;; r0: PFN + ASID
81 and3 r0, r0, #(MMU_CONTEXT_ASID_MASK)
84 or r0, r1 ; r0: PFN + ASID
104 ;; r0: PFN + ASID
109 ;; r0: PFN + ASID
[all …]
/linux-4.1.27/arch/arm/boot/compressed/
Dhead.S75 mov r0, \val
80 mov r0, \val
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
110 mov r0, r4
129 mov r0, r0
131 ARM( mov r0, r0 )
160 mov r0, #0x17 @ angel_SWIreason_EnterSVC
164 safe_svcmode_maskall r0
212 mov r0, pc
[all …]
Dll_char_wr.S38 @ Smashable regs: {r0 - r3}, [r4 - r7], (r8 - fp), [ip], (sp), [lr], (pc)
59 add r0, r0, r5, lsl #3 @ Move to bottom of character
65 @ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
71 str r7, [r0, -r5]!
76 str r7, [r0, -r5]!
83 @ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
93 sub r0, r0, r5 @ avoid ip
94 stmia r0, {r4, ip}
103 sub r0, r0, r5 @ avoid ip
104 stmia r0, {r4, ip}
[all …]
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/
Dstartup.inc10 move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
12 move.d $r0, [$r1]
14 move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
16 move.d $r0, [$r1]
18 move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
20 move.d $r0, [$r1]
22 move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
24 move.d $r0, [$r1]
26 move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
28 move.d $r0, [$r1]
[all …]
/linux-4.1.27/arch/sh/kernel/vsyscall/
Dvsyscall-sigreturn.S11 or r0, r0
12 or r0, r0
13 or r0, r0
14 or r0, r0
15 or r0, r0
28 or r0, r0
29 or r0, r0
30 or r0, r0
31 or r0, r0
32 or r0, r0
/linux-4.1.27/arch/cris/arch-v10/kernel/
Dhead.S148 move.d $pc,$r0
149 and.d 0x7fffffff,$r0 ; get rid of the non-cache bit
150 cmp.d 0x10000,$r0 ; arbitrary... just something above this code
166 move.d START_ETHERNET_CLOCK, $r0
167 move.d $r0, [R_NETWORK_GEN_CONFIG]
171 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
172 move.d $r0, [R_WAITSTATES]
174 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
175 move.d $r0, [R_BUS_CONFIG]
198 moveq 0, $r0 ; source
[all …]
/linux-4.1.27/arch/sh/kernel/cpu/sh2/
Dentry.S40 ! r0 <- point sp
44 ! r0 = temporary
50 mov.l @r2,r0
52 or r0,r3 ! set MD
53 tst r0,r0
57 mov.l __md_bit,r0
58 mov.l r0,@r2 ! enter kernel mode
61 mov #(THREAD_SIZE >> 8),r0
62 shll8 r0
63 add r2,r0
[all …]
/linux-4.1.27/arch/powerpc/platforms/powermac/
Dcache.S47 rlwinm r0,r11,0,~MSR_EE
48 rlwinm r0,r0,0,~MSR_DR
50 mtmsr r0
82 1: lwz r0,0(r4)
124 1: lwz r0,0(r4)
161 rlwinm. r0,r3,0,31,31
171 mfspr r0,SPRN_HID0
172 rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
173 mtspr SPRN_HID0,r0
179 mfspr r0,SPRN_HID0
[all …]
/linux-4.1.27/arch/unicore32/boot/compressed/
Dhead.S25 mov r0, #0xD3
26 mov.a asr, r0
28 adr r0, LC0
29 ldm (r1, r2, r3, r5, r6, r7, r8), [r0]+
30 ldw sp, [r0+], #28
31 sub.a r0, r0, r1 @ calculate the delta offset
46 add r5, r5, r0
47 add r7, r7, r0
48 add r8, r8, r0
56 add r2, r2, r0
[all …]
/linux-4.1.27/arch/s390/kernel/vdso32/
Dclock_gettime.S39 lm %r0,%r1,1(%r15)
40 s %r0,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
43 ahi %r0,-1
44 2: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */
45 lr %r2,%r0
46 l %r0,__VDSO_TK_MULT(%r5)
48 mr %r0,%r0
50 a %r0,__VDSO_TK_MULT(%r5)
51 3: alr %r0,%r2
52 al %r0,__VDSO_WTOM_NSEC(%r5)
[all …]
Dgettimeofday.S34 lm %r0,%r1,1(%r15)
35 s %r0,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
38 ahi %r0,-1
39 3: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */
40 st %r0,0(%r15)
41 l %r0,__VDSO_TK_MULT(%r5)
43 mr %r0,%r0
45 a %r0,__VDSO_TK_MULT(%r5)
46 4: al %r0,0(%r15)
47 al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */
[all …]
/linux-4.1.27/arch/arm/common/
Dmcpm_head.S33 1901: adr r0, 1902b
35 mov r0, r9
37 adr r0, 1903b
39 mov r0, r10
41 adr r0, 1904b
56 mrc p15, 0, r0, c0, c0, 5 @ MPIDR
57 ubfx r9, r0, #0, #8 @ r9 = cpu
58 ubfx r10, r0, #8, #8 @ r10 = cluster
76 ldmia r5, {r0, r6, r7, r8, r11}
77 add r0, r5, r0 @ r0 = mcpm_entry_early_pokes
[all …]
/linux-4.1.27/arch/sh/boot/compressed/
Dhead_32.S19 mova 1f, r0
21 cmp/eq r2, r0
23 sub r0, r2
24 mov.l bss_start_addr, r0
26 and r1, r0 ! align cache line
28 mov r0, r1
39 mov.l r4, @r0
40 mov.l r5, @(4,r0)
41 mov.l r6, @(8,r0)
42 mov.l r7, @(12,r0)
[all …]
/linux-4.1.27/tools/perf/arch/arm/tests/
Dregs_load.S40 str r0, [r0, #R0]
41 str r1, [r0, #R1]
42 str r2, [r0, #R2]
43 str r3, [r0, #R3]
44 str r4, [r0, #R4]
45 str r5, [r0, #R5]
46 str r6, [r0, #R6]
47 str r7, [r0, #R7]
48 str r8, [r0, #R8]
49 str r9, [r0, #R9]
[all …]
/linux-4.1.27/arch/sh/kernel/
Dhead_32.S62 mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
63 ldc r0, sr
66 mov #0, r0
67 ldc r0, r6_bank
77 PREFI(5f, r0)
78 PREFI(6f, r0)
81 mov.l 2f, r0
82 mov r0, r15 ! Set initial r15 (stack pointer)
84 mov.l 7f, r0
85 ldc r0, r7_bank ! ... and initial thread_info
[all …]
Dentry-common.S61 mov.l 1f, r0
62 jmp @r0
84 mov #OFF_SR, r0
85 mov.l @(r0,r15), r0 ! get status register
86 shll r0
87 shll r0 ! kernel space?
88 get_current_thread_info r8, r0
209 mov #-ENOSYS, r0
211 mov.l r0, @(OFF_R0,r15) ! Return value
214 mov #OFF_SR, r0
[all …]
/linux-4.1.27/arch/parisc/kernel/
Dhpmc.S134 ldo 8(%r0),%r4 /* PSW Q on, PSW M off */
136 mtctl %r0,pcsq
137 mtctl %r0,pcsq
155 ldo PDC_PIM(%r0), arg0
156 ldo PDC_PIM_HPMC(%r0),arg1 /* Transfer HPMC data */
171 ldo PDC_IO(%r0),arg0
172 ldo 0(%r0),arg1 /* log IO errors */
173 ldo 0(%r0),arg2 /* reserved */
174 ldo 0(%r0),arg3 /* reserved */
175 stw %r0,-52(sp) /* reserved */
[all …]
Dhead.S49 mtsp %r0,%sr4
50 mtsp %r0,%sr5
51 mtsp %r0,%sr6
52 mtsp %r0,%sr7
63 stw,ma %r0,4(%r3)
109 ldo 0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */
120 copy %r0,%r2
139 stw %r10,0x10(%r0) /* MEM_RENDEZ */
140 stw %r0,0x28(%r0) /* MEM_RENDEZ_HI - assume addr < 4GB */
165 stw %r0,0x10(%r0) /* MEM_RENDEZ */
[all …]
Dsyscall.S80 gate lws_start, %r0 /* increase privilege */
91 gate .+8, %r0 /* increase privilege */
105 gate .+8, %r0 /* become privileged */
106 mtsp %r0,%sr4 /* get kernel space into sr4 */
107 mtsp %r0,%sr5 /* get kernel space into sr5 */
108 mtsp %r0,%sr6 /* get kernel space into sr6 */
149 mtsp %r0,%sr7 /* get kernel space into sr7 */
159 STREG %r0, TASK_PT_PSW(%r1)
183 STREG %r0, TASK_PT_ORIG_R28(%r1) /* don't prohibit restarts */
209 and,COND(=) %r1, %r19, %r0
[all …]
Dpacache.S65 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
66 mtctl %r0, %cr17 /* Clear IIASQ tail */
67 mtctl %r0, %cr17 /* Clear IIASQ head */
168 rsm PSW_SM_I, %r0
176 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
177 mtctl %r0, %cr17 /* Clear IIASQ tail */
178 mtctl %r0, %cr17 /* Clear IIASQ head */
188 2: bv %r0(%r2)
211 mtsp %r0, %sr1
217 fice %r0(%sr1, %arg0)
[all …]
Dentry.S65 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
66 mtsp %r0, %sr4
67 mtsp %r0, %sr5
68 mtsp %r0, %sr6
72 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
73 mtctl %r0, %cr17 /* Clear IIASQ tail */
74 mtctl %r0, %cr17 /* Clear IIASQ head */
121 mtsp %r0,%sr7
356 depd %r0,63,SPACEID_SHIFT,\spc
369 or,COND(=) %r0,\spc,%r0
[all …]
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
Dentry.S40 ! r0 <- point sp
44 ! r0 = temporary
56 mov #(THREAD_SIZE >> 8),r0
57 shll8 r0
58 add r2,r0 ! r0 = kernel stack tail
60 mov r0,r15 ! switch kernel stack
65 mov.l @(4*4,r2),r0
66 mov.l r0,@-r15 ! original SR
68 mov.l @(3*4,r2),r0
69 mov.l r0,@-r15 ! original PC
[all …]
/linux-4.1.27/arch/arm/kernel/
Dhead-nommu.S147 orr r0, r0, #CR_A
149 bic r0, r0, #CR_A
152 bic r0, r0, #CR_C
155 bic r0, r0, #CR_Z
158 bic r0, r0, #CR_I
161 orr r0, r0, #CR_V
163 bic r0, r0, #CR_V
165 mcr p15, 0, r0, c1, c0, 0 @ write control reg
200 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
201 and r0, r0, #(MMFR0_PMSA) @ PMSA field
[all …]
Dhead.S169 mov r0, r4
171 add r6, r0, #PG_DIR_SIZE
172 1: str r3, [r0], #4
173 str r3, [r0], #4
174 str r3, [r0], #4
175 str r3, [r0], #4
176 teq r0, r6
184 mov r0, r4
191 str r7, [r0], #4 @ set top PGD entry bits
192 str r3, [r0], #4 @ set bottom PGD entry bits
[all …]
Dfiqasm.S29 mov r0, r0 @ avoid hazard prior to ARMv4
30 ldmia r0!, {r8 - r12}
31 ldr sp, [r0], #4
32 ldr lr, [r0]
34 mov r0, r0 @ avoid hazard prior to ARMv4
42 mov r0, r0 @ avoid hazard prior to ARMv4
43 stmia r0!, {r8 - r12}
44 str sp, [r0], #4
45 str lr, [r0]
47 mov r0, r0 @ avoid hazard prior to ARMv4
Dsleep.S72 stmfd sp!, {r0, r1} @ save suspend func arg and pointer
74 ALT_SMP(ldr r0, =mpidr_hash)
77 ldmia r0, {r1, r6-r8} @ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts
78 compute_mpidr_hash r0, r6, r7, r8, r2, r1
79 add r3, r3, r0, lsl #2
82 add r0, sp, #8 @ pointer to save block
85 ldmfd sp!, {r0, pc} @ call suspend fn
91 teq r0, #0
92 moveq r0, #1 @ force non-zero value
105 mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
[all …]
Dentry-ftrace.S67 ldr r0, =ftrace_trace_function
68 ldr r2, [r0]
69 adr r0, .Lftrace_stub
70 cmp r0, r2
76 cmp r0, r2
81 ldr r0, =ftrace_graph_entry_stub
82 cmp r0, r2
89 mcount_adjust_addr r0, lr @ instrumented function
99 mcount_adjust_addr r0, lr @ instrumented function
108 mov r0, r0
[all …]
Diwmmxt.S89 add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
92 str r0, [r3] @ this task now owns Concan regs
147 2: teq r0, #0 @ anything to load?
153 wldrd wR0, [r0, #MMX_WR0]
154 wldrd wR1, [r0, #MMX_WR1]
155 wldrd wR2, [r0, #MMX_WR2]
156 wldrd wR3, [r0, #MMX_WR3]
157 wldrd wR4, [r0, #MMX_WR4]
158 wldrd wR5, [r0, #MMX_WR5]
159 wldrd wR6, [r0, #MMX_WR6]
[all …]
Dentry-armv.S42 mov r0, sp
71 @ The abort handler must return the aborted address in r0, and
95 THUMB( stmia sp, {r0 - r12} )
129 ldmia r0, {r4 - r6}
130 add r0, sp, #S_PC @ here for interlock avoidance
132 str r4, [sp] @ save preserved r0
133 stmia r0, {r5 - r7} @ lr_<exception>,
136 mov r0, sp
152 UNWIND(.save {r0 - pc} )
155 SPFIX( str r0, [sp] ) @ temporarily saved
[all …]
Dentry-v7m.S26 adr r0, strerr
31 mov r0, sp
45 mrs r0, ipsr
47 and r0, r1
48 sub r0, #16
51 @ routine called with r0 = irq number, r1 = struct pt_regs *
59 ldr r0, [r1, V7M_SCB_ICSR]
60 tst r0, V7M_SCB_ICSR_RETTOBASE
67 mov r0, #V7M_SCB_ICSR_PENDSVSET
68 str r0, [r1, V7M_SCB_ICSR] @ raise PendSV
[all …]
Ddebug.S62 1: and r1, r0, #15
63 mov r0, r0, lsr #4
70 mov r0, r2
89 2: teq r0, #0
90 ldrneb r1, [r0], #1
98 mov r1, r0
99 mov r0, #0
106 str r2, [r0]
115 mov r1, r0
116 mov r0, #0x04 @ SYS_WRITE0
[all …]
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/
Dstartup.inc18 move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
20 move.d $r0, [$r1]
22 move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
24 move.d $r0, [$r1]
26 move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
28 move.d $r0, [$r1]
30 move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
32 move.d $r0, [$r1]
34 move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
36 move.d $r0, [$r1]
[all …]
/linux-4.1.27/arch/arm/crypto/
Dsha256-core.S_shipped103 stmdb sp!,{r0,r1,r2,r4-r11,lr}
104 ldmia r0,{r4,r5,r6,r7,r8,r9,r10,r11}
120 eor r0,r8,r8,ror#5
122 eor r0,r0,r8,ror#19 @ Sigma1(e)
130 ldrb r0,[r1,#1]
133 orr r2,r2,r0,lsl#16
137 eor r0,r8,r8,ror#5
139 eor r0,r0,r8,ror#19 @ Sigma1(e)
145 add r11,r11,r0,ror#6 @ h+=Sigma1(e)
149 eor r0,r4,r4,ror#11
[all …]
Daes-armv4.S154 mov r12,r0 @ inp
158 ldrb r0,[r12,#3] @ load input data in endian-neutral
162 orr r0,r0,r4,lsl#8
164 orr r0,r0,r5,lsl#16
166 orr r0,r0,r6,lsl#24
187 ldr r0,[r12,#0]
192 rev r0,r0
203 rev r0,r0
208 str r0,[r12,#0]
213 mov r4,r0,lsr#24 @ write output in endian-neutral
[all …]
/linux-4.1.27/arch/m32r/boot/
Dsetup.S66 ldi r0, #-2 ;LDIMM (r0, M32R_MCCR)
69 sth r1, @r0
72 ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
75 st r1, @r0
77 ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
80 st r1, @r0
82 ldi r0, #-96 ; DNCR0
85 st r1, @r0
88 st r1, @+r0
91 st r1, @+r0
[all …]
/linux-4.1.27/tools/testing/selftests/powerpc/copyloops/
Dmemcpy_power7.S55 lbz r0,0(r4)
57 stb r0,0(r3)
61 lhz r0,0(r4)
63 sth r0,0(r3)
67 lwz r0,0(r4)
69 stw r0,0(r3)
76 mflr r0
87 std r0,STACKFRAMESIZE+16(r1)
95 ld r0,0(r4)
112 std r0,0(r3)
[all …]
Dcopyuser_power7.S70 ld r0,STACKFRAMESIZE+16(r1)
71 mtlr r0
122 err1; lbz r0,0(r4)
124 err1; stb r0,0(r3)
128 err1; lhz r0,0(r4)
130 err1; sth r0,0(r3)
134 err1; lwz r0,0(r4)
136 err1; stw r0,0(r3)
143 mflr r0
154 std r0,STACKFRAMESIZE+16(r1)
[all …]
Dmemcpy_64.S56 andi. r0,r4,7
97 subf r4,r0,r4
99 sldi r10,r0,3
104 add r5,r5,r0
109 ld r0,8(r4)
112 srd r7,r0,r11
113 sld r8,r0,r10
116 ld r0,8(r4)
117 # s1<< in r8, d0=(s0<<|s1>>) in r7, s3 in r0, s2 in r9, nix in r6 & r12
120 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
[all …]
/linux-4.1.27/arch/avr32/kernel/
Dentry-avr32b.S77 #define tlbmiss_save pushm r0-r3
78 #define tlbmiss_restore popm r0-r3
98 mfsr r0, SYSREG_TLBEAR
107 lsr r2, r0, PGDIR_SHIFT
109 bfextu r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
115 mfsr r0, SYSREG_TLBARLO
129 clz r2, r0
146 bld r0, 31
152 stmts --sp, r0-lr
196 stmts --sp, r0-lr
[all …]
/linux-4.1.27/arch/powerpc/platforms/pseries/
DhvCall.S36 mflr r0; \
45 std r0,16(r1); \
63 ld r0,STACK_FRAME_OVERHEAD+STK_PARAM(R3)(r1); \
66 mr r3,r0; \
68 ld r0,STACK_FRAME_OVERHEAD+16(r1); \
71 mtlr r0
111 mfcr r0
112 stw r0,8(r1)
116 lwz r0,8(r1)
117 mtcrf 0xff,r0
[all …]
/linux-4.1.27/arch/openrisc/kernel/
Dhead.S37 l.or gpr,r0,r0
54 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
57 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
60 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
63 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
66 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
[all …]
/linux-4.1.27/arch/arm/mach-mvebu/
Dcoherency_ll.S94 mov r0, lr
98 reteq r0
100 mov lr, r0
101 add r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
103 ldrex r2, [r0]
105 strex r1, r2, [r0]
119 mov r0, lr
123 reteq r0
125 mov lr, r0
126 add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
[all …]
Dpmsu_ll.S19 mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
20 and r0, r0, #15
21 add r1, r1, r0
22 mov r0, #0x0
23 strb r0, [r1] @ switch SCU power state to Normal mode
61 adr r0, 1f
62 ldr r0, [r0] @ load the address of the
64 ldr r0, [r0] @ load the value in the
66 ARM_BE8(rev r0, r0) @ the value is stored LE
67 mov pc, r0 @ jump to this value
/linux-4.1.27/arch/blackfin/mach-bf561/
Datomic.S42 r1 = r0 & r1;
43 cli r0;
67 cli r0;
98 sti r0;
107 [--sp] = r0;
137 r0 = [sp++]; define
146 [--sp] = r0;
186 r0 = [sp++]; define
202 r7 = r0;
279 p1 = r0;
[all …]
/linux-4.1.27/arch/s390/kernel/
Drelocate_kernel.S32 stmg %r0,%r15,gprregs-.base(%r13)
33 lghi %r0,3
34 sllg %r0,%r0,31
35 stg %r0,0x1d0(%r0)
36 la %r0,.back_pgm-.base(%r13)
37 stg %r0,0x1d8(%r0)
39 mvc 0(8,%r0),0(%r1)
40 la %r0,.back-.base(%r13)
41 st %r0,4(%r0)
42 oi 4(%r0),0x80
[all …]
/linux-4.1.27/arch/sh/lib64/
Dstrcpy.S28 addi r2, 8, r0
34 sub r2, r23, r0
37 ldx.q r0, r21, r5
54 addi r0, 8, r0
61 sthi.q r0, -1, r4
65 addi r0, 8, r0
72 st.b r0,-8,r4
75 addi r0,1,r0
81 stlo.q r0, 0, r5
82 ldx.q r0, r20, r4
[all …]
Dmemcpy.S15 ! any other registers in the range r0-r7: trashed
53 movi 25,r0
54 bgeu/u r4,r0,tr0
55 nsb r4,r0
56 shlli r0,5,r0
58 sub r1, r0, r0
59 L0: ptrel r0,tr0
68 stlo.l r2, 0, r0
88 ld.b r3,0,r0
89 st.b r2,0,r0
[all …]
Dcopy_user_memcpy.S13 ! any other registers in the range r0-r7: trashed
68 movi 25,r0
69 bgeu/u r4,r0,tr0
70 nsb r4,r0
71 shlli r0,5,r0
73 sub r1, r0, r0
74 L0: ptrel r0,tr0
83 stlo.l r2, 0, r0
103 ld.b r3,0,r0
104 st.b r2,0,r0
[all …]
/linux-4.1.27/arch/blackfin/include/asm/
Dcontext.S60 [--sp] = r0; /* Skip reserved */
62 r0 = RETI; define
63 [--sp] = r0;
68 [--sp] = r0; /* Skip IPEND as well. */
71 r0 = 0x3f; define
72 sti r0;
74 cli r0;
83 r0 = 0 (x); define
84 l0 = r0;
85 l1 = r0;
[all …]
/linux-4.1.27/sound/oss/
Dvidc_fill.S21 1: cmp r0, r1
23 ldrb r4, [r0], #1
34 1: cmp r0, r1
36 ldr r4, [r0], #2
48 1: cmp r0, r1
50 ldrb r4, [r0], #1
60 1: cmp r0, r1
62 ldr r4, [r0], #2
75 1: cmp r0, r1
77 ldr r5, [r0], #2
[all …]
/linux-4.1.27/arch/arm/kvm/
Dinit.S71 cmp r0, #0 @ We have a SP?
79 mrc p15, 4, r0, c2, c0, 2 @ HTCR
81 bic r0, r0, r2
84 orr r0, r0, r1
85 mcr p15, 4, r0, c2, c0, 2 @ HTCR
90 bic r0, r0, #(~VTCR_HTCR_SH) @ clear non-reusable HTCR bits
91 orr r1, r0, r1
97 mrc p15, 0, r0, c10, c2, 0
98 mcr p15, 4, r0, c10, c2, 0
99 mrc p15, 0, r0, c10, c2, 1
[all …]
Dinterrupts.S53 add r0, r0, #KVM_VTTBR
54 ldrd r2, r3, [r0]
57 mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored)
87 mov r0, #0 @ rn parameter for c15 flushes is SBZ
90 mcr p15, 4, r0, c8, c3, 4
92 mcr p15, 0, r0, c7, c1, 0
212 mov r0, r1 @ Return the return code
216 mov r0, #0 @ Clear upper bits in return value
281 push {r0-r2}
282 mrrc p15, 6, r0, r1, c2 @ Read VTTBR
[all …]
/linux-4.1.27/arch/arm/mach-s3c64xx/
Dsleep.S60 ldr r0, [ r3, #S3C64XX_GPNCON ]
61 bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
63 orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
65 str r0, [ r3, #S3C64XX_GPNCON ]
67 ldr r0, [ r3, #S3C64XX_GPNDAT ]
68 bic r0, r0, #0xf << 12 @ GPN12..15
69 orr r0, r0, #1 << 15 @ GPN15
70 str r0, [ r3, #S3C64XX_GPNDAT ]
/linux-4.1.27/arch/score/kernel/
Dentry.S109 sw r0, [r28, TI_REGS]
112 mv r5, r0
117 mv r4, r0
127 sw r8, [r0, PT_EMA]
128 mv r4, r0
131 mv r4, r0
137 mv r4, r0
140 mv r4, r0
146 mv r4, r0
149 mv r4, r0
[all …]
/linux-4.1.27/arch/arm/mach-ep93xx/
Dcrunch-bits.S82 add r0, r10, #TI_CRUNCH_STATE @ get task crunch save area
85 str r0, [r3] @ this task now owns crunch
146 teq r0, #0 @ anything to load?
151 cfldr64 mvdx0, [r0, #CRUNCH_DSPSC] @ load status word
154 cfldr32 mvfx0, [r0, #CRUNCH_MVAX0L] @ load 72b accumulators
156 cfldr32 mvfx0, [r0, #CRUNCH_MVAX0M]
158 cfldr32 mvfx0, [r0, #CRUNCH_MVAX0H]
160 cfldr32 mvfx0, [r0, #CRUNCH_MVAX1L]
162 cfldr32 mvfx0, [r0, #CRUNCH_MVAX1M]
164 cfldr32 mvfx0, [r0, #CRUNCH_MVAX1H]
[all …]
/linux-4.1.27/arch/unicore32/lib/
Ddelay.S28 mul r0, r2, r0
29 ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
32 mov r0, r0 >> #14 @ max = 0x0001ffff
34 mul r0, r2, r0 @ max = 2^32-1
35 mov.a r0, r0 >> #6
46 sub.a r0, r0, #2
/linux-4.1.27/arch/hexagon/kernel/
Dhead.S58 r0 = r24; /* aka __pa(swapper_pg_dir) */ define
97 r0 = add(r0,r2) /* r0 = address of correct PTE */ define
104 memw(r0 ++ #4) = r1
112 r0 = add(r1, r24); /* advance to 0xc0000000 entry */ define
124 memw(r0 ++ #4) = r1;
127 r0 = r24; define
151 r0 = #__HVM_PDE_S_INVALID define
170 r0 = r24 define
175 r0.h = #hi(_K_provisional_vec)
176 r0.l = #lo(_K_provisional_vec)
[all …]
/linux-4.1.27/arch/cris/boot/rescue/
Dkimagerescue.S56 move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
57 move.b $r0, [R_PORT_PA_DIR]
58 move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
59 move.b $r0, [R_PORT_PA_DATA]
61 move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
62 move.b $r0, [R_PORT_PB_DIR]
63 move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
64 move.b $r0, [R_PORT_PB_DATA]
77 moveq 0, $r0
78 move.d $r0, [SERXOFF]
[all …]
/linux-4.1.27/arch/blackfin/kernel/
Dftrace-entry.S38 [--sp] = r0;
47 r0 = rets; define
49 r0 += -MCOUNT_INSN_SIZE;
65 r0 = [sp++]; define
119 [--sp] = r0;
131 r0 = rets; define
133 r0 += -MCOUNT_INSN_SIZE;
142 r0 = [sp++]; define
161 [--sp] = r0;
166 r0 = sp; /* unsigned long *parent */ define
[all …]
/linux-4.1.27/arch/sh/boards/mach-se/7724/
Dsdram.S42 mov.l @(SH_SLEEP_MODE, r5), r0
43 tst #SUSP_SH_RSTANDBY, r0
62 mov.l FRQCRA,r0
63 mov.l @r0,r3
66 mov.l r3, @r0
68 mov.l LSTATS,r0
71 mov.l @r0,r3
88 mov #100,r0
90 dt r0
105 mov #100,r0
[all …]
/linux-4.1.27/arch/powerpc/kernel/vdso32/
Dgettimeofday.S107 or r0,r6,r5
108 xor r0,r0,r0
109 add r9,r9,r0
110 lwz r0,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
111 cmpl cr0,r8,r0 /* check if updated */
141 li r0,__NR_clock_gettime
176 li r0,__NR_clock_getres
225 andi. r0,r8,1 /* pending update ? loop */
227 xor r0,r8,r8 /* create dependency */
228 add r9,r9,r0
[all …]
/linux-4.1.27/arch/powerpc/kvm/
Dbook3s_hv_rmhandlers.S48 mflr r0
49 std r0, PPC_LR_STKOFF(r1)
53 li r0,MSR_RI
54 andc r0,r10,r0
57 mtmsrd r0,1 /* clear RI in MSR */
154 li r0, MSR_RI
155 andc r6, r6, r0
184 65: lbz r0, VCORE_IN_GUEST(r5)
185 cmpwi r0, 0
194 li r0, 1
[all …]
/linux-4.1.27/arch/s390/include/asm/
Dstring.h55 register int r0 asm("0") = (char) c; in memchr()
64 : "+a" (ret), "+&a" (s) : "d" (r0) : "cc"); in memchr()
70 register int r0 asm("0") = (char) c; in memscan()
76 : "+a" (ret), "+&a" (s) : "d" (r0) : "cc"); in memscan()
82 register int r0 asm("0") = 0; in strcat()
92 : "d" (r0), "0" (0) : "cc", "memory" ); in strcat()
98 register int r0 asm("0") = 0; in strcpy()
104 : "+&a" (dst), "+&a" (src) : "d" (r0) in strcpy()
111 register unsigned long r0 asm("0") = 0; in strlen()
117 : "+d" (r0), "+a" (tmp) : : "cc"); in strlen()
[all …]
/linux-4.1.27/arch/arm/mach-davinci/
Dsleep.S53 stmfd sp!, {r0-r12, lr} @ save registers on stack
58 ldmia r0, {r0-r4}
65 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
68 str ip, [r0, #DDR2_SDRCR_OFFSET]
70 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
72 str ip, [r0, #DDR2_SDRCR_OFFSET]
79 mov r7, r0
80 mov r0, #0x2
82 mov r0, r7
159 mov r7, r0
[all …]
/linux-4.1.27/arch/powerpc/kernel/vdso64/
Dgettimeofday.S94 or r0,r6,r9
95 xor r0,r0,r0
96 add r3,r3,r0
97 ld r0,CFG_TB_UPDATE_COUNT(r3)
98 cmpld cr0,r0,r8 /* check if updated */
126 li r0,__NR_clock_gettime
161 li r0,__NR_clock_getres
208 andi. r0,r8,1 /* pending update ? loop */
210 xor r0,r8,r8 /* create dependency */
211 add r3,r3,r0
[all …]
/linux-4.1.27/arch/arm/mach-imx/
Dsuspend-imx6.S81 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
96 ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
97 ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
99 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
101 add r7, r7, r0
110 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
111 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
152 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
153 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
154 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
[all …]
/linux-4.1.27/arch/powerpc/crypto/
Dsha1-powerpc-asm.S29 andc r0,RD(t),RB(t); \
32 or r6,r6,r0; \
33 add r0,RE(t),r15; \
35 add r14,r0,W(t); \
42 andc r0,RD(t),RB(t); \
45 or r6,r6,r0; \
46 add r0,RE(t),r15; \
50 add r0,r0,W(t); \
52 add RT(t),RT(t),r0; \
60 add r0,RE(t),r15; \
[all …]

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