Lines Matching refs:r0
30 st r0, @-sp
37 ld r0, @(MDEVP_offset, r3) ; r0: PFN + ASID (MDEVP reg.)
44 ;; r0: PFN + ASID (MDEVP reg.)
47 ;; r0: PFN + ASID
73 ;; r0: MDEVP reg. (included ASID)
76 ;; r0: PFN + ASID
81 and3 r0, r0, #(MMU_CONTEXT_ASID_MASK)
84 or r0, r1 ; r0: PFN + ASID
104 ;; r0: PFN + ASID
109 ;; r0: PFN + ASID
131 ;; r0: PFN + ASID
135 ;; r0: PFN + ASID
141 srl3 r3, r0, #22
162 srl3 r3, r0, #10
177 ;; r0: PFN + ASID
181 st r0, @r1 ; set_tlb_tag(entry++, address);
189 ld r0, @sp+
196 ;; r0: PFN + ASID
200 ;; r0: PFN + ASID
214 st r0, @-sp
221 ld r0, @(MDEVA_offset,r3) ; r0: address (MDEVA reg.)
229 mv r0, r2 ; address = bpc;
257 ; r0: address, r2: entry
263 srl3 r4, r0, #22
280 srl3 r3, r0, #10
292 ; r0: address, r1: pte_data, r2: entry
296 and r3, r0
308 ld r0, @sp+
323 seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
324 or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
326 st r1, @(MPSZ_offset,r0) ; Set MPSZ Reg(Page size 4KB:0 16KB:1 64KB:2)
328 st r1, @(MASID_offset,r0) ; Set ASID Zero
331 seth r0, #high(ITLB_BASE) ; Set ITLB_BASE higher
332 or3 r0, r0, #low(ITLB_BASE) ; Set ITLB_BASE lower
337 addi r0, #-4
340 st r2, @+r0 ; VPA <- 0
341 st r2, @+r0 ; PPA <- 0