Lines Matching refs:r0
148 move.d $pc,$r0
149 and.d 0x7fffffff,$r0 ; get rid of the non-cache bit
150 cmp.d 0x10000,$r0 ; arbitrary... just something above this code
166 move.d START_ETHERNET_CLOCK, $r0
167 move.d $r0, [R_NETWORK_GEN_CONFIG]
171 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
172 move.d $r0, [R_WAITSTATES]
174 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
175 move.d $r0, [R_BUS_CONFIG]
198 moveq 0, $r0 ; source
203 1: move.w [$r0+], $r3
279 move.d __init_end, $r0; the image will be after the end of init
280 move.d [$r0], $r1 ; cramfs assumes same endian on host/target
287 move.d [$r0 + 4], $r2 ; cramfs_super.size (again, no need to swapwb)
300 add.d $r2, $r0
307 1: move.w [$r0=$r0-2],$r3
316 moveq 0, $r0
317 move.d $r0, [romfs_in_flash]
344 move.d ibr_start,$r0 ; this symbol is set by the linker script
345 move $r0,$ibr
346 move.d $r0,[etrax_irv] ; set the interrupt base register and pointer
350 move.d __bss_start, $r0
352 1: clear.d [$r0+]
353 cmp.d $r1, $r0
359 moveq 0,$r0
360 move.d $r0,[R_ATA_CTRL_DATA]
361 move.d $r0,[R_ATA_TRANSFER_CNT]
362 move.d $r0,[R_ATA_CONFIG]
365 move.d $r0, [$r1]; assert ATA bus-reset
372 move.d 0x08000000,$r0
373 move.d $r0,[$r1]
380 moveq 0,$r0
381 move.d $r0,[R_EXT_DMA_0_ADDR]
390 | IO_FIELD (R_EXT_DMA_0_CMD, trf_count, 0),$r0
391 move.d $r0,[R_EXT_DMA_0_CMD]
395 moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
396 move.b $r0,[R_DMA_CH4_CMD]
397 1: move.b [R_DMA_CH4_CMD],$r0
398 and.b IO_MASK (R_DMA_CH4_CMD, cmd),$r0
399 cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
405 moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
406 move.b $r0,[R_DMA_CH5_CMD]
407 1: move.b [R_DMA_CH5_CMD],$r0
408 and.b IO_MASK (R_DMA_CH5_CMD, cmd),$r0
409 cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
416 moveq 0,$r0
420 or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0
422 or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0
437 | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0
447 | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
451 or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0
455 or.d IO_STATE (R_GEN_CONFIG, g8_15dir, out),$r0
458 or.d IO_STATE (R_GEN_CONFIG, g16_23dir, out),$r0
462 or.d IO_STATE (R_GEN_CONFIG, g24dir, out),$r0
465 move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
467 move.d $r0,[R_GEN_CONFIG]
470 moveq 4,$r0
471 move.b $r0,[R_DMA_CH6_CMD] ; reset (ser0 dma out)
472 move.b $r0,[R_DMA_CH7_CMD] ; reset (ser0 dma in)
473 1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish
474 and.b 7,$r0
475 cmp.b 4,$r0
478 1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish
479 and.b 7,$r0
480 cmp.b 4,$r0
485 moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
486 move.b $r0,[R_DMA_CH8_CMD] ; reset (ser1 dma out)
487 move.b $r0,[R_DMA_CH9_CMD] ; reset (ser1 dma in)
488 1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish
489 andq IO_MASK (R_DMA_CH8_CMD, cmd),$r0
490 cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
493 1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish
494 andq IO_MASK (R_DMA_CH9_CMD, cmd),$r0
495 cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0
502 move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0
504 or.b IO_STATE (R_PORT_PA_DIR, dir7, output),$r0
506 move.b $r0,[port_pa_dir_shadow]
507 move.b $r0,[R_PORT_PA_DIR]
508 move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0
511 and.b ~(1 << 7),$r0
513 or.b (1 << 7),$r0
516 move.b $r0,[port_pa_data_shadow]
517 move.b $r0,[R_PORT_PA_DATA]
519 move.b CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG,$r0
520 move.b $r0,[port_pb_config_shadow]
521 move.b $r0,[R_PORT_PB_CONFIG]
522 move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0
524 or.b IO_STATE (R_PORT_PB_DIR, dir5, output),$r0
526 move.b $r0,[port_pb_dir_shadow]
527 move.b $r0,[R_PORT_PB_DIR]
528 move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0
531 and.b ~(1 << 5),$r0
533 or.b (1 << 5),$r0
536 move.b $r0,[port_pb_data_shadow]
537 move.b $r0,[R_PORT_PB_DATA]
539 moveq 0, $r0
540 move.d $r0,[port_pb_i2c_shadow]
541 move.d $r0, [R_PORT_PB_I2C]
543 moveq 0,$r0
546 and.d ~(1 << 10),$r0
548 or.d (1 << 10),$r0
553 and.d ~(1 << 11),$r0
555 or.d (1 << 11),$r0
558 move.d $r0,[port_g_data_shadow]
559 move.d $r0,[R_PORT_G_DATA]
565 | IO_FIELD (R_SERIAL0_XOFF, xoff_char, 0),$r0
566 move.d $r0,[R_SERIAL0_XOFF]
570 | IO_STATE (R_SERIAL0_BAUD, rec_baud, c115k2Hz),$r0
571 move.b $r0,[R_SERIAL0_BAUD]
581 | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0
582 move.b $r0,[R_SERIAL0_REC_CTRL]
592 | IO_STATE (R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit),$r0
593 move.b $r0,[R_SERIAL0_TR_CTRL]
599 | IO_FIELD (R_SERIAL1_XOFF, xoff_char, 0),$r0
600 move.d $r0,[R_SERIAL1_XOFF]
604 | IO_STATE (R_SERIAL1_BAUD, rec_baud, c115k2Hz),$r0
605 move.b $r0,[R_SERIAL1_BAUD]
615 | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0
616 move.b $r0,[R_SERIAL1_REC_CTRL]
626 | IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0
627 move.b $r0,[R_SERIAL1_TR_CTRL]
634 | IO_FIELD (R_SERIAL2_XOFF, xoff_char, 0),$r0
635 move.d $r0,[R_SERIAL2_XOFF]
639 | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0
640 move.b $r0,[R_SERIAL2_BAUD]
650 | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0
651 move.b $r0,[R_SERIAL2_REC_CTRL]
661 | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0
662 move.b $r0,[R_SERIAL2_TR_CTRL]
670 | IO_FIELD (R_SERIAL3_XOFF, xoff_char, 0),$r0
671 move.d $r0,[R_SERIAL3_XOFF]
675 | IO_STATE (R_SERIAL3_BAUD, rec_baud, c115k2Hz),$r0
676 move.b $r0,[R_SERIAL3_BAUD]
686 | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0
687 move.b $r0,[R_SERIAL3_REC_CTRL]
697 | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0
698 move.b $r0,[R_SERIAL3_TR_CTRL]