Lines Matching refs:r0
147 orr r0, r0, #CR_A
149 bic r0, r0, #CR_A
152 bic r0, r0, #CR_C
155 bic r0, r0, #CR_Z
158 bic r0, r0, #CR_I
161 orr r0, r0, #CR_V
163 bic r0, r0, #CR_V
165 mcr p15, 0, r0, c1, c0, 0 @ write control reg
200 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
201 and r0, r0, #(MMFR0_PMSA) @ PMSA field
202 teq r0, #(MMFR0_PMSAv7) @ PMSA v7
207 mrc p15, 0, r0, c0, c0, 4 @ MPUIR
208 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
210 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
213 set_region_nr r0, #MPU_RAM_REGION
216 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
219 setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
221 setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
225 set_region_nr r0, #MPU_BG_REGION
228 mov r0, #0 @ BG region starts at 0x0
232 setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled
234 setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
238 set_region_nr r0, #MPU_VECTORS_REGION
241 mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE
246 setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled
248 setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
252 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
253 bic r0, r0, #CR_BR @ Disable the 'default mem-map'
254 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
255 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU