Lines Matching refs:r0
74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
75 bic r0, r0, #0x1000 @ ...i............
76 bic r0, r0, #0x000e @ ............wca.
77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
102 ret r0
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mov r0, #0
124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
170 sub r3, r1, r0 @ calculate total size
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
177 add r0, r0, #CACHE_DLINESIZE
178 cmp r0, r1
208 bic r0, r0, #CACHE_DLINESIZE - 1
209 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
211 add r0, r0, #CACHE_DLINESIZE
212 cmp r0, r1
214 mcr p15, 0, r0, c7, c10, 4 @ drain WB
215 mov r0, #0
228 add r1, r0, r1
229 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
230 add r0, r0, #CACHE_DLINESIZE
231 cmp r0, r1
233 mov r0, #0
234 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
235 mcr p15, 0, r0, c7, c10, 4 @ drain WB
252 tst r0, #CACHE_DLINESIZE - 1
253 bic r0, r0, #CACHE_DLINESIZE - 1
254 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
257 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
258 add r0, r0, #CACHE_DLINESIZE
259 cmp r0, r1
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
277 add r0, r0, #CACHE_DLINESIZE
278 cmp r0, r1
280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
292 bic r0, r0, #CACHE_DLINESIZE - 1
293 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
294 add r0, r0, #CACHE_DLINESIZE
295 cmp r0, r1
297 mcr p15, 0, r0, c7, c10, 4 @ drain WB
307 add r1, r1, r0
334 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
335 add r0, r0, #CACHE_DLINESIZE
371 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
385 mov r0, r0
386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
387 mcr p15, 0, r0, c7, c10, 4 @ drain WB
393 mov r0, #0
394 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
395 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
401 mrc p15, 0, r0, c1, c0 @ get control register v4
402 bic r0, r0, r5
403 orr r0, r0, r6