Lines Matching refs:r0
39 mov r0, #0
40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
47 mov r0, #0
48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
50 bic r0, r0, #0x1000 @ ...i............
51 bic r0, r0, #0x000e @ ............wca.
52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 ret r0
98 mov r0, r0 @ safety
99 mov r0, r0 @ safety
100 mov r0, r0 @ safety
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mov r0, r0 @ safety
103 mov r0, r0 @ safety
104 mov r0, r0 @ safety
105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
120 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
121 add r0, r0, #DCACHELINESIZE
140 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
156 mov r0, r0
157 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
158 mcr p15, 0, r0, c7, c10, 4 @ drain WB
173 mrc p15, 0, r0, c1, c0 @ get control register v4
174 bic r0, r0, r5
175 orr r0, r0, r6