Lines Matching refs:r0
75 mov r0, \val
80 mov r0, \val
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
110 mov r0, r4
129 mov r0, r0
131 ARM( mov r0, r0 )
160 mov r0, #0x17 @ angel_SWIreason_EnterSVC
164 safe_svcmode_maskall r0
212 mov r0, pc
213 cmp r0, r4
214 ldrcc r0, LC0+32
215 addcc r0, r0, pc
216 cmpcc r4, r0
220 restart: adr r0, LC0
221 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
222 ldr sp, [r0, #28]
228 sub r0, r0, r1 @ calculate the delta offset
229 add r6, r6, r0 @ _edata
230 add r10, r10, r0 @ inflated kernel size location
247 add sp, sp, r0
320 stmfd sp!, {r0-r3, ip, lr}
321 mov r0, r8
331 cmp r0, #1
332 sub r0, r4, #TEXT_OFFSET
333 bic r0, r0, #1
334 add r0, r0, #0x100
339 ldmfd sp!, {r0-r3, ip, lr}
417 mrs r0, spsr
418 and r0, r0, #MODE_MASK
419 cmp r0, #HYP_MODE
423 sub r0, r0, r5
424 add r0, r0, r10
435 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
437 stmdb r9!, {r0 - r3, r10 - r12, lr}
450 adr r0, BSYM(restart)
451 add r0, r0, r6
452 mov pc, r0
468 orrs r1, r0, r5
471 add r11, r11, r0
472 add r12, r12, r0
480 add r2, r2, r0
481 add r3, r3, r0
488 add r1, r1, r0 @ This fixes up C references
509 addlo r1, r1, r0 @ table. This fixes up the
515 not_relocated: mov r0, #0
516 1: str r0, [r2], #4 @ clear bss
517 str r0, [r2], #4
518 str r0, [r2], #4
519 str r0, [r2], #4
539 mov r0, r4
550 mrs r0, spsr @ Get saved CPU boot mode
551 and r0, r0, #MODE_MASK
552 cmp r0, #HYP_MODE @ if not booted in HYP mode...
556 ldr r0, [r12]
557 add r0, r0, r12
585 params: ldr r0, =0x10000100 @ params_phys for RPC
617 mov r0, #0x3f @ 4G, the whole
618 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
619 mcr p15, 0, r0, c6, c7, 1
621 mov r0, #0x80 @ PR7
622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
624 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
626 mov r0, #0xc000
627 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
628 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
630 mov r0, #0
631 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
632 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
633 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
634 mrc p15, 0, r0, c1, c0, 0 @ read control reg
636 orr r0, r0, #0x002d @ .... .... ..1. 11.1
637 orr r0, r0, #0x1000 @ ...1 .... .... ....
639 mcr p15, 0, r0, c1, c0, 0 @ write control reg
641 mov r0, #0
642 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
643 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
647 mov r0, #0x3f @ 4G, the whole
648 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
650 mov r0, #0x80 @ PR7
651 mcr p15, 0, r0, c2, c0, 0 @ cache on
652 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
654 mov r0, #0xc000
655 mcr p15, 0, r0, c5, c0, 0 @ access permission
657 mov r0, #0
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
663 mrc p15, 0, r0, c1, c0, 0 @ read control reg
665 orr r0, r0, #0x000d @ .... .... .... 11.1
667 mov r0, #0
668 mcr p15, 0, r0, c1, c0, 0 @ write control reg
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
687 mov r0, r3
688 mov r9, r0, lsr #18
699 str r1, [r0], #4 @ 1:1 mapping
701 teq r0, r2
714 add r0, r3, r2, lsl #2
715 str r1, [r0], #4
717 str r1, [r0]
724 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
725 bic r0, r0, #2 @ A (no unaligned access fault)
726 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
727 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
732 mov r0, #4 @ put dcache in WT mode
733 mcr p15, 7, r0, c15, c0, 0
741 mov r0, #0
742 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
743 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
744 mrc p15, 0, r0, c1, c0, 0 @ read control reg
745 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
746 orr r0, r0, #0x0030
747 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
749 mov r0, #0
750 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
761 mov r0, #0
762 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
764 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
766 mrc p15, 0, r0, c1, c0, 0 @ read control reg
767 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
768 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
769 orr r0, r0, #0x003c @ write buffer
770 bic r0, r0, #2 @ A (no unaligned access fault)
771 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
774 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
776 orrne r0, r0, #1 @ MMU enabled
784 mcr p15, 0, r0, c7, c5, 4 @ ISB
785 mcr p15, 0, r0, c1, c0, 0 @ load control register
786 mrc p15, 0, r0, c1, c0, 0 @ and read it back
787 mov r0, #0
788 mcr p15, 0, r0, c7, c5, 4 @ ISB
795 mov r0, #0
796 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
797 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
798 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
799 mrc p15, 0, r0, c1, c0, 0 @ read control reg
800 orr r0, r0, #0x1000 @ I-cache enable
802 mov r0, #0
803 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
809 orr r0, r0, #0x000d @ Write buffer, mmu
816 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
817 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
818 sub pc, lr, r0, lsr #32 @ properly flush pipeline
1046 mrc p15, 0, r0, c1, c0
1047 bic r0, r0, #0x000d
1048 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1049 mov r0, #0
1050 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1051 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1052 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1056 mrc p15, 0, r0, c1, c0
1057 bic r0, r0, #0x000d
1058 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1059 mov r0, #0
1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1065 mrc p15, 0, r0, c1, c0
1066 bic r0, r0, #0x000d
1067 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1068 mov r0, #0
1069 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1070 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1075 mrc p15, 0, r0, c1, c0
1077 bic r0, r0, #0x000d
1079 bic r0, r0, #0x000c
1081 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1084 mov r0, #0
1086 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1088 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1089 mcr p15, 0, r0, c7, c10, 4 @ DSB
1090 mcr p15, 0, r0, c7, c5, 4 @ ISB
1154 stmfd sp!, {r0-r7, r9-r11}
1155 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1156 ands r3, r0, #0x7000000 @ extract loc from clidr
1162 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1195 ldmfd sp!, {r0-r7, r9-r11}
1210 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1211 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1266 @ phex corrupts {r0, r1, r2, r3}
1271 movmi r0, r3
1273 and r2, r0, #15
1274 mov r0, r0, lsr #4
1281 @ puts corrupts {r0, r1, r2, r3}
1283 1: ldrb r2, [r0], #1
1293 teq r0, #0
1296 @ putc corrupts {r0, r1, r2, r3}
1298 mov r2, r0
1299 mov r0, #0
1303 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1304 memdump: mov r12, r0
1307 2: mov r0, r11, lsl #2
1308 add r0, r0, r12
1311 mov r0, #':'
1313 1: mov r0, #' '
1315 ldr r0, [r12, r11, lsl #2]
1318 and r0, r11, #7
1319 teq r0, #3
1320 moveq r0, #' '
1322 and r0, r11, #7
1324 teq r0, #7
1326 mov r0, #'\n'
1349 mov r0, #0 @ must be 0