1/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2   2004, 2005
3   Free Software Foundation, Inc.
4
5This file is free software; you can redistribute it and/or modify it
6under the terms of the GNU General Public License as published by the
7Free Software Foundation; either version 2, or (at your option) any
8later version.
9
10In addition to the permissions in the GNU General Public License, the
11Free Software Foundation gives you unlimited permission to link the
12compiled version of this file into combinations with other programs,
13and to distribute those combinations without any restriction coming
14from the use of this file.  (The General Public License restrictions
15do apply in other respects; for example, they cover modification of
16the file, and distribution when not linked into a combine
17executable.)
18
19This file is distributed in the hope that it will be useful, but
20WITHOUT ANY WARRANTY; without even the implied warranty of
21MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
22General Public License for more details.
23
24You should have received a copy of the GNU General Public License
25along with this program; see the file COPYING.  If not, write to
26the Free Software Foundation, 51 Franklin Street, Fifth Floor,
27Boston, MA 02110-1301, USA.  */
28
29!! libgcc routines for the Renesas / SuperH SH CPUs.
30!! Contributed by Steve Chamberlain.
31!! sac@cygnus.com
32
33	.balign 4
34	.global	__udivsi3
35	.type	__udivsi3, @function
36div8:
37	div1 r5,r4
38div7:
39	div1 r5,r4; div1 r5,r4; div1 r5,r4
40	div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
41
42divx4:
43	div1 r5,r4; rotcl r0
44	div1 r5,r4; rotcl r0
45	div1 r5,r4; rotcl r0
46	rts; div1 r5,r4
47
48__udivsi3:
49	sts.l pr,@-r15
50	extu.w r5,r0
51	cmp/eq r5,r0
52	bf/s large_divisor
53	div0u
54	swap.w r4,r0
55	shlr16 r4
56	bsr div8
57	shll16 r5
58	bsr div7
59	div1 r5,r4
60	xtrct r4,r0
61	xtrct r0,r4
62	bsr div8
63	swap.w r4,r4
64	bsr div7
65	div1 r5,r4
66	lds.l @r15+,pr
67	xtrct r4,r0
68	swap.w r0,r0
69	rotcl r0
70	rts
71	shlr16 r5
72
73large_divisor:
74	mov #0,r0
75	xtrct r4,r0
76	xtrct r0,r4
77	bsr divx4
78	rotcl r0
79	bsr divx4
80	rotcl r0
81	bsr divx4
82	rotcl r0
83	bsr divx4
84	rotcl r0
85	lds.l @r15+,pr
86	rts
87	rotcl r0
88