Lines Matching refs:r0
64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
65 bic r0, r0, #0x1000 @ ...i............
66 bic r0, r0, #0x000e @ ............wca.
67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 ret r0
103 mov r0, #0
105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 sub r3, r1, r0 @ calculate total size
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 add r0, r0, #CACHE_DLINESIZE
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
182 add r0, r0, #CACHE_DLINESIZE
183 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
184 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
185 add r0, r0, #CACHE_DLINESIZE
187 cmp r0, r1
217 bic r0, r0, #CACHE_DLINESIZE - 1
218 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 add r0, r0, #CACHE_DLINESIZE
221 cmp r0, r1
223 mcr p15, 0, r0, c7, c10, 4 @ drain WB
224 mov r0, #0
237 add r1, r0, r1
238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
239 add r0, r0, #CACHE_DLINESIZE
240 cmp r0, r1
242 mov r0, #0
243 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
244 mcr p15, 0, r0, c7, c10, 4 @ drain WB
262 tst r0, #CACHE_DLINESIZE - 1
263 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
267 bic r0, r0, #CACHE_DLINESIZE - 1
268 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
269 add r0, r0, #CACHE_DLINESIZE
270 cmp r0, r1
272 mcr p15, 0, r0, c7, c10, 4 @ drain WB
287 bic r0, r0, #CACHE_DLINESIZE - 1
288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
289 add r0, r0, #CACHE_DLINESIZE
290 cmp r0, r1
293 mcr p15, 0, r0, c7, c10, 4 @ drain WB
305 bic r0, r0, #CACHE_DLINESIZE - 1
308 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
310 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
312 add r0, r0, #CACHE_DLINESIZE
313 cmp r0, r1
315 mcr p15, 0, r0, c7, c10, 4 @ drain WB
325 add r1, r1, r0
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
351 add r0, r0, #CACHE_DLINESIZE
355 mcr p15, 0, r0, c7, c10, 4 @ drain WB
380 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
394 mov r0, r0
396 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
398 mcr p15, 0, r0, c7, c10, 4 @ drain WB
411 stmia r0, {r4 - r6}
419 ldmia r0, {r4 - r6}
423 mov r0, r6 @ control register
430 mov r0, #0
431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
432 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
434 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
439 mov r0, #4 @ disable write-back on caches explicitly
440 mcr p15, 7, r0, c15, c0, 0
445 mrc p15, 0, r0, c1, c0 @ get control register v4
446 bic r0, r0, r5
447 orr r0, r0, r6
449 orr r0, r0, #0x4000 @ .1.. .... .... ....