Lines Matching refs:r0
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 bx r0
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, r2
101 stmia r0!, {r4 - r5}
114 stmia r0, {r5 - r11}
122 ldmia r0!, {r4 - r5}
125 ldmia r0, {r5 - r11}
150 mov r0, r8 @ control register
187 stmia r0!, {r4 - r5}
193 ldmia r0!, {r4 - r5}
229 stmia r0!, {r6 - r10}
235 ldmia r0!, {r6 - r10}
272 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
274 ldmia r12, {r0-r5, lr}
276 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
277 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
278 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
279 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
280 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
281 mcreq p15, 0, r0, c1, c0, 1
311 mrc p15, 1, r0, c15, c1, 1
312 orr r0, r0, #PJ4B_CLEAN_LINE
313 orr r0, r0, #PJ4B_INTER_PARITY
314 bic r0, r0, #PJ4B_STATIC_BP
315 mcr p15, 1, r0, c15, c1, 1
318 mrc p15, 1, r0, c15, c1, 2
319 bic r0, r0, #PJ4B_FAST_LDR
320 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
321 mcr p15, 1, r0, c15, c1, 2
324 mrc p15, 1, r0, c15, c2, 0
326 orr r0, r0, #PJ4B_SMP_CFB
328 orr r0, r0, #PJ4B_L1_PAR_CHK
329 orr r0, r0, #PJ4B_BROADCAST_CACHE
330 mcr p15, 1, r0, c15, c2, 0
333 mrc p15, 1, r0, c15, c1, 0
334 orr r0, r0, #PJ4B_WFI_WFE
335 mcr p15, 1, r0, c15, c1, 0
341 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
343 ldmia r12, {r0-r5, lr}
346 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
347 and r10, r0, #0xff000000 @ ARM?
350 and r5, r0, #0x00f00000 @ variant
351 and r6, r0, #0x0000000f @ revision
353 ubfx r0, r0, #4, #12 @ primary part number
357 teq r0, r10
384 teq r0, r10
418 teq r0, r10
440 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
441 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
442 teq r0, #(1 << 12) @ check if ThumbEE is present
446 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
447 orr r0, r0, #1 @ set the 1st bit in order to
448 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
458 mrc p15, 0, r0, c1, c0, 0 @ read control register
459 bic r0, r0, r5 @ clear bits them
460 orr r0, r0, r6 @ set them
461 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions