Lines Matching refs:r0
80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 ret r0
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 mov r0, #0
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
184 sub r3, r1, r0 @ calculate total size
190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
192 add r0, r0, #CACHE_DLINESIZE
193 cmp r0, r1
228 bic r0, r0, #CACHE_DLINESIZE - 1
232 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
236 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
238 add r0, r0, #CACHE_DLINESIZE
239 cmp r0, r1
242 mov r0, #0
257 add r1, r0, r1
258 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
260 add r0, r0, #CACHE_DLINESIZE
261 cmp r0, r1
283 tst r0, #CACHE_DLINESIZE - 1
284 bic r0, r0, #CACHE_DLINESIZE - 1
286 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
292 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
293 add r0, r0, #CACHE_DLINESIZE
294 cmp r0, r1
313 bic r0, r0, #CACHE_DLINESIZE - 1
314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
316 add r0, r0, #CACHE_DLINESIZE
317 cmp r0, r1
334 bic r0, r0, #CACHE_DLINESIZE - 1
336 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
338 add r0, r0, #CACHE_DLINESIZE
339 cmp r0, r1
352 add r1, r1, r0
379 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
381 add r0, r0, #CACHE_DLINESIZE
421 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
435 mov r0, r0
437 mcr p15, 0, r0, c7, c10, 4
438 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
440 mcr p15, 0, r0, c7, c10, 4 @ drain WB
446 mov r0, #0
447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
455 mrc p15, 0, r0, c1, c0 @ get control register v4
456 bic r0, r0, r5
457 orr r0, r0, r6
459 orr r0, r0, #0x4000 @ .R.. .... .... ....