Lines Matching refs:r0
71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0, #0x1000 @ ...i............
73 bic r0, r0, #0x000e @ ............wca.
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 ret r0
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 sub r3, r1, r0 @ calculate total size
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 add r0, r0, #CACHE_DLINESIZE
175 cmp r0, r1
209 bic r0, r0, #CACHE_DLINESIZE - 1
212 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 add r0, r0, #CACHE_DLINESIZE
218 cmp r0, r1
221 mov r0, #0
236 add r1, r0, r1
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
238 add r0, r0, #CACHE_DLINESIZE
239 cmp r0, r1
261 tst r0, #CACHE_DLINESIZE - 1
262 bic r0, r0, #CACHE_DLINESIZE - 1
263 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
266 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
267 add r0, r0, #CACHE_DLINESIZE
268 cmp r0, r1
287 bic r0, r0, #CACHE_DLINESIZE - 1
288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
289 add r0, r0, #CACHE_DLINESIZE
290 cmp r0, r1
307 bic r0, r0, #CACHE_DLINESIZE - 1
308 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
309 add r0, r0, #CACHE_DLINESIZE
310 cmp r0, r1
323 add r1, r1, r0
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
351 add r0, r0, #CACHE_DLINESIZE
378 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
392 mov r0, r0
394 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
401 mov r0, #0
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
409 mov r0, #4 @ explicitly disable writeback
410 mcr p15, 7, r0, c15, c0, 0
414 mrc p15, 0, r0, c1, c0 @ get control register v4
415 bic r0, r0, r5
416 orr r0, r0, r6
418 orr r0, r0, #0x4000 @ .R.. .... .... ....