Lines Matching refs:r0
42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
43 bic r0, r0, #0x1000 @ ...i............
44 bic r0, r0, #0x0006 @ .............ca.
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 ret r0
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
84 add r0, r0, #D_CACHE_LINE_SIZE
103 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
104 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
150 stmia r0, {r4 - r9}
161 ldmia r0, {r4 - r9}
174 mov r0, r9 @ control register
200 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
202 orr r0, r0, #0x20
203 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
207 mov r0, #0
208 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
220 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
225 mrc p15, 0, r0, c1, c0, 0 @ read control register
226 bic r0, r0, r5 @ clear bits them
227 orr r0, r0, r6 @ set them
242 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration