Lines Matching refs:r0
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 bic r0, r0, #0x1800 @ ...iz...........
56 bic r0, r0, #0x0006 @ .............ca.
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 ret r0
93 mov r0, #0
94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
104 mov r0, #0
105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
147 sub r3, r1, r0 @ calculate total size
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
153 add r0, r0, #CACHE_DLINESIZE
154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
156 add r0, r0, #CACHE_DLINESIZE
157 cmp r0, r1
189 bic r0, r0, #CACHE_DLINESIZE - 1
190 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
192 add r0, r0, #CACHE_DLINESIZE
193 cmp r0, r1
195 mcr p15, 0, r0, c7, c10, 4 @ drain WB
196 mov r0, #0
209 add r1, r0, r1
210 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
211 add r0, r0, #CACHE_DLINESIZE
212 cmp r0, r1
214 mov r0, #0
215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
216 mcr p15, 0, r0, c7, c10, 4 @ drain WB
233 tst r0, #CACHE_DLINESIZE - 1
234 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
237 bic r0, r0, #CACHE_DLINESIZE - 1
238 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
239 add r0, r0, #CACHE_DLINESIZE
240 cmp r0, r1
242 mcr p15, 0, r0, c7, c10, 4 @ drain WB
256 bic r0, r0, #CACHE_DLINESIZE - 1
257 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
258 add r0, r0, #CACHE_DLINESIZE
259 cmp r0, r1
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
273 bic r0, r0, #CACHE_DLINESIZE - 1
275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
276 add r0, r0, #CACHE_DLINESIZE
277 cmp r0, r1
279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
289 add r1, r1, r0
313 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
314 add r0, r0, #CACHE_DLINESIZE
317 mcr p15, 0, r0, c7, c10, 4 @ drain WB
333 orr r0, r0, #0x18 @ cache the page table in L2
334 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
346 mov r0, r0
347 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB
363 stmia r0, {r4 - r9} @ store cp regs
368 ldmia r0, {r4 - r9} @ load cp regs
381 mov r0, r9 @ control register
388 mov r0, #0
389 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
390 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
395 mov r0, #0 @ don't allow CP access