Lines Matching refs:r0
49 cpu_id r0
50 cmp r0, #0 @ CPU0?
59 cpu_to_csr_reg r1, r0
65 movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
67 bic r1, r1, r0
76 mov32 r0, TEGRA_ARM_PERIF_BASE
77 ldr r1, [r0]
79 str r1, [r0]
130 mrc p15, 0, r0, c1, c0, 0 @ read system control register
131 orr r0, r0, #1 << 14 @ erratum 716044
132 mcr p15, 0, r0, c1, c0, 0 @ write system control register
133 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
134 orr r0, r0, #1 << 4 @ erratum 742230
135 orr r0, r0, #1 << 11 @ erratum 751472
136 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
146 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
147 orr r0, r0, #1 << 6 @ erratum 743622
148 orr r0, r0, #1 << 11 @ erratum 751472
149 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
173 mov r0, #CPU_NOT_RESETTABLE
175 strneb r0, [r5, #__tegra20_cpu1_resettable_status_offset]
236 mov32 r0, 0x1111
237 mov r1, r0, lsl r10
253 ldr r0, [r6, +r2]
254 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
255 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
256 str r0, [r6, +r2]
259 mov r0, #FLOW_CTRL_WAITEVENT
260 str r0, [r6, +r1]
261 ldr r0, [r6, +r1] @ memory barrier
269 mov r0, r11, lsl #8
270 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET