Lines Matching refs:r0
37 l.or gpr,r0,r0
54 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
57 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
60 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
63 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
66 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
67 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
69 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
70 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
76 #define EXCEPTION_STORE_GPR9 l.sw 0x10(r0),r9
77 #define EXCEPTION_LOAD_GPR9 l.lwz r9,0x10(r0)
79 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
80 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
82 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
83 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
85 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
86 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
88 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
89 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
91 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
92 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
99 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
100 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
102 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
103 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
105 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
106 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
112 #define EXCEPTION_T_STORE_GPR31 l.sw 0x84(r0),r31
113 #define EXCEPTION_T_LOAD_GPR31(reg) l.lwz reg,0x84(r0)
158 l.mfspr r30,r0,SPR_ESR_BASE ;\
180 l.mfspr r12,r0,SPR_EPCR_BASE ;\
182 l.mfspr r12,r0,SPR_ESR_BASE ;\
195 l.mfspr r4,r0,SPR_EEAR_BASE ;\
199 l.ori r30,r0,(EXCEPTION_SR) ;\
200 l.mtspr r0,r30,SPR_ESR_BASE ;\
203 l.mtspr r0,r30,SPR_EPCR_BASE ;\
236 l.ori r3,r0,lo(_string_unhandled_exception) ;\
237 l.mfspr r3,r0,SPR_NPC ;\
242 l.ori r3,r0,lo(_string_epc_prefix) ;\
244 l.mfspr r3,r0,SPR_EPCR_BASE ;\
246 l.ori r3,r0,lo(_string_nl) ;\
260 l.mfspr r12,r0,SPR_EPCR_BASE ;\
262 l.mfspr r12,r0,SPR_ESR_BASE ;\
277 l.mfspr r4,r0,SPR_EEAR_BASE ;\
281 l.ori r31,r0,(EXCEPTION_SR) ;\
282 l.mtspr r0,r31,SPR_ESR_BASE ;\
285 l.mtspr r0,r31,SPR_EPCR_BASE ;\
446 l.or r25,r0,r3 /* pointer to fdt */
452 l.ori r3,r0,0x1
453 l.mtspr r0,r3,SPR_SR
494 l.ori r4,r0,0x0
509 l.sw (0)(r28),r0
528 l.addi r7,r0,128 /* Maximum number of sets */
530 l.mtspr r5,r0,0x0
531 l.mtspr r6,r0,0x0
535 l.sfeq r7,r0
547 l.mfspr r30,r0,SPR_SR
551 l.mtspr r0,r30,SPR_SR
580 l.or r25,r0,r0
583 l.or r3,r0,r25
639 l.mfspr r24,r0,SPR_UPR
641 l.sfeq r26,r0
646 l.mfspr r6,r0,SPR_SR
647 l.addi r5,r0,-1
650 l.mtspr r0,r5,SPR_SR
657 l.mfspr r24,r0,SPR_ICCFGR
660 l.ori r30,r0,16
669 l.ori r30,r0,1
673 l.addi r6,r0,0
679 l.mtspr r0,r6,SPR_ICBIR
686 l.mfspr r6,r0,SPR_SR
688 l.mtspr r0,r6,SPR_SR
705 l.mfspr r24,r0,SPR_UPR
707 l.sfeq r26,r0
712 l.mfspr r6,r0,SPR_SR
713 l.addi r5,r0,-1
716 l.mtspr r0,r5,SPR_SR
723 l.mfspr r24,r0,SPR_DCCFGR
726 l.ori r30,r0,16
735 l.ori r30,r0,1
739 l.addi r6,r0,0
742 l.mtspr r0,r6,SPR_DCBIR
748 l.mfspr r6,r0,SPR_SR
750 l.mtspr r0,r6,SPR_SR
794 l.mfspr r6,r0,SPR_ESR_BASE //
811 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
818 l.mfspr r6, r0, SPR_DMMUCFGR
821 l.ori r5, r0, 0x1
890 l.mfspr r6,r0,SPR_ESR_BASE //
898 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
905 l.mfspr r6, r0, SPR_IMMUCFGR
908 l.ori r5, r0, 0x1
979 l.mfspr r2,r0,SPR_EEAR_BASE
993 l.sfne r3,r0
1003 l.addi r3,r0,0xffffe000 // PAGE_MASK
1021 l.sfne r4,r0 // is pte present
1023 l.addi r3,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1029 l.mfspr r6, r0, SPR_DMMUCFGR
1032 l.ori r3, r0, 0x1
1041 l.mfspr r2,r0,SPR_EEAR_BASE
1042 l.addi r3,r0,0xffffe000 // PAGE_MASK
1080 l.mfspr r2,r0,SPR_EEAR_BASE
1096 l.sfne r3,r0
1107 l.addi r3,r0,0xffffe000 // PAGE_MASK
1128 l.sfne r4,r0 // is pte present
1130 l.addi r3,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1137 l.sfeq r3,r0
1140 l.mfspr r6, r0, SPR_IMMUCFGR
1143 l.ori r3, r0, 0x1
1162 l.mfspr r2,r0,SPR_EEAR_BASE
1163 l.addi r3,r0,0xffffe000 // PAGE_MASK
1266 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1272 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1317 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1323 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1382 l.mtspr r0,r5,SPR_EPCR_BASE
1393 l.mfspr r21,r0,SPR_ICCFGR
1396 l.ori r23,r0,16
1399 l.mtspr r0,r5,SPR_ICBIR
1401 l.mtspr r0,r5,SPR_ICBIR
1424 l.sfeq r7,r0
1431 l.addi r6,r0,0x20
1440 l.addi r6,r0,0x60
1466 l.addi r8,r0,32 // shift register
1478 l.sfeq r7,r0
1486 l.sflts r8,r0
1499 l.addi r6,r0,0x20
1508 l.addi r6,r0,0x60
1553 l.addi r4,r0,0x7
1556 l.addi r4,r0,0x0
1559 l.addi r4,r0,0x3
1565 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1567 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)