1/*
2 * L2C-310 early resume code.  This can be used by platforms to restore
3 * the settings of their L2 cache controller before restoring the
4 * processor state.
5 *
6 * This code can only be used to if you are running in the secure world.
7 */
8#include <linux/linkage.h>
9#include <asm/assembler.h>
10#include <asm/hardware/cache-l2x0.h>
11
12	.text
13
14ENTRY(l2c310_early_resume)
15	adr	r0, 1f
16	ldr	r2, [r0]
17	add	r0, r2, r0
18
19	ldmia	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
20	@ r1 = phys address of L2C-310 controller
21	@ r2 = aux_ctrl
22	@ r3 = tag_latency
23	@ r4 = data_latency
24	@ r5 = filter_start
25	@ r6 = filter_end
26	@ r7 = prefetch_ctrl
27	@ r8 = pwr_ctrl
28
29	@ Check that the address has been initialised
30	teq	r1, #0
31	reteq	lr
32
33	@ The prefetch and power control registers are revision dependent
34	@ and can be written whether or not the L2 cache is enabled
35	ldr	r0, [r1, #L2X0_CACHE_ID]
36	and	r0, r0, #L2X0_CACHE_ID_RTL_MASK
37	cmp	r0, #L310_CACHE_ID_RTL_R2P0
38	strcs	r7, [r1, #L310_PREFETCH_CTRL]
39	cmp	r0, #L310_CACHE_ID_RTL_R3P0
40	strcs	r8, [r1, #L310_POWER_CTRL]
41
42	@ Don't setup the L2 cache if it is already enabled
43	ldr	r0, [r1, #L2X0_CTRL]
44	tst	r0, #L2X0_CTRL_EN
45	retne	lr
46
47	str	r3, [r1, #L310_TAG_LATENCY_CTRL]
48	str	r4, [r1, #L310_DATA_LATENCY_CTRL]
49	str	r6, [r1, #L310_ADDR_FILTER_END]
50	str	r5, [r1, #L310_ADDR_FILTER_START]
51
52	str	r2, [r1, #L2X0_AUX_CTRL]
53	mov	r9, #L2X0_CTRL_EN
54	str	r9, [r1, #L2X0_CTRL]
55	ret	lr
56ENDPROC(l2c310_early_resume)
57
58	.align
591:	.long	l2x0_saved_regs - .
60