Lines Matching refs:r0
81 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
96 ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
97 ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
99 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
101 add r7, r7, r0
110 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
111 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
152 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
153 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
154 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
155 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
172 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
174 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
176 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
180 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
188 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
207 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
209 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
211 add r8, r8, r0
240 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
258 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
270 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
320 ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
322 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
327 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]