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/linux-4.1.27/arch/arm/boot/dts/
Ds3c2416.dtsi36 clocks: clock-controller@0x4c000000 { label
47 clocks = <&clocks PCLK_PWM>;
55 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
56 <&clocks SCLK_UART>;
63 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
64 <&clocks SCLK_UART>;
71 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
72 <&clocks SCLK_UART>;
81 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
82 <&clocks SCLK_UART>;
[all …]
Ds5pv210.dtsi60 external-clocks {
89 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
101 clocks: clock-controller@e0100000 { label
105 clocks = <&xxti>, <&xusbxti>;
141 clocks = <&clocks CLK_PDMA0>;
153 clocks = <&clocks CLK_PDMA1>;
168 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
184 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
198 clocks = <&clocks CLK_KEYIF>;
208 clocks = <&clocks CLK_I2C0>;
[all …]
Domap3xxx-clocks.dtsi20 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
27 clocks = <&osc_sys_ck>;
37 clocks = <&osc_sys_ck>;
45 clocks = <&dpll3_ck>;
53 clocks = <&dpll3_m2_ck>;
61 clocks = <&dpll4_ck>;
69 clocks = <&dpll3_m2x2_ck>;
77 clocks = <&sys_ck>;
87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
95 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Domap24xx-clocks.dtsi14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
22 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
36 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
80 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
88 clocks = <&aplls_clkin_ck>;
96 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
105 clocks = <&osc_ck>;
127 clocks = <&sys_ck>, <&sys_ck>;
134 clocks = <&sys_ck>;
[all …]
Domap54xx-clocks.dtsi20 clocks = <&pad_clks_src_ck>;
40 clocks = <&slimbus_src_clk>;
108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
115 clocks = <&dpll_abe_ck>;
121 clocks = <&dpll_abe_x2_ck>;
130 clocks = <&dpll_abe_m2x2_ck>;
138 clocks = <&dpll_abe_m2x2_ck>;
147 clocks = <&aess_fclk>;
156 clocks = <&dpll_abe_m2x2_ck>;
164 clocks = <&dpll_abe_x2_ck>;
[all …]
Domap44xx-clocks.dtsi26 clocks = <&pad_clks_src_ck>;
52 clocks = <&slimbus_src_clk>;
138 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
145 clocks = <&dpll_abe_ck>;
152 clocks = <&dpll_abe_x2_ck>;
163 clocks = <&dpll_abe_m2x2_ck>;
171 clocks = <&dpll_abe_m2x2_ck>;
180 clocks = <&abe_clk>;
189 clocks = <&dpll_abe_x2_ck>;
200 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
[all …]
Dam33xx-clocks.dtsi14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
22 clocks = <&sys_clkin_ck>;
30 clocks = <&sys_clkin_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Dam43xx-clocks.dtsi14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Ds3c64xx.dtsi69 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
70 <&clocks SCLK_MMC0>;
80 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
81 <&clocks SCLK_MMC1>;
91 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
92 <&clocks SCLK_MMC2>;
102 clocks = <&clocks PCLK_WDT>;
112 clocks = <&clocks PCLK_IIC0>;
125 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
126 <&clocks SCLK_UART>;
[all …]
Ddra7xx-clocks.dtsi14 clocks = <&atl_gfclk_mux>;
20 clocks = <&atl_gfclk_mux>;
26 clocks = <&atl_gfclk_mux>;
32 clocks = <&atl_gfclk_mux>;
194 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
201 clocks = <&dpll_abe_ck>;
207 clocks = <&dpll_abe_x2_ck>;
218 clocks = <&dpll_abe_m2x2_ck>;
227 clocks = <&dpll_abe_ck>;
238 clocks = <&dpll_abe_x2_ck>;
[all …]
Domap2430-clocks.dtsi15 clocks = <&func_96m_ck>, <&mcbsp_clks>;
22 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
36 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
42 clocks = <&func_96m_ck>, <&mcbsp_clks>;
50 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
58 clocks = <&dsp_fck>;
66 clocks = <&dsp_fck>;
76 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
82 clocks = <&core_ck>;
[all …]
Domap2420-clocks.dtsi15 clocks = <&core_ck>;
23 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
31 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
37 clocks = <&sys_clkout2_src>;
47 clocks = <&dsp_fck>;
55 clocks = <&dsp_fck>;
65 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
71 clocks = <&core_ck>;
79 clocks = <&core_ck>;
88 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
[all …]
Domap34xx-omap36xx-clocks.dtsi14 clocks = <&l4_ick>;
22 clocks = <&security_l4_ick2>;
30 clocks = <&security_l4_ick2>;
38 clocks = <&security_l4_ick2>;
46 clocks = <&security_l4_ick2>;
54 clocks = <&dpll4_m5x2_ck>;
63 clocks = <&l4_ick>;
71 clocks = <&core_96m_fck>;
79 clocks = <&l3_ick>;
87 clocks = <&security_l3_ick>;
[all …]
Dr8a7794.dtsi58 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
77 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
134 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
164 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
174 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
183 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
192 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
201 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
210 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
219 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
[all …]
Dste-nomadik-stn8815.dtsi32 clocks = <&timclk>, <&pclk>;
41 clocks = <&timclk>, <&pclk>;
55 clocks = <&pclk>;
68 clocks = <&pclk>;
81 clocks = <&pclk>;
94 clocks = <&pclk>;
191 clocks = <&mxtal>;
199 clocks = <&mxtal>;
206 clocks = <&pll1>;
214 clocks = <&hclk>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&sys_ck>, <&sys_ck>;
40 clocks = <&dpll5_ck>;
49 clocks = <&core_ck>;
57 clocks = <&core_ck>;
65 clocks = <&core_ck>;
73 clocks = <&core_ck>;
81 clocks = <&dpll4_m2x2_ck>;
89 clocks = <&core_ck>;
[all …]
Dsocfpga.dtsi90 clocks = <&l4_main_clk>;
99 clocks = <&can0_clk>;
107 clocks = <&can1_clk>;
115 clocks {
144 clocks = <&osc1>;
150 clocks = <&main_pll>;
158 clocks = <&main_pll>;
166 clocks = <&main_pll>;
174 clocks = <&main_pll>;
181 clocks = <&main_pll>;
[all …]
Domap3430es1-clocks.dtsi14 clocks = <&l3_ick>;
22 clocks = <&l3_ick>;
31 clocks = <&gfx_l3_ck>;
39 clocks = <&gfx_l3_fck>;
47 clocks = <&gfx_l3_fck>;
55 clocks = <&sys_ck>;
63 clocks = <&core_48m_fck>;
71 clocks = <&corex2_fck>;
79 clocks = <&corex2_fck>;
88 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
[all …]
Ddm816x-clocks.dtsi12 clocks = <&sys_clkin_ck &sys_clkin_ck>;
28 clocks = <&sys_clkin_ck &sys_clkin_ck>;
40 clocks = <&sys_clkin_ck &sys_clkin_ck>;
51 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
92 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
100 clocks = <&clkout_pre_ck>;
109 clocks = <&clkout_div_ck>;
114 /* CM_DPLL clocks p1795 */
118 clocks = <&main_fapll 1>;
126 clocks = <&main_fapll 2>;
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
37 clocks = <&ssi_ssr_fck>;
45 clocks = <&core_l3_ick>;
53 clocks = <&l4_ick>;
61 clocks = <&ssi_l4_ick>;
69 clocks = <&omap_96m_fck>;
77 clocks = <&sys_ck>;
85 clocks = <&omap_96m_fck>;
[all …]
Dwm8750.dtsi71 clocks {
90 clocks = <&ref25>;
97 clocks = <&ref25>;
104 clocks = <&ref25>;
111 clocks = <&ref25>;
118 clocks = <&ref25>;
125 clocks = <&plla>;
132 clocks = <&pllb>;
139 clocks = <&pllb>;
146 clocks = <&plld>;
[all …]
Dr7s72100.dtsi33 clocks {
38 /* External clocks */
55 /* Fixed factor clocks */
59 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
67 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
75 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
81 /* Special CPG clocks */
84 compatible = "renesas,r7s72100-cpg-clocks",
85 "renesas,rz-cpg-clocks";
87 clocks = <&extal_clk>, <&usb_x1_clk>;
[all …]
Dkeystone-clocks.dtsi11 clocks {
19 clocks = <&mainpllclk>, <&refclksys>;
29 clocks = <&mainmuxclk>;
38 clocks = <&mainmuxclk>;
47 clocks = <&mainmuxclk>;
57 clocks = <&mainmuxclk>;
67 clocks = <&chipclk1>;
76 clocks = <&chipclk1>;
85 clocks = <&papllclk>;
94 clocks = <&chipclk1>;
[all …]
Dk2hk-clocks.dtsi11 clocks {
15 clocks = <&refclkarm>;
24 clocks = <&refclksys>;
32 clocks = <&refclkpass>;
41 clocks = <&refclkddr3a>;
50 clocks = <&refclkddr3b>;
59 clocks = <&chipclk16>;
69 clocks = <&chipclk1rstiso13>;
79 clocks = <&chipclk12>;
89 clocks = <&chipclk1>;
[all …]
Dr8a7779.dtsi71 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
174 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
184 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
194 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
204 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
212 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
221 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
230 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
239 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
248 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
[all …]
Dsh73a0.dtsi45 clocks = <&twd_clk>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
[all …]
Dr8a7740.dtsi60 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
87 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
109 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
131 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
153 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
162 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
179 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
193 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
202 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
212 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
[all …]
Dr8a7791.dtsi52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
105 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
117 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
129 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
141 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
153 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
165 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
177 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
184 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
[all …]
Dwm8850.dtsi68 clocks {
87 clocks = <&ref24>;
94 clocks = <&ref24>;
101 clocks = <&ref24>;
108 clocks = <&ref24>;
115 clocks = <&ref24>;
122 clocks = <&ref24>;
129 clocks = <&ref24>;
136 clocks = <&plla>;
143 clocks = <&pllb>;
[all …]
Dr8a7790.dtsi53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
136 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
148 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
160 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
172 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
184 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
196 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
203 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
219 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
238 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
[all …]
Defm32gg.dtsi29 clocks = <&cmu clk_HFPERCLKADC0>;
41 clocks = <&cmu clk_HFPERCLKGPIO>;
51 clocks = <&cmu clk_HFPERCLKI2C0>;
62 clocks = <&cmu clk_HFPERCLKI2C1>;
73 clocks = <&cmu clk_HFPERCLKUSART0>;
83 clocks = <&cmu clk_HFPERCLKUSART1>;
93 clocks = <&cmu clk_HFPERCLKUSART2>;
101 clocks = <&cmu clk_HFPERCLKUSART0>;
109 clocks = <&cmu clk_HFPERCLKUSART1>;
117 clocks = <&cmu clk_HFPERCLKUSART2>;
[all …]
Dversatile-ab.dts40 clocks = <&xtal24mhz>;
49 clocks = <&xtal24mhz>;
57 clocks = <&xtal24mhz>;
120 clocks = <&pclk>;
128 clocks = <&xtal24mhz>, <&pclk>;
136 clocks = <&xtal24mhz>, <&pclk>;
144 clocks = <&xtal24mhz>, <&pclk>;
151 clocks = <&pclk>;
158 clocks = <&pclk>;
166 clocks = <&osc1>, <&pclk>;
[all …]
Dwm8505.dtsi68 clocks {
87 clocks = <&ref25>;
94 clocks = <&ref25>;
101 clocks = <&ref25>;
108 clocks = <&ref25>;
115 clocks = <&plla>;
122 clocks = <&pllb>;
129 clocks = <&pllb>;
136 clocks = <&plld>;
143 clocks = <&ref24>;
[all …]
Dk2l-clocks.dtsi11 clocks {
15 clocks = <&refclksys>;
24 clocks = <&refclksys>;
32 clocks = <&refclksys>;
41 clocks = <&refclksys>;
50 clocks = <&chipclk12>;
60 clocks = <&chipclk12>;
70 clocks = <&chipclk1>;
80 clocks = <&chipclk1>;
90 clocks = <&chipclk1>;
[all …]
Dhisi-x5hd2.dtsi45 clocks = <&clock HIX5HD2_FIXED_24M>;
59 clocks = <&clock HIX5HD2_FIXED_24M>;
68 clocks = <&clock HIX5HD2_FIXED_24M>;
77 clocks = <&clock HIX5HD2_FIXED_24M>;
86 clocks = <&clock HIX5HD2_FIXED_24M>;
94 clocks = <&clock HIX5HD2_FIXED_83M>;
103 clocks = <&clock HIX5HD2_FIXED_83M>;
112 clocks = <&clock HIX5HD2_FIXED_83M>;
121 clocks = <&clock HIX5HD2_FIXED_83M>;
130 clocks = <&clock HIX5HD2_FIXED_83M>;
[all …]
Dsun4i-a10.dtsi35 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
52 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
61 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
74 clocks = <&cpu>;
125 clocks {
132 * other mux clocks when a specific parent clock is not
161 clocks = <&osc24M>;
169 clocks = <&osc24M>;
177 clocks = <&osc24M>;
[all …]
Dr8a7778.dtsi55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
154 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
164 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
174 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
184 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
194 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
208 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
222 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
236 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
289 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
[all …]
Dimx27.dtsi49 clocks {
73 clocks = <&clks IMX27_CLK_CPU_DIV>;
96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
142 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
151 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
158 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
[all …]
Dste-u300.dts46 /* Slow bridge clocks under PLL13 */
52 clocks = <&pll13>;
59 clocks = <&slow_clk>;
66 clocks = <&slow_clk>;
73 clocks = <&slow_clk>;
80 clocks = <&slow_clk>;
87 clocks = <&slow_clk>;
99 clocks = <&pll208>;
106 clocks = <&app208>;
113 clocks = <&pll208>;
[all …]
Dr8a73a4.dtsi99 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
232 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
242 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
253 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
264 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
275 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
286 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
297 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
[all …]
Dsun5i-a10s.dtsi34 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
58 clocks {
65 * other mux clocks when a specific parent clock is not
94 clocks = <&osc24M>;
102 clocks = <&osc24M>;
110 clocks = <&osc24M>;
118 clocks = <&osc24M>;
127 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
135 clocks = <&cpu>;
[all …]
Dsun5i-a13.dtsi33 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
46 clocks = <&cpu>;
99 clocks {
106 * other mux clocks when a specific parent clock is not
135 clocks = <&osc24M>;
143 clocks = <&osc24M>;
151 clocks = <&osc24M>;
159 clocks = <&osc24M>;
168 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
176 clocks = <&cpu>;
[all …]
Dimx25.dtsi56 clocks {
86 clocks = <&clks 48>;
97 clocks = <&clks 48>;
107 clocks = <&clks 75>, <&clks 75>;
116 clocks = <&clks 76>, <&clks 76>;
125 clocks = <&clks 120>, <&clks 57>;
134 clocks = <&clks 121>, <&clks 57>;
144 clocks = <&clks 48>;
154 clocks = <&clks 51>;
165 clocks = <&clks 78>, <&clks 78>;
[all …]
Dexynos4.dtsi63 clocks = <&clock_audss EXYNOS_I2S_BUS>;
169 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
189 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
200 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
211 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
222 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
233 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
248 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
264 clocks = <&clock CLK_WDT>;
274 clocks = <&clock CLK_RTC>;
[all …]
Dexynos5250.dtsi124 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
150 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
206 clocks = <&clock CLK_FIN_PLL>;
222 clocks = <&clock CLK_WDT>;
231 clocks = <&clock CLK_G2D>;
240 clocks = <&clock CLK_MFC>;
245 clocks = <&clock CLK_RTC>;
255 clocks = <&clock CLK_TMU>;
280 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
285 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
[all …]
Dexynos5420.dtsi170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
179 clocks = <&clock CLK_MFC>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
254 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
267 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
283 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
332 clocks = <&clock CLK_RTC>;
[all …]
Dam35xx-clocks.dtsi14 clocks = <&ipss_ick>;
22 clocks = <&rmii_ck>;
30 clocks = <&ipss_ick>;
38 clocks = <&pclk_ck>;
46 clocks = <&ipss_ick>;
54 clocks = <&sys_ck>;
62 clocks = <&sys_ck>;
71 clocks = <&core_l3_ick>;
91 clocks = <&core_l4_ick>;
99 clocks = <&core_48m_fck>;
[all …]
Dimx51.dtsi48 clocks {
85 clocks = <&clks IMX5_CLK_CPU_PODF>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
231 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
[all …]
Drk3xxx.dtsi52 clocks = <&cru ACLK_DMA1>;
62 clocks = <&cru ACLK_DMA1>;
73 clocks = <&cru ACLK_DMA2>;
101 clocks = <&cru CORE_PERI>;
108 clocks = <&cru CORE_PERI>;
126 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
137 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
145 clocks = <&cru HCLK_OTG0>;
154 clocks = <&cru HCLK_OTG1>;
168 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
[all …]
Dimx53.dtsi53 clocks = <&clks IMX5_CLK_ARM>;
79 clocks {
119 clocks = <&clks IMX5_CLK_SATA_GATE>,
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
204 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
216 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
228 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
241 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
255 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
[all …]
Dwm8650.dtsi65 clocks {
84 clocks = <&ref25>;
91 clocks = <&ref25>;
98 clocks = <&ref25>;
105 clocks = <&ref25>;
112 clocks = <&ref25>;
119 clocks = <&plla>;
126 clocks = <&pllb>;
133 clocks = <&pllb>;
140 clocks = <&plld>;
[all …]
Datlas6.dtsi30 clocks = <&clks 12>;
87 clocks = <&clks 42>;
101 clocks = <&clks 5>;
108 clocks = <&clks 32>;
122 clocks = <&clks 34>;
133 clocks = <&clks 35>;
148 clocks = <&clks 32>;
162 clocks = <&clks 33>;
183 clocks = <&clks 9>;
191 clocks = <&clks 8>;
[all …]
Dzynq-7000.dtsi26 clocks = <&clkc 3>;
40 clocks = <&clkc 3>;
72 clocks = <&clkc 12>;
78 clocks = <&clkc 19>, <&clkc 36>;
90 clocks = <&clkc 20>, <&clkc 37>;
102 clocks = <&clkc 42>;
112 clocks = <&clkc 38>;
123 clocks = <&clkc 39>;
156 clocks = <&clkc 23>, <&clkc 40>;
165 clocks = <&clkc 24>, <&clkc 41>;
[all …]
Decx-common.dtsi52 clocks = <&eclk>;
60 clocks = <&pclk>;
70 clocks = <&pclk>;
81 clocks = <&pclk>;
92 clocks = <&pclk>;
103 clocks = <&pclk>;
112 clocks = <&pclk>;
120 clocks = <&pclk>;
128 clocks = <&pclk>;
145 clocks {
[all …]
Dsun6i-a31.dtsi71 clocks = <&pll6 0>;
79 clocks = <&pll6 0>;
136 clocks {
158 clocks = <&osc24M>;
166 clocks = <&osc24M>;
181 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
189 clocks = <&cpu>;
197 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
205 clocks = <&ahb1>;
226 clocks = <&ahb1>;
[all …]
Dvfxxx.dtsi90 clocks = <&clks VF610_CLK_DMAMUX0>,
99 clocks = <&clks VF610_CLK_FLEXCAN0>,
109 clocks = <&clks VF610_CLK_UART0>;
121 clocks = <&clks VF610_CLK_UART1>;
133 clocks = <&clks VF610_CLK_UART2>;
145 clocks = <&clks VF610_CLK_UART3>;
159 clocks = <&clks VF610_CLK_DSPI0>;
171 clocks = <&clks VF610_CLK_DSPI1>;
181 clocks = <&clks VF610_CLK_SAI2>;
193 clocks = <&clks VF610_CLK_PIT>;
[all …]
Dsun7i-a20.dtsi73 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
82 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
90 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
104 clocks = <&cpu>;
178 clocks {
202 clocks = <&osc24M>;
210 clocks = <&osc24M>;
218 clocks = <&osc24M>;
226 clocks = <&osc24M>;
234 clocks = <&osc24M>;
[all …]
Demev2.dtsi58 clocks@e0110000 {
71 clocks = <&c32ki>;
79 clocks = <&pll3_fo>;
85 clocks = <&pll3_fo>;
91 clocks = <&pll3_fo>;
97 clocks = <&pll3_fo>;
103 clocks = <&usia_u0_sclkdiv>;
109 clocks = <&usib_u1_sclkdiv>;
115 clocks = <&usib_u2_sclkdiv>;
121 clocks = <&usib_u3_sclkdiv>;
[all …]
Dtegra20.dtsi17 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
30 clocks = <&tegra_car TEGRA20_CLK_MPE>;
39 clocks = <&tegra_car TEGRA20_CLK_VI>;
48 clocks = <&tegra_car TEGRA20_CLK_EPP>;
57 clocks = <&tegra_car TEGRA20_CLK_ISP>;
66 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
74 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
83 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
100 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
117 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
[all …]
Dtegra30.dtsi39 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
95 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
108 clocks = <&tegra_car TEGRA30_CLK_MPE>;
117 clocks = <&tegra_car TEGRA30_CLK_VI>;
126 clocks = <&tegra_car TEGRA30_CLK_EPP>;
135 clocks = <&tegra_car TEGRA30_CLK_ISP>;
144 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
152 clocks = <&tegra_car TEGRA30_CLK_GR3D
164 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
183 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
[all …]
Dstih416-clock.dtsi13 clocks {
37 clocks = <&clk_sysin>;
49 clocks = <&clk_sysin>;
59 clocks = <&clk_s_a0_osc_prediv>,
74 clocks = <&clk_s_a0_osc_prediv>,
95 clocks = <&clk_sysin>;
107 clocks = <&clk_sysin>;
117 clocks = <&clk_s_a1_osc_prediv>,
132 clocks = <&clk_s_a1_osc_prediv>,
159 clocks = <&clk_sysin>;
[all …]
Datlas7.dtsi67 clocks = <&car 62>;
78 clocks = <&car 62>;
209 clocks = <&car 89>;
224 clocks = <&car 90>;
235 clocks = <&car 88>;
244 clocks = <&car 91>;
255 clocks = <&car 92>;
266 clocks = <&car 93>;
277 clocks = <&car 94>;
293 clocks = <&car 95>;
[all …]
Dprima2.dtsi32 clocks = <&clks 12>;
98 clocks = <&clks 42>;
112 clocks = <&clks 5>;
119 clocks = <&clks 32>;
139 clocks = <&clks 35>;
154 clocks = <&clks 32>;
168 clocks = <&clks 33>;
189 clocks = <&clks 9>;
197 clocks = <&clks 8>;
213 clocks = <&clks 11>;
[all …]
Dstih415-clock.dtsi12 clocks {
36 clocks = <&clk_sysin>;
48 clocks = <&clk_sysin>;
58 clocks = <&clk_s_a0_osc_prediv>,
73 clocks = <&clk_s_a0_osc_prediv>,
94 clocks = <&clk_sysin>;
106 clocks = <&clk_sysin>;
116 clocks = <&clk_s_a1_osc_prediv>,
131 clocks = <&clk_s_a1_osc_prediv>,
157 clocks = <&clk_sysin>;
[all …]
Dimx50.dtsi51 clocks {
105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
154 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
166 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
178 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
191 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
[all …]
Dtegra114.dtsi18 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
31 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
39 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
48 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
67 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
86 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
97 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
113 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
161 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
211 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
[all …]
Dintegratorcp.dts18 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
35 clocks = <&xtal_codec>;
74 clocks = <&xtal24mhz>;
83 clocks = <&xtal24mhz>;
92 clocks = <&xtal24mhz>;
104 clocks = <&xtal25mhz>;
110 clocks = <&timclk>;
116 clocks = <&timclk>;
159 clocks = <&pclk>;
165 clocks = <&uartclk>, <&pclk>;
[all …]
Dexynos3250.dtsi72 fixed-rate-clocks {
179 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
203 clocks = <&cmu CLK_TMU_APBIF>;
225 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
251 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
266 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
277 clocks = <&cmu CLK_USBOTG>;
288 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
300 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
312 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
[all …]
Dkirkwood.dtsi19 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
49 clocks = <&gate_clk 17>;
63 clocks = <&gate_clk 7>;
122 core_clk: core-clocks@10030 {
135 clocks = <&gate_clk 7>;
150 clocks = <&gate_clk 7>;
162 clocks = <&gate_clk 7>;
172 clocks = <&gate_clk 7>;
183 clocks = <&gate_clk 7>;
194 clocks = <&gate_clk 7>;
[all …]
Dimx6sx.dtsi73 clocks = <&clks IMX6SX_CLK_ARM>,
94 clocks {
146 clocks = <&clks IMX6SX_CLK_OCRAM>;
169 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
180 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
213 clocks = <&clks IMX6SX_CLK_SPDIF>,
234 clocks = <&clks IMX6SX_CLK_ECSPI1>,
246 clocks = <&clks IMX6SX_CLK_ECSPI2>,
258 clocks = <&clks IMX6SX_CLK_ECSPI3>,
270 clocks = <&clks IMX6SX_CLK_ECSPI4>,
[all …]
Dimx35.dtsi70 clocks = <&clks 51>;
81 clocks = <&clks 53>;
90 clocks = <&clks 9>, <&clks 70>;
99 clocks = <&clks 9>, <&clks 71>;
110 clocks = <&clks 52>;
121 clocks = <&clks 68>;
134 clocks = <&clks 35 &clks 35>;
156 clocks = <&clks 9>, <&clks 72>;
168 clocks = <&clks 36 &clks 36>;
176 clocks = <&clks 46>, <&clks 8>;
[all …]
Dsun9i-a80.dtsi117 clocks {
144 clocks = <&osc24M>;
152 clocks = <&osc24M>;
160 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
168 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
176 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
184 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
192 clocks = <&osc24M>, <&pll4>;
200 clocks = <&osc24M>, <&pll4>;
208 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
[all …]
Dhi3620.dtsi115 clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
125 clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
135 clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
145 clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
155 clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
170 clocks = <&clock HI3620_UARTCLK0>;
179 clocks = <&clock HI3620_UARTCLK1>;
188 clocks = <&clock HI3620_UARTCLK2>;
197 clocks = <&clock HI3620_UARTCLK3>;
206 clocks = <&clock HI3620_UARTCLK4>;
[all …]
Dat91sam9261.dtsi49 clocks {
78 clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>;
89 clocks = <&lcd_clk>, <&hclk1>;
122 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
130 clocks = <&udc_clk>, <&udpck>;
144 clocks = <&mci0_clk>;
157 clocks = <&twi0_clk>;
169 clocks = <&usart0_clk>;
182 clocks = <&usart1_clk>;
195 clocks = <&usart2_clk>;
[all …]
Dsun8i-a23.dtsi68 clocks = <&pll6 0>;
94 clocks {
117 clocks = <&osc24M>;
133 clocks = <&osc24M>;
148 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
156 clocks = <&cpu>;
164 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
172 clocks = <&ahb1>;
180 clocks = <&ahb1>;
196 clocks = <&apb1>;
[all …]
Domap36xx-clocks.dtsi14 clocks = <&sys_ck>, <&sys_ck>;
21 clocks = <&dpll4_m5x2_mul_ck>;
31 clocks = <&dpll4_m2x2_mul_ck>;
40 clocks = <&dpll3_m3x2_mul_ck>;
49 clocks = <&dpll4_m3x2_mul_ck>;
58 clocks = <&dpll4_m6x2_mul_ck>;
67 clocks = <&per_48m_fck>;
96 clocks = <&dpll4_ck>;
101 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
Dk2e-clocks.dtsi11 clocks {
15 clocks = <&refclksys>;
23 clocks = <&refclkpass>;
32 clocks = <&refclkddr3a>;
41 clocks = <&chipclk16>;
51 clocks = <&chipclk12>;
61 clocks = <&chipclk12>;
71 clocks = <&chipclk13>;
Dstih407-clock.dtsi10 clocks {
31 clocks = <&clk_m_a9>;
47 clocks = <&clk_sysin>;
54 * ARM CPU related clocks.
61 clocks = <&clockgen_a9_pll 0>,
74 clocks = <&clk_s_c0_flexgen 13>;
101 clocks = <&clk_sysin>;
111 clocks = <&clk_s_a0_pll 0>,
123 clocks = <&clk_sysin>;
139 clocks = <&clk_sysin>;
[all …]
Dstih416.dtsi94 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
107 clocks = <&clk_sysin>;
114 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
127 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
140 clocks = <&clk_sysin>;
153 clocks = <&clk_sysin>;
181 clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
203 clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
211 clocks = <&clk_sysin>;
235 clocks = <&clk_sysin>;
[all …]
Dat91sam9n12.dtsi53 clocks {
95 clocks = <&ddrck>;
120 clocks = <&main_xtal>;
127 clocks = <&main_rc_osc>, <&main_osc>;
134 clocks = <&main>;
151 clocks = <&plla>;
158 clocks = <&main>;
169 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
178 clocks = <&pllb>;
186 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
[all …]
Dimx6sl.dtsi58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
78 clocks {
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
148 clocks = <&clks IMX6SL_CLK_ECSPI1>,
160 clocks = <&clks IMX6SL_CLK_ECSPI2>,
172 clocks = <&clks IMX6SL_CLK_ECSPI3>,
184 clocks = <&clks IMX6SL_CLK_ECSPI4>,
195 clocks = <&clks IMX6SL_CLK_UART>,
208 clocks = <&clks IMX6SL_CLK_UART>,
221 clocks = <&clks IMX6SL_CLK_UART>,
[all …]
Dste-dbx5x0.dtsi52 clocks {
82 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
91 clocks = <&smp_twd_clk>;
99 clocks = <&rtc_clk>;
115 clocks = <&prcc_pclk 1 9>;
130 clocks = <&prcc_pclk 1 9>;
145 clocks = <&prcc_pclk 3 8>;
160 clocks = <&prcc_pclk 3 8>;
175 clocks = <&prcc_pclk 3 8>;
190 clocks = <&prcc_pclk 3 8>;
[all …]
Dvt8500.dtsi58 clocks {
71 clocks = <&ref24>;
79 clocks = <&ref24>;
87 clocks = <&ref24>;
95 clocks = <&ref24>;
135 clocks = <&clkuart0>;
143 clocks = <&clkuart1>;
151 clocks = <&clkuart2>;
159 clocks = <&clkuart3>;
Drk3288.dtsi75 clocks = <&cru ARMCLK>;
109 clocks = <&cru ACLK_DMAC2>;
119 clocks = <&cru ACLK_DMAC1>;
130 clocks = <&cru ACLK_DMAC1>;
156 clocks = <&xin24m>, <&cru PCLK_TIMER>;
168 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
179 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
190 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
201 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
214 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
[all …]
Dexynos5440.dtsi111 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
119 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
131 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
167 clocks = <&clock CLK_B_125>;
177 clocks = <&clock CLK_B_125>;
185 clocks = <&clock CLK_B_125>;
196 clocks = <&clock CLK_GMAC0>;
212 clocks = <&clock CLK_B_125>;
220 clocks = <&clock CLK_B_125>;
229 clocks = <&clock CLK_B_125>;
[all …]
Dqcom-ipq8064.dtsi64 clocks {
81 clocks = <&lcc AHBIX_CLK>,
122 clocks = <&sleep_clk>;
153 clocks = <&gcc GSBI2_H_CLK>;
167 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
177 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
191 clocks = <&gcc GSBI4_H_CLK>;
205 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
215 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
228 clocks = <&gcc GSBI5_H_CLK>;
[all …]
Dat91sam9263.dtsi51 clocks {
108 clocks = <&main_xtal>;
114 clocks = <&main_osc>;
121 clocks = <&main>;
133 clocks = <&main>;
145 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
154 clocks = <&pllb>;
162 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
197 clocks = <&usb>;
203 clocks = <&usb>;
[all …]
Darm-realview-pb1176.dts67 clocks = <&xtal24mhz>;
75 clocks = <&xtal24mhz>;
83 clocks = <&xtal24mhz>;
91 clocks = <&xtal24mhz>;
99 clocks = <&xtal24mhz>;
102 /* FIXME: this actually hangs off the PLL clocks */
220 clocks = <&timclk>, <&timclk>, <&pclk>;
230 clocks = <&timclk>, <&timclk>, <&pclk>;
239 clocks = <&pclk>;
252 clocks = <&pclk>;
[all …]
Darmada-38x.dtsi91 clocks = <&coreclk 0>;
101 clocks = <&coreclk 0>;
111 clocks = <&coreclk 0>;
121 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
157 clocks = <&coreclk 2>;
176 clocks = <&coreclk 0>;
187 clocks = <&coreclk 0>;
198 clocks = <&coreclk 0>;
209 clocks = <&coreclk 0>;
[all …]
Dtegra124.dtsi42 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
88 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
101 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
116 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
131 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
143 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
157 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
186 clocks = <&tegra_car TEGRA124_CLK_GPU>,
215 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
235 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
[all …]
Dberlin2q.dtsi77 clocks = <&chip CLKID_SDIO1XIN>;
85 clocks = <&chip CLKID_SDIO1XIN>;
94 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
115 clocks = <&chip CLKID_TWD>;
138 clocks = <&chip CLKID_USB2>;
163 clocks = <&chip CLKID_GETH0>;
270 clocks = <&chip CLKID_CFG>;
283 clocks = <&chip CLKID_CFG>;
292 clocks = <&chip CLKID_CFG>;
300 clocks = <&chip CLKID_CFG>;
[all …]
Dstih410-clock.dtsi10 clocks {
33 clocks = <&clk_m_a9>;
49 clocks = <&clk_sysin>;
56 * ARM CPU related clocks.
63 clocks = <&clockgen_a9_pll 0>,
76 clocks = <&clk_s_c0_flexgen 13>;
103 clocks = <&clk_sysin>;
113 clocks = <&clk_s_a0_pll 0>,
126 clocks = <&clk_sysin>;
142 clocks = <&clk_sysin>;
[all …]
Dstih418-clock.dtsi10 clocks {
33 clocks = <&clk_m_a9>;
49 clocks = <&clk_sysin>;
56 * ARM CPU related clocks.
63 clocks = <&clockgen_a9_pll 0>,
76 clocks = <&clk_s_c0_flexgen 13>;
103 clocks = <&clk_sysin>;
113 clocks = <&clk_s_a0_pll 0>,
126 clocks = <&clk_sysin>;
142 clocks = <&clk_sysin>;
[all …]
Darmada-370-xp.dtsi95 clocks = <&coreclk 0>;
105 clocks = <&coreclk 0>;
115 clocks = <&coreclk 0>;
125 clocks = <&coreclk 0>;
135 clocks = <&coreclk 0>;
158 clocks = <&coreclk 0>;
169 clocks = <&coreclk 0>;
179 clocks = <&coreclk 0>;
189 clocks = <&coreclk 0>;
199 clocks = <&coreclk 0>;
[all …]
Dimx6qdl.dtsi59 clocks {
99 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
110 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
127 clocks = <&clks IMX6QDL_CLK_TWD>;
160 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
193 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
212 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
226 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
240 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
254 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
[all …]
Darmada-375.dtsi67 clocks {
124 clocks = <&coreclk 0>;
134 clocks = <&coreclk 0>;
144 clocks = <&coreclk 0>;
154 clocks = <&coreclk 0>;
164 clocks = <&coreclk 0>;
190 clocks = <&coreclk 2>;
207 clocks = <&gateclk 19>;
217 clocks = <&gateclk 3>, <&gateclk 19>;
247 clocks = <&coreclk 0>;
[all …]
Dexynos4415.dtsi191 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
249 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
264 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
275 clocks = <&cmu CLK_USBDEVICE>;
286 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
298 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
310 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
322 clocks = <&cmu CLK_USBHOST>;
348 clocks = <&cmu CLK_USBHOST>;
365 clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
[all …]
Dimx1.dtsi49 clocks = <&clks IMX1_CLK_MCU>;
72 clocks = <&clks IMX1_CLK_HCLK>,
81 clocks = <&clks IMX1_CLK_HCLK>,
90 clocks = <&clks IMX1_CLK_DUMMY>,
101 clocks = <&clks IMX1_CLK_HCLK>,
111 clocks = <&clks IMX1_CLK_HCLK>,
122 clocks = <&clks IMX1_CLK_DUMMY>,
131 clocks = <&clks IMX1_CLK_HCLK>,
141 clocks = <&clks IMX1_CLK_UART3_GATE>,
161 clocks = <&clks IMX1_CLK_DUMMY>,
[all …]
Dkeystone.dtsi86 /include/ "keystone-clocks.dtsi"
94 clocks = <&clkuart0>;
104 clocks = <&clkuart1>;
112 clocks = <&clki2c>;
122 clocks = <&clki2c>;
132 clocks = <&clki2c>;
144 clocks = <&clkspi>;
155 clocks = <&clkspi>;
166 clocks = <&clkspi>;
184 clocks = <&clkusb>;
[all …]
Dbcm21664.dtsi67 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
77 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
87 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
109 clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
130 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
138 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
146 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
154 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
164 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
174 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
[all …]
Dat91sam9x5.dtsi55 clocks {
103 clocks = <&ddrck>;
128 clocks = <&main_xtal>;
135 clocks = <&main_rc_osc>, <&main_osc>;
142 clocks = <&main>;
159 clocks = <&plla>;
166 clocks = <&main>;
173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
182 clocks = <&plladiv>, <&utmi>;
190 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
[all …]
Dhip04.dtsi232 clocks = <&clk_50m>, <&clk_50m>;
260 clocks = <&clk_168m>;
278 clocks = <&clk_375m>;
292 clocks = <&clk_375m>;
306 clocks = <&clk_375m>;
320 clocks = <&clk_375m>;
334 clocks = <&clk_375m>;
492 clocks = <&clk_375m>;
546 clocks = <&clk_375m>;
600 clocks = <&clk_375m>;
[all …]
Dberlin2.dtsi59 clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
68 clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
78 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
108 clocks = <&chip CLKID_TWD>;
114 clocks = <&chip CLKID_GETH1>;
137 clocks = <&chip CLKID_GETH0>;
236 clocks = <&chip CLKID_CFG>;
245 clocks = <&chip CLKID_CFG>;
254 clocks = <&chip CLKID_CFG>;
263 clocks = <&chip CLKID_CFG>;
[all …]
Ddove.dtsi72 clocks = <&gate_clk 4>;
90 clocks = <&gate_clk 5>;
120 clocks = <&core_clk 0>;
134 clocks = <&core_clk 0>;
143 clocks = <&core_clk 0>;
152 clocks = <&core_clk 0>;
163 clocks = <&core_clk 0>;
172 clocks = <&core_clk 0>;
183 clocks = <&core_clk 0>;
218 clocks = <&core_clk 0>;
[all …]
Dat91sam9g45.dtsi57 clocks {
105 clocks = <&ddrck>;
112 clocks = <&ddrck>;
129 clocks = <&main_xtal>;
135 clocks = <&main_osc>;
142 clocks = <&main>;
159 clocks = <&plla>;
166 clocks = <&main>;
173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
181 clocks = <&plladiv>, <&utmi>;
[all …]
Dat91rm9200.dtsi55 clocks {
112 clocks = <&main_xtal>;
118 clocks = <&main_osc>;
125 clocks = <&main>;
137 clocks = <&main>;
149 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
158 clocks = <&pllb>;
166 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
201 clocks = <&usb>;
207 clocks = <&usb>;
[all …]
Dat91sam9260.dtsi52 clocks {
115 clocks = <&main_xtal>;
121 clocks = <&main_osc>;
134 clocks = <&slow_rc_osc>, <&slow_xtal>;
141 clocks = <&main>;
153 clocks = <&main>;
164 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
173 clocks = <&pllb>;
181 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
204 clocks = <&usb>;
[all …]
Dstih407-family.dtsi47 clocks = <&arm_periph_clk>;
122 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
133 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
144 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
156 clocks = <&clk_sysin>;
167 clocks = <&clk_sysin>;
176 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
189 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
202 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
215 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
[all …]
Dberlin2cd.dtsi56 clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
80 clocks = <&chip CLKID_TWD>;
102 clocks = <&chip CLKID_GETH1>;
120 clocks = <&chip CLKID_GETH0>;
219 clocks = <&chip CLKID_CFG>;
228 clocks = <&chip CLKID_CFG>;
237 clocks = <&chip CLKID_CFG>;
246 clocks = <&chip CLKID_CFG>;
255 clocks = <&chip CLKID_CFG>;
264 clocks = <&chip CLKID_CFG>;
[all …]
Dls1021a.dtsi73 clocks = <&cluster1_clk>;
80 clocks = <&cluster1_clk>;
163 clocks = <&sysclk>;
172 clocks = <&sysclk>;
181 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
193 clocks = <&platform_clk 1>;
206 clocks = <&platform_clk 1>;
219 clocks = <&platform_clk 1>;
230 clocks = <&platform_clk 1>;
241 clocks = <&platform_clk 1>;
[all …]
Domap36xx.dtsi52 clocks = <&sys_ck>;
94 clocks = <&dss_tv_fck>, <&dss_96m_fck>;
101 clocks = <&ssi_ssr_fck>,
109 /include/ "omap34xx-omap36xx-clocks.dtsi"
110 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
111 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
112 /include/ "omap36xx-clocks.dtsi"
Dpxa168.dtsi63 clocks = <&soc_clocks PXA168_CLK_UART0>;
72 clocks = <&soc_clocks PXA168_CLK_UART1>;
81 clocks = <&soc_clocks PXA168_CLK_UART2>;
94 clocks = <&soc_clocks PXA168_CLK_GPIO>;
122 clocks = <&soc_clocks PXA168_CLK_TWSI0>;
132 clocks = <&soc_clocks PXA168_CLK_TWSI1>;
142 clocks = <&soc_clocks PXA168_CLK_RTC>;
148 soc_clocks: clocks{
Dsama5d3.dtsi62 clocks {
110 clocks = <&mci0_clk>;
125 clocks = <&spi0_clk>;
139 clocks = <&ssc0_clk>;
148 clocks = <&tcb0_clk>;
163 clocks = <&twi0_clk>;
178 clocks = <&twi1_clk>;
191 clocks = <&usart0_clk>;
205 clocks = <&usart1_clk>;
216 clocks = <&uart0_clk>;
[all …]
Darmada-39x.dtsi118 clocks = <&coreclk 2>;
137 clocks = <&coreclk 0>;
148 clocks = <&coreclk 0>;
159 clocks = <&coreclk 0>;
170 clocks = <&coreclk 0>;
181 clocks = <&coreclk 0>;
192 clocks = <&coreclk 0>;
202 clocks = <&coreclk 0>;
212 clocks = <&coreclk 0>;
222 clocks = <&coreclk 0>;
[all …]
Dsama5d4.dtsi92 clocks {
130 clocks = <&udphs_clk>, <&utmi>;
257 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
267 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
306 clocks = <&hsmc_clk>;
321 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
350 clocks = <&dma1_clk>;
360 clocks = <&isi_clk>;
372 clocks = <&ddrck>, <&mpddr_clk>;
381 clocks = <&dma0_clk>;
[all …]
Dbcm11351.dtsi67 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
77 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
87 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
97 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
119 clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
142 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
150 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
158 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
166 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
181 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
[all …]
Dstih415.dtsi85 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
94 clocks = <&clk_sysin>;
103 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
116 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
129 clocks = <&clk_sysin>;
142 clocks = <&clk_sysin>;
173 clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
196 clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
203 clocks = <&clk_sysin>;
215 clocks = <&clk_sysin>;
[all …]
Dat91sam9rl.dtsi53 clocks {
90 clocks = <&lcd_clk>, <&lcd_clk>;
124 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
135 clocks = <&mci0_clk>;
146 clocks = <&twi0_clk>;
167 clocks = <&usart0_clk>;
180 clocks = <&usart1_clk>;
193 clocks = <&usart2_clk>;
206 clocks = <&usart3_clk>;
234 clocks = <&pwm_clk>;
[all …]
Dintegratorap.dts34 clocks = <&xtal24mhz>;
54 clocks = <&xtal24mhz>;
59 clocks = <&xtal24mhz>;
64 clocks = <&xtal24mhz>;
121 clocks = <&pclk>;
128 clocks = <&uartclk>, <&pclk>;
135 clocks = <&uartclk>, <&pclk>;
142 clocks = <&xtal24mhz>, <&pclk>;
149 clocks = <&xtal24mhz>, <&pclk>;
Dhip01.dtsi52 clocks = <&hisi_refclk144mhz>;
62 clocks = <&hisi_refclk144mhz>;
72 clocks = <&hisi_refclk144mhz>;
82 clocks = <&hisi_refclk144mhz>;
100 clocks = <&hisi_refclk144mhz>;
107 clocks = <&hisi_refclk144mhz>;
Dpxa910.dtsi75 clocks = <&soc_clocks PXA910_CLK_UART0>;
84 clocks = <&soc_clocks PXA910_CLK_UART1>;
93 clocks = <&soc_clocks PXA910_CLK_UART2>;
107 clocks = <&soc_clocks PXA910_CLK_GPIO>;
136 clocks = <&soc_clocks PXA910_CLK_TWSI0>;
148 clocks = <&soc_clocks PXA910_CLK_TWSI1>;
158 clocks = <&soc_clocks PXA910_CLK_RTC>;
164 soc_clocks: clocks{
Dimx31.dtsi58 clocks = <&clks 10>, <&clks 30>;
67 clocks = <&clks 10>, <&clks 31>;
75 clocks = <&clks 10>, <&clks 49>;
85 clocks = <&clks 10>, <&clks 50>;
102 clocks = <&clks 10>, <&clks 48>;
111 clocks = <&clks 25>;
133 clocks = <&clks 10>, <&clks 22>;
Dstih410.dtsi36 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
50 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
62 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
76 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
102 assigned-clocks = <&clk_s_d2_quadfs 0>,
139 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
164 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
192 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
214 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
Daxm55xx.dtsi28 clocks {
119 clocks = <&clks AXXIA_CLK_PER>;
128 clocks = <&clks AXXIA_CLK_PER>;
137 clocks = <&clks AXXIA_CLK_PER>;
146 clocks = <&clks AXXIA_CLK_PER>;
163 clocks = <&clks AXXIA_CLK_PER>;
181 clocks = <&clks AXXIA_CLK_PER>;
192 clocks = <&clks AXXIA_CLK_PER>;
Darmada-xp.dtsi110 clocks = <&coreclk 0>;
122 clocks = <&coreclk 0>;
134 clocks = <&coreclk 0>;
155 clocks = <&coreclk 1>;
164 clocks = <&coreclk 2>, <&refclk>;
170 clocks = <&coreclk 2>, <&refclk>;
183 clocks = <&gateclk 2>;
188 clocks = <&gateclk 18>;
192 clocks = <&gateclk 19>;
199 clocks = <&gateclk 20>;
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.txt3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
17 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
18 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
19 - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
20 - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
[all …]
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
[all …]
Dexynos5260-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
26 Phy clocks:
28 There are several clocks which are generated by specific PHYs.
29 These clocks are fed into the clock controller and then routed to
30 the hardware blocks. These clocks are defined as fixed clocks in the
71 - clocks: list of clock identifiers which are fed as the input to
73 the input clocks for a given controller.
[all …]
Drenesas,rcar-gen2-cpg-clocks.txt3 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
9 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
10 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
11 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
12 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
13 - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
17 - clocks: References to the parent clocks: first to the EXTAL clock, second
20 - clock-output-names: The names of the clocks. Supported clocks are "main",
29 compatible = "renesas,r8a7790-cpg-clocks",
30 "renesas,rcar-gen2-cpg-clocks";
[all …]
Drenesas,rz-cpg-clocks.txt3 The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
4 CPU and GPU clocks, and several fixed ratio dividers.
9 - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
10 - "renesas,rz-cpg-clocks" for the generic RZ CPG
12 - clocks: References to possible parent clocks. Order must match clock modes
15 - clock-output-names: The names of the clocks. Supported clocks are "pll",
24 compatible = "renesas,r7s72100-cpg-clocks",
25 "renesas,rz-cpg-clocks";
27 clocks = <&extal_clk>, <&usb_x1_clk>;
Drenesas,cpg-div6-clocks.txt3 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
10 - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11 - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
12 - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
13 - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
14 - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
15 - "renesas,cpg-div6-clock" for generic DIV6 clocks
17 - clocks: Reference to the parent clock(s); either one, four, or eight
18 clocks must be specified. For clocks with multiple parents, invalid
30 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
Dexynos7-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
45 - clocks: list of clock identifiers which are fed as the input to
47 find the input clocks for a given controller.
49 - clock-names: list of names of clocks which are fed as the input
52 Input clocks for top0 clock controller:
60 Input clocks for top1 clock controller:
67 Input clocks for ccore clock controller:
[all …]
Dvf610-clock.txt9 - clocks: list of clock identifiers which are external input clocks to the
11 the input clocks for a given controller.
12 - clock-names: list of names of clocks which are exteral input clocks to the
15 Input clocks for top clock controller:
22 ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
31 clocks = <&sxosc>, <&fxosc>;
39 clocks = <&clks VF610_CLK_UART1>;
Drenesas,r8a73a4-cpg-clocks.txt3 The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
8 - compatible: Must be "renesas,r8a73a4-cpg-clocks"
12 - clocks: Reference to the parent clocks ("extal1" and "extal2")
16 - clock-output-names: The names of the clocks. Supported clocks are "main",
25 compatible = "renesas,r8a73a4-cpg-clocks";
27 clocks = <&extal1_clk>, <&extal2_clk>;
Drenesas,sh73a0-cpg-clocks.txt5 The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
10 - compatible: Must be "renesas,sh73a0-cpg-clocks"
14 - clocks: Reference to the parent clocks ("extal1" and "extal2")
18 - clock-output-names: The names of the clocks. Supported clocks are "main",
27 compatible = "renesas,sh73a0-cpg-clocks";
29 clocks = <&extal1_clk>, <&extal2_clk>;
Dat91-clock.txt25 All at91 specific clocks (clocks defined below) must be child
47 at91 peripheral clocks
53 at91 pll clocks
61 at91 programmable clocks
67 at91 system clocks
93 /* put at91 slow clocks here */
113 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
123 clocks = <&slow_xtal>;
128 - clocks : shall encode the slow clk sources (see atmel datasheet).
134 clocks = <&slow_rc_osc &slow_osc>;
[all …]
Dsamsung,s3c2412-clock.txt15 to specify the clock which they consume. Some of the clocks are available only
18 All available clocks are defined as preprocessor macros in
22 External clocks:
24 There are several clocks that are generated outside the SoC. It is expected
32 clocks: clock-controller@4c000000 {
40 "clocks" and "clock-names" properties):
47 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
48 <&clocks SCLK_UART>;
Drenesas,r8a7779-cpg-clocks.txt3 The CPG generates core clocks for the R8A7779. It includes one PLL and
8 - compatible: Must be "renesas,r8a7779-cpg-clocks"
11 - clocks: Reference to the parent clock
13 - clock-output-names: The names of the clocks. Supported clocks are "plla",
21 compatible = "renesas,r8a7779-cpg-clocks";
23 clocks = <&extal_clk>;
Drenesas,r8a7740-cpg-clocks.txt5 The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
10 - compatible: Must be "renesas,r8a7740-cpg-clocks"
14 - clocks: Reference to the three parent clocks
16 - clock-output-names: The names of the clocks. Supported clocks are
27 compatible = "renesas,r8a7740-cpg-clocks";
29 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
Dclk-s5pv210-audss.txt3 The Samsung Audio Subsystem clock controller generates and supplies clocks
13 - clocks:
23 - clock-names: Aliases for the above clocks. They should be "hclk",
26 All available clocks are defined as preprocessor macros in
38 clocks = <&clocks DOUT_HCLKP>, <&xxti>,
39 <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
44 about 'clocks' and 'clock-names' property.
50 clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
Dsamsung,s5pv210-clock.txt20 All available clocks are defined as preprocessor macros in
23 External clocks:
25 There are several clocks that are generated outside the SoC. It is expected
33 A subset of above clocks available on given board shall be specified in
36 documentation[1] for more information how to specify these clocks.
48 Example: Required external clocks:
66 "clocks" and "clock-names" properties):
75 clocks = <&clocks UART0>, <&clocks UART0>,
76 <&clocks SCLK_UART0>;
Dsamsung,s3c2443-clock.txt18 to specify the clock which they consume. Some of the clocks are available only
21 All available clocks are defined as preprocessor macros in
25 External clocks:
27 There are several clocks that are generated outside the SoC. It is expected
37 clocks: clock-controller@4c000000 {
45 "clocks" and "clock-names" properties):
53 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
54 <&clocks SCLK_UART>;
Dpistachio-clock.txt8 External clocks:
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
28 - clocks: Must contain an entry for each clock in clock-names.
29 - clock-names: Must include "xtal" (see "External clocks") and
37 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
57 - clocks: Must contain an entry for each clock in clock-names.
65 clocks = <&clk_core CLK_PERIPH_SYS>;
74 The peripheral general control block generates system interface clocks and
85 - clocks: Must contain an entry for each clock in clock-names.
[all …]
Demev2-clock.txt7 This is not a clock provider, but clocks under SMU depend on it.
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
34 - clocks: Input clock as described in clock-bindings.txt
42 clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
49 clocks = <&usia_u0_sclkdiv>;
59 clocks = <&usia_u0_sclk>;
81 clocks = <&c32ki>;
89 clocks = <&pll3_fo>;
95 clocks = <&usia_u0_sclkdiv>;
Drenesas,r8a7778-cpg-clocks.txt3 The CPG generates core clocks for the R8A7778. It includes two PLLs and
8 - compatible: Must be "renesas,r8a7778-cpg-clocks"
11 - clock-output-names: The names of the clocks. Supported clocks are
19 compatible = "renesas,r8a7778-cpg-clocks";
22 clocks = <&extal_clk>;
Dste-u300-syscon-clock.txt3 Bindings for the gated system controller clocks:
15 - clocks: parent clock(s)
17 The available clocks per type are as follows:
50 clocks = <&slow_clk>;
56 clocks = <&gpio_clk>;
67 - clocks: parent clock(s)
72 clocks = <&mmc_pclk>;
77 clocks = <&mmc_pclk>, <&mmc_mclk>;
Dqoriq-clock.txt34 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
35 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
58 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
59 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
60 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
61 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
70 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
71 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
78 - clocks: Should be the phandle of input parent clock
81 output clocks
[all …]
Dvt8500.txt15 Required properties for PLL clocks:
17 - clocks : shall be the input parent clock phandle for the clock. This should
21 Required properties for device clocks:
22 - clocks : shall be the input parent clock phandle for the clock. This should
29 Device clocks are required to have one or both of the following sets of
33 Gated device clocks:
41 Divisor device clocks:
62 clocks = <&ref25>;
69 clocks = <&pllb>;
Dsamsung,s3c2410-clock.txt18 to specify the clock which they consume. Some of the clocks are available only
21 All available clocks are defined as preprocessor macros in
25 External clocks:
33 clocks: clock-controller@4c000000 {
41 "clocks" and "clock-names" properties):
48 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
Dclock-bindings.txt44 clocks by index. The names should reflect the clock output signal
47 clock-indices: If the identifying number for the clocks in the node
51 For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
66 clocks: List of phandle and clock specifier pairs, one pair
73 order as the clocks property. Consumers drivers
75 with clocks specifiers.
77 clocks from this node. Useful for bus nodes to provide a
83 clocks = <&osc 1>, <&ref 0>;
107 clocks = <&osc 0>;
120 clocks = <&osc 0>, <&pll 1>;
[all …]
Dnvidia,tegra124-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
19 (for Tegra124-specific clocks).
35 clocks = <&tegra_car TEGRA124_CLK_USB2>;
42 clocks {
63 clocks = <&clk_32k> <&osc>;
Dsunxi.txt24 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
60 "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
62 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
63 "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
65 "allwinner,sun7i-a20-out-clk" - for the external output clocks
73 Required properties for all clocks:
75 - clocks : shall be the input parent clock(s) phandle for the clock. For
76 multiplexed clocks, the list order must match the hardware
88 And "allwinner,*-usb-clk" clocks also require:
95 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
[all …]
Dclk-exynos-audss.txt3 The Samsung Audio Subsystem clock controller generates and supplies clocks
19 - clocks:
31 - clock-names: Aliases for the above clocks. They should be "pll_ref",
34 The following is the list of clocks generated by the controller. Each clock is
36 clock which they consume. Some of the clocks are available only on a particular
39 Provided clocks:
65 Example 2: An example of a clock controller node with the input clocks
72 clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
79 about 'clocks' and 'clock-names' property.
88 clocks = <&clock_audss EXYNOS_I2S_BUS>,
Dsamsung,s3c64xx-clock.txt19 to specify the clock which they consume. Some of the clocks are available only
22 All available clocks are defined as preprocessor macros in
26 External clocks:
28 There are several clocks that are generated outside the SoC. It is expected
47 Example: Required external clocks:
65 "clocks" and "clock-names" properties):
74 clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
Dnvidia,tegra30-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
33 clocks = <&tegra_car TEGRA30_CLK_USB2>;
40 clocks {
61 clocks = <&clk_32k> <&osc>;
Dnvidia,tegra20-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
33 clocks = <&tegra_car TEGRA20_CLK_USB2>;
40 clocks {
61 clocks = <&clk_32k> <&osc>;
Dnvidia,tegra114-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
33 clocks = <&tegra_car TEGRA114_CLK_USB2>;
40 clocks {
61 clocks = <&clk_32k> <&osc>;
Drockchip.txt7 == Gate clocks ==
15 the 10 individual gates containing 16 clocks each.
23 - clocks : should contain the parent clock for each individual gate,
24 therefore the number of clocks elements should match the number of
27 Example using multiple gate clocks:
32 clocks = <&dummy>, <&dummy>,
57 clocks = <&xin24m>, <&xin24m>,
Dxgene.txt13 Required properties for SoC or PCP PLL clocks:
15 - clocks : shall be the input parent clock phandle for the clock. This should
20 Optional properties for PLL clocks:
23 Required properties for device clocks:
31 - clocks : shall be the input parent clock phandle for the clock.
34 Optional properties for device clocks:
53 clocks = <&refclk 0>;
63 clocks = <&refclk 0>;
73 clocks = <&socplldiv2 0>;
83 clocks = <&socplldiv2 0>;
[all …]
Dmvebu-core-clock.txt5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
47 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
48 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
49 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
50 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
51 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
52 "marvell,dove-core-clock" - for Dove SoC core clocks
67 core_clk: core-clocks@d0214 {
77 clocks = <&core_clk 0>;
Dkeystone-pll.txt16 - clocks : parent clock phandle
27 clocks = <&refclksys>;
36 clocks = <&refclkpass>;
45 - clocks : link phandles of parent clocks
57 clocks = <&mainpllclk>, <&refclkmain>;
67 - clocks : parent clock phandle
79 clocks = <&mainmuxclk>;
Dbcm-cygnus-clock.txt6 Currently various "fixed" clocks are declared for peripheral drivers that use
7 the common clock framework to reference their core clocks. Proper support of
8 these clocks will be added later
12 clocks {
Dmvebu-cpu-clock.txt5 "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
9 - clocks : shall be the input parent clock phandle for the clock.
15 clocks = <&coreclk 1>;
21 clocks = <&cpuclk 0>;
/linux-4.1.27/Documentation/devicetree/bindings/gpu/
Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
67 - clocks: from common clock binding: handle hardware IP needed clocks, the
68 number of clocks may depend of the SoC type.
[all …]
Dnvidia,tegra20-host1x.txt12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
28 - clocks: Must contain one entry, for the module clock.
29 See ../clocks/clock-bindings.txt for details.
41 - clocks: Must contain one entry, for the module clock.
42 See ../clocks/clock-bindings.txt for details.
54 - clocks: Must contain one entry, for the module clock.
55 See ../clocks/clock-bindings.txt for details.
67 - clocks: Must contain one entry, for the module clock.
68 See ../clocks/clock-bindings.txt for details.
[all …]
Dsamsung-g2d.txt13 - clocks : from common clock binding: handle to G2D clocks.
14 - clock-names : names of clocks listed in clocks property, in the same
25 clocks = <&clock 177>, <&clock 277>;
/linux-4.1.27/drivers/clk/bcm/
Dclk-bcm281xx.c27 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
52 .clocks = CLOCKS("ref_crystal",
61 .clocks = CLOCKS("var_312m",
85 .clocks = CLOCKS("ref_crystal",
104 .clocks = CLOCKS("ref_crystal",
116 .clocks = CLOCKS("ref_crystal",
128 .clocks = CLOCKS("ref_crystal",
140 .clocks = CLOCKS("ref_crystal",
152 .clocks = CLOCKS("ref_crystal",
[all …]
Dclk-bcm21664.c25 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
67 .clocks = CLOCKS("ref_crystal",
79 .clocks = CLOCKS("ref_crystal",
91 .clocks = CLOCKS("ref_crystal",
103 .clocks = CLOCKS("ref_crystal",
114 .clocks = CLOCKS("ref_32k"), /* Verify */
119 .clocks = CLOCKS("ref_32k"), /* Verify */
124 .clocks = CLOCKS("ref_32k"), /* Verify */
129 .clocks = CLOCKS("ref_32k"), /* Verify */
[all …]
/linux-4.1.27/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi107 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
120 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
133 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
141 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
151 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
163 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
171 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
181 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
192 clocks = <&clock_peric0 PCLK_UART0>,
202 clocks = <&clock_peric1 PCLK_UART1>,
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/clock/ti/
Ddra7-atl.txt5 functional clock but can be configured to provide different clocks.
9 In order to provide the support for ATL and it's output clocks (which can be used
14 To be able to integrate the ATL clocks with DT clock tree.
15 Provides ccf level representation of the ATL clocks to be used by drivers.
25 - clocks : link phandles to functional clock of ATL
34 - ti,provided-clocks : List of phandles to the clocks associated with the ATL
35 - clocks : link phandles to functional clock of ATL
50 /* clock bindings for atl provided clocks */
54 clocks = <&atl_gfclk_mux>;
60 clocks = <&atl_gfclk_mux>;
[all …]
Dcomposite.txt16 The binding must provide a list of the component clocks that shall be
17 merged to this clock. The component clocks shall be of one of the
27 - clocks : link phandles of component clocks
35 clocks = <&l4_ick>;
43 clocks = <&l4_ick>;
53 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
Dgate.txt34 - clocks : link to phandle of parent clock
48 clocks = <&core_96m_fck>;
56 clocks = <&core_48m_fck>;
64 clocks = <&dpll4_m4x2_ck>;
72 clocks = <&ipss_ick>;
80 clocks = <&emu_src_mux_ck>;
86 clocks = <&dpll4_m2x2_mul_ck>;
95 clocks = <&core_ck>;
103 clocks = <&core_ck>;
Dmux.txt10 By default the "clocks" property lists the parents in the same order
13 clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
41 - clocks : link phandles of parent clocks
57 …clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&vir…
65 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
73 clocks = <&core_96m_fck>, <&mcbsp_clks>;
/linux-4.1.27/arch/powerpc/boot/dts/
Dmpc5121.dtsi54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
71 clocks = <&clks MPC512x_CLK_NFC>;
84 clocks {
143 clocks = <&osc>;
164 clocks = <&clks MPC512x_CLK_BDLC>,
176 clocks = <&clks MPC512x_CLK_BDLC>,
190 clocks = <&clks MPC512x_CLK_IPS>,
201 clocks = <&clks MPC512x_CLK_I2C>;
211 clocks = <&clks MPC512x_CLK_I2C>;
221 clocks = <&clks MPC512x_CLK_I2C>;
[all …]
Dmpc5125twr.dts59 clocks {
107 clocks = <&osc>;
133 clocks = <&clks MPC512x_CLK_BDLC>,
145 clocks = <&clks MPC512x_CLK_BDLC>,
157 clocks = <&clks MPC512x_CLK_IPS>,
168 clocks = <&clks MPC512x_CLK_I2C>;
178 clocks = <&clks MPC512x_CLK_I2C>;
188 clocks = <&clks MPC512x_CLK_I2C>;
201 clocks = <&clks MPC512x_CLK_DIU>;
222 clocks = <&clks MPC512x_CLK_FEC>;
[all …]
/linux-4.1.27/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi111 clocks = <&misc_clk>;
121 clocks = <&misc_clk>;
131 clocks = <&misc_clk>;
141 clocks = <&misc_clk>;
152 clocks = <&misc_clk &misc_clk>;
162 clocks = <&misc_clk &misc_clk>;
169 clocks = <&misc_clk>;
182 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
194 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
206 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/serial/
Dcdns,uart.txt7 - clocks: Must contain phandles to the UART clocks
8 See ../clocks/clock-bindings.txt for details.
9 - clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
10 See ../clocks/clock-bindings.txt for details.
16 clocks = <&clkc 23>, <&clkc 40>;
Dsamsung_uart.txt21 - clock-names: input names of clocks used by the controller:
26 - clocks: phandles and specifiers for all clocks specified in "clock-names"
55 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
56 <&clocks SCLK_UART>;
/linux-4.1.27/arch/arm/mach-w90x900/
Dclock.c66 unsigned int clocks = clk->cken; in nuc900_clk_enable() local
72 clken |= clocks; in nuc900_clk_enable()
74 clken &= ~clocks; in nuc900_clk_enable()
81 unsigned int clocks = clk->cken; in nuc900_subclk_enable() local
87 clken |= clocks; in nuc900_subclk_enable()
89 clken &= ~clocks; in nuc900_subclk_enable()
/linux-4.1.27/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi73 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
83 clocks = <&v2m_clk24mhz>;
95 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
103 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
111 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
119 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
127 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
135 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
143 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
151 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
[all …]
Djuno-motherboard.dtsi65 clocks = <&mb_clk25mhz>;
86 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
100 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
108 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
116 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
124 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
132 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
140 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
148 clocks = <&soc_smc50mhz>;
/linux-4.1.27/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi107 clocks {
121 clocks = <&refclk 0>;
131 clocks = <&refclk 0>;
141 clocks = <&socpll 0>;
151 clocks = <&socplldiv2 0>;
161 clocks = <&socplldiv2 0>;
174 clocks = <&ethclk 0>;
183 clocks = <&socplldiv2 0>;
193 clocks = <&socplldiv2 0>;
203 clocks = <&socplldiv2 0>;
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/input/touchscreen/
Dstmpe.txt8 - st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 ->
9 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6
10 -> 144 clocks), recommended is 4.
/linux-4.1.27/arch/powerpc/boot/dts/fsl/
Dt4240si-pre.dtsi71 clocks = <&mux0>;
78 clocks = <&mux0>;
85 clocks = <&mux0>;
92 clocks = <&mux0>;
99 clocks = <&mux1>;
106 clocks = <&mux1>;
113 clocks = <&mux1>;
120 clocks = <&mux1>;
127 clocks = <&mux2>;
134 clocks = <&mux2>;
[all …]
/linux-4.1.27/drivers/clk/
Dclk-max-gen.c114 struct clk **clocks; in max_gen_clk_probe() local
119 clocks = devm_kzalloc(dev, sizeof(struct clk *) * num_init, GFP_KERNEL); in max_gen_clk_probe()
120 if (!clocks) in max_gen_clk_probe()
150 clocks[i] = max_gen_clk_register(dev, &max_gen_clks[i]); in max_gen_clk_probe()
151 if (IS_ERR(clocks[i])) { in max_gen_clk_probe()
152 ret = PTR_ERR(clocks[i]); in max_gen_clk_probe()
159 platform_set_drvdata(pdev, clocks); in max_gen_clk_probe()
168 of_data->clks = clocks; in max_gen_clk_probe()
/linux-4.1.27/Documentation/devicetree/bindings/crypto/
Dqcom-qce.txt7 - clocks : phandle to clock-controller plus clock-specifier pair
8 - clock-names : "iface" clocks register interface
9 "bus" clocks data transfer interface
10 "core" clocks rest of the crypto block
19 clocks = <&gcc GCC_CE2_AHB_CLK>,
/linux-4.1.27/Documentation/devicetree/bindings/drm/msm/
Dmdp.txt9 - clocks: device clocks
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: the following clocks are required:
40 clocks =
Dgpu.txt7 - clocks: device clocks
8 See ../clocks/clock-bindings.txt for details.
9 - clock-names: the following clocks are required:
37 clocks =
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dimg-ir-rev1.txt13 - clocks: List of clock specifiers as described in standard
15 Up to 3 clocks may be specified in the following order:
19 - clock-names: List of clock names corresponding to the clocks
20 specified in the clocks property.
32 clocks = <&clk_32khz>;
/linux-4.1.27/arch/xtensa/boot/dts/
Dxtfpga.dtsi38 clocks {
64 clocks = <&osc>;
72 clocks = <&osc>;
80 clocks = <&cdce706 4>;
91 clocks = <&osc>;
97 clocks = <&clk54>;
130 clocks = <&cdce706 4>;
/linux-4.1.27/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.txt5 - clocks: A list of phandle + clock-specifier pairs for the
6 clocks listed in clock-names
11 Optional clocks:
28 clocks = <&gcc USB30_0_UTMI_CLK>;
38 clocks = <&gcc USB30_0_MASTER_CLK>;
49 clocks = <&gcc USB30_0_MASTER_CLK>;
/linux-4.1.27/arch/arc/boot/dts/
Dabilis_tb10x.dtsi54 clocks = <&pll0>;
60 clocks = <&pll0>;
100 clocks = <&ahb_clk>;
116 clocks = <&ahb_clk>;
127 clocks = <&ahb_clk>;
136 clocks = <&ahb_clk>;
145 clocks = <&ahb_clk>;
154 clocks = <&ahb_clk>;
163 clocks = <&ahb_clk>;
175 clocks = <&ahb_clk>;
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/video/
Drenesas,du.txt20 - clocks: A list of phandles + clock-specifier pairs, one for each entry in
22 - clock-names: Name of the clocks. This property is model-dependent.
26 per LVDS encoder. The functional clocks must be named "du.x" with "x"
27 being the channel numerical index. The LVDS clocks must be named
29 - In addition to the functional and encoder clocks, all DU versions also
30 support externally supplied pixel clocks. Those clocks are optional.
61 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
/linux-4.1.27/Documentation/devicetree/bindings/timer/
Darm,sp804.txt11 - clocks: clocks driving the dual timer hardware. This list should be 1 or 3
12 clocks. With 3 clocks, the order is timer0 clock, timer1 clock,
27 clocks = <&timclk1 &timclk2 &pclk>;
Dbrcm,kona-timer.txt11 - clocks: phandle + clock specifier pair of the external clock
14 Only one of clocks or clock-frequency should be specified.
16 Refer to clocks/clock-bindings.txt for generic clock consumer properties.
23 clocks = <&hub_timer_clk>;
/linux-4.1.27/drivers/ata/
Dpata_atp867x.c156 unsigned char clocks = clk; in atp867x_get_active_clocks_shifted() local
163 clocks++; in atp867x_get_active_clocks_shifted()
165 switch (clocks) { in atp867x_get_active_clocks_shifted()
167 clocks = 1; in atp867x_get_active_clocks_shifted()
175 clocks = 7; /* 12 clk */ in atp867x_get_active_clocks_shifted()
179 clocks = 0; in atp867x_get_active_clocks_shifted()
184 return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT; in atp867x_get_active_clocks_shifted()
189 unsigned char clocks = clk; in atp867x_get_recover_clocks_shifted() local
191 switch (clocks) { in atp867x_get_recover_clocks_shifted()
193 clocks = 1; in atp867x_get_recover_clocks_shifted()
[all …]
/linux-4.1.27/arch/mips/ar7/
Dclock.c253 struct tnetd7300_clocks *clocks = in tnetd7300_init_clocks() local
258 &clocks->bus, bootcr, AR7_AFE_CLOCK); in tnetd7300_init_clocks()
262 &clocks->cpu, bootcr, AR7_AFE_CLOCK); in tnetd7300_init_clocks()
267 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp, in tnetd7300_init_clocks()
270 iounmap(clocks); in tnetd7300_init_clocks()
337 struct tnetd7200_clocks *clocks = in tnetd7200_init_clocks() local
355 tnetd7200_set_clock(dsp_base, &clocks->dsp, in tnetd7200_init_clocks()
364 tnetd7200_set_clock(cpu_base, &clocks->cpu, in tnetd7200_init_clocks()
377 tnetd7200_set_clock(cpu_base, &clocks->cpu, in tnetd7200_init_clocks()
385 tnetd7200_set_clock(dsp_base, &clocks->dsp, in tnetd7200_init_clocks()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/arm/omap/
Dprcm.txt3 Power Reset and Clock Manager lists the device clocks and clockdomains under
32 - clocks: clocks for this module
41 cm_clocks: clocks {
61 clocks = <&sdrc_ick>;
/linux-4.1.27/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-vcc.txt3 The crossbar can take up to 4 input clocks and control up to 16
4 output clocks. Not all inputs or outputs have to be in use in a
6 select any of the input clocks and apply a divide (by 1,2,4 or 8) to
23 - clocks : from common clock binding
30 16 strings are provided then no clocks will be created
40 clocks = <&clk_s_vcc_hd>,
/linux-4.1.27/Documentation/devicetree/bindings/drm/bridge/
Ddw_hdmi.txt11 - clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
13 the clocks are soc specific, the clock-names should be "iahb", "isfr"
23 - clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
31 clocks = <&clks 123>, <&clks 124>;

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