1* Core Clock bindings for Marvell MVEBU SoCs
2
3Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4reading the Sample-At-Reset (SAR) register. The core clock consumer should
5specify the desired clock by having the clock ID in its "clocks" phandle cell.
6
7The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk    (Internal Bus clock)
9 1 = cpuclk  (CPU clock)
10 2 = nbclk   (L2 Cache clock)
11 3 = hclk    (DRAM control clock)
12 4 = dramclk (DDR clock)
13
14The following is a list of provided IDs and clock names on Armada 375:
15 0 = tclk    (Internal Bus clock)
16 1 = cpuclk  (CPU clock)
17 2 = l2clk   (L2 Cache clock)
18 3 = ddrclk  (DDR clock)
19
20The following is a list of provided IDs and clock names on Armada 380/385:
21 0 = tclk    (Internal Bus clock)
22 1 = cpuclk  (CPU clock)
23 2 = l2clk   (L2 Cache clock)
24 3 = ddrclk  (DDR clock)
25
26The following is a list of provided IDs and clock names on Armada 39x:
27 0 = tclk    (Internal Bus clock)
28 1 = cpuclk  (CPU clock)
29 2 = nbclk   (Coherent Fabric clock)
30 3 = hclk    (SDRAM Controller Internal Clock)
31 4 = dclk    (SDRAM Interface Clock)
32 5 = refclk  (Reference Clock)
33
34The following is a list of provided IDs and clock names on Kirkwood and Dove:
35 0 = tclk   (Internal Bus clock)
36 1 = cpuclk (CPU0 clock)
37 2 = l2clk  (L2 Cache clock derived from CPU0 clock)
38 3 = ddrclk (DDR controller clock derived from CPU0 clock)
39
40The following is a list of provided IDs and clock names on Orion5x:
41 0 = tclk   (Internal Bus clock)
42 1 = cpuclk (CPU0 clock)
43 2 = ddrclk (DDR controller clock derived from CPU0 clock)
44
45Required properties:
46- compatible : shall be one of the following:
47	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
48	"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
49	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
50	"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
51	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
52	"marvell,dove-core-clock" - for Dove SoC core clocks
53	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
54	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
55	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
56	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
57	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
58- reg : shall be the register address of the Sample-At-Reset (SAR) register
59- #clock-cells : from common clock binding; shall be set to 1
60
61Optional properties:
62- clock-output-names : from common clock binding; allows overwrite default clock
63	output names ("tclk", "cpuclk", "l2clk", "ddrclk")
64
65Example:
66
67core_clk: core-clocks@d0214 {
68	compatible = "marvell,dove-core-clock";
69	reg = <0xd0214 0x4>;
70	#clock-cells = <1>;
71};
72
73spi0: spi@10600 {
74	compatible = "marvell,orion-spi";
75	/* ... */
76	/* get tclk from core clock provider */
77	clocks = <&core_clk 0>;
78};
79