Lines Matching refs:clocks

24 	"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
60 	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
62 	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
63 	"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
65 	"allwinner,sun7i-a20-out-clk" - for the external output clocks
73 Required properties for all clocks:
75 - clocks : shall be the input parent clock(s) phandle for the clock. For
76 	multiplexed clocks, the list order must match the hardware
88 And "allwinner,*-usb-clk" clocks also require:
95 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
96 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
98 Clock consumers should specify the desired clocks they use with a
99 "clocks" phandle cell. Consumers that are using a gated clock should
102 For the other clocks with "#clock-cells" = 1, the additional ID shall
109 The "allwinner,*-mmc-clk" clocks have three different outputs: the
110 main clock, with the ID 0, and the output and sample clocks, with the
123 	clocks = <&osc24M_fixed>;
131 	clocks = <&osc24M>;
139 	clocks = <&osc24M>;
147 	clocks = <&osc24M>;
155 	clocks = <&osc32k>, <&osc24M>, <&pll1>;
163 	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
189 	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
196 	clocks = <&ahb0_gates 8>;