1/* 2 * SAMSUNG EXYNOS5250 SoC device tree source 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. 8 * EXYNOS5250 based board files can include this file and provide 9 * values for board specfic bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, 13 * additional nodes can be added to this file. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18*/ 19 20#include <dt-bindings/clock/exynos5250.h> 21#include "exynos5.dtsi" 22#include "exynos5250-pinctrl.dtsi" 23#include "exynos4-cpu-thermal.dtsi" 24#include <dt-bindings/clock/exynos-audss-clk.h> 25 26/ { 27 compatible = "samsung,exynos5250", "samsung,exynos5"; 28 29 aliases { 30 spi0 = &spi_0; 31 spi1 = &spi_1; 32 spi2 = &spi_2; 33 gsc0 = &gsc_0; 34 gsc1 = &gsc_1; 35 gsc2 = &gsc_2; 36 gsc3 = &gsc_3; 37 mshc0 = &mmc_0; 38 mshc1 = &mmc_1; 39 mshc2 = &mmc_2; 40 mshc3 = &mmc_3; 41 i2c0 = &i2c_0; 42 i2c1 = &i2c_1; 43 i2c2 = &i2c_2; 44 i2c3 = &i2c_3; 45 i2c4 = &i2c_4; 46 i2c5 = &i2c_5; 47 i2c6 = &i2c_6; 48 i2c7 = &i2c_7; 49 i2c8 = &i2c_8; 50 i2c9 = &i2c_9; 51 pinctrl0 = &pinctrl_0; 52 pinctrl1 = &pinctrl_1; 53 pinctrl2 = &pinctrl_2; 54 pinctrl3 = &pinctrl_3; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a15"; 64 reg = <0>; 65 clock-frequency = <1700000000>; 66 cooling-min-level = <15>; 67 cooling-max-level = <9>; 68 #cooling-cells = <2>; /* min followed by max */ 69 }; 70 cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a15"; 73 reg = <1>; 74 clock-frequency = <1700000000>; 75 }; 76 }; 77 78 sysram@02020000 { 79 compatible = "mmio-sram"; 80 reg = <0x02020000 0x30000>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0 0x02020000 0x30000>; 84 85 smp-sysram@0 { 86 compatible = "samsung,exynos4210-sysram"; 87 reg = <0x0 0x1000>; 88 }; 89 90 smp-sysram@2f000 { 91 compatible = "samsung,exynos4210-sysram-ns"; 92 reg = <0x2f000 0x1000>; 93 }; 94 }; 95 96 pd_gsc: gsc-power-domain@10044000 { 97 compatible = "samsung,exynos4210-pd"; 98 reg = <0x10044000 0x20>; 99 #power-domain-cells = <0>; 100 }; 101 102 pd_mfc: mfc-power-domain@10044040 { 103 compatible = "samsung,exynos4210-pd"; 104 reg = <0x10044040 0x20>; 105 #power-domain-cells = <0>; 106 }; 107 108 pd_disp1: disp1-power-domain@100440A0 { 109 compatible = "samsung,exynos4210-pd"; 110 reg = <0x100440A0 0x20>; 111 #power-domain-cells = <0>; 112 }; 113 114 clock: clock-controller@10010000 { 115 compatible = "samsung,exynos5250-clock"; 116 reg = <0x10010000 0x30000>; 117 #clock-cells = <1>; 118 }; 119 120 clock_audss: audss-clock-controller@3810000 { 121 compatible = "samsung,exynos5250-audss-clock"; 122 reg = <0x03810000 0x0C>; 123 #clock-cells = <1>; 124 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 125 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 126 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 127 }; 128 129 timer { 130 compatible = "arm,armv7-timer"; 131 interrupts = <1 13 0xf08>, 132 <1 14 0xf08>, 133 <1 11 0xf08>, 134 <1 10 0xf08>; 135 /* Unfortunately we need this since some versions of U-Boot 136 * on Exynos don't set the CNTFRQ register, so we need the 137 * value from DT. 138 */ 139 clock-frequency = <24000000>; 140 }; 141 142 mct@101C0000 { 143 compatible = "samsung,exynos4210-mct"; 144 reg = <0x101C0000 0x800>; 145 interrupt-controller; 146 #interrupt-cells = <2>; 147 interrupt-parent = <&mct_map>; 148 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 149 <4 0>, <5 0>; 150 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 151 clock-names = "fin_pll", "mct"; 152 153 mct_map: mct-map { 154 #interrupt-cells = <2>; 155 #address-cells = <0>; 156 #size-cells = <0>; 157 interrupt-map = <0x0 0 &combiner 23 3>, 158 <0x1 0 &combiner 23 4>, 159 <0x2 0 &combiner 25 2>, 160 <0x3 0 &combiner 25 3>, 161 <0x4 0 &gic 0 120 0>, 162 <0x5 0 &gic 0 121 0>; 163 }; 164 }; 165 166 pmu { 167 compatible = "arm,cortex-a15-pmu"; 168 interrupt-parent = <&combiner>; 169 interrupts = <1 2>, <22 4>; 170 }; 171 172 pinctrl_0: pinctrl@11400000 { 173 compatible = "samsung,exynos5250-pinctrl"; 174 reg = <0x11400000 0x1000>; 175 interrupts = <0 46 0>; 176 177 wakup_eint: wakeup-interrupt-controller { 178 compatible = "samsung,exynos4210-wakeup-eint"; 179 interrupt-parent = <&gic>; 180 interrupts = <0 32 0>; 181 }; 182 }; 183 184 pinctrl_1: pinctrl@13400000 { 185 compatible = "samsung,exynos5250-pinctrl"; 186 reg = <0x13400000 0x1000>; 187 interrupts = <0 45 0>; 188 }; 189 190 pinctrl_2: pinctrl@10d10000 { 191 compatible = "samsung,exynos5250-pinctrl"; 192 reg = <0x10d10000 0x1000>; 193 interrupts = <0 50 0>; 194 }; 195 196 pinctrl_3: pinctrl@03860000 { 197 compatible = "samsung,exynos5250-pinctrl"; 198 reg = <0x03860000 0x1000>; 199 interrupts = <0 47 0>; 200 }; 201 202 pmu_system_controller: system-controller@10040000 { 203 compatible = "samsung,exynos5250-pmu", "syscon"; 204 reg = <0x10040000 0x5000>; 205 clock-names = "clkout16"; 206 clocks = <&clock CLK_FIN_PLL>; 207 #clock-cells = <1>; 208 interrupt-controller; 209 #interrupt-cells = <3>; 210 interrupt-parent = <&gic>; 211 }; 212 213 sysreg_system_controller: syscon@10050000 { 214 compatible = "samsung,exynos5-sysreg", "syscon"; 215 reg = <0x10050000 0x5000>; 216 }; 217 218 watchdog@101D0000 { 219 compatible = "samsung,exynos5250-wdt"; 220 reg = <0x101D0000 0x100>; 221 interrupts = <0 42 0>; 222 clocks = <&clock CLK_WDT>; 223 clock-names = "watchdog"; 224 samsung,syscon-phandle = <&pmu_system_controller>; 225 }; 226 227 g2d@10850000 { 228 compatible = "samsung,exynos5250-g2d"; 229 reg = <0x10850000 0x1000>; 230 interrupts = <0 91 0>; 231 clocks = <&clock CLK_G2D>; 232 clock-names = "fimg2d"; 233 }; 234 235 mfc: codec@11000000 { 236 compatible = "samsung,mfc-v6"; 237 reg = <0x11000000 0x10000>; 238 interrupts = <0 96 0>; 239 power-domains = <&pd_mfc>; 240 clocks = <&clock CLK_MFC>; 241 clock-names = "mfc"; 242 }; 243 244 rtc: rtc@101E0000 { 245 clocks = <&clock CLK_RTC>; 246 clock-names = "rtc"; 247 interrupt-parent = <&pmu_system_controller>; 248 status = "disabled"; 249 }; 250 251 tmu: tmu@10060000 { 252 compatible = "samsung,exynos5250-tmu"; 253 reg = <0x10060000 0x100>; 254 interrupts = <0 65 0>; 255 clocks = <&clock CLK_TMU>; 256 clock-names = "tmu_apbif"; 257 #include "exynos4412-tmu-sensor-conf.dtsi" 258 }; 259 260 thermal-zones { 261 cpu_thermal: cpu-thermal { 262 polling-delay-passive = <0>; 263 polling-delay = <0>; 264 thermal-sensors = <&tmu 0>; 265 266 cooling-maps { 267 map0 { 268 /* Corresponds to 800MHz at freq_table */ 269 cooling-device = <&cpu0 9 9>; 270 }; 271 map1 { 272 /* Corresponds to 200MHz at freq_table */ 273 cooling-device = <&cpu0 15 15>; 274 }; 275 }; 276 }; 277 }; 278 279 serial@12C00000 { 280 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 281 clock-names = "uart", "clk_uart_baud0"; 282 }; 283 284 serial@12C10000 { 285 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 286 clock-names = "uart", "clk_uart_baud0"; 287 }; 288 289 serial@12C20000 { 290 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 291 clock-names = "uart", "clk_uart_baud0"; 292 }; 293 294 serial@12C30000 { 295 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 296 clock-names = "uart", "clk_uart_baud0"; 297 }; 298 299 sata: sata@122F0000 { 300 compatible = "snps,dwc-ahci"; 301 samsung,sata-freq = <66>; 302 reg = <0x122F0000 0x1ff>; 303 interrupts = <0 115 0>; 304 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 305 clock-names = "sata", "sclk_sata"; 306 phys = <&sata_phy>; 307 phy-names = "sata-phy"; 308 status = "disabled"; 309 }; 310 311 sata_phy: sata-phy@12170000 { 312 compatible = "samsung,exynos5250-sata-phy"; 313 reg = <0x12170000 0x1ff>; 314 clocks = <&clock CLK_SATA_PHYCTRL>; 315 clock-names = "sata_phyctrl"; 316 #phy-cells = <0>; 317 samsung,syscon-phandle = <&pmu_system_controller>; 318 status = "disabled"; 319 }; 320 321 i2c_0: i2c@12C60000 { 322 compatible = "samsung,s3c2440-i2c"; 323 reg = <0x12C60000 0x100>; 324 interrupts = <0 56 0>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 clocks = <&clock CLK_I2C0>; 328 clock-names = "i2c"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&i2c0_bus>; 331 samsung,sysreg-phandle = <&sysreg_system_controller>; 332 status = "disabled"; 333 }; 334 335 i2c_1: i2c@12C70000 { 336 compatible = "samsung,s3c2440-i2c"; 337 reg = <0x12C70000 0x100>; 338 interrupts = <0 57 0>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clocks = <&clock CLK_I2C1>; 342 clock-names = "i2c"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&i2c1_bus>; 345 samsung,sysreg-phandle = <&sysreg_system_controller>; 346 status = "disabled"; 347 }; 348 349 i2c_2: i2c@12C80000 { 350 compatible = "samsung,s3c2440-i2c"; 351 reg = <0x12C80000 0x100>; 352 interrupts = <0 58 0>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clocks = <&clock CLK_I2C2>; 356 clock-names = "i2c"; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&i2c2_bus>; 359 samsung,sysreg-phandle = <&sysreg_system_controller>; 360 status = "disabled"; 361 }; 362 363 i2c_3: i2c@12C90000 { 364 compatible = "samsung,s3c2440-i2c"; 365 reg = <0x12C90000 0x100>; 366 interrupts = <0 59 0>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 clocks = <&clock CLK_I2C3>; 370 clock-names = "i2c"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&i2c3_bus>; 373 samsung,sysreg-phandle = <&sysreg_system_controller>; 374 status = "disabled"; 375 }; 376 377 i2c_4: i2c@12CA0000 { 378 compatible = "samsung,s3c2440-i2c"; 379 reg = <0x12CA0000 0x100>; 380 interrupts = <0 60 0>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&clock CLK_I2C4>; 384 clock-names = "i2c"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&i2c4_bus>; 387 status = "disabled"; 388 }; 389 390 i2c_5: i2c@12CB0000 { 391 compatible = "samsung,s3c2440-i2c"; 392 reg = <0x12CB0000 0x100>; 393 interrupts = <0 61 0>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&clock CLK_I2C5>; 397 clock-names = "i2c"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&i2c5_bus>; 400 status = "disabled"; 401 }; 402 403 i2c_6: i2c@12CC0000 { 404 compatible = "samsung,s3c2440-i2c"; 405 reg = <0x12CC0000 0x100>; 406 interrupts = <0 62 0>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 clocks = <&clock CLK_I2C6>; 410 clock-names = "i2c"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&i2c6_bus>; 413 status = "disabled"; 414 }; 415 416 i2c_7: i2c@12CD0000 { 417 compatible = "samsung,s3c2440-i2c"; 418 reg = <0x12CD0000 0x100>; 419 interrupts = <0 63 0>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 clocks = <&clock CLK_I2C7>; 423 clock-names = "i2c"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&i2c7_bus>; 426 status = "disabled"; 427 }; 428 429 i2c_8: i2c@12CE0000 { 430 compatible = "samsung,s3c2440-hdmiphy-i2c"; 431 reg = <0x12CE0000 0x1000>; 432 interrupts = <0 64 0>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 clocks = <&clock CLK_I2C_HDMI>; 436 clock-names = "i2c"; 437 status = "disabled"; 438 }; 439 440 i2c_9: i2c@121D0000 { 441 compatible = "samsung,exynos5-sata-phy-i2c"; 442 reg = <0x121D0000 0x100>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clocks = <&clock CLK_SATA_PHYI2C>; 446 clock-names = "i2c"; 447 status = "disabled"; 448 }; 449 450 spi_0: spi@12d20000 { 451 compatible = "samsung,exynos4210-spi"; 452 status = "disabled"; 453 reg = <0x12d20000 0x100>; 454 interrupts = <0 66 0>; 455 dmas = <&pdma0 5 456 &pdma0 4>; 457 dma-names = "tx", "rx"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 461 clock-names = "spi", "spi_busclk0"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&spi0_bus>; 464 }; 465 466 spi_1: spi@12d30000 { 467 compatible = "samsung,exynos4210-spi"; 468 status = "disabled"; 469 reg = <0x12d30000 0x100>; 470 interrupts = <0 67 0>; 471 dmas = <&pdma1 5 472 &pdma1 4>; 473 dma-names = "tx", "rx"; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 477 clock-names = "spi", "spi_busclk0"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&spi1_bus>; 480 }; 481 482 spi_2: spi@12d40000 { 483 compatible = "samsung,exynos4210-spi"; 484 status = "disabled"; 485 reg = <0x12d40000 0x100>; 486 interrupts = <0 68 0>; 487 dmas = <&pdma0 7 488 &pdma0 6>; 489 dma-names = "tx", "rx"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 493 clock-names = "spi", "spi_busclk0"; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&spi2_bus>; 496 }; 497 498 mmc_0: mmc@12200000 { 499 compatible = "samsung,exynos5250-dw-mshc"; 500 interrupts = <0 75 0>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0x12200000 0x1000>; 504 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 505 clock-names = "biu", "ciu"; 506 fifo-depth = <0x80>; 507 status = "disabled"; 508 }; 509 510 mmc_1: mmc@12210000 { 511 compatible = "samsung,exynos5250-dw-mshc"; 512 interrupts = <0 76 0>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <0x12210000 0x1000>; 516 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 517 clock-names = "biu", "ciu"; 518 fifo-depth = <0x80>; 519 status = "disabled"; 520 }; 521 522 mmc_2: mmc@12220000 { 523 compatible = "samsung,exynos5250-dw-mshc"; 524 interrupts = <0 77 0>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 reg = <0x12220000 0x1000>; 528 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 529 clock-names = "biu", "ciu"; 530 fifo-depth = <0x80>; 531 status = "disabled"; 532 }; 533 534 mmc_3: mmc@12230000 { 535 compatible = "samsung,exynos5250-dw-mshc"; 536 reg = <0x12230000 0x1000>; 537 interrupts = <0 78 0>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 541 clock-names = "biu", "ciu"; 542 fifo-depth = <0x80>; 543 status = "disabled"; 544 }; 545 546 i2s0: i2s@03830000 { 547 compatible = "samsung,s5pv210-i2s"; 548 status = "disabled"; 549 reg = <0x03830000 0x100>; 550 dmas = <&pdma0 10 551 &pdma0 9 552 &pdma0 8>; 553 dma-names = "tx", "rx", "tx-sec"; 554 clocks = <&clock_audss EXYNOS_I2S_BUS>, 555 <&clock_audss EXYNOS_I2S_BUS>, 556 <&clock_audss EXYNOS_SCLK_I2S>; 557 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 558 samsung,idma-addr = <0x03000000>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2s0_bus>; 561 }; 562 563 i2s1: i2s@12D60000 { 564 compatible = "samsung,s3c6410-i2s"; 565 status = "disabled"; 566 reg = <0x12D60000 0x100>; 567 dmas = <&pdma1 12 568 &pdma1 11>; 569 dma-names = "tx", "rx"; 570 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 571 clock-names = "iis", "i2s_opclk0"; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2s1_bus>; 574 }; 575 576 i2s2: i2s@12D70000 { 577 compatible = "samsung,s3c6410-i2s"; 578 status = "disabled"; 579 reg = <0x12D70000 0x100>; 580 dmas = <&pdma0 12 581 &pdma0 11>; 582 dma-names = "tx", "rx"; 583 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 584 clock-names = "iis", "i2s_opclk0"; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&i2s2_bus>; 587 }; 588 589 usb@12000000 { 590 compatible = "samsung,exynos5250-dwusb3"; 591 clocks = <&clock CLK_USB3>; 592 clock-names = "usbdrd30"; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges; 596 597 usbdrd_dwc3: dwc3 { 598 compatible = "synopsys,dwc3"; 599 reg = <0x12000000 0x10000>; 600 interrupts = <0 72 0>; 601 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 602 phy-names = "usb2-phy", "usb3-phy"; 603 }; 604 }; 605 606 usbdrd_phy: phy@12100000 { 607 compatible = "samsung,exynos5250-usbdrd-phy"; 608 reg = <0x12100000 0x100>; 609 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 610 clock-names = "phy", "ref"; 611 samsung,pmu-syscon = <&pmu_system_controller>; 612 #phy-cells = <1>; 613 }; 614 615 ehci: usb@12110000 { 616 compatible = "samsung,exynos4210-ehci"; 617 reg = <0x12110000 0x100>; 618 interrupts = <0 71 0>; 619 620 clocks = <&clock CLK_USB2>; 621 clock-names = "usbhost"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 port@0 { 625 reg = <0>; 626 phys = <&usb2_phy_gen 1>; 627 }; 628 }; 629 630 ohci: usb@12120000 { 631 compatible = "samsung,exynos4210-ohci"; 632 reg = <0x12120000 0x100>; 633 interrupts = <0 71 0>; 634 635 clocks = <&clock CLK_USB2>; 636 clock-names = "usbhost"; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 port@0 { 640 reg = <0>; 641 phys = <&usb2_phy_gen 1>; 642 }; 643 }; 644 645 usb2_phy_gen: phy@12130000 { 646 compatible = "samsung,exynos5250-usb2-phy"; 647 reg = <0x12130000 0x100>; 648 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; 649 clock-names = "phy", "ref"; 650 #phy-cells = <1>; 651 samsung,sysreg-phandle = <&sysreg_system_controller>; 652 samsung,pmureg-phandle = <&pmu_system_controller>; 653 }; 654 655 pwm: pwm@12dd0000 { 656 compatible = "samsung,exynos4210-pwm"; 657 reg = <0x12dd0000 0x100>; 658 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 659 #pwm-cells = <3>; 660 clocks = <&clock CLK_PWM>; 661 clock-names = "timers"; 662 }; 663 664 amba { 665 #address-cells = <1>; 666 #size-cells = <1>; 667 compatible = "arm,amba-bus"; 668 interrupt-parent = <&gic>; 669 ranges; 670 671 pdma0: pdma@121A0000 { 672 compatible = "arm,pl330", "arm,primecell"; 673 reg = <0x121A0000 0x1000>; 674 interrupts = <0 34 0>; 675 clocks = <&clock CLK_PDMA0>; 676 clock-names = "apb_pclk"; 677 #dma-cells = <1>; 678 #dma-channels = <8>; 679 #dma-requests = <32>; 680 }; 681 682 pdma1: pdma@121B0000 { 683 compatible = "arm,pl330", "arm,primecell"; 684 reg = <0x121B0000 0x1000>; 685 interrupts = <0 35 0>; 686 clocks = <&clock CLK_PDMA1>; 687 clock-names = "apb_pclk"; 688 #dma-cells = <1>; 689 #dma-channels = <8>; 690 #dma-requests = <32>; 691 }; 692 693 mdma0: mdma@10800000 { 694 compatible = "arm,pl330", "arm,primecell"; 695 reg = <0x10800000 0x1000>; 696 interrupts = <0 33 0>; 697 clocks = <&clock CLK_MDMA0>; 698 clock-names = "apb_pclk"; 699 #dma-cells = <1>; 700 #dma-channels = <8>; 701 #dma-requests = <1>; 702 }; 703 704 mdma1: mdma@11C10000 { 705 compatible = "arm,pl330", "arm,primecell"; 706 reg = <0x11C10000 0x1000>; 707 interrupts = <0 124 0>; 708 clocks = <&clock CLK_MDMA1>; 709 clock-names = "apb_pclk"; 710 #dma-cells = <1>; 711 #dma-channels = <8>; 712 #dma-requests = <1>; 713 }; 714 }; 715 716 gsc_0: gsc@13e00000 { 717 compatible = "samsung,exynos5-gsc"; 718 reg = <0x13e00000 0x1000>; 719 interrupts = <0 85 0>; 720 power-domains = <&pd_gsc>; 721 clocks = <&clock CLK_GSCL0>; 722 clock-names = "gscl"; 723 }; 724 725 gsc_1: gsc@13e10000 { 726 compatible = "samsung,exynos5-gsc"; 727 reg = <0x13e10000 0x1000>; 728 interrupts = <0 86 0>; 729 power-domains = <&pd_gsc>; 730 clocks = <&clock CLK_GSCL1>; 731 clock-names = "gscl"; 732 }; 733 734 gsc_2: gsc@13e20000 { 735 compatible = "samsung,exynos5-gsc"; 736 reg = <0x13e20000 0x1000>; 737 interrupts = <0 87 0>; 738 power-domains = <&pd_gsc>; 739 clocks = <&clock CLK_GSCL2>; 740 clock-names = "gscl"; 741 }; 742 743 gsc_3: gsc@13e30000 { 744 compatible = "samsung,exynos5-gsc"; 745 reg = <0x13e30000 0x1000>; 746 interrupts = <0 88 0>; 747 power-domains = <&pd_gsc>; 748 clocks = <&clock CLK_GSCL3>; 749 clock-names = "gscl"; 750 }; 751 752 hdmi: hdmi { 753 compatible = "samsung,exynos4212-hdmi"; 754 reg = <0x14530000 0x70000>; 755 power-domains = <&pd_disp1>; 756 interrupts = <0 95 0>; 757 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 758 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 759 <&clock CLK_MOUT_HDMI>; 760 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 761 "sclk_hdmiphy", "mout_hdmi"; 762 samsung,syscon-phandle = <&pmu_system_controller>; 763 }; 764 765 mixer { 766 compatible = "samsung,exynos5250-mixer"; 767 reg = <0x14450000 0x10000>; 768 power-domains = <&pd_disp1>; 769 interrupts = <0 94 0>; 770 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 771 <&clock CLK_SCLK_HDMI>; 772 clock-names = "mixer", "hdmi", "sclk_hdmi"; 773 }; 774 775 dp_phy: video-phy@10040720 { 776 compatible = "samsung,exynos5250-dp-video-phy"; 777 samsung,pmu-syscon = <&pmu_system_controller>; 778 #phy-cells = <0>; 779 }; 780 781 dp: dp-controller@145B0000 { 782 power-domains = <&pd_disp1>; 783 clocks = <&clock CLK_DP>; 784 clock-names = "dp"; 785 phys = <&dp_phy>; 786 phy-names = "dp"; 787 }; 788 789 fimd: fimd@14400000 { 790 power-domains = <&pd_disp1>; 791 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 792 clock-names = "sclk_fimd", "fimd"; 793 }; 794 795 adc: adc@12D10000 { 796 compatible = "samsung,exynos-adc-v1"; 797 reg = <0x12D10000 0x100>; 798 interrupts = <0 106 0>; 799 clocks = <&clock CLK_ADC>; 800 clock-names = "adc"; 801 #io-channel-cells = <1>; 802 io-channel-ranges; 803 samsung,syscon-phandle = <&pmu_system_controller>; 804 status = "disabled"; 805 }; 806 807 sss@10830000 { 808 compatible = "samsung,exynos4210-secss"; 809 reg = <0x10830000 0x10000>; 810 interrupts = <0 112 0>; 811 clocks = <&clock CLK_SSS>; 812 clock-names = "secss"; 813 }; 814}; 815