1* Samsung Exynos5433 CMU (Clock Management Units) 2 3The Exynos5433 clock controller generates and supplies clock to various 4controllers within the Exynos5433 SoC. 5 6Required Properties: 7 8- compatible: should be one of the following. 9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP 10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS 11 domains and bus clocks. 12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF 13 which generates clocks for LLI (Low Latency Interface) IP. 14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF 15 which generates clocks for DRAM Memory Controller domain. 16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC 17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. 18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS 19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. 20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS 21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. 22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D 23 which generates clocks for G2D/MDMA IPs. 24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP 25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. 26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD 27 which generates clocks for Cortex-A5/BUS/AUDIO clocks. 28 - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" 29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS 30 which generates global data buses clock and global peripheral buses clock. 31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D 32 which generates clocks for 3D Graphics Engine IP. 33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL 34 which generates clocks for GSCALER IPs. 35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO 36 which generates clocks for Cortex-A53 Quad-core processor. 37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS 38 which generates clocks for Cortex-A57 Quad-core processor, CoreSight and 39 L2 cache controller. 40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL 41 which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. 42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC 43 which generates clocks for MFC(Multi-Format Codec) IP. 44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC 45 which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. 46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP 47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. 48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0 49 which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} 50 IPs. 51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 52 which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. 53 54- reg: physical base address of the controller and length of memory mapped 55 region. 56 57- #clock-cells: should be 1. 58 59- clocks: list of the clock controller input clock identifiers, 60 from common clock bindings. Please refer the next section 61 to find the input clocks for a given controller. 62 63- clock-names: list of the clock controller input clock names, 64 as described in clock-bindings.txt. 65 66 Input clocks for top clock controller: 67 - oscclk 68 - sclk_mphy_pll 69 - sclk_mfc_pll 70 - sclk_bus_pll 71 72 Input clocks for cpif clock controller: 73 - oscclk 74 75 Input clocks for mif clock controller: 76 - oscclk 77 - sclk_mphy_pll 78 79 Input clocks for fsys clock controller: 80 - oscclk 81 - sclk_ufs_mphy 82 - div_aclk_fsys_200 83 - sclk_pcie_100_fsys 84 - sclk_ufsunipro_fsys 85 - sclk_mmc2_fsys 86 - sclk_mmc1_fsys 87 - sclk_mmc0_fsys 88 - sclk_usbhost30_fsys 89 - sclk_usbdrd30_fsys 90 91 Input clocks for g2d clock controller: 92 - oscclk 93 - aclk_g2d_266 94 - aclk_g2d_400 95 96 Input clocks for disp clock controller: 97 - oscclk 98 - sclk_dsim1_disp 99 - sclk_dsim0_disp 100 - sclk_dsd_disp 101 - sclk_decon_tv_eclk_disp 102 - sclk_decon_vclk_disp 103 - sclk_decon_eclk_disp 104 - sclk_decon_tv_vclk_disp 105 - aclk_disp_333 106 107 Input clocks for bus0 clock controller: 108 - aclk_bus0_400 109 110 Input clocks for bus1 clock controller: 111 - aclk_bus1_400 112 113 Input clocks for bus2 clock controller: 114 - oscclk 115 - aclk_bus2_400 116 117 Input clocks for g3d clock controller: 118 - oscclk 119 - aclk_g3d_400 120 121 Input clocks for gscl clock controller: 122 - oscclk 123 - aclk_gscl_111 124 - aclk_gscl_333 125 126 Input clocks for apollo clock controller: 127 - oscclk 128 - sclk_bus_pll_apollo 129 130 Input clocks for atlas clock controller: 131 - oscclk 132 - sclk_bus_pll_atlas 133 134 Input clocks for mscl clock controller: 135 - oscclk 136 - sclk_jpeg_mscl 137 - aclk_mscl_400 138 139 Input clocks for mfc clock controller: 140 - oscclk 141 - aclk_mfc_400 142 143 Input clocks for hevc clock controller: 144 - oscclk 145 - aclk_hevc_400 146 147 Input clocks for isp clock controller: 148 - oscclk 149 - aclk_isp_dis_400 150 - aclk_isp_400 151 152 Input clocks for cam0 clock controller: 153 - oscclk 154 - aclk_cam0_333 155 - aclk_cam0_400 156 - aclk_cam0_552 157 158 Input clocks for cam1 clock controller: 159 - oscclk 160 - sclk_isp_uart_cam1 161 - sclk_isp_spi1_cam1 162 - sclk_isp_spi0_cam1 163 - aclk_cam1_333 164 - aclk_cam1_400 165 - aclk_cam1_552 166 167Each clock is assigned an identifier and client nodes can use this identifier 168to specify the clock which they consume. 169 170All available clocks are defined as preprocessor macros in 171dt-bindings/clock/exynos5433.h header and can be used in device 172tree sources. 173 174Example 1: Examples of 'oscclk' source clock node are listed below. 175 176 xxti: xxti { 177 compatible = "fixed-clock"; 178 clock-output-names = "oscclk"; 179 #clock-cells = <0>; 180 }; 181 182Example 2: Examples of clock controller nodes are listed below. 183 184 cmu_top: clock-controller@10030000 { 185 compatible = "samsung,exynos5433-cmu-top"; 186 reg = <0x10030000 0x0c04>; 187 #clock-cells = <1>; 188 189 clock-names = "oscclk", 190 "sclk_mphy_pll", 191 "sclk_mfc_pll", 192 "sclk_bus_pll"; 193 clocks = <&xxti>, 194 <&cmu_cpif CLK_SCLK_MPHY_PLL>, 195 <&cmu_mif CLK_SCLK_MFC_PLL>, 196 <&cmu_mif CLK_SCLK_BUS_PLL>; 197 }; 198 199 cmu_cpif: clock-controller@10fc0000 { 200 compatible = "samsung,exynos5433-cmu-cpif"; 201 reg = <0x10fc0000 0x0c04>; 202 #clock-cells = <1>; 203 204 clock-names = "oscclk"; 205 clocks = <&xxti>; 206 }; 207 208 cmu_mif: clock-controller@105b0000 { 209 compatible = "samsung,exynos5433-cmu-mif"; 210 reg = <0x105b0000 0x100c>; 211 #clock-cells = <1>; 212 213 clock-names = "oscclk", 214 "sclk_mphy_pll"; 215 clocks = <&xxti>, 216 <&cmu_cpif CLK_SCLK_MPHY_PLL>; 217 }; 218 219 cmu_peric: clock-controller@14c80000 { 220 compatible = "samsung,exynos5433-cmu-peric"; 221 reg = <0x14c80000 0x0b08>; 222 #clock-cells = <1>; 223 }; 224 225 cmu_peris: clock-controller@10040000 { 226 compatible = "samsung,exynos5433-cmu-peris"; 227 reg = <0x10040000 0x0b20>; 228 #clock-cells = <1>; 229 }; 230 231 cmu_fsys: clock-controller@156e0000 { 232 compatible = "samsung,exynos5433-cmu-fsys"; 233 reg = <0x156e0000 0x0b04>; 234 #clock-cells = <1>; 235 236 clock-names = "oscclk", 237 "sclk_ufs_mphy", 238 "div_aclk_fsys_200", 239 "sclk_pcie_100_fsys", 240 "sclk_ufsunipro_fsys", 241 "sclk_mmc2_fsys", 242 "sclk_mmc1_fsys", 243 "sclk_mmc0_fsys", 244 "sclk_usbhost30_fsys", 245 "sclk_usbdrd30_fsys"; 246 clocks = <&xxti>, 247 <&cmu_cpif CLK_SCLK_UFS_MPHY>, 248 <&cmu_top CLK_DIV_ACLK_FSYS_200>, 249 <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 250 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, 251 <&cmu_top CLK_SCLK_MMC2_FSYS>, 252 <&cmu_top CLK_SCLK_MMC1_FSYS>, 253 <&cmu_top CLK_SCLK_MMC0_FSYS>, 254 <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 255 <&cmu_top CLK_SCLK_USBDRD30_FSYS>; 256 }; 257 258 cmu_g2d: clock-controller@12460000 { 259 compatible = "samsung,exynos5433-cmu-g2d"; 260 reg = <0x12460000 0x0b08>; 261 #clock-cells = <1>; 262 263 clock-names = "oscclk", 264 "aclk_g2d_266", 265 "aclk_g2d_400"; 266 clocks = <&xxti>, 267 <&cmu_top CLK_ACLK_G2D_266>, 268 <&cmu_top CLK_ACLK_G2D_400>; 269 }; 270 271 cmu_disp: clock-controller@13b90000 { 272 compatible = "samsung,exynos5433-cmu-disp"; 273 reg = <0x13b90000 0x0c04>; 274 #clock-cells = <1>; 275 276 clock-names = "oscclk", 277 "sclk_dsim1_disp", 278 "sclk_dsim0_disp", 279 "sclk_dsd_disp", 280 "sclk_decon_tv_eclk_disp", 281 "sclk_decon_vclk_disp", 282 "sclk_decon_eclk_disp", 283 "sclk_decon_tv_vclk_disp", 284 "aclk_disp_333"; 285 clocks = <&xxti>, 286 <&cmu_mif CLK_SCLK_DSIM1_DISP>, 287 <&cmu_mif CLK_SCLK_DSIM0_DISP>, 288 <&cmu_mif CLK_SCLK_DSD_DISP>, 289 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 290 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, 291 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 292 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, 293 <&cmu_mif CLK_ACLK_DISP_333>; 294 }; 295 296 cmu_aud: clock-controller@114c0000 { 297 compatible = "samsung,exynos5433-cmu-aud"; 298 reg = <0x114c0000 0x0b04>; 299 #clock-cells = <1>; 300 }; 301 302 cmu_bus0: clock-controller@13600000 { 303 compatible = "samsung,exynos5433-cmu-bus0"; 304 reg = <0x13600000 0x0b04>; 305 #clock-cells = <1>; 306 307 clock-names = "aclk_bus0_400"; 308 clocks = <&cmu_top CLK_ACLK_BUS0_400>; 309 }; 310 311 cmu_bus1: clock-controller@14800000 { 312 compatible = "samsung,exynos5433-cmu-bus1"; 313 reg = <0x14800000 0x0b04>; 314 #clock-cells = <1>; 315 316 clock-names = "aclk_bus1_400"; 317 clocks = <&cmu_top CLK_ACLK_BUS1_400>; 318 }; 319 320 cmu_bus2: clock-controller@13400000 { 321 compatible = "samsung,exynos5433-cmu-bus2"; 322 reg = <0x13400000 0x0b04>; 323 #clock-cells = <1>; 324 325 clock-names = "oscclk", "aclk_bus2_400"; 326 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; 327 }; 328 329 cmu_g3d: clock-controller@14aa0000 { 330 compatible = "samsung,exynos5433-cmu-g3d"; 331 reg = <0x14aa0000 0x1000>; 332 #clock-cells = <1>; 333 334 clock-names = "oscclk", "aclk_g3d_400"; 335 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; 336 }; 337 338 cmu_gscl: clock-controller@13cf0000 { 339 compatible = "samsung,exynos5433-cmu-gscl"; 340 reg = <0x13cf0000 0x0b10>; 341 #clock-cells = <1>; 342 343 clock-names = "oscclk", 344 "aclk_gscl_111", 345 "aclk_gscl_333"; 346 clocks = <&xxti>, 347 <&cmu_top CLK_ACLK_GSCL_111>, 348 <&cmu_top CLK_ACLK_GSCL_333>; 349 }; 350 351 cmu_apollo: clock-controller@11900000 { 352 compatible = "samsung,exynos5433-cmu-apollo"; 353 reg = <0x11900000 0x1088>; 354 #clock-cells = <1>; 355 356 clock-names = "oscclk", "sclk_bus_pll_apollo"; 357 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; 358 }; 359 360 cmu_atlas: clock-controller@11800000 { 361 compatible = "samsung,exynos5433-cmu-atlas"; 362 reg = <0x11800000 0x1088>; 363 #clock-cells = <1>; 364 365 clock-names = "oscclk", "sclk_bus_pll_atlas"; 366 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; 367 }; 368 369 cmu_mscl: clock-controller@105d0000 { 370 compatible = "samsung,exynos5433-cmu-mscl"; 371 reg = <0x105d0000 0x0b10>; 372 #clock-cells = <1>; 373 374 clock-names = "oscclk", 375 "sclk_jpeg_mscl", 376 "aclk_mscl_400"; 377 clocks = <&xxti>, 378 <&cmu_top CLK_SCLK_JPEG_MSCL>, 379 <&cmu_top CLK_ACLK_MSCL_400>; 380 }; 381 382 cmu_mfc: clock-controller@15280000 { 383 compatible = "samsung,exynos5433-cmu-mfc"; 384 reg = <0x15280000 0x0b08>; 385 #clock-cells = <1>; 386 387 clock-names = "oscclk", "aclk_mfc_400"; 388 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; 389 }; 390 391 cmu_hevc: clock-controller@14f80000 { 392 compatible = "samsung,exynos5433-cmu-hevc"; 393 reg = <0x14f80000 0x0b08>; 394 #clock-cells = <1>; 395 396 clock-names = "oscclk", "aclk_hevc_400"; 397 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; 398 }; 399 400 cmu_isp: clock-controller@146d0000 { 401 compatible = "samsung,exynos5433-cmu-isp"; 402 reg = <0x146d0000 0x0b0c>; 403 #clock-cells = <1>; 404 405 clock-names = "oscclk", 406 "aclk_isp_dis_400", 407 "aclk_isp_400"; 408 clocks = <&xxti>, 409 <&cmu_top CLK_ACLK_ISP_DIS_400>, 410 <&cmu_top CLK_ACLK_ISP_400>; 411 }; 412 413 cmu_cam0: clock-controller@120d0000 { 414 compatible = "samsung,exynos5433-cmu-cam0"; 415 reg = <0x120d0000 0x0b0c>; 416 #clock-cells = <1>; 417 418 clock-names = "oscclk", 419 "aclk_cam0_333", 420 "aclk_cam0_400", 421 "aclk_cam0_552"; 422 clocks = <&xxti>, 423 <&cmu_top CLK_ACLK_CAM0_333>, 424 <&cmu_top CLK_ACLK_CAM0_400>, 425 <&cmu_top CLK_ACLK_CAM0_552>; 426 }; 427 428 cmu_cam1: clock-controller@145d0000 { 429 compatible = "samsung,exynos5433-cmu-cam1"; 430 reg = <0x145d0000 0x0b08>; 431 #clock-cells = <1>; 432 433 clock-names = "oscclk", 434 "sclk_isp_uart_cam1", 435 "sclk_isp_spi1_cam1", 436 "sclk_isp_spi0_cam1", 437 "aclk_cam1_333", 438 "aclk_cam1_400", 439 "aclk_cam1_552"; 440 clocks = <&xxti>, 441 <&cmu_top CLK_SCLK_ISP_UART_CAM1>, 442 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, 443 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, 444 <&cmu_top CLK_ACLK_CAM1_333>, 445 <&cmu_top CLK_ACLK_CAM1_400>, 446 <&cmu_top CLK_ACLK_CAM1_552>; 447 }; 448 449Example 3: UART controller node that consumes the clock generated by the clock 450 controller. 451 452 serial_0: serial@14C10000 { 453 compatible = "samsung,exynos5433-uart"; 454 reg = <0x14C10000 0x100>; 455 interrupts = <0 421 0>; 456 clocks = <&cmu_peric CLK_PCLK_UART0>, 457 <&cmu_peric CLK_SCLK_UART0>; 458 clock-names = "uart", "clk_uart_baud0"; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&uart0_bus>; 461 status = "disabled"; 462 }; 463