Lines Matching refs:clocks

3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
13     - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14     - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15     - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16     - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
17     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
18     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
19     - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
20     - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
21     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
23     clocks. The first register is the clock control register and is mandatory.
26   - clocks: Reference to the parent clocks, one per output clock. The parents
27     must appear in the same order as the output clocks.
29   - clock-output-names: The name of the clocks as free-form strings
30   - clock-indices: Indices of the gate clocks into the group (0 to 31)
32 The clocks, clock-output-names and clock-indices properties contain one entry
34 clocks must not be declared.
43 		compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
45 		clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,