1* Renesas CPG Module Stop (MSTP) Clocks 2 3The CPG can gate SoC device clocks. The gates are organized in groups of up to 432 gates. 5 6This device tree binding describes a single 32 gate clocks group per node. 7Clocks are referenced by user nodes by the MSTP node phandle and the clock 8index in the group, from 0 to 31. 9 10Required Properties: 11 12 - compatible: Must be one of the following 13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks 14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks 15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks 16 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks 17 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks 18 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks 19 - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks 20 - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks 21 - "renesas,cpg-mstp-clock" for generic MSTP gate clocks 22 - reg: Base address and length of the I/O mapped registers used by the MSTP 23 clocks. The first register is the clock control register and is mandatory. 24 The second register is the clock status register and is optional when not 25 implemented in hardware. 26 - clocks: Reference to the parent clocks, one per output clock. The parents 27 must appear in the same order as the output clocks. 28 - #clock-cells: Must be 1 29 - clock-output-names: The name of the clocks as free-form strings 30 - clock-indices: Indices of the gate clocks into the group (0 to 31) 31 32The clocks, clock-output-names and clock-indices properties contain one entry 33per gate clock. The MSTP groups are sparsely populated. Unimplemented gate 34clocks must not be declared. 35 36 37Example 38------- 39 40 #include <dt-bindings/clock/r8a7790-clock.h> 41 42 mstp3_clks: mstp3_clks@e615013c { 43 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 44 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 45 clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, 46 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, 47 <&mmc0_clk>; 48 #clock-cells = <1>; 49 clock-output-names = 50 "tpu0", "mmcif1", "sdhi3", "sdhi2", 51 "sdhi1", "sdhi0", "mmcif0"; 52 clock-indices = < 53 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 54 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 55 R8A7790_CLK_MMCIF0 56 >; 57 }; 58