Lines Matching refs:clocks
53 clocks = <&clks IMX5_CLK_ARM>;
79 clocks {
119 clocks = <&clks IMX5_CLK_SATA_GATE>,
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
204 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
216 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
228 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
241 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
255 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
267 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
283 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
290 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
299 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
320 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
330 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
340 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
387 clocks = <&clks IMX5_CLK_DUMMY>;
395 clocks = <&clks IMX5_CLK_DUMMY>;
402 clocks = <&clks IMX5_CLK_DUMMY>;
410 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
431 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
477 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
487 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
497 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
507 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
517 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
527 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
582 clocks = <&clks IMX5_CLK_I2C3_GATE>;
590 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
613 clocks = <&clks IMX5_CLK_IIM_GATE>;
620 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
629 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
639 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
649 clocks = <&clks IMX5_CLK_SDMA_GATE>,
662 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
674 clocks = <&clks IMX5_CLK_I2C2_GATE>;
684 clocks = <&clks IMX5_CLK_I2C1_GATE>;
694 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
714 clocks = <&clks IMX5_CLK_NFC_GATE>;
724 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
738 clocks = <&clks IMX5_CLK_FEC_GATE>,
749 clocks = <&clks IMX5_CLK_TVE_GATE>,
765 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
776 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
785 clocks = <&clks IMX5_CLK_OCRAM>;