1#include <dt-bindings/clock/tegra30-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra30-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7#include "skeleton.dtsi" 8 9/ { 10 compatible = "nvidia,tegra30"; 11 interrupt-parent = <&lic>; 12 13 pcie-controller@00003000 { 14 compatible = "nvidia,tegra30-pcie"; 15 device_type = "pci"; 16 reg = <0x00003000 0x00000800 /* PADS registers */ 17 0x00003800 0x00000200 /* AFI registers */ 18 0x10000000 0x10000000>; /* configuration space */ 19 reg-names = "pads", "afi", "cs"; 20 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 21 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22 interrupt-names = "intr", "msi"; 23 24 #interrupt-cells = <1>; 25 interrupt-map-mask = <0 0 0 0>; 26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 27 28 bus-range = <0x00 0xff>; 29 #address-cells = <3>; 30 #size-cells = <2>; 31 32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ 33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ 36 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ 37 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 38 39 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 40 <&tegra_car TEGRA30_CLK_AFI>, 41 <&tegra_car TEGRA30_CLK_PLL_E>, 42 <&tegra_car TEGRA30_CLK_CML0>; 43 clock-names = "pex", "afi", "pll_e", "cml"; 44 resets = <&tegra_car 70>, 45 <&tegra_car 72>, 46 <&tegra_car 74>; 47 reset-names = "pex", "afi", "pcie_x"; 48 status = "disabled"; 49 50 pci@1,0 { 51 device_type = "pci"; 52 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 53 reg = <0x000800 0 0 0 0>; 54 status = "disabled"; 55 56 #address-cells = <3>; 57 #size-cells = <2>; 58 ranges; 59 60 nvidia,num-lanes = <2>; 61 }; 62 63 pci@2,0 { 64 device_type = "pci"; 65 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 66 reg = <0x001000 0 0 0 0>; 67 status = "disabled"; 68 69 #address-cells = <3>; 70 #size-cells = <2>; 71 ranges; 72 73 nvidia,num-lanes = <2>; 74 }; 75 76 pci@3,0 { 77 device_type = "pci"; 78 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 79 reg = <0x001800 0 0 0 0>; 80 status = "disabled"; 81 82 #address-cells = <3>; 83 #size-cells = <2>; 84 ranges; 85 86 nvidia,num-lanes = <2>; 87 }; 88 }; 89 90 host1x@50000000 { 91 compatible = "nvidia,tegra30-host1x", "simple-bus"; 92 reg = <0x50000000 0x00024000>; 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 94 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 95 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <1>; 100 #size-cells = <1>; 101 102 ranges = <0x54000000 0x54000000 0x04000000>; 103 104 mpe@54040000 { 105 compatible = "nvidia,tegra30-mpe"; 106 reg = <0x54040000 0x00040000>; 107 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&tegra_car TEGRA30_CLK_MPE>; 109 resets = <&tegra_car 60>; 110 reset-names = "mpe"; 111 }; 112 113 vi@54080000 { 114 compatible = "nvidia,tegra30-vi"; 115 reg = <0x54080000 0x00040000>; 116 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA30_CLK_VI>; 118 resets = <&tegra_car 20>; 119 reset-names = "vi"; 120 }; 121 122 epp@540c0000 { 123 compatible = "nvidia,tegra30-epp"; 124 reg = <0x540c0000 0x00040000>; 125 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&tegra_car TEGRA30_CLK_EPP>; 127 resets = <&tegra_car 19>; 128 reset-names = "epp"; 129 }; 130 131 isp@54100000 { 132 compatible = "nvidia,tegra30-isp"; 133 reg = <0x54100000 0x00040000>; 134 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&tegra_car TEGRA30_CLK_ISP>; 136 resets = <&tegra_car 23>; 137 reset-names = "isp"; 138 }; 139 140 gr2d@54140000 { 141 compatible = "nvidia,tegra30-gr2d"; 142 reg = <0x54140000 0x00040000>; 143 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 145 resets = <&tegra_car 21>; 146 reset-names = "2d"; 147 }; 148 149 gr3d@54180000 { 150 compatible = "nvidia,tegra30-gr3d"; 151 reg = <0x54180000 0x00040000>; 152 clocks = <&tegra_car TEGRA30_CLK_GR3D 153 &tegra_car TEGRA30_CLK_GR3D2>; 154 clock-names = "3d", "3d2"; 155 resets = <&tegra_car 24>, 156 <&tegra_car 98>; 157 reset-names = "3d", "3d2"; 158 }; 159 160 dc@54200000 { 161 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; 162 reg = <0x54200000 0x00040000>; 163 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 165 <&tegra_car TEGRA30_CLK_PLL_P>; 166 clock-names = "dc", "parent"; 167 resets = <&tegra_car 27>; 168 reset-names = "dc"; 169 170 iommus = <&mc TEGRA_SWGROUP_DC>; 171 172 nvidia,head = <0>; 173 174 rgb { 175 status = "disabled"; 176 }; 177 }; 178 179 dc@54240000 { 180 compatible = "nvidia,tegra30-dc"; 181 reg = <0x54240000 0x00040000>; 182 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 184 <&tegra_car TEGRA30_CLK_PLL_P>; 185 clock-names = "dc", "parent"; 186 resets = <&tegra_car 26>; 187 reset-names = "dc"; 188 189 iommus = <&mc TEGRA_SWGROUP_DCB>; 190 191 nvidia,head = <1>; 192 193 rgb { 194 status = "disabled"; 195 }; 196 }; 197 198 hdmi@54280000 { 199 compatible = "nvidia,tegra30-hdmi"; 200 reg = <0x54280000 0x00040000>; 201 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 203 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 204 clock-names = "hdmi", "parent"; 205 resets = <&tegra_car 51>; 206 reset-names = "hdmi"; 207 status = "disabled"; 208 }; 209 210 tvo@542c0000 { 211 compatible = "nvidia,tegra30-tvo"; 212 reg = <0x542c0000 0x00040000>; 213 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&tegra_car TEGRA30_CLK_TVO>; 215 status = "disabled"; 216 }; 217 218 dsi@54300000 { 219 compatible = "nvidia,tegra30-dsi"; 220 reg = <0x54300000 0x00040000>; 221 clocks = <&tegra_car TEGRA30_CLK_DSIA>; 222 resets = <&tegra_car 48>; 223 reset-names = "dsi"; 224 status = "disabled"; 225 }; 226 }; 227 228 timer@50040600 { 229 compatible = "arm,cortex-a9-twd-timer"; 230 reg = <0x50040600 0x20>; 231 interrupt-parent = <&intc>; 232 interrupts = <GIC_PPI 13 233 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 234 clocks = <&tegra_car TEGRA30_CLK_TWD>; 235 }; 236 237 intc: interrupt-controller@50041000 { 238 compatible = "arm,cortex-a9-gic"; 239 reg = <0x50041000 0x1000 240 0x50040100 0x0100>; 241 interrupt-controller; 242 #interrupt-cells = <3>; 243 interrupt-parent = <&intc>; 244 }; 245 246 cache-controller@50043000 { 247 compatible = "arm,pl310-cache"; 248 reg = <0x50043000 0x1000>; 249 arm,data-latency = <6 6 2>; 250 arm,tag-latency = <5 5 2>; 251 cache-unified; 252 cache-level = <2>; 253 }; 254 255 lic: interrupt-controller@60004000 { 256 compatible = "nvidia,tegra30-ictlr"; 257 reg = <0x60004000 0x100>, 258 <0x60004100 0x50>, 259 <0x60004200 0x50>, 260 <0x60004300 0x50>, 261 <0x60004400 0x50>; 262 interrupt-controller; 263 #interrupt-cells = <3>; 264 interrupt-parent = <&intc>; 265 }; 266 267 timer@60005000 { 268 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 269 reg = <0x60005000 0x400>; 270 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 277 }; 278 279 tegra_car: clock@60006000 { 280 compatible = "nvidia,tegra30-car"; 281 reg = <0x60006000 0x1000>; 282 #clock-cells = <1>; 283 #reset-cells = <1>; 284 }; 285 286 flow-controller@60007000 { 287 compatible = "nvidia,tegra30-flowctrl"; 288 reg = <0x60007000 0x1000>; 289 }; 290 291 apbdma: dma@6000a000 { 292 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 293 reg = <0x6000a000 0x1400>; 294 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 327 resets = <&tegra_car 34>; 328 reset-names = "dma"; 329 #dma-cells = <1>; 330 }; 331 332 ahb: ahb@6000c004 { 333 compatible = "nvidia,tegra30-ahb"; 334 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ 335 }; 336 337 gpio: gpio@6000d000 { 338 compatible = "nvidia,tegra30-gpio"; 339 reg = <0x6000d000 0x1000>; 340 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 348 #gpio-cells = <2>; 349 gpio-controller; 350 #interrupt-cells = <2>; 351 interrupt-controller; 352 }; 353 354 apbmisc@70000800 { 355 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 356 reg = <0x70000800 0x64 /* Chip revision */ 357 0x70000008 0x04>; /* Strapping options */ 358 }; 359 360 pinmux: pinmux@70000868 { 361 compatible = "nvidia,tegra30-pinmux"; 362 reg = <0x70000868 0xd4 /* Pad control registers */ 363 0x70003000 0x3e4>; /* Mux registers */ 364 }; 365 366 /* 367 * There are two serial driver i.e. 8250 based simple serial 368 * driver and APB DMA based serial driver for higher baudrate 369 * and performace. To enable the 8250 based driver, the compatible 370 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable 371 * the APB DMA based serial driver, the comptible is 372 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 373 */ 374 uarta: serial@70006000 { 375 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 376 reg = <0x70006000 0x40>; 377 reg-shift = <2>; 378 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 380 resets = <&tegra_car 6>; 381 reset-names = "serial"; 382 dmas = <&apbdma 8>, <&apbdma 8>; 383 dma-names = "rx", "tx"; 384 status = "disabled"; 385 }; 386 387 uartb: serial@70006040 { 388 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 389 reg = <0x70006040 0x40>; 390 reg-shift = <2>; 391 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 393 resets = <&tegra_car 7>; 394 reset-names = "serial"; 395 dmas = <&apbdma 9>, <&apbdma 9>; 396 dma-names = "rx", "tx"; 397 status = "disabled"; 398 }; 399 400 uartc: serial@70006200 { 401 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 402 reg = <0x70006200 0x100>; 403 reg-shift = <2>; 404 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 406 resets = <&tegra_car 55>; 407 reset-names = "serial"; 408 dmas = <&apbdma 10>, <&apbdma 10>; 409 dma-names = "rx", "tx"; 410 status = "disabled"; 411 }; 412 413 uartd: serial@70006300 { 414 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 415 reg = <0x70006300 0x100>; 416 reg-shift = <2>; 417 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 419 resets = <&tegra_car 65>; 420 reset-names = "serial"; 421 dmas = <&apbdma 19>, <&apbdma 19>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 426 uarte: serial@70006400 { 427 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 428 reg = <0x70006400 0x100>; 429 reg-shift = <2>; 430 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 432 resets = <&tegra_car 66>; 433 reset-names = "serial"; 434 dmas = <&apbdma 20>, <&apbdma 20>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 pwm: pwm@7000a000 { 440 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 441 reg = <0x7000a000 0x100>; 442 #pwm-cells = <2>; 443 clocks = <&tegra_car TEGRA30_CLK_PWM>; 444 resets = <&tegra_car 17>; 445 reset-names = "pwm"; 446 status = "disabled"; 447 }; 448 449 rtc@7000e000 { 450 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 451 reg = <0x7000e000 0x100>; 452 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&tegra_car TEGRA30_CLK_RTC>; 454 }; 455 456 i2c@7000c000 { 457 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 458 reg = <0x7000c000 0x100>; 459 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 463 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 464 clock-names = "div-clk", "fast-clk"; 465 resets = <&tegra_car 12>; 466 reset-names = "i2c"; 467 dmas = <&apbdma 21>, <&apbdma 21>; 468 dma-names = "rx", "tx"; 469 status = "disabled"; 470 }; 471 472 i2c@7000c400 { 473 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 474 reg = <0x7000c400 0x100>; 475 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 479 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 480 clock-names = "div-clk", "fast-clk"; 481 resets = <&tegra_car 54>; 482 reset-names = "i2c"; 483 dmas = <&apbdma 22>, <&apbdma 22>; 484 dma-names = "rx", "tx"; 485 status = "disabled"; 486 }; 487 488 i2c@7000c500 { 489 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 490 reg = <0x7000c500 0x100>; 491 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 495 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 496 clock-names = "div-clk", "fast-clk"; 497 resets = <&tegra_car 67>; 498 reset-names = "i2c"; 499 dmas = <&apbdma 23>, <&apbdma 23>; 500 dma-names = "rx", "tx"; 501 status = "disabled"; 502 }; 503 504 i2c@7000c700 { 505 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 506 reg = <0x7000c700 0x100>; 507 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 511 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 512 resets = <&tegra_car 103>; 513 reset-names = "i2c"; 514 clock-names = "div-clk", "fast-clk"; 515 dmas = <&apbdma 26>, <&apbdma 26>; 516 dma-names = "rx", "tx"; 517 status = "disabled"; 518 }; 519 520 i2c@7000d000 { 521 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 522 reg = <0x7000d000 0x100>; 523 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 527 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 528 clock-names = "div-clk", "fast-clk"; 529 resets = <&tegra_car 47>; 530 reset-names = "i2c"; 531 dmas = <&apbdma 24>, <&apbdma 24>; 532 dma-names = "rx", "tx"; 533 status = "disabled"; 534 }; 535 536 spi@7000d400 { 537 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 538 reg = <0x7000d400 0x200>; 539 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 543 resets = <&tegra_car 41>; 544 reset-names = "spi"; 545 dmas = <&apbdma 15>, <&apbdma 15>; 546 dma-names = "rx", "tx"; 547 status = "disabled"; 548 }; 549 550 spi@7000d600 { 551 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 552 reg = <0x7000d600 0x200>; 553 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 557 resets = <&tegra_car 44>; 558 reset-names = "spi"; 559 dmas = <&apbdma 16>, <&apbdma 16>; 560 dma-names = "rx", "tx"; 561 status = "disabled"; 562 }; 563 564 spi@7000d800 { 565 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 566 reg = <0x7000d800 0x200>; 567 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 571 resets = <&tegra_car 46>; 572 reset-names = "spi"; 573 dmas = <&apbdma 17>, <&apbdma 17>; 574 dma-names = "rx", "tx"; 575 status = "disabled"; 576 }; 577 578 spi@7000da00 { 579 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 580 reg = <0x7000da00 0x200>; 581 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 585 resets = <&tegra_car 68>; 586 reset-names = "spi"; 587 dmas = <&apbdma 18>, <&apbdma 18>; 588 dma-names = "rx", "tx"; 589 status = "disabled"; 590 }; 591 592 spi@7000dc00 { 593 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 594 reg = <0x7000dc00 0x200>; 595 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 599 resets = <&tegra_car 104>; 600 reset-names = "spi"; 601 dmas = <&apbdma 27>, <&apbdma 27>; 602 dma-names = "rx", "tx"; 603 status = "disabled"; 604 }; 605 606 spi@7000de00 { 607 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 608 reg = <0x7000de00 0x200>; 609 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 613 resets = <&tegra_car 106>; 614 reset-names = "spi"; 615 dmas = <&apbdma 28>, <&apbdma 28>; 616 dma-names = "rx", "tx"; 617 status = "disabled"; 618 }; 619 620 kbc@7000e200 { 621 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 622 reg = <0x7000e200 0x100>; 623 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&tegra_car TEGRA30_CLK_KBC>; 625 resets = <&tegra_car 36>; 626 reset-names = "kbc"; 627 status = "disabled"; 628 }; 629 630 pmc@7000e400 { 631 compatible = "nvidia,tegra30-pmc"; 632 reg = <0x7000e400 0x400>; 633 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 634 clock-names = "pclk", "clk32k_in"; 635 }; 636 637 mc: memory-controller@7000f000 { 638 compatible = "nvidia,tegra30-mc"; 639 reg = <0x7000f000 0x400>; 640 clocks = <&tegra_car TEGRA30_CLK_MC>; 641 clock-names = "mc"; 642 643 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 644 645 #iommu-cells = <1>; 646 }; 647 648 fuse@7000f800 { 649 compatible = "nvidia,tegra30-efuse"; 650 reg = <0x7000f800 0x400>; 651 clocks = <&tegra_car TEGRA30_CLK_FUSE>; 652 clock-names = "fuse"; 653 resets = <&tegra_car 39>; 654 reset-names = "fuse"; 655 }; 656 657 ahub@70080000 { 658 compatible = "nvidia,tegra30-ahub"; 659 reg = <0x70080000 0x200 660 0x70080200 0x100>; 661 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 663 <&tegra_car TEGRA30_CLK_APBIF>; 664 clock-names = "d_audio", "apbif"; 665 resets = <&tegra_car 106>, /* d_audio */ 666 <&tegra_car 107>, /* apbif */ 667 <&tegra_car 30>, /* i2s0 */ 668 <&tegra_car 11>, /* i2s1 */ 669 <&tegra_car 18>, /* i2s2 */ 670 <&tegra_car 101>, /* i2s3 */ 671 <&tegra_car 102>, /* i2s4 */ 672 <&tegra_car 108>, /* dam0 */ 673 <&tegra_car 109>, /* dam1 */ 674 <&tegra_car 110>, /* dam2 */ 675 <&tegra_car 10>; /* spdif */ 676 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 677 "i2s3", "i2s4", "dam0", "dam1", "dam2", 678 "spdif"; 679 dmas = <&apbdma 1>, <&apbdma 1>, 680 <&apbdma 2>, <&apbdma 2>, 681 <&apbdma 3>, <&apbdma 3>, 682 <&apbdma 4>, <&apbdma 4>; 683 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 684 "rx3", "tx3"; 685 ranges; 686 #address-cells = <1>; 687 #size-cells = <1>; 688 689 tegra_i2s0: i2s@70080300 { 690 compatible = "nvidia,tegra30-i2s"; 691 reg = <0x70080300 0x100>; 692 nvidia,ahub-cif-ids = <4 4>; 693 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 694 resets = <&tegra_car 30>; 695 reset-names = "i2s"; 696 status = "disabled"; 697 }; 698 699 tegra_i2s1: i2s@70080400 { 700 compatible = "nvidia,tegra30-i2s"; 701 reg = <0x70080400 0x100>; 702 nvidia,ahub-cif-ids = <5 5>; 703 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 704 resets = <&tegra_car 11>; 705 reset-names = "i2s"; 706 status = "disabled"; 707 }; 708 709 tegra_i2s2: i2s@70080500 { 710 compatible = "nvidia,tegra30-i2s"; 711 reg = <0x70080500 0x100>; 712 nvidia,ahub-cif-ids = <6 6>; 713 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 714 resets = <&tegra_car 18>; 715 reset-names = "i2s"; 716 status = "disabled"; 717 }; 718 719 tegra_i2s3: i2s@70080600 { 720 compatible = "nvidia,tegra30-i2s"; 721 reg = <0x70080600 0x100>; 722 nvidia,ahub-cif-ids = <7 7>; 723 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 724 resets = <&tegra_car 101>; 725 reset-names = "i2s"; 726 status = "disabled"; 727 }; 728 729 tegra_i2s4: i2s@70080700 { 730 compatible = "nvidia,tegra30-i2s"; 731 reg = <0x70080700 0x100>; 732 nvidia,ahub-cif-ids = <8 8>; 733 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 734 resets = <&tegra_car 102>; 735 reset-names = "i2s"; 736 status = "disabled"; 737 }; 738 }; 739 740 sdhci@78000000 { 741 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 742 reg = <0x78000000 0x200>; 743 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 745 resets = <&tegra_car 14>; 746 reset-names = "sdhci"; 747 status = "disabled"; 748 }; 749 750 sdhci@78000200 { 751 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 752 reg = <0x78000200 0x200>; 753 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 755 resets = <&tegra_car 9>; 756 reset-names = "sdhci"; 757 status = "disabled"; 758 }; 759 760 sdhci@78000400 { 761 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 762 reg = <0x78000400 0x200>; 763 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 765 resets = <&tegra_car 69>; 766 reset-names = "sdhci"; 767 status = "disabled"; 768 }; 769 770 sdhci@78000600 { 771 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 772 reg = <0x78000600 0x200>; 773 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 775 resets = <&tegra_car 15>; 776 reset-names = "sdhci"; 777 status = "disabled"; 778 }; 779 780 usb@7d000000 { 781 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 782 reg = <0x7d000000 0x4000>; 783 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 784 phy_type = "utmi"; 785 clocks = <&tegra_car TEGRA30_CLK_USBD>; 786 resets = <&tegra_car 22>; 787 reset-names = "usb"; 788 nvidia,needs-double-reset; 789 nvidia,phy = <&phy1>; 790 status = "disabled"; 791 }; 792 793 phy1: usb-phy@7d000000 { 794 compatible = "nvidia,tegra30-usb-phy"; 795 reg = <0x7d000000 0x4000 0x7d000000 0x4000>; 796 phy_type = "utmi"; 797 clocks = <&tegra_car TEGRA30_CLK_USBD>, 798 <&tegra_car TEGRA30_CLK_PLL_U>, 799 <&tegra_car TEGRA30_CLK_USBD>; 800 clock-names = "reg", "pll_u", "utmi-pads"; 801 resets = <&tegra_car 22>, <&tegra_car 22>; 802 reset-names = "usb", "utmi-pads"; 803 nvidia,hssync-start-delay = <9>; 804 nvidia,idle-wait-delay = <17>; 805 nvidia,elastic-limit = <16>; 806 nvidia,term-range-adj = <6>; 807 nvidia,xcvr-setup = <51>; 808 nvidia.xcvr-setup-use-fuses; 809 nvidia,xcvr-lsfslew = <1>; 810 nvidia,xcvr-lsrslew = <1>; 811 nvidia,xcvr-hsslew = <32>; 812 nvidia,hssquelch-level = <2>; 813 nvidia,hsdiscon-level = <5>; 814 nvidia,has-utmi-pad-registers; 815 status = "disabled"; 816 }; 817 818 usb@7d004000 { 819 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 820 reg = <0x7d004000 0x4000>; 821 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 822 phy_type = "utmi"; 823 clocks = <&tegra_car TEGRA30_CLK_USB2>; 824 resets = <&tegra_car 58>; 825 reset-names = "usb"; 826 nvidia,phy = <&phy2>; 827 status = "disabled"; 828 }; 829 830 phy2: usb-phy@7d004000 { 831 compatible = "nvidia,tegra30-usb-phy"; 832 reg = <0x7d004000 0x4000 0x7d000000 0x4000>; 833 phy_type = "utmi"; 834 clocks = <&tegra_car TEGRA30_CLK_USB2>, 835 <&tegra_car TEGRA30_CLK_PLL_U>, 836 <&tegra_car TEGRA30_CLK_USBD>; 837 clock-names = "reg", "pll_u", "utmi-pads"; 838 resets = <&tegra_car 58>, <&tegra_car 22>; 839 reset-names = "usb", "utmi-pads"; 840 nvidia,hssync-start-delay = <9>; 841 nvidia,idle-wait-delay = <17>; 842 nvidia,elastic-limit = <16>; 843 nvidia,term-range-adj = <6>; 844 nvidia,xcvr-setup = <51>; 845 nvidia.xcvr-setup-use-fuses; 846 nvidia,xcvr-lsfslew = <2>; 847 nvidia,xcvr-lsrslew = <2>; 848 nvidia,xcvr-hsslew = <32>; 849 nvidia,hssquelch-level = <2>; 850 nvidia,hsdiscon-level = <5>; 851 status = "disabled"; 852 }; 853 854 usb@7d008000 { 855 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 856 reg = <0x7d008000 0x4000>; 857 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 858 phy_type = "utmi"; 859 clocks = <&tegra_car TEGRA30_CLK_USB3>; 860 resets = <&tegra_car 59>; 861 reset-names = "usb"; 862 nvidia,phy = <&phy3>; 863 status = "disabled"; 864 }; 865 866 phy3: usb-phy@7d008000 { 867 compatible = "nvidia,tegra30-usb-phy"; 868 reg = <0x7d008000 0x4000 0x7d000000 0x4000>; 869 phy_type = "utmi"; 870 clocks = <&tegra_car TEGRA30_CLK_USB3>, 871 <&tegra_car TEGRA30_CLK_PLL_U>, 872 <&tegra_car TEGRA30_CLK_USBD>; 873 clock-names = "reg", "pll_u", "utmi-pads"; 874 resets = <&tegra_car 59>, <&tegra_car 22>; 875 reset-names = "usb", "utmi-pads"; 876 nvidia,hssync-start-delay = <0>; 877 nvidia,idle-wait-delay = <17>; 878 nvidia,elastic-limit = <16>; 879 nvidia,term-range-adj = <6>; 880 nvidia,xcvr-setup = <51>; 881 nvidia.xcvr-setup-use-fuses; 882 nvidia,xcvr-lsfslew = <2>; 883 nvidia,xcvr-lsrslew = <2>; 884 nvidia,xcvr-hsslew = <32>; 885 nvidia,hssquelch-level = <2>; 886 nvidia,hsdiscon-level = <5>; 887 status = "disabled"; 888 }; 889 890 cpus { 891 #address-cells = <1>; 892 #size-cells = <0>; 893 894 cpu@0 { 895 device_type = "cpu"; 896 compatible = "arm,cortex-a9"; 897 reg = <0>; 898 }; 899 900 cpu@1 { 901 device_type = "cpu"; 902 compatible = "arm,cortex-a9"; 903 reg = <1>; 904 }; 905 906 cpu@2 { 907 device_type = "cpu"; 908 compatible = "arm,cortex-a9"; 909 reg = <2>; 910 }; 911 912 cpu@3 { 913 device_type = "cpu"; 914 compatible = "arm,cortex-a9"; 915 reg = <3>; 916 }; 917 }; 918 919 pmu { 920 compatible = "arm,cortex-a9-pmu"; 921 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 925 }; 926}; 927