1* Clock Block on Freescale QorIQ Platforms
2
3Freescale qoriq chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including
7cores and peripheral IP blocks.
8Please refer to the Reference Manual for details.
9
10All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11which the chip complies.
12
13Chassis Version		Example Chips
14---------------		-------------
151.0			p4080, p5020, p5040
162.0			t4240, b4860, t1040
17
181. Clock Block Binding
19
20Required properties:
21- compatible: Should contain a specific clock block compatible string
22	and a single chassis clock compatible string.
23	Clock block strings include, but not limited to, one of the:
24	* "fsl,p2041-clockgen"
25	* "fsl,p3041-clockgen"
26	* "fsl,p4080-clockgen"
27	* "fsl,p5020-clockgen"
28	* "fsl,p5040-clockgen"
29	* "fsl,t4240-clockgen"
30	* "fsl,b4420-clockgen"
31	* "fsl,b4860-clockgen"
32	* "fsl,ls1021a-clockgen"
33	Chassis clock strings include:
34	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
35	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
36- reg: Describes the address of the device's resources within the
37	address space defined by its parent bus, and resource zero
38	represents the clock register set
39- clock-frequency: Input system clock frequency
40
41Recommended properties:
42- ranges: Allows valid translation between child's address space and
43	parent's. Must be present if the device has sub-nodes.
44- #address-cells: Specifies the number of cells used to represent
45	physical base addresses.  Must be present if the device has
46	sub-nodes and set to 1 if present
47- #size-cells: Specifies the number of cells used to represent
48	the size of an address. Must be present if the device has
49	sub-nodes and set to 1 if present
50
512. Clock Provider/Consumer Binding
52
53Most of the bindings are from the common clock binding[1].
54 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
55
56Required properties:
57- compatible : Should include one of the following:
58	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
59	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
60	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
61	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
62	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
63		It takes parent's clock-frequency as its clock.
64	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
65		It takes parent's clock-frequency as its clock.
66	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
67	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
68- #clock-cells: From common clock binding. The number of cells in a
69	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
70	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
71	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
72	clock-specifier cell may take the following values:
73	* 0 - equal to the PLL frequency
74	* 1 - equal to the PLL frequency divided by 2
75	* 2 - equal to the PLL frequency divided by 4
76
77Recommended properties:
78- clocks: Should be the phandle of input parent clock
79- clock-names: From common clock binding, indicates the clock name
80- clock-output-names: From common clock binding, indicates the names of
81	output clocks
82- reg: Should be the offset and length of clock block base address.
83	The length should be 4.
84
85Example for clock block and clock provider:
86/ {
87	clockgen: global-utilities@e1000 {
88		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
89		ranges = <0x0 0xe1000 0x1000>;
90		clock-frequency = <133333333>;
91		reg = <0xe1000 0x1000>;
92		#address-cells = <1>;
93		#size-cells = <1>;
94
95		sysclk: sysclk {
96			#clock-cells = <0>;
97			compatible = "fsl,qoriq-sysclk-1.0";
98			clock-output-names = "sysclk";
99		};
100
101		pll0: pll0@800 {
102			#clock-cells = <1>;
103			reg = <0x800 0x4>;
104			compatible = "fsl,qoriq-core-pll-1.0";
105			clocks = <&sysclk>;
106			clock-output-names = "pll0", "pll0-div2";
107		};
108
109		pll1: pll1@820 {
110			#clock-cells = <1>;
111			reg = <0x820 0x4>;
112			compatible = "fsl,qoriq-core-pll-1.0";
113			clocks = <&sysclk>;
114			clock-output-names = "pll1", "pll1-div2";
115		};
116
117		mux0: mux0@0 {
118			#clock-cells = <0>;
119			reg = <0x0 0x4>;
120			compatible = "fsl,qoriq-core-mux-1.0";
121			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
122			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
123			clock-output-names = "cmux0";
124		};
125
126		mux1: mux1@20 {
127			#clock-cells = <0>;
128			reg = <0x20 0x4>;
129			compatible = "fsl,qoriq-core-mux-1.0";
130			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
131			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
132			clock-output-names = "cmux1";
133		};
134
135		platform-pll: platform-pll@c00 {
136			#clock-cells = <1>;
137			reg = <0xc00 0x4>;
138			compatible = "fsl,qoriq-platform-pll-1.0";
139			clocks = <&sysclk>;
140			clock-output-names = "platform-pll", "platform-pll-div2";
141		};
142	};
143};
144
145Example for clock consumer:
146
147/ {
148	cpu0: PowerPC,e5500@0 {
149		...
150		clocks = <&mux0>;
151		...
152	};
153};
154