1/* 2 * Device Tree Source for the r8a73a4 SoC 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Magnus Damm 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r8a73a4-clock.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15 16/ { 17 compatible = "renesas,r8a73a4"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a15"; 29 reg = <0>; 30 clock-frequency = <1500000000>; 31 power-domains = <&pd_a2sl>; 32 }; 33 }; 34 35 ptm { 36 compatible = "arm,coresight-etm3x"; 37 power-domains = <&pd_d4>; 38 }; 39 40 timer { 41 compatible = "arm,armv7-timer"; 42 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 43 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 44 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 45 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 46 }; 47 48 dbsc1: memory-controller@e6790000 { 49 compatible = "renesas,dbsc-r8a73a4"; 50 reg = <0 0xe6790000 0 0x10000>; 51 power-domains = <&pd_a3bc>; 52 }; 53 54 dbsc2: memory-controller@e67a0000 { 55 compatible = "renesas,dbsc-r8a73a4"; 56 reg = <0 0xe67a0000 0 0x10000>; 57 power-domains = <&pd_a3bc>; 58 }; 59 60 dmac: dma-multiplexer { 61 compatible = "renesas,shdma-mux"; 62 #dma-cells = <1>; 63 dma-channels = <20>; 64 dma-requests = <256>; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges; 68 69 dma0: dma-controller@e6700020 { 70 compatible = "renesas,shdma-r8a73a4"; 71 reg = <0 0xe6700020 0 0x89e0>; 72 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 73 0 200 IRQ_TYPE_LEVEL_HIGH 74 0 201 IRQ_TYPE_LEVEL_HIGH 75 0 202 IRQ_TYPE_LEVEL_HIGH 76 0 203 IRQ_TYPE_LEVEL_HIGH 77 0 204 IRQ_TYPE_LEVEL_HIGH 78 0 205 IRQ_TYPE_LEVEL_HIGH 79 0 206 IRQ_TYPE_LEVEL_HIGH 80 0 207 IRQ_TYPE_LEVEL_HIGH 81 0 208 IRQ_TYPE_LEVEL_HIGH 82 0 209 IRQ_TYPE_LEVEL_HIGH 83 0 210 IRQ_TYPE_LEVEL_HIGH 84 0 211 IRQ_TYPE_LEVEL_HIGH 85 0 212 IRQ_TYPE_LEVEL_HIGH 86 0 213 IRQ_TYPE_LEVEL_HIGH 87 0 214 IRQ_TYPE_LEVEL_HIGH 88 0 215 IRQ_TYPE_LEVEL_HIGH 89 0 216 IRQ_TYPE_LEVEL_HIGH 90 0 217 IRQ_TYPE_LEVEL_HIGH 91 0 218 IRQ_TYPE_LEVEL_HIGH 92 0 219 IRQ_TYPE_LEVEL_HIGH>; 93 interrupt-names = "error", 94 "ch0", "ch1", "ch2", "ch3", 95 "ch4", "ch5", "ch6", "ch7", 96 "ch8", "ch9", "ch10", "ch11", 97 "ch12", "ch13", "ch14", "ch15", 98 "ch16", "ch17", "ch18", "ch19"; 99 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; 100 power-domains = <&pd_a3sp>; 101 }; 102 }; 103 104 i2c5: i2c@e60b0000 { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 108 reg = <0 0xe60b0000 0 0x428>; 109 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; 111 power-domains = <&pd_a3sp>; 112 113 status = "disabled"; 114 }; 115 116 cmt1: timer@e6130000 { 117 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; 118 reg = <0 0xe6130000 0 0x1004>; 119 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 121 clock-names = "fck"; 122 power-domains = <&pd_c5>; 123 124 renesas,channels-mask = <0xff>; 125 126 status = "disabled"; 127 }; 128 129 irqc0: interrupt-controller@e61c0000 { 130 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 131 #interrupt-cells = <2>; 132 interrupt-controller; 133 reg = <0 0xe61c0000 0 0x200>; 134 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 135 <0 1 IRQ_TYPE_LEVEL_HIGH>, 136 <0 2 IRQ_TYPE_LEVEL_HIGH>, 137 <0 3 IRQ_TYPE_LEVEL_HIGH>, 138 <0 4 IRQ_TYPE_LEVEL_HIGH>, 139 <0 5 IRQ_TYPE_LEVEL_HIGH>, 140 <0 6 IRQ_TYPE_LEVEL_HIGH>, 141 <0 7 IRQ_TYPE_LEVEL_HIGH>, 142 <0 8 IRQ_TYPE_LEVEL_HIGH>, 143 <0 9 IRQ_TYPE_LEVEL_HIGH>, 144 <0 10 IRQ_TYPE_LEVEL_HIGH>, 145 <0 11 IRQ_TYPE_LEVEL_HIGH>, 146 <0 12 IRQ_TYPE_LEVEL_HIGH>, 147 <0 13 IRQ_TYPE_LEVEL_HIGH>, 148 <0 14 IRQ_TYPE_LEVEL_HIGH>, 149 <0 15 IRQ_TYPE_LEVEL_HIGH>, 150 <0 16 IRQ_TYPE_LEVEL_HIGH>, 151 <0 17 IRQ_TYPE_LEVEL_HIGH>, 152 <0 18 IRQ_TYPE_LEVEL_HIGH>, 153 <0 19 IRQ_TYPE_LEVEL_HIGH>, 154 <0 20 IRQ_TYPE_LEVEL_HIGH>, 155 <0 21 IRQ_TYPE_LEVEL_HIGH>, 156 <0 22 IRQ_TYPE_LEVEL_HIGH>, 157 <0 23 IRQ_TYPE_LEVEL_HIGH>, 158 <0 24 IRQ_TYPE_LEVEL_HIGH>, 159 <0 25 IRQ_TYPE_LEVEL_HIGH>, 160 <0 26 IRQ_TYPE_LEVEL_HIGH>, 161 <0 27 IRQ_TYPE_LEVEL_HIGH>, 162 <0 28 IRQ_TYPE_LEVEL_HIGH>, 163 <0 29 IRQ_TYPE_LEVEL_HIGH>, 164 <0 30 IRQ_TYPE_LEVEL_HIGH>, 165 <0 31 IRQ_TYPE_LEVEL_HIGH>; 166 power-domains = <&pd_c4>; 167 }; 168 169 irqc1: interrupt-controller@e61c0200 { 170 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 reg = <0 0xe61c0200 0 0x200>; 174 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 175 <0 33 IRQ_TYPE_LEVEL_HIGH>, 176 <0 34 IRQ_TYPE_LEVEL_HIGH>, 177 <0 35 IRQ_TYPE_LEVEL_HIGH>, 178 <0 36 IRQ_TYPE_LEVEL_HIGH>, 179 <0 37 IRQ_TYPE_LEVEL_HIGH>, 180 <0 38 IRQ_TYPE_LEVEL_HIGH>, 181 <0 39 IRQ_TYPE_LEVEL_HIGH>, 182 <0 40 IRQ_TYPE_LEVEL_HIGH>, 183 <0 41 IRQ_TYPE_LEVEL_HIGH>, 184 <0 42 IRQ_TYPE_LEVEL_HIGH>, 185 <0 43 IRQ_TYPE_LEVEL_HIGH>, 186 <0 44 IRQ_TYPE_LEVEL_HIGH>, 187 <0 45 IRQ_TYPE_LEVEL_HIGH>, 188 <0 46 IRQ_TYPE_LEVEL_HIGH>, 189 <0 47 IRQ_TYPE_LEVEL_HIGH>, 190 <0 48 IRQ_TYPE_LEVEL_HIGH>, 191 <0 49 IRQ_TYPE_LEVEL_HIGH>, 192 <0 50 IRQ_TYPE_LEVEL_HIGH>, 193 <0 51 IRQ_TYPE_LEVEL_HIGH>, 194 <0 52 IRQ_TYPE_LEVEL_HIGH>, 195 <0 53 IRQ_TYPE_LEVEL_HIGH>, 196 <0 54 IRQ_TYPE_LEVEL_HIGH>, 197 <0 55 IRQ_TYPE_LEVEL_HIGH>, 198 <0 56 IRQ_TYPE_LEVEL_HIGH>, 199 <0 57 IRQ_TYPE_LEVEL_HIGH>; 200 power-domains = <&pd_c4>; 201 }; 202 203 pfc: pfc@e6050000 { 204 compatible = "renesas,pfc-r8a73a4"; 205 reg = <0 0xe6050000 0 0x9000>; 206 gpio-controller; 207 #gpio-cells = <2>; 208 interrupts-extended = 209 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, 210 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, 211 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, 212 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, 213 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, 214 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, 215 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, 216 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, 217 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, 218 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, 219 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, 220 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, 221 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, 222 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, 223 <&irqc1 24 0>, <&irqc1 25 0>; 224 power-domains = <&pd_c5>; 225 }; 226 227 thermal@e61f0000 { 228 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 229 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 230 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 231 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; 233 power-domains = <&pd_c5>; 234 }; 235 236 i2c0: i2c@e6500000 { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 240 reg = <0 0xe6500000 0 0x428>; 241 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; 243 power-domains = <&pd_a3sp>; 244 status = "disabled"; 245 }; 246 247 i2c1: i2c@e6510000 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 251 reg = <0 0xe6510000 0 0x428>; 252 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; 254 power-domains = <&pd_a3sp>; 255 status = "disabled"; 256 }; 257 258 i2c2: i2c@e6520000 { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 262 reg = <0 0xe6520000 0 0x428>; 263 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; 265 power-domains = <&pd_a3sp>; 266 status = "disabled"; 267 }; 268 269 i2c3: i2c@e6530000 { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 273 reg = <0 0xe6530000 0 0x428>; 274 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; 276 power-domains = <&pd_a3sp>; 277 status = "disabled"; 278 }; 279 280 i2c4: i2c@e6540000 { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 284 reg = <0 0xe6540000 0 0x428>; 285 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; 287 power-domains = <&pd_a3sp>; 288 status = "disabled"; 289 }; 290 291 i2c6: i2c@e6550000 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 295 reg = <0 0xe6550000 0 0x428>; 296 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; 298 power-domains = <&pd_a3sp>; 299 status = "disabled"; 300 }; 301 302 i2c7: i2c@e6560000 { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 306 reg = <0 0xe6560000 0 0x428>; 307 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; 309 power-domains = <&pd_a3sp>; 310 status = "disabled"; 311 }; 312 313 i2c8: i2c@e6570000 { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 317 reg = <0 0xe6570000 0 0x428>; 318 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; 320 power-domains = <&pd_a3sp>; 321 status = "disabled"; 322 }; 323 324 scifb0: serial@e6c20000 { 325 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 326 reg = <0 0xe6c20000 0 0x100>; 327 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; 329 clock-names = "sci_ick"; 330 power-domains = <&pd_a3sp>; 331 status = "disabled"; 332 }; 333 334 scifb1: serial@e6c30000 { 335 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 336 reg = <0 0xe6c30000 0 0x100>; 337 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; 339 clock-names = "sci_ick"; 340 power-domains = <&pd_a3sp>; 341 status = "disabled"; 342 }; 343 344 scifa0: serial@e6c40000 { 345 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 346 reg = <0 0xe6c40000 0 0x100>; 347 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; 349 clock-names = "sci_ick"; 350 power-domains = <&pd_a3sp>; 351 status = "disabled"; 352 }; 353 354 scifa1: serial@e6c50000 { 355 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 356 reg = <0 0xe6c50000 0 0x100>; 357 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; 359 clock-names = "sci_ick"; 360 power-domains = <&pd_a3sp>; 361 status = "disabled"; 362 }; 363 364 scifb2: serial@e6ce0000 { 365 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 366 reg = <0 0xe6ce0000 0 0x100>; 367 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; 369 clock-names = "sci_ick"; 370 power-domains = <&pd_a3sp>; 371 status = "disabled"; 372 }; 373 374 scifb3: serial@e6cf0000 { 375 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 376 reg = <0 0xe6cf0000 0 0x100>; 377 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; 379 clock-names = "sci_ick"; 380 power-domains = <&pd_c4>; 381 status = "disabled"; 382 }; 383 384 sdhi0: sd@ee100000 { 385 compatible = "renesas,sdhi-r8a73a4"; 386 reg = <0 0xee100000 0 0x100>; 387 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; 389 power-domains = <&pd_a3sp>; 390 cap-sd-highspeed; 391 status = "disabled"; 392 }; 393 394 sdhi1: sd@ee120000 { 395 compatible = "renesas,sdhi-r8a73a4"; 396 reg = <0 0xee120000 0 0x100>; 397 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; 399 power-domains = <&pd_a3sp>; 400 cap-sd-highspeed; 401 status = "disabled"; 402 }; 403 404 sdhi2: sd@ee140000 { 405 compatible = "renesas,sdhi-r8a73a4"; 406 reg = <0 0xee140000 0 0x100>; 407 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; 409 power-domains = <&pd_a3sp>; 410 cap-sd-highspeed; 411 status = "disabled"; 412 }; 413 414 mmcif0: mmc@ee200000 { 415 compatible = "renesas,sh-mmcif"; 416 reg = <0 0xee200000 0 0x80>; 417 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; 419 power-domains = <&pd_a3sp>; 420 reg-io-width = <4>; 421 status = "disabled"; 422 }; 423 424 mmcif1: mmc@ee220000 { 425 compatible = "renesas,sh-mmcif"; 426 reg = <0 0xee220000 0 0x80>; 427 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; 429 power-domains = <&pd_a3sp>; 430 reg-io-width = <4>; 431 status = "disabled"; 432 }; 433 434 gic: interrupt-controller@f1001000 { 435 compatible = "arm,cortex-a15-gic"; 436 #interrupt-cells = <3>; 437 #address-cells = <0>; 438 interrupt-controller; 439 reg = <0 0xf1001000 0 0x1000>, 440 <0 0xf1002000 0 0x1000>, 441 <0 0xf1004000 0 0x2000>, 442 <0 0xf1006000 0 0x2000>; 443 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 444 }; 445 446 bsc: bus@fec10000 { 447 compatible = "renesas,bsc-r8a73a4", "renesas,bsc", 448 "simple-pm-bus"; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 ranges = <0 0 0 0x20000000>; 452 reg = <0 0xfec10000 0 0x400>; 453 clocks = <&zb_clk>; 454 power-domains = <&pd_c4>; 455 }; 456 457 clocks { 458 #address-cells = <2>; 459 #size-cells = <2>; 460 ranges; 461 462 /* External root clocks */ 463 extalr_clk: extalr_clk { 464 compatible = "fixed-clock"; 465 #clock-cells = <0>; 466 clock-frequency = <32768>; 467 clock-output-names = "extalr"; 468 }; 469 extal1_clk: extal1_clk { 470 compatible = "fixed-clock"; 471 #clock-cells = <0>; 472 clock-frequency = <25000000>; 473 clock-output-names = "extal1"; 474 }; 475 extal2_clk: extal2_clk { 476 compatible = "fixed-clock"; 477 #clock-cells = <0>; 478 clock-frequency = <48000000>; 479 clock-output-names = "extal2"; 480 }; 481 fsiack_clk: fsiack_clk { 482 compatible = "fixed-clock"; 483 #clock-cells = <0>; 484 /* This value must be overridden by the board. */ 485 clock-frequency = <0>; 486 clock-output-names = "fsiack"; 487 }; 488 fsibck_clk: fsibck_clk { 489 compatible = "fixed-clock"; 490 #clock-cells = <0>; 491 /* This value must be overridden by the board. */ 492 clock-frequency = <0>; 493 clock-output-names = "fsibck"; 494 }; 495 496 /* Special CPG clocks */ 497 cpg_clocks: cpg_clocks@e6150000 { 498 compatible = "renesas,r8a73a4-cpg-clocks"; 499 reg = <0 0xe6150000 0 0x10000>; 500 clocks = <&extal1_clk>, <&extal2_clk>; 501 #clock-cells = <1>; 502 clock-output-names = "main", "pll0", "pll1", "pll2", 503 "pll2s", "pll2h", "z", "z2", 504 "i", "m3", "b", "m1", "m2", 505 "zx", "zs", "hp"; 506 }; 507 508 /* Variable factor clocks (DIV6) */ 509 zb_clk: zb_clk@e6150010 { 510 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 511 reg = <0 0xe6150010 0 4>; 512 clocks = <&pll1_div2_clk>, <0>, 513 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 514 #clock-cells = <0>; 515 clock-output-names = "zb"; 516 }; 517 sdhi0_clk: sdhi0_clk@e6150074 { 518 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 519 reg = <0 0xe6150074 0 4>; 520 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 521 <0>, <&extal2_clk>; 522 #clock-cells = <0>; 523 clock-output-names = "sdhi0ck"; 524 }; 525 sdhi1_clk: sdhi1_clk@e6150078 { 526 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 527 reg = <0 0xe6150078 0 4>; 528 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 529 <0>, <&extal2_clk>; 530 #clock-cells = <0>; 531 clock-output-names = "sdhi1ck"; 532 }; 533 sdhi2_clk: sdhi2_clk@e615007c { 534 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 535 reg = <0 0xe615007c 0 4>; 536 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 537 <0>, <&extal2_clk>; 538 #clock-cells = <0>; 539 clock-output-names = "sdhi2ck"; 540 }; 541 mmc0_clk: mmc0_clk@e6150240 { 542 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 543 reg = <0 0xe6150240 0 4>; 544 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 545 <0>, <&extal2_clk>; 546 #clock-cells = <0>; 547 clock-output-names = "mmc0"; 548 }; 549 mmc1_clk: mmc1_clk@e6150244 { 550 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 551 reg = <0 0xe6150244 0 4>; 552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 553 <0>, <&extal2_clk>; 554 #clock-cells = <0>; 555 clock-output-names = "mmc1"; 556 }; 557 vclk1_clk: vclk1_clk@e6150008 { 558 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 559 reg = <0 0xe6150008 0 4>; 560 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 561 <0>, <&extal2_clk>, <&main_div2_clk>, 562 <&extalr_clk>, <0>, <0>; 563 #clock-cells = <0>; 564 clock-output-names = "vclk1"; 565 }; 566 vclk2_clk: vclk2_clk@e615000c { 567 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 568 reg = <0 0xe615000c 0 4>; 569 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 570 <0>, <&extal2_clk>, <&main_div2_clk>, 571 <&extalr_clk>, <0>, <0>; 572 #clock-cells = <0>; 573 clock-output-names = "vclk2"; 574 }; 575 vclk3_clk: vclk3_clk@e615001c { 576 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 577 reg = <0 0xe615001c 0 4>; 578 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 579 <0>, <&extal2_clk>, <&main_div2_clk>, 580 <&extalr_clk>, <0>, <0>; 581 #clock-cells = <0>; 582 clock-output-names = "vclk3"; 583 }; 584 vclk4_clk: vclk4_clk@e6150014 { 585 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 586 reg = <0 0xe6150014 0 4>; 587 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 588 <0>, <&extal2_clk>, <&main_div2_clk>, 589 <&extalr_clk>, <0>, <0>; 590 #clock-cells = <0>; 591 clock-output-names = "vclk4"; 592 }; 593 vclk5_clk: vclk5_clk@e6150034 { 594 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 595 reg = <0 0xe6150034 0 4>; 596 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 597 <0>, <&extal2_clk>, <&main_div2_clk>, 598 <&extalr_clk>, <0>, <0>; 599 #clock-cells = <0>; 600 clock-output-names = "vclk5"; 601 }; 602 fsia_clk: fsia_clk@e6150018 { 603 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 604 reg = <0 0xe6150018 0 4>; 605 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 606 <&fsiack_clk>, <0>; 607 #clock-cells = <0>; 608 clock-output-names = "fsia"; 609 }; 610 fsib_clk: fsib_clk@e6150090 { 611 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 612 reg = <0 0xe6150090 0 4>; 613 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 614 <&fsibck_clk>, <0>; 615 #clock-cells = <0>; 616 clock-output-names = "fsib"; 617 }; 618 mp_clk: mp_clk@e6150080 { 619 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 620 reg = <0 0xe6150080 0 4>; 621 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 622 <&extal2_clk>, <&extal2_clk>; 623 #clock-cells = <0>; 624 clock-output-names = "mp"; 625 }; 626 m4_clk: m4_clk@e6150098 { 627 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 628 reg = <0 0xe6150098 0 4>; 629 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; 630 #clock-cells = <0>; 631 clock-output-names = "m4"; 632 }; 633 hsi_clk: hsi_clk@e615026c { 634 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 635 reg = <0 0xe615026c 0 4>; 636 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, 637 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 638 #clock-cells = <0>; 639 clock-output-names = "hsi"; 640 }; 641 spuv_clk: spuv_clk@e6150094 { 642 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 643 reg = <0 0xe6150094 0 4>; 644 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 645 <&extal2_clk>, <&extal2_clk>; 646 #clock-cells = <0>; 647 clock-output-names = "spuv"; 648 }; 649 650 /* Fixed factor clocks */ 651 main_div2_clk: main_div2_clk { 652 compatible = "fixed-factor-clock"; 653 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; 654 #clock-cells = <0>; 655 clock-div = <2>; 656 clock-mult = <1>; 657 clock-output-names = "main_div2"; 658 }; 659 pll0_div2_clk: pll0_div2_clk { 660 compatible = "fixed-factor-clock"; 661 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; 662 #clock-cells = <0>; 663 clock-div = <2>; 664 clock-mult = <1>; 665 clock-output-names = "pll0_div2"; 666 }; 667 pll1_div2_clk: pll1_div2_clk { 668 compatible = "fixed-factor-clock"; 669 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; 670 #clock-cells = <0>; 671 clock-div = <2>; 672 clock-mult = <1>; 673 clock-output-names = "pll1_div2"; 674 }; 675 extal1_div2_clk: extal1_div2_clk { 676 compatible = "fixed-factor-clock"; 677 clocks = <&extal1_clk>; 678 #clock-cells = <0>; 679 clock-div = <2>; 680 clock-mult = <1>; 681 clock-output-names = "extal1_div2"; 682 }; 683 684 /* Gate clocks */ 685 mstp2_clks: mstp2_clks@e6150138 { 686 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 687 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 688 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 689 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 690 #clock-cells = <1>; 691 clock-indices = < 692 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 693 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 694 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 695 R8A73A4_CLK_DMAC 696 >; 697 clock-output-names = 698 "scifa0", "scifa1", "scifb0", "scifb1", 699 "scifb2", "scifb3", "dmac"; 700 }; 701 mstp3_clks: mstp3_clks@e615013c { 702 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 703 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 704 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, 705 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, 706 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 707 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks 708 R8A73A4_CLK_HP>, <&cpg_clocks 709 R8A73A4_CLK_HP>, <&extalr_clk>; 710 #clock-cells = <1>; 711 clock-indices = < 712 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 713 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 714 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 715 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 716 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 717 R8A73A4_CLK_CMT1 718 >; 719 clock-output-names = 720 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", 721 "mmcif0", "iic6", "iic7", "iic0", "iic1", 722 "cmt1"; 723 }; 724 mstp4_clks: mstp4_clks@e6150140 { 725 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 726 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 727 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 728 <&cpg_clocks R8A73A4_CLK_HP>; 729 #clock-cells = <1>; 730 clock-indices = < 731 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 732 R8A73A4_CLK_IIC3 733 >; 734 clock-output-names = 735 "iic5", "iic4", "iic3"; 736 }; 737 mstp5_clks: mstp5_clks@e6150144 { 738 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 739 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 740 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 741 #clock-cells = <1>; 742 clock-indices = < 743 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 744 >; 745 clock-output-names = 746 "thermal", "iic8"; 747 }; 748 }; 749 750 sysc: system-controller@e6180000 { 751 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; 752 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; 753 754 pm-domains { 755 pd_c5: c5 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 #power-domain-cells = <0>; 759 760 pd_c4: c4@0 { 761 reg = <0>; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 #power-domain-cells = <0>; 765 766 pd_a3sg: a3sg@16 { 767 reg = <16>; 768 #power-domain-cells = <0>; 769 }; 770 771 pd_a3ex: a3ex@17 { 772 reg = <17>; 773 #power-domain-cells = <0>; 774 }; 775 776 pd_a3sp: a3sp@18 { 777 reg = <18>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 #power-domain-cells = <0>; 781 782 pd_a2us: a2us@19 { 783 reg = <19>; 784 #power-domain-cells = <0>; 785 }; 786 }; 787 788 pd_a3sm: a3sm@20 { 789 reg = <20>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 #power-domain-cells = <0>; 793 794 pd_a2sl: a2sl@21 { 795 reg = <21>; 796 #power-domain-cells = <0>; 797 }; 798 }; 799 800 pd_a3km: a3km@22 { 801 reg = <22>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #power-domain-cells = <0>; 805 806 pd_a2kl: a2kl@23 { 807 reg = <23>; 808 #power-domain-cells = <0>; 809 }; 810 }; 811 }; 812 813 pd_c4ma: c4ma@1 { 814 reg = <1>; 815 #power-domain-cells = <0>; 816 }; 817 818 pd_c4cl: c4cl@2 { 819 reg = <2>; 820 #power-domain-cells = <0>; 821 }; 822 823 pd_d4: d4@3 { 824 reg = <3>; 825 #power-domain-cells = <0>; 826 }; 827 828 pd_a4bc: a4bc@4 { 829 reg = <4>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 #power-domain-cells = <0>; 833 834 pd_a3bc: a3bc@5 { 835 reg = <5>; 836 #power-domain-cells = <0>; 837 }; 838 }; 839 840 pd_a4l: a4l@6 { 841 reg = <6>; 842 #power-domain-cells = <0>; 843 }; 844 845 pd_a4lc: a4lc@7 { 846 reg = <7>; 847 #power-domain-cells = <0>; 848 }; 849 850 pd_a4mp: a4mp@8 { 851 reg = <8>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 #power-domain-cells = <0>; 855 856 pd_a3mp: a3mp@9 { 857 reg = <9>; 858 #power-domain-cells = <0>; 859 }; 860 861 pd_a3vc: a3vc@10 { 862 reg = <10>; 863 #power-domain-cells = <0>; 864 }; 865 }; 866 867 pd_a4sf: a4sf@11 { 868 reg = <11>; 869 #power-domain-cells = <0>; 870 }; 871 872 pd_a3r: a3r@12 { 873 reg = <12>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 #power-domain-cells = <0>; 877 878 pd_a2rv: a2rv@13 { 879 reg = <13>; 880 #power-domain-cells = <0>; 881 }; 882 883 pd_a2is: a2is@14 { 884 reg = <14>; 885 #power-domain-cells = <0>; 886 }; 887 }; 888 }; 889 }; 890 }; 891}; 892