1* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
4and several fixed ratio dividers.
5
6Required Properties:
7
8  - compatible: Must be one of
9    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
10    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
11    - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
12    - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
13    - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
14
15  - reg: Base address and length of the memory resource used by the CPG
16
17  - clocks: References to the parent clocks: first to the EXTAL clock, second
18    to the USB_EXTAL clock
19  - #clock-cells: Must be 1
20  - clock-output-names: The names of the clocks. Supported clocks are "main",
21    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
22    "adsp"
23
24
25Example
26-------
27
28	cpg_clocks: cpg_clocks@e6150000 {
29		compatible = "renesas,r8a7790-cpg-clocks",
30			     "renesas,rcar-gen2-cpg-clocks";
31		reg = <0 0xe6150000 0 0x1000>;
32		clocks = <&extal_clk &usb_extal_clk>;
33		#clock-cells = <1>;
34		clock-output-names = "main", "pll0, "pll1", "pll3",
35				     "lb", "qspi", "sdh", "sd0", "sd1", "z",
36				     "rcan", "adsp";
37	};
38