1/* 2 * Device Tree Source for OMAP4 clock data 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10&cm1_clocks { 11 extalt_clkin_ck: extalt_clkin_ck { 12 #clock-cells = <0>; 13 compatible = "fixed-clock"; 14 clock-frequency = <59000000>; 15 }; 16 17 pad_clks_src_ck: pad_clks_src_ck { 18 #clock-cells = <0>; 19 compatible = "fixed-clock"; 20 clock-frequency = <12000000>; 21 }; 22 23 pad_clks_ck: pad_clks_ck { 24 #clock-cells = <0>; 25 compatible = "ti,gate-clock"; 26 clocks = <&pad_clks_src_ck>; 27 ti,bit-shift = <8>; 28 reg = <0x0108>; 29 }; 30 31 pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { 32 #clock-cells = <0>; 33 compatible = "fixed-clock"; 34 clock-frequency = <12000000>; 35 }; 36 37 secure_32k_clk_src_ck: secure_32k_clk_src_ck { 38 #clock-cells = <0>; 39 compatible = "fixed-clock"; 40 clock-frequency = <32768>; 41 }; 42 43 slimbus_src_clk: slimbus_src_clk { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <12000000>; 47 }; 48 49 slimbus_clk: slimbus_clk { 50 #clock-cells = <0>; 51 compatible = "ti,gate-clock"; 52 clocks = <&slimbus_src_clk>; 53 ti,bit-shift = <10>; 54 reg = <0x0108>; 55 }; 56 57 sys_32k_ck: sys_32k_ck { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <32768>; 61 }; 62 63 virt_12000000_ck: virt_12000000_ck { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <12000000>; 67 }; 68 69 virt_13000000_ck: virt_13000000_ck { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <13000000>; 73 }; 74 75 virt_16800000_ck: virt_16800000_ck { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <16800000>; 79 }; 80 81 virt_19200000_ck: virt_19200000_ck { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <19200000>; 85 }; 86 87 virt_26000000_ck: virt_26000000_ck { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <26000000>; 91 }; 92 93 virt_27000000_ck: virt_27000000_ck { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <27000000>; 97 }; 98 99 virt_38400000_ck: virt_38400000_ck { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <38400000>; 103 }; 104 105 tie_low_clock_ck: tie_low_clock_ck { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <0>; 109 }; 110 111 utmi_phy_clkout_ck: utmi_phy_clkout_ck { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <60000000>; 115 }; 116 117 xclk60mhsp1_ck: xclk60mhsp1_ck { 118 #clock-cells = <0>; 119 compatible = "fixed-clock"; 120 clock-frequency = <60000000>; 121 }; 122 123 xclk60mhsp2_ck: xclk60mhsp2_ck { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 clock-frequency = <60000000>; 127 }; 128 129 xclk60motg_ck: xclk60motg_ck { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 clock-frequency = <60000000>; 133 }; 134 135 dpll_abe_ck: dpll_abe_ck { 136 #clock-cells = <0>; 137 compatible = "ti,omap4-dpll-m4xen-clock"; 138 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; 139 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 140 }; 141 142 dpll_abe_x2_ck: dpll_abe_x2_ck { 143 #clock-cells = <0>; 144 compatible = "ti,omap4-dpll-x2-clock"; 145 clocks = <&dpll_abe_ck>; 146 reg = <0x01f0>; 147 }; 148 149 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { 150 #clock-cells = <0>; 151 compatible = "ti,divider-clock"; 152 clocks = <&dpll_abe_x2_ck>; 153 ti,max-div = <31>; 154 ti,autoidle-shift = <8>; 155 reg = <0x01f0>; 156 ti,index-starts-at-one; 157 ti,invert-autoidle-bit; 158 }; 159 160 abe_24m_fclk: abe_24m_fclk { 161 #clock-cells = <0>; 162 compatible = "fixed-factor-clock"; 163 clocks = <&dpll_abe_m2x2_ck>; 164 clock-mult = <1>; 165 clock-div = <8>; 166 }; 167 168 abe_clk: abe_clk { 169 #clock-cells = <0>; 170 compatible = "ti,divider-clock"; 171 clocks = <&dpll_abe_m2x2_ck>; 172 ti,max-div = <4>; 173 reg = <0x0108>; 174 ti,index-power-of-two; 175 }; 176 177 aess_fclk: aess_fclk { 178 #clock-cells = <0>; 179 compatible = "ti,divider-clock"; 180 clocks = <&abe_clk>; 181 ti,bit-shift = <24>; 182 ti,max-div = <2>; 183 reg = <0x0528>; 184 }; 185 186 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { 187 #clock-cells = <0>; 188 compatible = "ti,divider-clock"; 189 clocks = <&dpll_abe_x2_ck>; 190 ti,max-div = <31>; 191 ti,autoidle-shift = <8>; 192 reg = <0x01f4>; 193 ti,index-starts-at-one; 194 ti,invert-autoidle-bit; 195 }; 196 197 core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck { 198 #clock-cells = <0>; 199 compatible = "ti,mux-clock"; 200 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; 201 ti,bit-shift = <23>; 202 reg = <0x012c>; 203 }; 204 205 dpll_core_ck: dpll_core_ck { 206 #clock-cells = <0>; 207 compatible = "ti,omap4-dpll-core-clock"; 208 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; 209 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 210 }; 211 212 dpll_core_x2_ck: dpll_core_x2_ck { 213 #clock-cells = <0>; 214 compatible = "ti,omap4-dpll-x2-clock"; 215 clocks = <&dpll_core_ck>; 216 }; 217 218 dpll_core_m6x2_ck: dpll_core_m6x2_ck { 219 #clock-cells = <0>; 220 compatible = "ti,divider-clock"; 221 clocks = <&dpll_core_x2_ck>; 222 ti,max-div = <31>; 223 ti,autoidle-shift = <8>; 224 reg = <0x0140>; 225 ti,index-starts-at-one; 226 ti,invert-autoidle-bit; 227 }; 228 229 dpll_core_m2_ck: dpll_core_m2_ck { 230 #clock-cells = <0>; 231 compatible = "ti,divider-clock"; 232 clocks = <&dpll_core_ck>; 233 ti,max-div = <31>; 234 ti,autoidle-shift = <8>; 235 reg = <0x0130>; 236 ti,index-starts-at-one; 237 ti,invert-autoidle-bit; 238 }; 239 240 ddrphy_ck: ddrphy_ck { 241 #clock-cells = <0>; 242 compatible = "fixed-factor-clock"; 243 clocks = <&dpll_core_m2_ck>; 244 clock-mult = <1>; 245 clock-div = <2>; 246 }; 247 248 dpll_core_m5x2_ck: dpll_core_m5x2_ck { 249 #clock-cells = <0>; 250 compatible = "ti,divider-clock"; 251 clocks = <&dpll_core_x2_ck>; 252 ti,max-div = <31>; 253 ti,autoidle-shift = <8>; 254 reg = <0x013c>; 255 ti,index-starts-at-one; 256 ti,invert-autoidle-bit; 257 }; 258 259 div_core_ck: div_core_ck { 260 #clock-cells = <0>; 261 compatible = "ti,divider-clock"; 262 clocks = <&dpll_core_m5x2_ck>; 263 reg = <0x0100>; 264 ti,max-div = <2>; 265 }; 266 267 div_iva_hs_clk: div_iva_hs_clk { 268 #clock-cells = <0>; 269 compatible = "ti,divider-clock"; 270 clocks = <&dpll_core_m5x2_ck>; 271 ti,max-div = <4>; 272 reg = <0x01dc>; 273 ti,index-power-of-two; 274 }; 275 276 div_mpu_hs_clk: div_mpu_hs_clk { 277 #clock-cells = <0>; 278 compatible = "ti,divider-clock"; 279 clocks = <&dpll_core_m5x2_ck>; 280 ti,max-div = <4>; 281 reg = <0x019c>; 282 ti,index-power-of-two; 283 }; 284 285 dpll_core_m4x2_ck: dpll_core_m4x2_ck { 286 #clock-cells = <0>; 287 compatible = "ti,divider-clock"; 288 clocks = <&dpll_core_x2_ck>; 289 ti,max-div = <31>; 290 ti,autoidle-shift = <8>; 291 reg = <0x0138>; 292 ti,index-starts-at-one; 293 ti,invert-autoidle-bit; 294 }; 295 296 dll_clk_div_ck: dll_clk_div_ck { 297 #clock-cells = <0>; 298 compatible = "fixed-factor-clock"; 299 clocks = <&dpll_core_m4x2_ck>; 300 clock-mult = <1>; 301 clock-div = <2>; 302 }; 303 304 dpll_abe_m2_ck: dpll_abe_m2_ck { 305 #clock-cells = <0>; 306 compatible = "ti,divider-clock"; 307 clocks = <&dpll_abe_ck>; 308 ti,max-div = <31>; 309 reg = <0x01f0>; 310 ti,index-starts-at-one; 311 }; 312 313 dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck { 314 #clock-cells = <0>; 315 compatible = "ti,composite-no-wait-gate-clock"; 316 clocks = <&dpll_core_x2_ck>; 317 ti,bit-shift = <8>; 318 reg = <0x0134>; 319 }; 320 321 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { 322 #clock-cells = <0>; 323 compatible = "ti,composite-divider-clock"; 324 clocks = <&dpll_core_x2_ck>; 325 ti,max-div = <31>; 326 reg = <0x0134>; 327 ti,index-starts-at-one; 328 }; 329 330 dpll_core_m3x2_ck: dpll_core_m3x2_ck { 331 #clock-cells = <0>; 332 compatible = "ti,composite-clock"; 333 clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; 334 }; 335 336 dpll_core_m7x2_ck: dpll_core_m7x2_ck { 337 #clock-cells = <0>; 338 compatible = "ti,divider-clock"; 339 clocks = <&dpll_core_x2_ck>; 340 ti,max-div = <31>; 341 ti,autoidle-shift = <8>; 342 reg = <0x0144>; 343 ti,index-starts-at-one; 344 ti,invert-autoidle-bit; 345 }; 346 347 iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck { 348 #clock-cells = <0>; 349 compatible = "ti,mux-clock"; 350 clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; 351 ti,bit-shift = <23>; 352 reg = <0x01ac>; 353 }; 354 355 dpll_iva_ck: dpll_iva_ck { 356 #clock-cells = <0>; 357 compatible = "ti,omap4-dpll-clock"; 358 clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; 359 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 360 }; 361 362 dpll_iva_x2_ck: dpll_iva_x2_ck { 363 #clock-cells = <0>; 364 compatible = "ti,omap4-dpll-x2-clock"; 365 clocks = <&dpll_iva_ck>; 366 }; 367 368 dpll_iva_m4x2_ck: dpll_iva_m4x2_ck { 369 #clock-cells = <0>; 370 compatible = "ti,divider-clock"; 371 clocks = <&dpll_iva_x2_ck>; 372 ti,max-div = <31>; 373 ti,autoidle-shift = <8>; 374 reg = <0x01b8>; 375 ti,index-starts-at-one; 376 ti,invert-autoidle-bit; 377 }; 378 379 dpll_iva_m5x2_ck: dpll_iva_m5x2_ck { 380 #clock-cells = <0>; 381 compatible = "ti,divider-clock"; 382 clocks = <&dpll_iva_x2_ck>; 383 ti,max-div = <31>; 384 ti,autoidle-shift = <8>; 385 reg = <0x01bc>; 386 ti,index-starts-at-one; 387 ti,invert-autoidle-bit; 388 }; 389 390 dpll_mpu_ck: dpll_mpu_ck { 391 #clock-cells = <0>; 392 compatible = "ti,omap4-dpll-clock"; 393 clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; 394 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 395 }; 396 397 dpll_mpu_m2_ck: dpll_mpu_m2_ck { 398 #clock-cells = <0>; 399 compatible = "ti,divider-clock"; 400 clocks = <&dpll_mpu_ck>; 401 ti,max-div = <31>; 402 ti,autoidle-shift = <8>; 403 reg = <0x0170>; 404 ti,index-starts-at-one; 405 ti,invert-autoidle-bit; 406 }; 407 408 per_hs_clk_div_ck: per_hs_clk_div_ck { 409 #clock-cells = <0>; 410 compatible = "fixed-factor-clock"; 411 clocks = <&dpll_abe_m3x2_ck>; 412 clock-mult = <1>; 413 clock-div = <2>; 414 }; 415 416 usb_hs_clk_div_ck: usb_hs_clk_div_ck { 417 #clock-cells = <0>; 418 compatible = "fixed-factor-clock"; 419 clocks = <&dpll_abe_m3x2_ck>; 420 clock-mult = <1>; 421 clock-div = <3>; 422 }; 423 424 l3_div_ck: l3_div_ck { 425 #clock-cells = <0>; 426 compatible = "ti,divider-clock"; 427 clocks = <&div_core_ck>; 428 ti,bit-shift = <4>; 429 ti,max-div = <2>; 430 reg = <0x0100>; 431 }; 432 433 l4_div_ck: l4_div_ck { 434 #clock-cells = <0>; 435 compatible = "ti,divider-clock"; 436 clocks = <&l3_div_ck>; 437 ti,bit-shift = <8>; 438 ti,max-div = <2>; 439 reg = <0x0100>; 440 }; 441 442 lp_clk_div_ck: lp_clk_div_ck { 443 #clock-cells = <0>; 444 compatible = "fixed-factor-clock"; 445 clocks = <&dpll_abe_m2x2_ck>; 446 clock-mult = <1>; 447 clock-div = <16>; 448 }; 449 450 mpu_periphclk: mpu_periphclk { 451 #clock-cells = <0>; 452 compatible = "fixed-factor-clock"; 453 clocks = <&dpll_mpu_ck>; 454 clock-mult = <1>; 455 clock-div = <2>; 456 }; 457 458 ocp_abe_iclk: ocp_abe_iclk { 459 #clock-cells = <0>; 460 compatible = "ti,divider-clock"; 461 clocks = <&aess_fclk>; 462 ti,bit-shift = <24>; 463 reg = <0x0528>; 464 ti,dividers = <2>, <1>; 465 }; 466 467 per_abe_24m_fclk: per_abe_24m_fclk { 468 #clock-cells = <0>; 469 compatible = "fixed-factor-clock"; 470 clocks = <&dpll_abe_m2_ck>; 471 clock-mult = <1>; 472 clock-div = <4>; 473 }; 474 475 dmic_sync_mux_ck: dmic_sync_mux_ck { 476 #clock-cells = <0>; 477 compatible = "ti,mux-clock"; 478 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; 479 ti,bit-shift = <25>; 480 reg = <0x0538>; 481 }; 482 483 func_dmic_abe_gfclk: func_dmic_abe_gfclk { 484 #clock-cells = <0>; 485 compatible = "ti,mux-clock"; 486 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 487 ti,bit-shift = <24>; 488 reg = <0x0538>; 489 }; 490 491 mcasp_sync_mux_ck: mcasp_sync_mux_ck { 492 #clock-cells = <0>; 493 compatible = "ti,mux-clock"; 494 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; 495 ti,bit-shift = <25>; 496 reg = <0x0540>; 497 }; 498 499 func_mcasp_abe_gfclk: func_mcasp_abe_gfclk { 500 #clock-cells = <0>; 501 compatible = "ti,mux-clock"; 502 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 503 ti,bit-shift = <24>; 504 reg = <0x0540>; 505 }; 506 507 mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { 508 #clock-cells = <0>; 509 compatible = "ti,mux-clock"; 510 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; 511 ti,bit-shift = <25>; 512 reg = <0x0548>; 513 }; 514 515 func_mcbsp1_gfclk: func_mcbsp1_gfclk { 516 #clock-cells = <0>; 517 compatible = "ti,mux-clock"; 518 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 519 ti,bit-shift = <24>; 520 reg = <0x0548>; 521 }; 522 523 mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { 524 #clock-cells = <0>; 525 compatible = "ti,mux-clock"; 526 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; 527 ti,bit-shift = <25>; 528 reg = <0x0550>; 529 }; 530 531 func_mcbsp2_gfclk: func_mcbsp2_gfclk { 532 #clock-cells = <0>; 533 compatible = "ti,mux-clock"; 534 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 535 ti,bit-shift = <24>; 536 reg = <0x0550>; 537 }; 538 539 mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { 540 #clock-cells = <0>; 541 compatible = "ti,mux-clock"; 542 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; 543 ti,bit-shift = <25>; 544 reg = <0x0558>; 545 }; 546 547 func_mcbsp3_gfclk: func_mcbsp3_gfclk { 548 #clock-cells = <0>; 549 compatible = "ti,mux-clock"; 550 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 551 ti,bit-shift = <24>; 552 reg = <0x0558>; 553 }; 554 555 slimbus1_fclk_1: slimbus1_fclk_1 { 556 #clock-cells = <0>; 557 compatible = "ti,gate-clock"; 558 clocks = <&func_24m_clk>; 559 ti,bit-shift = <9>; 560 reg = <0x0560>; 561 }; 562 563 slimbus1_fclk_0: slimbus1_fclk_0 { 564 #clock-cells = <0>; 565 compatible = "ti,gate-clock"; 566 clocks = <&abe_24m_fclk>; 567 ti,bit-shift = <8>; 568 reg = <0x0560>; 569 }; 570 571 slimbus1_fclk_2: slimbus1_fclk_2 { 572 #clock-cells = <0>; 573 compatible = "ti,gate-clock"; 574 clocks = <&pad_clks_ck>; 575 ti,bit-shift = <10>; 576 reg = <0x0560>; 577 }; 578 579 slimbus1_slimbus_clk: slimbus1_slimbus_clk { 580 #clock-cells = <0>; 581 compatible = "ti,gate-clock"; 582 clocks = <&slimbus_clk>; 583 ti,bit-shift = <11>; 584 reg = <0x0560>; 585 }; 586 587 timer5_sync_mux: timer5_sync_mux { 588 #clock-cells = <0>; 589 compatible = "ti,mux-clock"; 590 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; 591 ti,bit-shift = <24>; 592 reg = <0x0568>; 593 }; 594 595 timer6_sync_mux: timer6_sync_mux { 596 #clock-cells = <0>; 597 compatible = "ti,mux-clock"; 598 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; 599 ti,bit-shift = <24>; 600 reg = <0x0570>; 601 }; 602 603 timer7_sync_mux: timer7_sync_mux { 604 #clock-cells = <0>; 605 compatible = "ti,mux-clock"; 606 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; 607 ti,bit-shift = <24>; 608 reg = <0x0578>; 609 }; 610 611 timer8_sync_mux: timer8_sync_mux { 612 #clock-cells = <0>; 613 compatible = "ti,mux-clock"; 614 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; 615 ti,bit-shift = <24>; 616 reg = <0x0580>; 617 }; 618 619 dummy_ck: dummy_ck { 620 #clock-cells = <0>; 621 compatible = "fixed-clock"; 622 clock-frequency = <0>; 623 }; 624}; 625&prm_clocks { 626 sys_clkin_ck: sys_clkin_ck { 627 #clock-cells = <0>; 628 compatible = "ti,mux-clock"; 629 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 630 reg = <0x0110>; 631 ti,index-starts-at-one; 632 }; 633 634 abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck { 635 #clock-cells = <0>; 636 compatible = "ti,mux-clock"; 637 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 638 ti,bit-shift = <24>; 639 reg = <0x0108>; 640 }; 641 642 abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck { 643 #clock-cells = <0>; 644 compatible = "ti,mux-clock"; 645 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 646 reg = <0x010c>; 647 }; 648 649 dbgclk_mux_ck: dbgclk_mux_ck { 650 #clock-cells = <0>; 651 compatible = "fixed-factor-clock"; 652 clocks = <&sys_clkin_ck>; 653 clock-mult = <1>; 654 clock-div = <1>; 655 }; 656 657 l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck { 658 #clock-cells = <0>; 659 compatible = "ti,mux-clock"; 660 clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; 661 reg = <0x0108>; 662 }; 663 664 syc_clk_div_ck: syc_clk_div_ck { 665 #clock-cells = <0>; 666 compatible = "ti,divider-clock"; 667 clocks = <&sys_clkin_ck>; 668 reg = <0x0100>; 669 ti,max-div = <2>; 670 }; 671 672 gpio1_dbclk: gpio1_dbclk { 673 #clock-cells = <0>; 674 compatible = "ti,gate-clock"; 675 clocks = <&sys_32k_ck>; 676 ti,bit-shift = <8>; 677 reg = <0x1838>; 678 }; 679 680 dmt1_clk_mux: dmt1_clk_mux { 681 #clock-cells = <0>; 682 compatible = "ti,mux-clock"; 683 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 684 ti,bit-shift = <24>; 685 reg = <0x1840>; 686 }; 687 688 usim_ck: usim_ck { 689 #clock-cells = <0>; 690 compatible = "ti,divider-clock"; 691 clocks = <&dpll_per_m4x2_ck>; 692 ti,bit-shift = <24>; 693 reg = <0x1858>; 694 ti,dividers = <14>, <18>; 695 }; 696 697 usim_fclk: usim_fclk { 698 #clock-cells = <0>; 699 compatible = "ti,gate-clock"; 700 clocks = <&usim_ck>; 701 ti,bit-shift = <8>; 702 reg = <0x1858>; 703 }; 704 705 pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck { 706 #clock-cells = <0>; 707 compatible = "ti,mux-clock"; 708 clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; 709 ti,bit-shift = <20>; 710 reg = <0x1a20>; 711 }; 712 713 pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck { 714 #clock-cells = <0>; 715 compatible = "ti,mux-clock"; 716 clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; 717 ti,bit-shift = <22>; 718 reg = <0x1a20>; 719 }; 720 721 stm_clk_div_ck: stm_clk_div_ck { 722 #clock-cells = <0>; 723 compatible = "ti,divider-clock"; 724 clocks = <&pmd_stm_clock_mux_ck>; 725 ti,bit-shift = <27>; 726 ti,max-div = <64>; 727 reg = <0x1a20>; 728 ti,index-power-of-two; 729 }; 730 731 trace_clk_div_div_ck: trace_clk_div_div_ck { 732 #clock-cells = <0>; 733 compatible = "ti,divider-clock"; 734 clocks = <&pmd_trace_clk_mux_ck>; 735 ti,bit-shift = <24>; 736 reg = <0x1a20>; 737 ti,dividers = <0>, <1>, <2>, <0>, <4>; 738 }; 739 740 trace_clk_div_ck: trace_clk_div_ck { 741 #clock-cells = <0>; 742 compatible = "ti,clkdm-gate-clock"; 743 clocks = <&trace_clk_div_div_ck>; 744 }; 745}; 746 747&prm_clockdomains { 748 emu_sys_clkdm: emu_sys_clkdm { 749 compatible = "ti,clockdomain"; 750 clocks = <&trace_clk_div_ck>; 751 }; 752}; 753 754&cm2_clocks { 755 per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck { 756 #clock-cells = <0>; 757 compatible = "ti,mux-clock"; 758 clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; 759 ti,bit-shift = <23>; 760 reg = <0x014c>; 761 }; 762 763 dpll_per_ck: dpll_per_ck { 764 #clock-cells = <0>; 765 compatible = "ti,omap4-dpll-clock"; 766 clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; 767 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 768 }; 769 770 dpll_per_m2_ck: dpll_per_m2_ck { 771 #clock-cells = <0>; 772 compatible = "ti,divider-clock"; 773 clocks = <&dpll_per_ck>; 774 ti,max-div = <31>; 775 reg = <0x0150>; 776 ti,index-starts-at-one; 777 }; 778 779 dpll_per_x2_ck: dpll_per_x2_ck { 780 #clock-cells = <0>; 781 compatible = "ti,omap4-dpll-x2-clock"; 782 clocks = <&dpll_per_ck>; 783 reg = <0x0150>; 784 }; 785 786 dpll_per_m2x2_ck: dpll_per_m2x2_ck { 787 #clock-cells = <0>; 788 compatible = "ti,divider-clock"; 789 clocks = <&dpll_per_x2_ck>; 790 ti,max-div = <31>; 791 ti,autoidle-shift = <8>; 792 reg = <0x0150>; 793 ti,index-starts-at-one; 794 ti,invert-autoidle-bit; 795 }; 796 797 dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck { 798 #clock-cells = <0>; 799 compatible = "ti,composite-no-wait-gate-clock"; 800 clocks = <&dpll_per_x2_ck>; 801 ti,bit-shift = <8>; 802 reg = <0x0154>; 803 }; 804 805 dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck { 806 #clock-cells = <0>; 807 compatible = "ti,composite-divider-clock"; 808 clocks = <&dpll_per_x2_ck>; 809 ti,max-div = <31>; 810 reg = <0x0154>; 811 ti,index-starts-at-one; 812 }; 813 814 dpll_per_m3x2_ck: dpll_per_m3x2_ck { 815 #clock-cells = <0>; 816 compatible = "ti,composite-clock"; 817 clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; 818 }; 819 820 dpll_per_m4x2_ck: dpll_per_m4x2_ck { 821 #clock-cells = <0>; 822 compatible = "ti,divider-clock"; 823 clocks = <&dpll_per_x2_ck>; 824 ti,max-div = <31>; 825 ti,autoidle-shift = <8>; 826 reg = <0x0158>; 827 ti,index-starts-at-one; 828 ti,invert-autoidle-bit; 829 }; 830 831 dpll_per_m5x2_ck: dpll_per_m5x2_ck { 832 #clock-cells = <0>; 833 compatible = "ti,divider-clock"; 834 clocks = <&dpll_per_x2_ck>; 835 ti,max-div = <31>; 836 ti,autoidle-shift = <8>; 837 reg = <0x015c>; 838 ti,index-starts-at-one; 839 ti,invert-autoidle-bit; 840 }; 841 842 dpll_per_m6x2_ck: dpll_per_m6x2_ck { 843 #clock-cells = <0>; 844 compatible = "ti,divider-clock"; 845 clocks = <&dpll_per_x2_ck>; 846 ti,max-div = <31>; 847 ti,autoidle-shift = <8>; 848 reg = <0x0160>; 849 ti,index-starts-at-one; 850 ti,invert-autoidle-bit; 851 }; 852 853 dpll_per_m7x2_ck: dpll_per_m7x2_ck { 854 #clock-cells = <0>; 855 compatible = "ti,divider-clock"; 856 clocks = <&dpll_per_x2_ck>; 857 ti,max-div = <31>; 858 ti,autoidle-shift = <8>; 859 reg = <0x0164>; 860 ti,index-starts-at-one; 861 ti,invert-autoidle-bit; 862 }; 863 864 dpll_usb_ck: dpll_usb_ck { 865 #clock-cells = <0>; 866 compatible = "ti,omap4-dpll-j-type-clock"; 867 clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; 868 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 869 }; 870 871 dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { 872 #clock-cells = <0>; 873 compatible = "ti,fixed-factor-clock"; 874 clocks = <&dpll_usb_ck>; 875 ti,clock-div = <1>; 876 ti,autoidle-shift = <8>; 877 reg = <0x01b4>; 878 ti,clock-mult = <1>; 879 ti,invert-autoidle-bit; 880 }; 881 882 dpll_usb_m2_ck: dpll_usb_m2_ck { 883 #clock-cells = <0>; 884 compatible = "ti,divider-clock"; 885 clocks = <&dpll_usb_ck>; 886 ti,max-div = <127>; 887 ti,autoidle-shift = <8>; 888 reg = <0x0190>; 889 ti,index-starts-at-one; 890 ti,invert-autoidle-bit; 891 }; 892 893 ducati_clk_mux_ck: ducati_clk_mux_ck { 894 #clock-cells = <0>; 895 compatible = "ti,mux-clock"; 896 clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; 897 reg = <0x0100>; 898 }; 899 900 func_12m_fclk: func_12m_fclk { 901 #clock-cells = <0>; 902 compatible = "fixed-factor-clock"; 903 clocks = <&dpll_per_m2x2_ck>; 904 clock-mult = <1>; 905 clock-div = <16>; 906 }; 907 908 func_24m_clk: func_24m_clk { 909 #clock-cells = <0>; 910 compatible = "fixed-factor-clock"; 911 clocks = <&dpll_per_m2_ck>; 912 clock-mult = <1>; 913 clock-div = <4>; 914 }; 915 916 func_24mc_fclk: func_24mc_fclk { 917 #clock-cells = <0>; 918 compatible = "fixed-factor-clock"; 919 clocks = <&dpll_per_m2x2_ck>; 920 clock-mult = <1>; 921 clock-div = <8>; 922 }; 923 924 func_48m_fclk: func_48m_fclk { 925 #clock-cells = <0>; 926 compatible = "ti,divider-clock"; 927 clocks = <&dpll_per_m2x2_ck>; 928 reg = <0x0108>; 929 ti,dividers = <4>, <8>; 930 }; 931 932 func_48mc_fclk: func_48mc_fclk { 933 #clock-cells = <0>; 934 compatible = "fixed-factor-clock"; 935 clocks = <&dpll_per_m2x2_ck>; 936 clock-mult = <1>; 937 clock-div = <4>; 938 }; 939 940 func_64m_fclk: func_64m_fclk { 941 #clock-cells = <0>; 942 compatible = "ti,divider-clock"; 943 clocks = <&dpll_per_m4x2_ck>; 944 reg = <0x0108>; 945 ti,dividers = <2>, <4>; 946 }; 947 948 func_96m_fclk: func_96m_fclk { 949 #clock-cells = <0>; 950 compatible = "ti,divider-clock"; 951 clocks = <&dpll_per_m2x2_ck>; 952 reg = <0x0108>; 953 ti,dividers = <2>, <4>; 954 }; 955 956 init_60m_fclk: init_60m_fclk { 957 #clock-cells = <0>; 958 compatible = "ti,divider-clock"; 959 clocks = <&dpll_usb_m2_ck>; 960 reg = <0x0104>; 961 ti,dividers = <1>, <8>; 962 }; 963 964 per_abe_nc_fclk: per_abe_nc_fclk { 965 #clock-cells = <0>; 966 compatible = "ti,divider-clock"; 967 clocks = <&dpll_abe_m2_ck>; 968 reg = <0x0108>; 969 ti,max-div = <2>; 970 }; 971 972 aes1_fck: aes1_fck { 973 #clock-cells = <0>; 974 compatible = "ti,gate-clock"; 975 clocks = <&l3_div_ck>; 976 ti,bit-shift = <1>; 977 reg = <0x15a0>; 978 }; 979 980 aes2_fck: aes2_fck { 981 #clock-cells = <0>; 982 compatible = "ti,gate-clock"; 983 clocks = <&l3_div_ck>; 984 ti,bit-shift = <1>; 985 reg = <0x15a8>; 986 }; 987 988 dss_sys_clk: dss_sys_clk { 989 #clock-cells = <0>; 990 compatible = "ti,gate-clock"; 991 clocks = <&syc_clk_div_ck>; 992 ti,bit-shift = <10>; 993 reg = <0x1120>; 994 }; 995 996 dss_tv_clk: dss_tv_clk { 997 #clock-cells = <0>; 998 compatible = "ti,gate-clock"; 999 clocks = <&extalt_clkin_ck>; 1000 ti,bit-shift = <11>; 1001 reg = <0x1120>; 1002 }; 1003 1004 dss_dss_clk: dss_dss_clk { 1005 #clock-cells = <0>; 1006 compatible = "ti,gate-clock"; 1007 clocks = <&dpll_per_m5x2_ck>; 1008 ti,bit-shift = <8>; 1009 reg = <0x1120>; 1010 ti,set-rate-parent; 1011 }; 1012 1013 dss_48mhz_clk: dss_48mhz_clk { 1014 #clock-cells = <0>; 1015 compatible = "ti,gate-clock"; 1016 clocks = <&func_48mc_fclk>; 1017 ti,bit-shift = <9>; 1018 reg = <0x1120>; 1019 }; 1020 1021 fdif_fck: fdif_fck { 1022 #clock-cells = <0>; 1023 compatible = "ti,divider-clock"; 1024 clocks = <&dpll_per_m4x2_ck>; 1025 ti,bit-shift = <24>; 1026 ti,max-div = <4>; 1027 reg = <0x1028>; 1028 ti,index-power-of-two; 1029 }; 1030 1031 gpio2_dbclk: gpio2_dbclk { 1032 #clock-cells = <0>; 1033 compatible = "ti,gate-clock"; 1034 clocks = <&sys_32k_ck>; 1035 ti,bit-shift = <8>; 1036 reg = <0x1460>; 1037 }; 1038 1039 gpio3_dbclk: gpio3_dbclk { 1040 #clock-cells = <0>; 1041 compatible = "ti,gate-clock"; 1042 clocks = <&sys_32k_ck>; 1043 ti,bit-shift = <8>; 1044 reg = <0x1468>; 1045 }; 1046 1047 gpio4_dbclk: gpio4_dbclk { 1048 #clock-cells = <0>; 1049 compatible = "ti,gate-clock"; 1050 clocks = <&sys_32k_ck>; 1051 ti,bit-shift = <8>; 1052 reg = <0x1470>; 1053 }; 1054 1055 gpio5_dbclk: gpio5_dbclk { 1056 #clock-cells = <0>; 1057 compatible = "ti,gate-clock"; 1058 clocks = <&sys_32k_ck>; 1059 ti,bit-shift = <8>; 1060 reg = <0x1478>; 1061 }; 1062 1063 gpio6_dbclk: gpio6_dbclk { 1064 #clock-cells = <0>; 1065 compatible = "ti,gate-clock"; 1066 clocks = <&sys_32k_ck>; 1067 ti,bit-shift = <8>; 1068 reg = <0x1480>; 1069 }; 1070 1071 sgx_clk_mux: sgx_clk_mux { 1072 #clock-cells = <0>; 1073 compatible = "ti,mux-clock"; 1074 clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>; 1075 ti,bit-shift = <24>; 1076 reg = <0x1220>; 1077 }; 1078 1079 hsi_fck: hsi_fck { 1080 #clock-cells = <0>; 1081 compatible = "ti,divider-clock"; 1082 clocks = <&dpll_per_m2x2_ck>; 1083 ti,bit-shift = <24>; 1084 ti,max-div = <4>; 1085 reg = <0x1338>; 1086 ti,index-power-of-two; 1087 }; 1088 1089 iss_ctrlclk: iss_ctrlclk { 1090 #clock-cells = <0>; 1091 compatible = "ti,gate-clock"; 1092 clocks = <&func_96m_fclk>; 1093 ti,bit-shift = <8>; 1094 reg = <0x1020>; 1095 }; 1096 1097 mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck { 1098 #clock-cells = <0>; 1099 compatible = "ti,mux-clock"; 1100 clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>; 1101 ti,bit-shift = <25>; 1102 reg = <0x14e0>; 1103 }; 1104 1105 per_mcbsp4_gfclk: per_mcbsp4_gfclk { 1106 #clock-cells = <0>; 1107 compatible = "ti,mux-clock"; 1108 clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>; 1109 ti,bit-shift = <24>; 1110 reg = <0x14e0>; 1111 }; 1112 1113 hsmmc1_fclk: hsmmc1_fclk { 1114 #clock-cells = <0>; 1115 compatible = "ti,mux-clock"; 1116 clocks = <&func_64m_fclk>, <&func_96m_fclk>; 1117 ti,bit-shift = <24>; 1118 reg = <0x1328>; 1119 }; 1120 1121 hsmmc2_fclk: hsmmc2_fclk { 1122 #clock-cells = <0>; 1123 compatible = "ti,mux-clock"; 1124 clocks = <&func_64m_fclk>, <&func_96m_fclk>; 1125 ti,bit-shift = <24>; 1126 reg = <0x1330>; 1127 }; 1128 1129 ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m { 1130 #clock-cells = <0>; 1131 compatible = "ti,gate-clock"; 1132 clocks = <&func_48m_fclk>; 1133 ti,bit-shift = <8>; 1134 reg = <0x13e0>; 1135 }; 1136 1137 sha2md5_fck: sha2md5_fck { 1138 #clock-cells = <0>; 1139 compatible = "ti,gate-clock"; 1140 clocks = <&l3_div_ck>; 1141 ti,bit-shift = <1>; 1142 reg = <0x15c8>; 1143 }; 1144 1145 slimbus2_fclk_1: slimbus2_fclk_1 { 1146 #clock-cells = <0>; 1147 compatible = "ti,gate-clock"; 1148 clocks = <&per_abe_24m_fclk>; 1149 ti,bit-shift = <9>; 1150 reg = <0x1538>; 1151 }; 1152 1153 slimbus2_fclk_0: slimbus2_fclk_0 { 1154 #clock-cells = <0>; 1155 compatible = "ti,gate-clock"; 1156 clocks = <&func_24mc_fclk>; 1157 ti,bit-shift = <8>; 1158 reg = <0x1538>; 1159 }; 1160 1161 slimbus2_slimbus_clk: slimbus2_slimbus_clk { 1162 #clock-cells = <0>; 1163 compatible = "ti,gate-clock"; 1164 clocks = <&pad_slimbus_core_clks_ck>; 1165 ti,bit-shift = <10>; 1166 reg = <0x1538>; 1167 }; 1168 1169 smartreflex_core_fck: smartreflex_core_fck { 1170 #clock-cells = <0>; 1171 compatible = "ti,gate-clock"; 1172 clocks = <&l4_wkup_clk_mux_ck>; 1173 ti,bit-shift = <1>; 1174 reg = <0x0638>; 1175 }; 1176 1177 smartreflex_iva_fck: smartreflex_iva_fck { 1178 #clock-cells = <0>; 1179 compatible = "ti,gate-clock"; 1180 clocks = <&l4_wkup_clk_mux_ck>; 1181 ti,bit-shift = <1>; 1182 reg = <0x0630>; 1183 }; 1184 1185 smartreflex_mpu_fck: smartreflex_mpu_fck { 1186 #clock-cells = <0>; 1187 compatible = "ti,gate-clock"; 1188 clocks = <&l4_wkup_clk_mux_ck>; 1189 ti,bit-shift = <1>; 1190 reg = <0x0628>; 1191 }; 1192 1193 cm2_dm10_mux: cm2_dm10_mux { 1194 #clock-cells = <0>; 1195 compatible = "ti,mux-clock"; 1196 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 1197 ti,bit-shift = <24>; 1198 reg = <0x1428>; 1199 }; 1200 1201 cm2_dm11_mux: cm2_dm11_mux { 1202 #clock-cells = <0>; 1203 compatible = "ti,mux-clock"; 1204 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 1205 ti,bit-shift = <24>; 1206 reg = <0x1430>; 1207 }; 1208 1209 cm2_dm2_mux: cm2_dm2_mux { 1210 #clock-cells = <0>; 1211 compatible = "ti,mux-clock"; 1212 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 1213 ti,bit-shift = <24>; 1214 reg = <0x1438>; 1215 }; 1216 1217 cm2_dm3_mux: cm2_dm3_mux { 1218 #clock-cells = <0>; 1219 compatible = "ti,mux-clock"; 1220 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 1221 ti,bit-shift = <24>; 1222 reg = <0x1440>; 1223 }; 1224 1225 cm2_dm4_mux: cm2_dm4_mux { 1226 #clock-cells = <0>; 1227 compatible = "ti,mux-clock"; 1228 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 1229 ti,bit-shift = <24>; 1230 reg = <0x1448>; 1231 }; 1232 1233 cm2_dm9_mux: cm2_dm9_mux { 1234 #clock-cells = <0>; 1235 compatible = "ti,mux-clock"; 1236 clocks = <&sys_clkin_ck>, <&sys_32k_ck>; 1237 ti,bit-shift = <24>; 1238 reg = <0x1450>; 1239 }; 1240 1241 usb_host_fs_fck: usb_host_fs_fck { 1242 #clock-cells = <0>; 1243 compatible = "ti,gate-clock"; 1244 clocks = <&func_48mc_fclk>; 1245 ti,bit-shift = <1>; 1246 reg = <0x13d0>; 1247 }; 1248 1249 utmi_p1_gfclk: utmi_p1_gfclk { 1250 #clock-cells = <0>; 1251 compatible = "ti,mux-clock"; 1252 clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>; 1253 ti,bit-shift = <24>; 1254 reg = <0x1358>; 1255 }; 1256 1257 usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { 1258 #clock-cells = <0>; 1259 compatible = "ti,gate-clock"; 1260 clocks = <&utmi_p1_gfclk>; 1261 ti,bit-shift = <8>; 1262 reg = <0x1358>; 1263 }; 1264 1265 utmi_p2_gfclk: utmi_p2_gfclk { 1266 #clock-cells = <0>; 1267 compatible = "ti,mux-clock"; 1268 clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>; 1269 ti,bit-shift = <25>; 1270 reg = <0x1358>; 1271 }; 1272 1273 usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { 1274 #clock-cells = <0>; 1275 compatible = "ti,gate-clock"; 1276 clocks = <&utmi_p2_gfclk>; 1277 ti,bit-shift = <9>; 1278 reg = <0x1358>; 1279 }; 1280 1281 usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { 1282 #clock-cells = <0>; 1283 compatible = "ti,gate-clock"; 1284 clocks = <&init_60m_fclk>; 1285 ti,bit-shift = <10>; 1286 reg = <0x1358>; 1287 }; 1288 1289 usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { 1290 #clock-cells = <0>; 1291 compatible = "ti,gate-clock"; 1292 clocks = <&dpll_usb_m2_ck>; 1293 ti,bit-shift = <13>; 1294 reg = <0x1358>; 1295 }; 1296 1297 usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { 1298 #clock-cells = <0>; 1299 compatible = "ti,gate-clock"; 1300 clocks = <&init_60m_fclk>; 1301 ti,bit-shift = <11>; 1302 reg = <0x1358>; 1303 }; 1304 1305 usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { 1306 #clock-cells = <0>; 1307 compatible = "ti,gate-clock"; 1308 clocks = <&init_60m_fclk>; 1309 ti,bit-shift = <12>; 1310 reg = <0x1358>; 1311 }; 1312 1313 usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { 1314 #clock-cells = <0>; 1315 compatible = "ti,gate-clock"; 1316 clocks = <&dpll_usb_m2_ck>; 1317 ti,bit-shift = <14>; 1318 reg = <0x1358>; 1319 }; 1320 1321 usb_host_hs_func48mclk: usb_host_hs_func48mclk { 1322 #clock-cells = <0>; 1323 compatible = "ti,gate-clock"; 1324 clocks = <&func_48mc_fclk>; 1325 ti,bit-shift = <15>; 1326 reg = <0x1358>; 1327 }; 1328 1329 usb_host_hs_fck: usb_host_hs_fck { 1330 #clock-cells = <0>; 1331 compatible = "ti,gate-clock"; 1332 clocks = <&init_60m_fclk>; 1333 ti,bit-shift = <1>; 1334 reg = <0x1358>; 1335 }; 1336 1337 otg_60m_gfclk: otg_60m_gfclk { 1338 #clock-cells = <0>; 1339 compatible = "ti,mux-clock"; 1340 clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>; 1341 ti,bit-shift = <24>; 1342 reg = <0x1360>; 1343 }; 1344 1345 usb_otg_hs_xclk: usb_otg_hs_xclk { 1346 #clock-cells = <0>; 1347 compatible = "ti,gate-clock"; 1348 clocks = <&otg_60m_gfclk>; 1349 ti,bit-shift = <8>; 1350 reg = <0x1360>; 1351 }; 1352 1353 usb_otg_hs_ick: usb_otg_hs_ick { 1354 #clock-cells = <0>; 1355 compatible = "ti,gate-clock"; 1356 clocks = <&l3_div_ck>; 1357 ti,bit-shift = <0>; 1358 reg = <0x1360>; 1359 }; 1360 1361 usb_phy_cm_clk32k: usb_phy_cm_clk32k { 1362 #clock-cells = <0>; 1363 compatible = "ti,gate-clock"; 1364 clocks = <&sys_32k_ck>; 1365 ti,bit-shift = <8>; 1366 reg = <0x0640>; 1367 }; 1368 1369 usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { 1370 #clock-cells = <0>; 1371 compatible = "ti,gate-clock"; 1372 clocks = <&init_60m_fclk>; 1373 ti,bit-shift = <10>; 1374 reg = <0x1368>; 1375 }; 1376 1377 usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { 1378 #clock-cells = <0>; 1379 compatible = "ti,gate-clock"; 1380 clocks = <&init_60m_fclk>; 1381 ti,bit-shift = <8>; 1382 reg = <0x1368>; 1383 }; 1384 1385 usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { 1386 #clock-cells = <0>; 1387 compatible = "ti,gate-clock"; 1388 clocks = <&init_60m_fclk>; 1389 ti,bit-shift = <9>; 1390 reg = <0x1368>; 1391 }; 1392 1393 usb_tll_hs_ick: usb_tll_hs_ick { 1394 #clock-cells = <0>; 1395 compatible = "ti,gate-clock"; 1396 clocks = <&l4_div_ck>; 1397 ti,bit-shift = <0>; 1398 reg = <0x1368>; 1399 }; 1400}; 1401 1402&cm2_clockdomains { 1403 l3_init_clkdm: l3_init_clkdm { 1404 compatible = "ti,clockdomain"; 1405 clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>; 1406 }; 1407}; 1408 1409&scrm_clocks { 1410 auxclk0_src_gate_ck: auxclk0_src_gate_ck { 1411 #clock-cells = <0>; 1412 compatible = "ti,composite-no-wait-gate-clock"; 1413 clocks = <&dpll_core_m3x2_ck>; 1414 ti,bit-shift = <8>; 1415 reg = <0x0310>; 1416 }; 1417 1418 auxclk0_src_mux_ck: auxclk0_src_mux_ck { 1419 #clock-cells = <0>; 1420 compatible = "ti,composite-mux-clock"; 1421 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1422 ti,bit-shift = <1>; 1423 reg = <0x0310>; 1424 }; 1425 1426 auxclk0_src_ck: auxclk0_src_ck { 1427 #clock-cells = <0>; 1428 compatible = "ti,composite-clock"; 1429 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; 1430 }; 1431 1432 auxclk0_ck: auxclk0_ck { 1433 #clock-cells = <0>; 1434 compatible = "ti,divider-clock"; 1435 clocks = <&auxclk0_src_ck>; 1436 ti,bit-shift = <16>; 1437 ti,max-div = <16>; 1438 reg = <0x0310>; 1439 }; 1440 1441 auxclk1_src_gate_ck: auxclk1_src_gate_ck { 1442 #clock-cells = <0>; 1443 compatible = "ti,composite-no-wait-gate-clock"; 1444 clocks = <&dpll_core_m3x2_ck>; 1445 ti,bit-shift = <8>; 1446 reg = <0x0314>; 1447 }; 1448 1449 auxclk1_src_mux_ck: auxclk1_src_mux_ck { 1450 #clock-cells = <0>; 1451 compatible = "ti,composite-mux-clock"; 1452 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1453 ti,bit-shift = <1>; 1454 reg = <0x0314>; 1455 }; 1456 1457 auxclk1_src_ck: auxclk1_src_ck { 1458 #clock-cells = <0>; 1459 compatible = "ti,composite-clock"; 1460 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; 1461 }; 1462 1463 auxclk1_ck: auxclk1_ck { 1464 #clock-cells = <0>; 1465 compatible = "ti,divider-clock"; 1466 clocks = <&auxclk1_src_ck>; 1467 ti,bit-shift = <16>; 1468 ti,max-div = <16>; 1469 reg = <0x0314>; 1470 }; 1471 1472 auxclk2_src_gate_ck: auxclk2_src_gate_ck { 1473 #clock-cells = <0>; 1474 compatible = "ti,composite-no-wait-gate-clock"; 1475 clocks = <&dpll_core_m3x2_ck>; 1476 ti,bit-shift = <8>; 1477 reg = <0x0318>; 1478 }; 1479 1480 auxclk2_src_mux_ck: auxclk2_src_mux_ck { 1481 #clock-cells = <0>; 1482 compatible = "ti,composite-mux-clock"; 1483 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1484 ti,bit-shift = <1>; 1485 reg = <0x0318>; 1486 }; 1487 1488 auxclk2_src_ck: auxclk2_src_ck { 1489 #clock-cells = <0>; 1490 compatible = "ti,composite-clock"; 1491 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; 1492 }; 1493 1494 auxclk2_ck: auxclk2_ck { 1495 #clock-cells = <0>; 1496 compatible = "ti,divider-clock"; 1497 clocks = <&auxclk2_src_ck>; 1498 ti,bit-shift = <16>; 1499 ti,max-div = <16>; 1500 reg = <0x0318>; 1501 }; 1502 1503 auxclk3_src_gate_ck: auxclk3_src_gate_ck { 1504 #clock-cells = <0>; 1505 compatible = "ti,composite-no-wait-gate-clock"; 1506 clocks = <&dpll_core_m3x2_ck>; 1507 ti,bit-shift = <8>; 1508 reg = <0x031c>; 1509 }; 1510 1511 auxclk3_src_mux_ck: auxclk3_src_mux_ck { 1512 #clock-cells = <0>; 1513 compatible = "ti,composite-mux-clock"; 1514 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1515 ti,bit-shift = <1>; 1516 reg = <0x031c>; 1517 }; 1518 1519 auxclk3_src_ck: auxclk3_src_ck { 1520 #clock-cells = <0>; 1521 compatible = "ti,composite-clock"; 1522 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; 1523 }; 1524 1525 auxclk3_ck: auxclk3_ck { 1526 #clock-cells = <0>; 1527 compatible = "ti,divider-clock"; 1528 clocks = <&auxclk3_src_ck>; 1529 ti,bit-shift = <16>; 1530 ti,max-div = <16>; 1531 reg = <0x031c>; 1532 }; 1533 1534 auxclk4_src_gate_ck: auxclk4_src_gate_ck { 1535 #clock-cells = <0>; 1536 compatible = "ti,composite-no-wait-gate-clock"; 1537 clocks = <&dpll_core_m3x2_ck>; 1538 ti,bit-shift = <8>; 1539 reg = <0x0320>; 1540 }; 1541 1542 auxclk4_src_mux_ck: auxclk4_src_mux_ck { 1543 #clock-cells = <0>; 1544 compatible = "ti,composite-mux-clock"; 1545 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1546 ti,bit-shift = <1>; 1547 reg = <0x0320>; 1548 }; 1549 1550 auxclk4_src_ck: auxclk4_src_ck { 1551 #clock-cells = <0>; 1552 compatible = "ti,composite-clock"; 1553 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; 1554 }; 1555 1556 auxclk4_ck: auxclk4_ck { 1557 #clock-cells = <0>; 1558 compatible = "ti,divider-clock"; 1559 clocks = <&auxclk4_src_ck>; 1560 ti,bit-shift = <16>; 1561 ti,max-div = <16>; 1562 reg = <0x0320>; 1563 }; 1564 1565 auxclk5_src_gate_ck: auxclk5_src_gate_ck { 1566 #clock-cells = <0>; 1567 compatible = "ti,composite-no-wait-gate-clock"; 1568 clocks = <&dpll_core_m3x2_ck>; 1569 ti,bit-shift = <8>; 1570 reg = <0x0324>; 1571 }; 1572 1573 auxclk5_src_mux_ck: auxclk5_src_mux_ck { 1574 #clock-cells = <0>; 1575 compatible = "ti,composite-mux-clock"; 1576 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1577 ti,bit-shift = <1>; 1578 reg = <0x0324>; 1579 }; 1580 1581 auxclk5_src_ck: auxclk5_src_ck { 1582 #clock-cells = <0>; 1583 compatible = "ti,composite-clock"; 1584 clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; 1585 }; 1586 1587 auxclk5_ck: auxclk5_ck { 1588 #clock-cells = <0>; 1589 compatible = "ti,divider-clock"; 1590 clocks = <&auxclk5_src_ck>; 1591 ti,bit-shift = <16>; 1592 ti,max-div = <16>; 1593 reg = <0x0324>; 1594 }; 1595 1596 auxclkreq0_ck: auxclkreq0_ck { 1597 #clock-cells = <0>; 1598 compatible = "ti,mux-clock"; 1599 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1600 ti,bit-shift = <2>; 1601 reg = <0x0210>; 1602 }; 1603 1604 auxclkreq1_ck: auxclkreq1_ck { 1605 #clock-cells = <0>; 1606 compatible = "ti,mux-clock"; 1607 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1608 ti,bit-shift = <2>; 1609 reg = <0x0214>; 1610 }; 1611 1612 auxclkreq2_ck: auxclkreq2_ck { 1613 #clock-cells = <0>; 1614 compatible = "ti,mux-clock"; 1615 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1616 ti,bit-shift = <2>; 1617 reg = <0x0218>; 1618 }; 1619 1620 auxclkreq3_ck: auxclkreq3_ck { 1621 #clock-cells = <0>; 1622 compatible = "ti,mux-clock"; 1623 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1624 ti,bit-shift = <2>; 1625 reg = <0x021c>; 1626 }; 1627 1628 auxclkreq4_ck: auxclkreq4_ck { 1629 #clock-cells = <0>; 1630 compatible = "ti,mux-clock"; 1631 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1632 ti,bit-shift = <2>; 1633 reg = <0x0220>; 1634 }; 1635 1636 auxclkreq5_ck: auxclkreq5_ck { 1637 #clock-cells = <0>; 1638 compatible = "ti,mux-clock"; 1639 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; 1640 ti,bit-shift = <2>; 1641 reg = <0x0224>; 1642 }; 1643}; 1644