1/* 2 * Samsung's Exynos3250 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 8 * based board files can include this file and provide values for board specfic 9 * bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional 13 * nodes can be added to this file. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20#include "skeleton.dtsi" 21#include "exynos4-cpu-thermal.dtsi" 22#include <dt-bindings/clock/exynos3250.h> 23 24/ { 25 compatible = "samsung,exynos3250"; 26 interrupt-parent = <&gic>; 27 28 aliases { 29 pinctrl0 = &pinctrl_0; 30 pinctrl1 = &pinctrl_1; 31 mshc0 = &mshc_0; 32 mshc1 = &mshc_1; 33 spi0 = &spi_0; 34 spi1 = &spi_1; 35 i2c0 = &i2c_0; 36 i2c1 = &i2c_1; 37 i2c2 = &i2c_2; 38 i2c3 = &i2c_3; 39 i2c4 = &i2c_4; 40 i2c5 = &i2c_5; 41 i2c6 = &i2c_6; 42 i2c7 = &i2c_7; 43 serial0 = &serial_0; 44 serial1 = &serial_1; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0>; 55 clock-frequency = <1000000000>; 56 }; 57 58 cpu1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <1>; 62 clock-frequency = <1000000000>; 63 }; 64 }; 65 66 soc: soc { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges; 71 72 fixed-rate-clocks { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 xusbxti: clock@0 { 77 compatible = "fixed-clock"; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 reg = <0>; 81 clock-frequency = <0>; 82 #clock-cells = <0>; 83 clock-output-names = "xusbxti"; 84 }; 85 86 xxti: clock@1 { 87 compatible = "fixed-clock"; 88 reg = <1>; 89 clock-frequency = <0>; 90 #clock-cells = <0>; 91 clock-output-names = "xxti"; 92 }; 93 94 xtcxo: clock@2 { 95 compatible = "fixed-clock"; 96 reg = <2>; 97 clock-frequency = <0>; 98 #clock-cells = <0>; 99 clock-output-names = "xtcxo"; 100 }; 101 }; 102 103 sysram@02020000 { 104 compatible = "mmio-sram"; 105 reg = <0x02020000 0x40000>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges = <0 0x02020000 0x40000>; 109 110 smp-sysram@0 { 111 compatible = "samsung,exynos4210-sysram"; 112 reg = <0x0 0x1000>; 113 }; 114 115 smp-sysram@3f000 { 116 compatible = "samsung,exynos4210-sysram-ns"; 117 reg = <0x3f000 0x1000>; 118 }; 119 }; 120 121 chipid@10000000 { 122 compatible = "samsung,exynos4210-chipid"; 123 reg = <0x10000000 0x100>; 124 }; 125 126 sys_reg: syscon@10010000 { 127 compatible = "samsung,exynos3-sysreg", "syscon"; 128 reg = <0x10010000 0x400>; 129 }; 130 131 pmu_system_controller: system-controller@10020000 { 132 compatible = "samsung,exynos3250-pmu", "syscon"; 133 reg = <0x10020000 0x4000>; 134 interrupt-controller; 135 #interrupt-cells = <3>; 136 interrupt-parent = <&gic>; 137 }; 138 139 mipi_phy: video-phy@10020710 { 140 compatible = "samsung,s5pv210-mipi-video-phy"; 141 reg = <0x10020710 8>; 142 #phy-cells = <1>; 143 }; 144 145 pd_cam: cam-power-domain@10023C00 { 146 compatible = "samsung,exynos4210-pd"; 147 reg = <0x10023C00 0x20>; 148 #power-domain-cells = <0>; 149 }; 150 151 pd_mfc: mfc-power-domain@10023C40 { 152 compatible = "samsung,exynos4210-pd"; 153 reg = <0x10023C40 0x20>; 154 #power-domain-cells = <0>; 155 }; 156 157 pd_g3d: g3d-power-domain@10023C60 { 158 compatible = "samsung,exynos4210-pd"; 159 reg = <0x10023C60 0x20>; 160 #power-domain-cells = <0>; 161 }; 162 163 pd_lcd0: lcd0-power-domain@10023C80 { 164 compatible = "samsung,exynos4210-pd"; 165 reg = <0x10023C80 0x20>; 166 #power-domain-cells = <0>; 167 }; 168 169 pd_isp: isp-power-domain@10023CA0 { 170 compatible = "samsung,exynos4210-pd"; 171 reg = <0x10023CA0 0x20>; 172 #power-domain-cells = <0>; 173 }; 174 175 cmu: clock-controller@10030000 { 176 compatible = "samsung,exynos3250-cmu"; 177 reg = <0x10030000 0x20000>; 178 #clock-cells = <1>; 179 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, 180 <&cmu CLK_MOUT_ACLK_266_SUB>; 181 assigned-clock-parents = <&cmu CLK_FIN_PLL>, 182 <&cmu CLK_FIN_PLL>; 183 }; 184 185 cmu_dmc: clock-controller@105C0000 { 186 compatible = "samsung,exynos3250-cmu-dmc"; 187 reg = <0x105C0000 0x2000>; 188 #clock-cells = <1>; 189 }; 190 191 rtc: rtc@10070000 { 192 compatible = "samsung,exynos3250-rtc"; 193 reg = <0x10070000 0x100>; 194 interrupts = <0 73 0>, <0 74 0>; 195 interrupt-parent = <&pmu_system_controller>; 196 status = "disabled"; 197 }; 198 199 tmu: tmu@100C0000 { 200 compatible = "samsung,exynos3250-tmu"; 201 reg = <0x100C0000 0x100>; 202 interrupts = <0 216 0>; 203 clocks = <&cmu CLK_TMU_APBIF>; 204 clock-names = "tmu_apbif"; 205 #include "exynos4412-tmu-sensor-conf.dtsi" 206 status = "disabled"; 207 }; 208 209 gic: interrupt-controller@10481000 { 210 compatible = "arm,cortex-a15-gic"; 211 #interrupt-cells = <3>; 212 interrupt-controller; 213 reg = <0x10481000 0x1000>, 214 <0x10482000 0x1000>, 215 <0x10484000 0x2000>, 216 <0x10486000 0x2000>; 217 interrupts = <1 9 0xf04>; 218 }; 219 220 mct@10050000 { 221 compatible = "samsung,exynos4210-mct"; 222 reg = <0x10050000 0x800>; 223 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, 224 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; 225 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 226 clock-names = "fin_pll", "mct"; 227 }; 228 229 pinctrl_1: pinctrl@11000000 { 230 compatible = "samsung,exynos3250-pinctrl"; 231 reg = <0x11000000 0x1000>; 232 interrupts = <0 225 0>; 233 234 wakeup-interrupt-controller { 235 compatible = "samsung,exynos4210-wakeup-eint"; 236 interrupts = <0 48 0>; 237 }; 238 }; 239 240 pinctrl_0: pinctrl@11400000 { 241 compatible = "samsung,exynos3250-pinctrl"; 242 reg = <0x11400000 0x1000>; 243 interrupts = <0 240 0>; 244 }; 245 246 fimd: fimd@11c00000 { 247 compatible = "samsung,exynos3250-fimd"; 248 reg = <0x11c00000 0x30000>; 249 interrupt-names = "fifo", "vsync", "lcd_sys"; 250 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 251 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 252 clock-names = "sclk_fimd", "fimd"; 253 power-domains = <&pd_lcd0>; 254 samsung,sysreg = <&sys_reg>; 255 status = "disabled"; 256 }; 257 258 dsi_0: dsi@11C80000 { 259 compatible = "samsung,exynos3250-mipi-dsi"; 260 reg = <0x11C80000 0x10000>; 261 interrupts = <0 83 0>; 262 samsung,phy-type = <0>; 263 power-domains = <&pd_lcd0>; 264 phys = <&mipi_phy 1>; 265 phy-names = "dsim"; 266 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 267 clock-names = "bus_clk", "pll_clk"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 hsotg: hsotg@12480000 { 274 compatible = "snps,dwc2"; 275 reg = <0x12480000 0x20000>; 276 interrupts = <0 141 0>; 277 clocks = <&cmu CLK_USBOTG>; 278 clock-names = "otg"; 279 phys = <&exynos_usbphy 0>; 280 phy-names = "usb2-phy"; 281 status = "disabled"; 282 }; 283 284 mshc_0: mshc@12510000 { 285 compatible = "samsung,exynos5250-dw-mshc"; 286 reg = <0x12510000 0x1000>; 287 interrupts = <0 142 0>; 288 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 289 clock-names = "biu", "ciu"; 290 fifo-depth = <0x80>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 }; 295 296 mshc_1: mshc@12520000 { 297 compatible = "samsung,exynos5250-dw-mshc"; 298 reg = <0x12520000 0x1000>; 299 interrupts = <0 143 0>; 300 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 301 clock-names = "biu", "ciu"; 302 fifo-depth = <0x80>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 status = "disabled"; 306 }; 307 308 exynos_usbphy: exynos-usbphy@125B0000 { 309 compatible = "samsung,exynos3250-usb2-phy"; 310 reg = <0x125B0000 0x100>; 311 samsung,pmureg-phandle = <&pmu_system_controller>; 312 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; 313 clock-names = "phy", "ref"; 314 #phy-cells = <1>; 315 status = "disabled"; 316 }; 317 318 amba { 319 compatible = "arm,amba-bus"; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges; 323 324 pdma0: pdma@12680000 { 325 compatible = "arm,pl330", "arm,primecell"; 326 reg = <0x12680000 0x1000>; 327 interrupts = <0 138 0>; 328 clocks = <&cmu CLK_PDMA0>; 329 clock-names = "apb_pclk"; 330 #dma-cells = <1>; 331 #dma-channels = <8>; 332 #dma-requests = <32>; 333 }; 334 335 pdma1: pdma@12690000 { 336 compatible = "arm,pl330", "arm,primecell"; 337 reg = <0x12690000 0x1000>; 338 interrupts = <0 139 0>; 339 clocks = <&cmu CLK_PDMA1>; 340 clock-names = "apb_pclk"; 341 #dma-cells = <1>; 342 #dma-channels = <8>; 343 #dma-requests = <32>; 344 }; 345 }; 346 347 adc: adc@126C0000 { 348 compatible = "samsung,exynos3250-adc", 349 "samsung,exynos-adc-v2"; 350 reg = <0x126C0000 0x100>; 351 interrupts = <0 137 0>; 352 clock-names = "adc", "sclk"; 353 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 354 #io-channel-cells = <1>; 355 io-channel-ranges; 356 samsung,syscon-phandle = <&pmu_system_controller>; 357 status = "disabled"; 358 }; 359 360 mfc: codec@13400000 { 361 compatible = "samsung,mfc-v7"; 362 reg = <0x13400000 0x10000>; 363 interrupts = <0 102 0>; 364 clock-names = "mfc", "sclk_mfc"; 365 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 366 power-domains = <&pd_mfc>; 367 status = "disabled"; 368 }; 369 370 serial_0: serial@13800000 { 371 compatible = "samsung,exynos4210-uart"; 372 reg = <0x13800000 0x100>; 373 interrupts = <0 109 0>; 374 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 375 clock-names = "uart", "clk_uart_baud0"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&uart0_data &uart0_fctl>; 378 status = "disabled"; 379 }; 380 381 serial_1: serial@13810000 { 382 compatible = "samsung,exynos4210-uart"; 383 reg = <0x13810000 0x100>; 384 interrupts = <0 110 0>; 385 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 386 clock-names = "uart", "clk_uart_baud0"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&uart1_data>; 389 status = "disabled"; 390 }; 391 392 i2c_0: i2c@13860000 { 393 #address-cells = <1>; 394 #size-cells = <0>; 395 compatible = "samsung,s3c2440-i2c"; 396 reg = <0x13860000 0x100>; 397 interrupts = <0 113 0>; 398 clocks = <&cmu CLK_I2C0>; 399 clock-names = "i2c"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c0_bus>; 402 status = "disabled"; 403 }; 404 405 i2c_1: i2c@13870000 { 406 #address-cells = <1>; 407 #size-cells = <0>; 408 compatible = "samsung,s3c2440-i2c"; 409 reg = <0x13870000 0x100>; 410 interrupts = <0 114 0>; 411 clocks = <&cmu CLK_I2C1>; 412 clock-names = "i2c"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c1_bus>; 415 status = "disabled"; 416 }; 417 418 i2c_2: i2c@13880000 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 compatible = "samsung,s3c2440-i2c"; 422 reg = <0x13880000 0x100>; 423 interrupts = <0 115 0>; 424 clocks = <&cmu CLK_I2C2>; 425 clock-names = "i2c"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&i2c2_bus>; 428 status = "disabled"; 429 }; 430 431 i2c_3: i2c@13890000 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 compatible = "samsung,s3c2440-i2c"; 435 reg = <0x13890000 0x100>; 436 interrupts = <0 116 0>; 437 clocks = <&cmu CLK_I2C3>; 438 clock-names = "i2c"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&i2c3_bus>; 441 status = "disabled"; 442 }; 443 444 i2c_4: i2c@138A0000 { 445 #address-cells = <1>; 446 #size-cells = <0>; 447 compatible = "samsung,s3c2440-i2c"; 448 reg = <0x138A0000 0x100>; 449 interrupts = <0 117 0>; 450 clocks = <&cmu CLK_I2C4>; 451 clock-names = "i2c"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&i2c4_bus>; 454 status = "disabled"; 455 }; 456 457 i2c_5: i2c@138B0000 { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 compatible = "samsung,s3c2440-i2c"; 461 reg = <0x138B0000 0x100>; 462 interrupts = <0 118 0>; 463 clocks = <&cmu CLK_I2C5>; 464 clock-names = "i2c"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&i2c5_bus>; 467 status = "disabled"; 468 }; 469 470 i2c_6: i2c@138C0000 { 471 #address-cells = <1>; 472 #size-cells = <0>; 473 compatible = "samsung,s3c2440-i2c"; 474 reg = <0x138C0000 0x100>; 475 interrupts = <0 119 0>; 476 clocks = <&cmu CLK_I2C6>; 477 clock-names = "i2c"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&i2c6_bus>; 480 status = "disabled"; 481 }; 482 483 i2c_7: i2c@138D0000 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 compatible = "samsung,s3c2440-i2c"; 487 reg = <0x138D0000 0x100>; 488 interrupts = <0 120 0>; 489 clocks = <&cmu CLK_I2C7>; 490 clock-names = "i2c"; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&i2c7_bus>; 493 status = "disabled"; 494 }; 495 496 spi_0: spi@13920000 { 497 compatible = "samsung,exynos4210-spi"; 498 reg = <0x13920000 0x100>; 499 interrupts = <0 121 0>; 500 dmas = <&pdma0 7>, <&pdma0 6>; 501 dma-names = "tx", "rx"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 505 clock-names = "spi", "spi_busclk0"; 506 samsung,spi-src-clk = <0>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&spi0_bus>; 509 status = "disabled"; 510 }; 511 512 spi_1: spi@13930000 { 513 compatible = "samsung,exynos4210-spi"; 514 reg = <0x13930000 0x100>; 515 interrupts = <0 122 0>; 516 dmas = <&pdma1 7>, <&pdma1 6>; 517 dma-names = "tx", "rx"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 521 clock-names = "spi", "spi_busclk0"; 522 samsung,spi-src-clk = <0>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&spi1_bus>; 525 status = "disabled"; 526 }; 527 528 i2s2: i2s@13970000 { 529 compatible = "samsung,s3c6410-i2s"; 530 reg = <0x13970000 0x100>; 531 interrupts = <0 126 0>; 532 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; 533 clock-names = "iis", "i2s_opclk0"; 534 dmas = <&pdma0 14>, <&pdma0 13>; 535 dma-names = "tx", "rx"; 536 pinctrl-0 = <&i2s2_bus>; 537 pinctrl-names = "default"; 538 status = "disabled"; 539 }; 540 541 pwm: pwm@139D0000 { 542 compatible = "samsung,exynos4210-pwm"; 543 reg = <0x139D0000 0x1000>; 544 interrupts = <0 104 0>, <0 105 0>, <0 106 0>, 545 <0 107 0>, <0 108 0>; 546 #pwm-cells = <3>; 547 status = "disabled"; 548 }; 549 550 pmu { 551 compatible = "arm,cortex-a7-pmu"; 552 interrupts = <0 18 0>, <0 19 0>; 553 }; 554 555 ppmu_dmc0: ppmu_dmc0@106a0000 { 556 compatible = "samsung,exynos-ppmu"; 557 reg = <0x106a0000 0x2000>; 558 status = "disabled"; 559 }; 560 561 ppmu_dmc1: ppmu_dmc1@106b0000 { 562 compatible = "samsung,exynos-ppmu"; 563 reg = <0x106b0000 0x2000>; 564 status = "disabled"; 565 }; 566 567 ppmu_cpu: ppmu_cpu@106c0000 { 568 compatible = "samsung,exynos-ppmu"; 569 reg = <0x106c0000 0x2000>; 570 status = "disabled"; 571 }; 572 573 ppmu_rightbus: ppmu_rightbus@112a0000 { 574 compatible = "samsung,exynos-ppmu"; 575 reg = <0x112a0000 0x2000>; 576 clocks = <&cmu CLK_PPMURIGHT>; 577 clock-names = "ppmu"; 578 status = "disabled"; 579 }; 580 581 ppmu_leftbus: ppmu_leftbus0@116a0000 { 582 compatible = "samsung,exynos-ppmu"; 583 reg = <0x116a0000 0x2000>; 584 clocks = <&cmu CLK_PPMULEFT>; 585 clock-names = "ppmu"; 586 status = "disabled"; 587 }; 588 589 ppmu_camif: ppmu_camif@11ac0000 { 590 compatible = "samsung,exynos-ppmu"; 591 reg = <0x11ac0000 0x2000>; 592 clocks = <&cmu CLK_PPMUCAMIF>; 593 clock-names = "ppmu"; 594 status = "disabled"; 595 }; 596 597 ppmu_lcd0: ppmu_lcd0@11e40000 { 598 compatible = "samsung,exynos-ppmu"; 599 reg = <0x11e40000 0x2000>; 600 clocks = <&cmu CLK_PPMULCD0>; 601 clock-names = "ppmu"; 602 status = "disabled"; 603 }; 604 605 ppmu_fsys: ppmu_fsys@12630000 { 606 compatible = "samsung,exynos-ppmu"; 607 reg = <0x12630000 0x2000>; 608 clocks = <&cmu CLK_PPMUFILE>; 609 clock-names = "ppmu"; 610 status = "disabled"; 611 }; 612 613 ppmu_g3d: ppmu_g3d@13220000 { 614 compatible = "samsung,exynos-ppmu"; 615 reg = <0x13220000 0x2000>; 616 clocks = <&cmu CLK_PPMUG3D>; 617 clock-names = "ppmu"; 618 status = "disabled"; 619 }; 620 621 ppmu_mfc: ppmu_mfc@13660000 { 622 compatible = "samsung,exynos-ppmu"; 623 reg = <0x13660000 0x2000>; 624 clocks = <&cmu CLK_PPMUMFC_L>; 625 clock-names = "ppmu"; 626 status = "disabled"; 627 }; 628 }; 629}; 630 631#include "exynos3250-pinctrl.dtsi" 632