Lines Matching refs:clocks
99 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
232 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
242 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
253 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
264 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
275 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
286 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
297 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
308 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
319 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
328 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
338 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
348 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
358 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
368 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
378 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
388 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
398 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
408 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
418 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
428 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
453 clocks = <&zb_clk>;
457 clocks {
462 /* External root clocks */
496 /* Special CPG clocks */
498 compatible = "renesas,r8a73a4-cpg-clocks";
500 clocks = <&extal1_clk>, <&extal2_clk>;
508 /* Variable factor clocks (DIV6) */
512 clocks = <&pll1_div2_clk>, <0>,
520 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
528 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
536 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
544 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
560 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
569 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
578 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
587 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
596 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
605 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
613 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
621 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
629 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
636 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
644 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
650 /* Fixed factor clocks */
653 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
661 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
669 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
677 clocks = <&extal1_clk>;
684 /* Gate clocks */
686 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
688 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
702 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
704 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
725 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
727 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
738 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
740 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;