1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include "skeleton.dtsi"
14
15#include <dt-bindings/thermal/thermal.h>
16
17#include <dt-bindings/dma/sun4i-a10.h>
18#include <dt-bindings/pinctrl/sun4i-a10.h>
19
20/ {
21	interrupt-parent = <&intc>;
22
23	aliases {
24		ethernet0 = &emac;
25	};
26
27	chosen {
28		#address-cells = <1>;
29		#size-cells = <1>;
30		ranges;
31
32		framebuffer@0 {
33			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
34			allwinner,pipeline = "de_be0-lcd0-hdmi";
35			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
36				 <&ahb_gates 44>;
37			status = "disabled";
38		};
39
40		framebuffer@1 {
41			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
42			allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
43			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
44				 <&ahb_gates 44>, <&ahb_gates 46>;
45			status = "disabled";
46		};
47
48		framebuffer@2 {
49			compatible = "allwinner,simple-framebuffer",
50				     "simple-framebuffer";
51			allwinner,pipeline = "de_fe0-de_be0-lcd0";
52			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
53				 <&ahb_gates 46>;
54			status = "disabled";
55		};
56
57		framebuffer@3 {
58			compatible = "allwinner,simple-framebuffer",
59				     "simple-framebuffer";
60			allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
61			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
62				 <&ahb_gates 44>, <&ahb_gates 46>;
63			status = "disabled";
64		};
65	};
66
67	cpus {
68		#address-cells = <1>;
69		#size-cells = <0>;
70		cpu0: cpu@0 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a8";
73			reg = <0x0>;
74			clocks = <&cpu>;
75			clock-latency = <244144>; /* 8 32k periods */
76			operating-points = <
77				/* kHz    uV */
78				1008000 1400000
79				912000  1350000
80				864000  1300000
81				624000  1250000
82				>;
83			#cooling-cells = <2>;
84			cooling-min-level = <0>;
85			cooling-max-level = <3>;
86		};
87	};
88
89	thermal-zones {
90		cpu_thermal {
91			/* milliseconds */
92			polling-delay-passive = <250>;
93			polling-delay = <1000>;
94			thermal-sensors = <&rtp>;
95
96			cooling-maps {
97				map0 {
98					trip = <&cpu_alert0>;
99					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
100				};
101			};
102
103			trips {
104				cpu_alert0: cpu_alert0 {
105					/* milliCelsius */
106					temperature = <850000>;
107					hysteresis = <2000>;
108					type = "passive";
109				};
110
111				cpu_crit: cpu_crit {
112					/* milliCelsius */
113					temperature = <100000>;
114					hysteresis = <2000>;
115					type = "critical";
116				};
117			};
118		};
119	};
120
121	memory {
122		reg = <0x40000000 0x80000000>;
123	};
124
125	clocks {
126		#address-cells = <1>;
127		#size-cells = <1>;
128		ranges;
129
130		/*
131		 * This is a dummy clock, to be used as placeholder on
132		 * other mux clocks when a specific parent clock is not
133		 * yet implemented. It should be dropped when the driver
134		 * is complete.
135		 */
136		dummy: dummy {
137			#clock-cells = <0>;
138			compatible = "fixed-clock";
139			clock-frequency = <0>;
140		};
141
142		osc24M: clk@01c20050 {
143			#clock-cells = <0>;
144			compatible = "allwinner,sun4i-a10-osc-clk";
145			reg = <0x01c20050 0x4>;
146			clock-frequency = <24000000>;
147			clock-output-names = "osc24M";
148		};
149
150		osc32k: clk@0 {
151			#clock-cells = <0>;
152			compatible = "fixed-clock";
153			clock-frequency = <32768>;
154			clock-output-names = "osc32k";
155		};
156
157		pll1: clk@01c20000 {
158			#clock-cells = <0>;
159			compatible = "allwinner,sun4i-a10-pll1-clk";
160			reg = <0x01c20000 0x4>;
161			clocks = <&osc24M>;
162			clock-output-names = "pll1";
163		};
164
165		pll4: clk@01c20018 {
166			#clock-cells = <0>;
167			compatible = "allwinner,sun4i-a10-pll1-clk";
168			reg = <0x01c20018 0x4>;
169			clocks = <&osc24M>;
170			clock-output-names = "pll4";
171		};
172
173		pll5: clk@01c20020 {
174			#clock-cells = <1>;
175			compatible = "allwinner,sun4i-a10-pll5-clk";
176			reg = <0x01c20020 0x4>;
177			clocks = <&osc24M>;
178			clock-output-names = "pll5_ddr", "pll5_other";
179		};
180
181		pll6: clk@01c20028 {
182			#clock-cells = <1>;
183			compatible = "allwinner,sun4i-a10-pll6-clk";
184			reg = <0x01c20028 0x4>;
185			clocks = <&osc24M>;
186			clock-output-names = "pll6_sata", "pll6_other", "pll6";
187		};
188
189		/* dummy is 200M */
190		cpu: cpu@01c20054 {
191			#clock-cells = <0>;
192			compatible = "allwinner,sun4i-a10-cpu-clk";
193			reg = <0x01c20054 0x4>;
194			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
195			clock-output-names = "cpu";
196		};
197
198		axi: axi@01c20054 {
199			#clock-cells = <0>;
200			compatible = "allwinner,sun4i-a10-axi-clk";
201			reg = <0x01c20054 0x4>;
202			clocks = <&cpu>;
203			clock-output-names = "axi";
204		};
205
206		axi_gates: clk@01c2005c {
207			#clock-cells = <1>;
208			compatible = "allwinner,sun4i-a10-axi-gates-clk";
209			reg = <0x01c2005c 0x4>;
210			clocks = <&axi>;
211			clock-output-names = "axi_dram";
212		};
213
214		ahb: ahb@01c20054 {
215			#clock-cells = <0>;
216			compatible = "allwinner,sun4i-a10-ahb-clk";
217			reg = <0x01c20054 0x4>;
218			clocks = <&axi>;
219			clock-output-names = "ahb";
220		};
221
222		ahb_gates: clk@01c20060 {
223			#clock-cells = <1>;
224			compatible = "allwinner,sun4i-a10-ahb-gates-clk";
225			reg = <0x01c20060 0x8>;
226			clocks = <&ahb>;
227			clock-output-names = "ahb_usb0", "ahb_ehci0",
228				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
229				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
230				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
231				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",
232				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
233				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
234				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
235				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
236				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
237				"ahb_de_fe1", "ahb_mp", "ahb_mali400";
238		};
239
240		apb0: apb0@01c20054 {
241			#clock-cells = <0>;
242			compatible = "allwinner,sun4i-a10-apb0-clk";
243			reg = <0x01c20054 0x4>;
244			clocks = <&ahb>;
245			clock-output-names = "apb0";
246		};
247
248		apb0_gates: clk@01c20068 {
249			#clock-cells = <1>;
250			compatible = "allwinner,sun4i-a10-apb0-gates-clk";
251			reg = <0x01c20068 0x4>;
252			clocks = <&apb0>;
253			clock-output-names = "apb0_codec", "apb0_spdif",
254				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
255				"apb0_ir1", "apb0_keypad";
256		};
257
258		apb1: clk@01c20058 {
259			#clock-cells = <0>;
260			compatible = "allwinner,sun4i-a10-apb1-clk";
261			reg = <0x01c20058 0x4>;
262			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
263			clock-output-names = "apb1";
264		};
265
266		apb1_gates: clk@01c2006c {
267			#clock-cells = <1>;
268			compatible = "allwinner,sun4i-a10-apb1-gates-clk";
269			reg = <0x01c2006c 0x4>;
270			clocks = <&apb1>;
271			clock-output-names = "apb1_i2c0", "apb1_i2c1",
272				"apb1_i2c2", "apb1_can", "apb1_scr",
273				"apb1_ps20", "apb1_ps21", "apb1_uart0",
274				"apb1_uart1", "apb1_uart2", "apb1_uart3",
275				"apb1_uart4", "apb1_uart5", "apb1_uart6",
276				"apb1_uart7";
277		};
278
279		nand_clk: clk@01c20080 {
280			#clock-cells = <0>;
281			compatible = "allwinner,sun4i-a10-mod0-clk";
282			reg = <0x01c20080 0x4>;
283			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
284			clock-output-names = "nand";
285		};
286
287		ms_clk: clk@01c20084 {
288			#clock-cells = <0>;
289			compatible = "allwinner,sun4i-a10-mod0-clk";
290			reg = <0x01c20084 0x4>;
291			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
292			clock-output-names = "ms";
293		};
294
295		mmc0_clk: clk@01c20088 {
296			#clock-cells = <1>;
297			compatible = "allwinner,sun4i-a10-mmc-clk";
298			reg = <0x01c20088 0x4>;
299			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
300			clock-output-names = "mmc0",
301					     "mmc0_output",
302					     "mmc0_sample";
303		};
304
305		mmc1_clk: clk@01c2008c {
306			#clock-cells = <1>;
307			compatible = "allwinner,sun4i-a10-mmc-clk";
308			reg = <0x01c2008c 0x4>;
309			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
310			clock-output-names = "mmc1",
311					     "mmc1_output",
312					     "mmc1_sample";
313		};
314
315		mmc2_clk: clk@01c20090 {
316			#clock-cells = <1>;
317			compatible = "allwinner,sun4i-a10-mmc-clk";
318			reg = <0x01c20090 0x4>;
319			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
320			clock-output-names = "mmc2",
321					     "mmc2_output",
322					     "mmc2_sample";
323		};
324
325		mmc3_clk: clk@01c20094 {
326			#clock-cells = <1>;
327			compatible = "allwinner,sun4i-a10-mmc-clk";
328			reg = <0x01c20094 0x4>;
329			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330			clock-output-names = "mmc3",
331					     "mmc3_output",
332					     "mmc3_sample";
333		};
334
335		ts_clk: clk@01c20098 {
336			#clock-cells = <0>;
337			compatible = "allwinner,sun4i-a10-mod0-clk";
338			reg = <0x01c20098 0x4>;
339			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
340			clock-output-names = "ts";
341		};
342
343		ss_clk: clk@01c2009c {
344			#clock-cells = <0>;
345			compatible = "allwinner,sun4i-a10-mod0-clk";
346			reg = <0x01c2009c 0x4>;
347			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
348			clock-output-names = "ss";
349		};
350
351		spi0_clk: clk@01c200a0 {
352			#clock-cells = <0>;
353			compatible = "allwinner,sun4i-a10-mod0-clk";
354			reg = <0x01c200a0 0x4>;
355			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
356			clock-output-names = "spi0";
357		};
358
359		spi1_clk: clk@01c200a4 {
360			#clock-cells = <0>;
361			compatible = "allwinner,sun4i-a10-mod0-clk";
362			reg = <0x01c200a4 0x4>;
363			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
364			clock-output-names = "spi1";
365		};
366
367		spi2_clk: clk@01c200a8 {
368			#clock-cells = <0>;
369			compatible = "allwinner,sun4i-a10-mod0-clk";
370			reg = <0x01c200a8 0x4>;
371			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
372			clock-output-names = "spi2";
373		};
374
375		pata_clk: clk@01c200ac {
376			#clock-cells = <0>;
377			compatible = "allwinner,sun4i-a10-mod0-clk";
378			reg = <0x01c200ac 0x4>;
379			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
380			clock-output-names = "pata";
381		};
382
383		ir0_clk: clk@01c200b0 {
384			#clock-cells = <0>;
385			compatible = "allwinner,sun4i-a10-mod0-clk";
386			reg = <0x01c200b0 0x4>;
387			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
388			clock-output-names = "ir0";
389		};
390
391		ir1_clk: clk@01c200b4 {
392			#clock-cells = <0>;
393			compatible = "allwinner,sun4i-a10-mod0-clk";
394			reg = <0x01c200b4 0x4>;
395			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
396			clock-output-names = "ir1";
397		};
398
399		usb_clk: clk@01c200cc {
400			#clock-cells = <1>;
401		        #reset-cells = <1>;
402			compatible = "allwinner,sun4i-a10-usb-clk";
403			reg = <0x01c200cc 0x4>;
404			clocks = <&pll6 1>;
405			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
406		};
407
408		spi3_clk: clk@01c200d4 {
409			#clock-cells = <0>;
410			compatible = "allwinner,sun4i-a10-mod0-clk";
411			reg = <0x01c200d4 0x4>;
412			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
413			clock-output-names = "spi3";
414		};
415	};
416
417	soc@01c00000 {
418		compatible = "simple-bus";
419		#address-cells = <1>;
420		#size-cells = <1>;
421		ranges;
422
423		dma: dma-controller@01c02000 {
424			compatible = "allwinner,sun4i-a10-dma";
425			reg = <0x01c02000 0x1000>;
426			interrupts = <27>;
427			clocks = <&ahb_gates 6>;
428			#dma-cells = <2>;
429		};
430
431		spi0: spi@01c05000 {
432			compatible = "allwinner,sun4i-a10-spi";
433			reg = <0x01c05000 0x1000>;
434			interrupts = <10>;
435			clocks = <&ahb_gates 20>, <&spi0_clk>;
436			clock-names = "ahb", "mod";
437			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
438			       <&dma SUN4I_DMA_DEDICATED 26>;
439			dma-names = "rx", "tx";
440			status = "disabled";
441			#address-cells = <1>;
442			#size-cells = <0>;
443		};
444
445		spi1: spi@01c06000 {
446			compatible = "allwinner,sun4i-a10-spi";
447			reg = <0x01c06000 0x1000>;
448			interrupts = <11>;
449			clocks = <&ahb_gates 21>, <&spi1_clk>;
450			clock-names = "ahb", "mod";
451			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
452			       <&dma SUN4I_DMA_DEDICATED 8>;
453			dma-names = "rx", "tx";
454			status = "disabled";
455			#address-cells = <1>;
456			#size-cells = <0>;
457		};
458
459		emac: ethernet@01c0b000 {
460			compatible = "allwinner,sun4i-a10-emac";
461			reg = <0x01c0b000 0x1000>;
462			interrupts = <55>;
463			clocks = <&ahb_gates 17>;
464			status = "disabled";
465		};
466
467		mdio: mdio@01c0b080 {
468			compatible = "allwinner,sun4i-a10-mdio";
469			reg = <0x01c0b080 0x14>;
470			status = "disabled";
471			#address-cells = <1>;
472			#size-cells = <0>;
473		};
474
475		mmc0: mmc@01c0f000 {
476			compatible = "allwinner,sun4i-a10-mmc";
477			reg = <0x01c0f000 0x1000>;
478			clocks = <&ahb_gates 8>,
479				 <&mmc0_clk 0>,
480				 <&mmc0_clk 1>,
481				 <&mmc0_clk 2>;
482			clock-names = "ahb",
483				      "mmc",
484				      "output",
485				      "sample";
486			interrupts = <32>;
487			status = "disabled";
488		};
489
490		mmc1: mmc@01c10000 {
491			compatible = "allwinner,sun4i-a10-mmc";
492			reg = <0x01c10000 0x1000>;
493			clocks = <&ahb_gates 9>,
494				 <&mmc1_clk 0>,
495				 <&mmc1_clk 1>,
496				 <&mmc1_clk 2>;
497			clock-names = "ahb",
498				      "mmc",
499				      "output",
500				      "sample";
501			interrupts = <33>;
502			status = "disabled";
503		};
504
505		mmc2: mmc@01c11000 {
506			compatible = "allwinner,sun4i-a10-mmc";
507			reg = <0x01c11000 0x1000>;
508			clocks = <&ahb_gates 10>,
509				 <&mmc2_clk 0>,
510				 <&mmc2_clk 1>,
511				 <&mmc2_clk 2>;
512			clock-names = "ahb",
513				      "mmc",
514				      "output",
515				      "sample";
516			interrupts = <34>;
517			status = "disabled";
518		};
519
520		mmc3: mmc@01c12000 {
521			compatible = "allwinner,sun4i-a10-mmc";
522			reg = <0x01c12000 0x1000>;
523			clocks = <&ahb_gates 11>,
524				 <&mmc3_clk 0>,
525				 <&mmc3_clk 1>,
526				 <&mmc3_clk 2>;
527			clock-names = "ahb",
528				      "mmc",
529				      "output",
530				      "sample";
531			interrupts = <35>;
532			status = "disabled";
533		};
534
535		usbphy: phy@01c13400 {
536			#phy-cells = <1>;
537			compatible = "allwinner,sun4i-a10-usb-phy";
538			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
539			reg-names = "phy_ctrl", "pmu1", "pmu2";
540			clocks = <&usb_clk 8>;
541			clock-names = "usb_phy";
542			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
543			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
544			status = "disabled";
545		};
546
547		ehci0: usb@01c14000 {
548			compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
549			reg = <0x01c14000 0x100>;
550			interrupts = <39>;
551			clocks = <&ahb_gates 1>;
552			phys = <&usbphy 1>;
553			phy-names = "usb";
554			status = "disabled";
555		};
556
557		ohci0: usb@01c14400 {
558			compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
559			reg = <0x01c14400 0x100>;
560			interrupts = <64>;
561			clocks = <&usb_clk 6>, <&ahb_gates 2>;
562			phys = <&usbphy 1>;
563			phy-names = "usb";
564			status = "disabled";
565		};
566
567		spi2: spi@01c17000 {
568			compatible = "allwinner,sun4i-a10-spi";
569			reg = <0x01c17000 0x1000>;
570			interrupts = <12>;
571			clocks = <&ahb_gates 22>, <&spi2_clk>;
572			clock-names = "ahb", "mod";
573			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
574			       <&dma SUN4I_DMA_DEDICATED 28>;
575			dma-names = "rx", "tx";
576			status = "disabled";
577			#address-cells = <1>;
578			#size-cells = <0>;
579		};
580
581		ahci: sata@01c18000 {
582			compatible = "allwinner,sun4i-a10-ahci";
583			reg = <0x01c18000 0x1000>;
584			interrupts = <56>;
585			clocks = <&pll6 0>, <&ahb_gates 25>;
586			status = "disabled";
587		};
588
589		ehci1: usb@01c1c000 {
590			compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
591			reg = <0x01c1c000 0x100>;
592			interrupts = <40>;
593			clocks = <&ahb_gates 3>;
594			phys = <&usbphy 2>;
595			phy-names = "usb";
596			status = "disabled";
597		};
598
599		ohci1: usb@01c1c400 {
600			compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
601			reg = <0x01c1c400 0x100>;
602			interrupts = <65>;
603			clocks = <&usb_clk 7>, <&ahb_gates 4>;
604			phys = <&usbphy 2>;
605			phy-names = "usb";
606			status = "disabled";
607		};
608
609		spi3: spi@01c1f000 {
610			compatible = "allwinner,sun4i-a10-spi";
611			reg = <0x01c1f000 0x1000>;
612			interrupts = <50>;
613			clocks = <&ahb_gates 23>, <&spi3_clk>;
614			clock-names = "ahb", "mod";
615			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
616			       <&dma SUN4I_DMA_DEDICATED 30>;
617			dma-names = "rx", "tx";
618			status = "disabled";
619			#address-cells = <1>;
620			#size-cells = <0>;
621		};
622
623		intc: interrupt-controller@01c20400 {
624			compatible = "allwinner,sun4i-a10-ic";
625			reg = <0x01c20400 0x400>;
626			interrupt-controller;
627			#interrupt-cells = <1>;
628		};
629
630		pio: pinctrl@01c20800 {
631			compatible = "allwinner,sun4i-a10-pinctrl";
632			reg = <0x01c20800 0x400>;
633			interrupts = <28>;
634			clocks = <&apb0_gates 5>;
635			gpio-controller;
636			interrupt-controller;
637			#interrupt-cells = <2>;
638			#size-cells = <0>;
639			#gpio-cells = <3>;
640
641			pwm0_pins_a: pwm0@0 {
642				allwinner,pins = "PB2";
643				allwinner,function = "pwm";
644				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
645				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
646			};
647
648			pwm1_pins_a: pwm1@0 {
649				allwinner,pins = "PI3";
650				allwinner,function = "pwm";
651				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
652				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
653			};
654
655			uart0_pins_a: uart0@0 {
656				allwinner,pins = "PB22", "PB23";
657				allwinner,function = "uart0";
658				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
659				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
660			};
661
662			uart0_pins_b: uart0@1 {
663				allwinner,pins = "PF2", "PF4";
664				allwinner,function = "uart0";
665				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
666				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
667			};
668
669			uart1_pins_a: uart1@0 {
670				allwinner,pins = "PA10", "PA11";
671				allwinner,function = "uart1";
672				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
673				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
674			};
675
676			i2c0_pins_a: i2c0@0 {
677				allwinner,pins = "PB0", "PB1";
678				allwinner,function = "i2c0";
679				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
680				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
681			};
682
683			i2c1_pins_a: i2c1@0 {
684				allwinner,pins = "PB18", "PB19";
685				allwinner,function = "i2c1";
686				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
687				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
688			};
689
690			i2c2_pins_a: i2c2@0 {
691				allwinner,pins = "PB20", "PB21";
692				allwinner,function = "i2c2";
693				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
694				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
695			};
696
697			emac_pins_a: emac0@0 {
698				allwinner,pins = "PA0", "PA1", "PA2",
699						"PA3", "PA4", "PA5", "PA6",
700						"PA7", "PA8", "PA9", "PA10",
701						"PA11", "PA12", "PA13", "PA14",
702						"PA15", "PA16";
703				allwinner,function = "emac";
704				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
705				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
706			};
707
708			mmc0_pins_a: mmc0@0 {
709				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
710				allwinner,function = "mmc0";
711				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
712				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
713			};
714
715			mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
716				allwinner,pins = "PH1";
717				allwinner,function = "gpio_in";
718				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
719				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
720			};
721
722			ir0_pins_a: ir0@0 {
723				allwinner,pins = "PB3","PB4";
724				allwinner,function = "ir0";
725				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
726				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
727			};
728
729			ir1_pins_a: ir1@0 {
730				allwinner,pins = "PB22","PB23";
731				allwinner,function = "ir1";
732				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
733				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
734			};
735
736			spi0_pins_a: spi0@0 {
737				allwinner,pins = "PI10", "PI11", "PI12", "PI13";
738				allwinner,function = "spi0";
739				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
740				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
741			};
742
743			spi1_pins_a: spi1@0 {
744				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
745				allwinner,function = "spi1";
746				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
747				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
748			};
749
750			spi2_pins_a: spi2@0 {
751				allwinner,pins = "PB14", "PB15", "PB16", "PB17";
752				allwinner,function = "spi2";
753				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
754				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
755			};
756
757			spi2_pins_b: spi2@1 {
758				allwinner,pins = "PC19", "PC20", "PC21", "PC22";
759				allwinner,function = "spi2";
760				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
761				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
762			};
763
764			ps20_pins_a: ps20@0 {
765				allwinner,pins = "PI20", "PI21";
766				allwinner,function = "ps2";
767				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
768				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
769			};
770
771			ps21_pins_a: ps21@0 {
772				allwinner,pins = "PH12", "PH13";
773				allwinner,function = "ps2";
774				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
775				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
776			};
777		};
778
779		timer@01c20c00 {
780			compatible = "allwinner,sun4i-a10-timer";
781			reg = <0x01c20c00 0x90>;
782			interrupts = <22>;
783			clocks = <&osc24M>;
784		};
785
786		wdt: watchdog@01c20c90 {
787			compatible = "allwinner,sun4i-a10-wdt";
788			reg = <0x01c20c90 0x10>;
789		};
790
791		rtc: rtc@01c20d00 {
792			compatible = "allwinner,sun4i-a10-rtc";
793			reg = <0x01c20d00 0x20>;
794			interrupts = <24>;
795		};
796
797		pwm: pwm@01c20e00 {
798			compatible = "allwinner,sun4i-a10-pwm";
799			reg = <0x01c20e00 0xc>;
800			clocks = <&osc24M>;
801			#pwm-cells = <3>;
802			status = "disabled";
803		};
804
805		ir0: ir@01c21800 {
806			compatible = "allwinner,sun4i-a10-ir";
807			clocks = <&apb0_gates 6>, <&ir0_clk>;
808			clock-names = "apb", "ir";
809			interrupts = <5>;
810			reg = <0x01c21800 0x40>;
811			status = "disabled";
812		};
813
814		ir1: ir@01c21c00 {
815			compatible = "allwinner,sun4i-a10-ir";
816			clocks = <&apb0_gates 7>, <&ir1_clk>;
817			clock-names = "apb", "ir";
818			interrupts = <6>;
819			reg = <0x01c21c00 0x40>;
820			status = "disabled";
821		};
822
823		lradc: lradc@01c22800 {
824			compatible = "allwinner,sun4i-a10-lradc-keys";
825			reg = <0x01c22800 0x100>;
826			interrupts = <31>;
827			status = "disabled";
828		};
829
830		sid: eeprom@01c23800 {
831			compatible = "allwinner,sun4i-a10-sid";
832			reg = <0x01c23800 0x10>;
833		};
834
835		rtp: rtp@01c25000 {
836			compatible = "allwinner,sun4i-a10-ts";
837			reg = <0x01c25000 0x100>;
838			interrupts = <29>;
839			#thermal-sensor-cells = <0>;
840		};
841
842		uart0: serial@01c28000 {
843			compatible = "snps,dw-apb-uart";
844			reg = <0x01c28000 0x400>;
845			interrupts = <1>;
846			reg-shift = <2>;
847			reg-io-width = <4>;
848			clocks = <&apb1_gates 16>;
849			status = "disabled";
850		};
851
852		uart1: serial@01c28400 {
853			compatible = "snps,dw-apb-uart";
854			reg = <0x01c28400 0x400>;
855			interrupts = <2>;
856			reg-shift = <2>;
857			reg-io-width = <4>;
858			clocks = <&apb1_gates 17>;
859			status = "disabled";
860		};
861
862		uart2: serial@01c28800 {
863			compatible = "snps,dw-apb-uart";
864			reg = <0x01c28800 0x400>;
865			interrupts = <3>;
866			reg-shift = <2>;
867			reg-io-width = <4>;
868			clocks = <&apb1_gates 18>;
869			status = "disabled";
870		};
871
872		uart3: serial@01c28c00 {
873			compatible = "snps,dw-apb-uart";
874			reg = <0x01c28c00 0x400>;
875			interrupts = <4>;
876			reg-shift = <2>;
877			reg-io-width = <4>;
878			clocks = <&apb1_gates 19>;
879			status = "disabled";
880		};
881
882		uart4: serial@01c29000 {
883			compatible = "snps,dw-apb-uart";
884			reg = <0x01c29000 0x400>;
885			interrupts = <17>;
886			reg-shift = <2>;
887			reg-io-width = <4>;
888			clocks = <&apb1_gates 20>;
889			status = "disabled";
890		};
891
892		uart5: serial@01c29400 {
893			compatible = "snps,dw-apb-uart";
894			reg = <0x01c29400 0x400>;
895			interrupts = <18>;
896			reg-shift = <2>;
897			reg-io-width = <4>;
898			clocks = <&apb1_gates 21>;
899			status = "disabled";
900		};
901
902		uart6: serial@01c29800 {
903			compatible = "snps,dw-apb-uart";
904			reg = <0x01c29800 0x400>;
905			interrupts = <19>;
906			reg-shift = <2>;
907			reg-io-width = <4>;
908			clocks = <&apb1_gates 22>;
909			status = "disabled";
910		};
911
912		uart7: serial@01c29c00 {
913			compatible = "snps,dw-apb-uart";
914			reg = <0x01c29c00 0x400>;
915			interrupts = <20>;
916			reg-shift = <2>;
917			reg-io-width = <4>;
918			clocks = <&apb1_gates 23>;
919			status = "disabled";
920		};
921
922		i2c0: i2c@01c2ac00 {
923			compatible = "allwinner,sun4i-a10-i2c";
924			reg = <0x01c2ac00 0x400>;
925			interrupts = <7>;
926			clocks = <&apb1_gates 0>;
927			status = "disabled";
928			#address-cells = <1>;
929			#size-cells = <0>;
930		};
931
932		i2c1: i2c@01c2b000 {
933			compatible = "allwinner,sun4i-a10-i2c";
934			reg = <0x01c2b000 0x400>;
935			interrupts = <8>;
936			clocks = <&apb1_gates 1>;
937			status = "disabled";
938			#address-cells = <1>;
939			#size-cells = <0>;
940		};
941
942		i2c2: i2c@01c2b400 {
943			compatible = "allwinner,sun4i-a10-i2c";
944			reg = <0x01c2b400 0x400>;
945			interrupts = <9>;
946			clocks = <&apb1_gates 2>;
947			status = "disabled";
948			#address-cells = <1>;
949			#size-cells = <0>;
950		};
951
952		ps20: ps2@01c2a000 {
953			compatible = "allwinner,sun4i-a10-ps2";
954			reg = <0x01c2a000 0x400>;
955			interrupts = <62>;
956			clocks = <&apb1_gates 6>;
957			status = "disabled";
958		};
959
960		ps21: ps2@01c2a400 {
961			compatible = "allwinner,sun4i-a10-ps2";
962			reg = <0x01c2a400 0x400>;
963			interrupts = <63>;
964			clocks = <&apb1_gates 7>;
965			status = "disabled";
966		};
967	};
968};
969