1/* 2 * Device Tree Source for the r8a7790 SoC 3 * 4 * Copyright (C) 2015 Renesas Electronics Corporation 5 * Copyright (C) 2013-2014 Renesas Solutions Corp. 6 * Copyright (C) 2014 Cogent Embedded Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13#include <dt-bindings/clock/r8a7790-clock.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16 17/ { 18 compatible = "renesas,r8a7790"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &iic0; 29 i2c5 = &iic1; 30 i2c6 = &iic2; 31 i2c7 = &iic3; 32 spi0 = &qspi; 33 spi1 = &msiof0; 34 spi2 = &msiof1; 35 spi3 = &msiof2; 36 spi4 = &msiof3; 37 vin0 = &vin0; 38 vin1 = &vin1; 39 vin2 = &vin2; 40 vin3 = &vin3; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a15"; 50 reg = <0>; 51 clock-frequency = <1300000000>; 52 voltage-tolerance = <1>; /* 1% */ 53 clocks = <&cpg_clocks R8A7790_CLK_Z>; 54 clock-latency = <300000>; /* 300 us */ 55 56 /* kHz - uV - OPPs unknown yet */ 57 operating-points = <1400000 1000000>, 58 <1225000 1000000>, 59 <1050000 1000000>, 60 < 875000 1000000>, 61 < 700000 1000000>, 62 < 350000 1000000>; 63 }; 64 65 cpu1: cpu@1 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a15"; 68 reg = <1>; 69 clock-frequency = <1300000000>; 70 }; 71 72 cpu2: cpu@2 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a15"; 75 reg = <2>; 76 clock-frequency = <1300000000>; 77 }; 78 79 cpu3: cpu@3 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a15"; 82 reg = <3>; 83 clock-frequency = <1300000000>; 84 }; 85 86 cpu4: cpu@4 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a7"; 89 reg = <0x100>; 90 clock-frequency = <780000000>; 91 }; 92 93 cpu5: cpu@5 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a7"; 96 reg = <0x101>; 97 clock-frequency = <780000000>; 98 }; 99 100 cpu6: cpu@6 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a7"; 103 reg = <0x102>; 104 clock-frequency = <780000000>; 105 }; 106 107 cpu7: cpu@7 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a7"; 110 reg = <0x103>; 111 clock-frequency = <780000000>; 112 }; 113 }; 114 115 gic: interrupt-controller@f1001000 { 116 compatible = "arm,cortex-a15-gic"; 117 #interrupt-cells = <3>; 118 #address-cells = <0>; 119 interrupt-controller; 120 reg = <0 0xf1001000 0 0x1000>, 121 <0 0xf1002000 0 0x1000>, 122 <0 0xf1004000 0 0x2000>, 123 <0 0xf1006000 0 0x2000>; 124 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 125 }; 126 127 gpio0: gpio@e6050000 { 128 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 129 reg = <0 0xe6050000 0 0x50>; 130 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 131 #gpio-cells = <2>; 132 gpio-controller; 133 gpio-ranges = <&pfc 0 0 32>; 134 #interrupt-cells = <2>; 135 interrupt-controller; 136 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; 137 }; 138 139 gpio1: gpio@e6051000 { 140 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 141 reg = <0 0xe6051000 0 0x50>; 142 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 143 #gpio-cells = <2>; 144 gpio-controller; 145 gpio-ranges = <&pfc 0 32 32>; 146 #interrupt-cells = <2>; 147 interrupt-controller; 148 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; 149 }; 150 151 gpio2: gpio@e6052000 { 152 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 153 reg = <0 0xe6052000 0 0x50>; 154 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 155 #gpio-cells = <2>; 156 gpio-controller; 157 gpio-ranges = <&pfc 0 64 32>; 158 #interrupt-cells = <2>; 159 interrupt-controller; 160 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; 161 }; 162 163 gpio3: gpio@e6053000 { 164 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 165 reg = <0 0xe6053000 0 0x50>; 166 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 96 32>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; 173 }; 174 175 gpio4: gpio@e6054000 { 176 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 177 reg = <0 0xe6054000 0 0x50>; 178 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 179 #gpio-cells = <2>; 180 gpio-controller; 181 gpio-ranges = <&pfc 0 128 32>; 182 #interrupt-cells = <2>; 183 interrupt-controller; 184 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; 185 }; 186 187 gpio5: gpio@e6055000 { 188 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 189 reg = <0 0xe6055000 0 0x50>; 190 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 191 #gpio-cells = <2>; 192 gpio-controller; 193 gpio-ranges = <&pfc 0 160 32>; 194 #interrupt-cells = <2>; 195 interrupt-controller; 196 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; 197 }; 198 199 thermal@e61f0000 { 200 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; 201 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 202 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; 204 }; 205 206 timer { 207 compatible = "arm,armv7-timer"; 208 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 209 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 210 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 211 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 212 }; 213 214 cmt0: timer@ffca0000 { 215 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; 216 reg = <0 0xffca0000 0 0x1004>; 217 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, 218 <0 143 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&mstp1_clks R8A7790_CLK_CMT0>; 220 clock-names = "fck"; 221 222 renesas,channels-mask = <0x60>; 223 224 status = "disabled"; 225 }; 226 227 cmt1: timer@e6130000 { 228 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; 229 reg = <0 0xe6130000 0 0x1004>; 230 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, 231 <0 121 IRQ_TYPE_LEVEL_HIGH>, 232 <0 122 IRQ_TYPE_LEVEL_HIGH>, 233 <0 123 IRQ_TYPE_LEVEL_HIGH>, 234 <0 124 IRQ_TYPE_LEVEL_HIGH>, 235 <0 125 IRQ_TYPE_LEVEL_HIGH>, 236 <0 126 IRQ_TYPE_LEVEL_HIGH>, 237 <0 127 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&mstp3_clks R8A7790_CLK_CMT1>; 239 clock-names = "fck"; 240 241 renesas,channels-mask = <0xff>; 242 243 status = "disabled"; 244 }; 245 246 irqc0: interrupt-controller@e61c0000 { 247 compatible = "renesas,irqc-r8a7790", "renesas,irqc"; 248 #interrupt-cells = <2>; 249 interrupt-controller; 250 reg = <0 0xe61c0000 0 0x200>; 251 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 252 <0 1 IRQ_TYPE_LEVEL_HIGH>, 253 <0 2 IRQ_TYPE_LEVEL_HIGH>, 254 <0 3 IRQ_TYPE_LEVEL_HIGH>; 255 }; 256 257 dmac0: dma-controller@e6700000 { 258 compatible = "renesas,rcar-dmac"; 259 reg = <0 0xe6700000 0 0x20000>; 260 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH 261 0 200 IRQ_TYPE_LEVEL_HIGH 262 0 201 IRQ_TYPE_LEVEL_HIGH 263 0 202 IRQ_TYPE_LEVEL_HIGH 264 0 203 IRQ_TYPE_LEVEL_HIGH 265 0 204 IRQ_TYPE_LEVEL_HIGH 266 0 205 IRQ_TYPE_LEVEL_HIGH 267 0 206 IRQ_TYPE_LEVEL_HIGH 268 0 207 IRQ_TYPE_LEVEL_HIGH 269 0 208 IRQ_TYPE_LEVEL_HIGH 270 0 209 IRQ_TYPE_LEVEL_HIGH 271 0 210 IRQ_TYPE_LEVEL_HIGH 272 0 211 IRQ_TYPE_LEVEL_HIGH 273 0 212 IRQ_TYPE_LEVEL_HIGH 274 0 213 IRQ_TYPE_LEVEL_HIGH 275 0 214 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "error", 277 "ch0", "ch1", "ch2", "ch3", 278 "ch4", "ch5", "ch6", "ch7", 279 "ch8", "ch9", "ch10", "ch11", 280 "ch12", "ch13", "ch14"; 281 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; 282 clock-names = "fck"; 283 #dma-cells = <1>; 284 dma-channels = <15>; 285 }; 286 287 dmac1: dma-controller@e6720000 { 288 compatible = "renesas,rcar-dmac"; 289 reg = <0 0xe6720000 0 0x20000>; 290 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 291 0 216 IRQ_TYPE_LEVEL_HIGH 292 0 217 IRQ_TYPE_LEVEL_HIGH 293 0 218 IRQ_TYPE_LEVEL_HIGH 294 0 219 IRQ_TYPE_LEVEL_HIGH 295 0 308 IRQ_TYPE_LEVEL_HIGH 296 0 309 IRQ_TYPE_LEVEL_HIGH 297 0 310 IRQ_TYPE_LEVEL_HIGH 298 0 311 IRQ_TYPE_LEVEL_HIGH 299 0 312 IRQ_TYPE_LEVEL_HIGH 300 0 313 IRQ_TYPE_LEVEL_HIGH 301 0 314 IRQ_TYPE_LEVEL_HIGH 302 0 315 IRQ_TYPE_LEVEL_HIGH 303 0 316 IRQ_TYPE_LEVEL_HIGH 304 0 317 IRQ_TYPE_LEVEL_HIGH 305 0 318 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-names = "error", 307 "ch0", "ch1", "ch2", "ch3", 308 "ch4", "ch5", "ch6", "ch7", 309 "ch8", "ch9", "ch10", "ch11", 310 "ch12", "ch13", "ch14"; 311 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; 312 clock-names = "fck"; 313 #dma-cells = <1>; 314 dma-channels = <15>; 315 }; 316 317 audma0: dma-controller@ec700000 { 318 compatible = "renesas,rcar-dmac"; 319 reg = <0 0xec700000 0 0x10000>; 320 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH 321 0 320 IRQ_TYPE_LEVEL_HIGH 322 0 321 IRQ_TYPE_LEVEL_HIGH 323 0 322 IRQ_TYPE_LEVEL_HIGH 324 0 323 IRQ_TYPE_LEVEL_HIGH 325 0 324 IRQ_TYPE_LEVEL_HIGH 326 0 325 IRQ_TYPE_LEVEL_HIGH 327 0 326 IRQ_TYPE_LEVEL_HIGH 328 0 327 IRQ_TYPE_LEVEL_HIGH 329 0 328 IRQ_TYPE_LEVEL_HIGH 330 0 329 IRQ_TYPE_LEVEL_HIGH 331 0 330 IRQ_TYPE_LEVEL_HIGH 332 0 331 IRQ_TYPE_LEVEL_HIGH 333 0 332 IRQ_TYPE_LEVEL_HIGH>; 334 interrupt-names = "error", 335 "ch0", "ch1", "ch2", "ch3", 336 "ch4", "ch5", "ch6", "ch7", 337 "ch8", "ch9", "ch10", "ch11", 338 "ch12"; 339 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; 340 clock-names = "fck"; 341 #dma-cells = <1>; 342 dma-channels = <13>; 343 }; 344 345 audma1: dma-controller@ec720000 { 346 compatible = "renesas,rcar-dmac"; 347 reg = <0 0xec720000 0 0x10000>; 348 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH 349 0 333 IRQ_TYPE_LEVEL_HIGH 350 0 334 IRQ_TYPE_LEVEL_HIGH 351 0 335 IRQ_TYPE_LEVEL_HIGH 352 0 336 IRQ_TYPE_LEVEL_HIGH 353 0 337 IRQ_TYPE_LEVEL_HIGH 354 0 338 IRQ_TYPE_LEVEL_HIGH 355 0 339 IRQ_TYPE_LEVEL_HIGH 356 0 340 IRQ_TYPE_LEVEL_HIGH 357 0 341 IRQ_TYPE_LEVEL_HIGH 358 0 342 IRQ_TYPE_LEVEL_HIGH 359 0 343 IRQ_TYPE_LEVEL_HIGH 360 0 344 IRQ_TYPE_LEVEL_HIGH 361 0 345 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-names = "error", 363 "ch0", "ch1", "ch2", "ch3", 364 "ch4", "ch5", "ch6", "ch7", 365 "ch8", "ch9", "ch10", "ch11", 366 "ch12"; 367 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; 368 clock-names = "fck"; 369 #dma-cells = <1>; 370 dma-channels = <13>; 371 }; 372 373 i2c0: i2c@e6508000 { 374 #address-cells = <1>; 375 #size-cells = <0>; 376 compatible = "renesas,i2c-r8a7790"; 377 reg = <0 0xe6508000 0 0x40>; 378 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&mstp9_clks R8A7790_CLK_I2C0>; 380 status = "disabled"; 381 }; 382 383 i2c1: i2c@e6518000 { 384 #address-cells = <1>; 385 #size-cells = <0>; 386 compatible = "renesas,i2c-r8a7790"; 387 reg = <0 0xe6518000 0 0x40>; 388 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&mstp9_clks R8A7790_CLK_I2C1>; 390 status = "disabled"; 391 }; 392 393 i2c2: i2c@e6530000 { 394 #address-cells = <1>; 395 #size-cells = <0>; 396 compatible = "renesas,i2c-r8a7790"; 397 reg = <0 0xe6530000 0 0x40>; 398 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&mstp9_clks R8A7790_CLK_I2C2>; 400 status = "disabled"; 401 }; 402 403 i2c3: i2c@e6540000 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 compatible = "renesas,i2c-r8a7790"; 407 reg = <0 0xe6540000 0 0x40>; 408 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&mstp9_clks R8A7790_CLK_I2C3>; 410 status = "disabled"; 411 }; 412 413 iic0: i2c@e6500000 { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; 417 reg = <0 0xe6500000 0 0x425>; 418 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&mstp3_clks R8A7790_CLK_IIC0>; 420 dmas = <&dmac0 0x61>, <&dmac0 0x62>; 421 dma-names = "tx", "rx"; 422 status = "disabled"; 423 }; 424 425 iic1: i2c@e6510000 { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; 429 reg = <0 0xe6510000 0 0x425>; 430 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&mstp3_clks R8A7790_CLK_IIC1>; 432 dmas = <&dmac0 0x65>, <&dmac0 0x66>; 433 dma-names = "tx", "rx"; 434 status = "disabled"; 435 }; 436 437 iic2: i2c@e6520000 { 438 #address-cells = <1>; 439 #size-cells = <0>; 440 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; 441 reg = <0 0xe6520000 0 0x425>; 442 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&mstp3_clks R8A7790_CLK_IIC2>; 444 dmas = <&dmac0 0x69>, <&dmac0 0x6a>; 445 dma-names = "tx", "rx"; 446 status = "disabled"; 447 }; 448 449 iic3: i2c@e60b0000 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; 453 reg = <0 0xe60b0000 0 0x425>; 454 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; 456 dmas = <&dmac0 0x77>, <&dmac0 0x78>; 457 dma-names = "tx", "rx"; 458 status = "disabled"; 459 }; 460 461 mmcif0: mmc@ee200000 { 462 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; 463 reg = <0 0xee200000 0 0x80>; 464 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; 466 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; 467 dma-names = "tx", "rx"; 468 reg-io-width = <4>; 469 status = "disabled"; 470 }; 471 472 mmcif1: mmc@ee220000 { 473 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; 474 reg = <0 0xee220000 0 0x80>; 475 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; 477 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; 478 dma-names = "tx", "rx"; 479 reg-io-width = <4>; 480 status = "disabled"; 481 }; 482 483 pfc: pfc@e6060000 { 484 compatible = "renesas,pfc-r8a7790"; 485 reg = <0 0xe6060000 0 0x250>; 486 }; 487 488 sdhi0: sd@ee100000 { 489 compatible = "renesas,sdhi-r8a7790"; 490 reg = <0 0xee100000 0 0x328>; 491 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; 493 dmas = <&dmac1 0xcd>, <&dmac1 0xce>; 494 dma-names = "tx", "rx"; 495 status = "disabled"; 496 }; 497 498 sdhi1: sd@ee120000 { 499 compatible = "renesas,sdhi-r8a7790"; 500 reg = <0 0xee120000 0 0x328>; 501 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; 503 dmas = <&dmac1 0xc9>, <&dmac1 0xca>; 504 dma-names = "tx", "rx"; 505 status = "disabled"; 506 }; 507 508 sdhi2: sd@ee140000 { 509 compatible = "renesas,sdhi-r8a7790"; 510 reg = <0 0xee140000 0 0x100>; 511 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; 513 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; 514 dma-names = "tx", "rx"; 515 status = "disabled"; 516 }; 517 518 sdhi3: sd@ee160000 { 519 compatible = "renesas,sdhi-r8a7790"; 520 reg = <0 0xee160000 0 0x100>; 521 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; 523 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; 524 dma-names = "tx", "rx"; 525 status = "disabled"; 526 }; 527 528 scifa0: serial@e6c40000 { 529 compatible = "renesas,scifa-r8a7790", "renesas,scifa"; 530 reg = <0 0xe6c40000 0 64>; 531 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; 533 clock-names = "sci_ick"; 534 status = "disabled"; 535 }; 536 537 scifa1: serial@e6c50000 { 538 compatible = "renesas,scifa-r8a7790", "renesas,scifa"; 539 reg = <0 0xe6c50000 0 64>; 540 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; 542 clock-names = "sci_ick"; 543 status = "disabled"; 544 }; 545 546 scifa2: serial@e6c60000 { 547 compatible = "renesas,scifa-r8a7790", "renesas,scifa"; 548 reg = <0 0xe6c60000 0 64>; 549 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; 551 clock-names = "sci_ick"; 552 status = "disabled"; 553 }; 554 555 scifb0: serial@e6c20000 { 556 compatible = "renesas,scifb-r8a7790", "renesas,scifb"; 557 reg = <0 0xe6c20000 0 64>; 558 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; 560 clock-names = "sci_ick"; 561 status = "disabled"; 562 }; 563 564 scifb1: serial@e6c30000 { 565 compatible = "renesas,scifb-r8a7790", "renesas,scifb"; 566 reg = <0 0xe6c30000 0 64>; 567 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; 569 clock-names = "sci_ick"; 570 status = "disabled"; 571 }; 572 573 scifb2: serial@e6ce0000 { 574 compatible = "renesas,scifb-r8a7790", "renesas,scifb"; 575 reg = <0 0xe6ce0000 0 64>; 576 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; 578 clock-names = "sci_ick"; 579 status = "disabled"; 580 }; 581 582 scif0: serial@e6e60000 { 583 compatible = "renesas,scif-r8a7790", "renesas,scif"; 584 reg = <0 0xe6e60000 0 64>; 585 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; 587 clock-names = "sci_ick"; 588 status = "disabled"; 589 }; 590 591 scif1: serial@e6e68000 { 592 compatible = "renesas,scif-r8a7790", "renesas,scif"; 593 reg = <0 0xe6e68000 0 64>; 594 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; 596 clock-names = "sci_ick"; 597 status = "disabled"; 598 }; 599 600 hscif0: serial@e62c0000 { 601 compatible = "renesas,hscif-r8a7790", "renesas,hscif"; 602 reg = <0 0xe62c0000 0 96>; 603 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; 605 clock-names = "sci_ick"; 606 status = "disabled"; 607 }; 608 609 hscif1: serial@e62c8000 { 610 compatible = "renesas,hscif-r8a7790", "renesas,hscif"; 611 reg = <0 0xe62c8000 0 96>; 612 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; 614 clock-names = "sci_ick"; 615 status = "disabled"; 616 }; 617 618 ether: ethernet@ee700000 { 619 compatible = "renesas,ether-r8a7790"; 620 reg = <0 0xee700000 0 0x400>; 621 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&mstp8_clks R8A7790_CLK_ETHER>; 623 phy-mode = "rmii"; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 status = "disabled"; 627 }; 628 629 sata0: sata@ee300000 { 630 compatible = "renesas,sata-r8a7790"; 631 reg = <0 0xee300000 0 0x2000>; 632 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&mstp8_clks R8A7790_CLK_SATA0>; 634 status = "disabled"; 635 }; 636 637 sata1: sata@ee500000 { 638 compatible = "renesas,sata-r8a7790"; 639 reg = <0 0xee500000 0 0x2000>; 640 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&mstp8_clks R8A7790_CLK_SATA1>; 642 status = "disabled"; 643 }; 644 645 hsusb: usb@e6590000 { 646 compatible = "renesas,usbhs-r8a7790"; 647 reg = <0 0xe6590000 0 0x100>; 648 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; 650 renesas,buswait = <4>; 651 phys = <&usb0 1>; 652 phy-names = "usb"; 653 status = "disabled"; 654 }; 655 656 usbphy: usb-phy@e6590100 { 657 compatible = "renesas,usb-phy-r8a7790"; 658 reg = <0 0xe6590100 0 0x100>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; 662 clock-names = "usbhs"; 663 status = "disabled"; 664 665 usb0: usb-channel@0 { 666 reg = <0>; 667 #phy-cells = <1>; 668 }; 669 usb2: usb-channel@2 { 670 reg = <2>; 671 #phy-cells = <1>; 672 }; 673 }; 674 675 vin0: video@e6ef0000 { 676 compatible = "renesas,vin-r8a7790"; 677 clocks = <&mstp8_clks R8A7790_CLK_VIN0>; 678 reg = <0 0xe6ef0000 0 0x1000>; 679 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; 680 status = "disabled"; 681 }; 682 683 vin1: video@e6ef1000 { 684 compatible = "renesas,vin-r8a7790"; 685 clocks = <&mstp8_clks R8A7790_CLK_VIN1>; 686 reg = <0 0xe6ef1000 0 0x1000>; 687 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; 688 status = "disabled"; 689 }; 690 691 vin2: video@e6ef2000 { 692 compatible = "renesas,vin-r8a7790"; 693 clocks = <&mstp8_clks R8A7790_CLK_VIN2>; 694 reg = <0 0xe6ef2000 0 0x1000>; 695 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; 696 status = "disabled"; 697 }; 698 699 vin3: video@e6ef3000 { 700 compatible = "renesas,vin-r8a7790"; 701 clocks = <&mstp8_clks R8A7790_CLK_VIN3>; 702 reg = <0 0xe6ef3000 0 0x1000>; 703 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>; 704 status = "disabled"; 705 }; 706 707 vsp1@fe920000 { 708 compatible = "renesas,vsp1"; 709 reg = <0 0xfe920000 0 0x8000>; 710 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; 712 713 renesas,has-sru; 714 renesas,#rpf = <5>; 715 renesas,#uds = <1>; 716 renesas,#wpf = <4>; 717 }; 718 719 vsp1@fe928000 { 720 compatible = "renesas,vsp1"; 721 reg = <0 0xfe928000 0 0x8000>; 722 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; 724 725 renesas,has-lut; 726 renesas,has-sru; 727 renesas,#rpf = <5>; 728 renesas,#uds = <3>; 729 renesas,#wpf = <4>; 730 }; 731 732 vsp1@fe930000 { 733 compatible = "renesas,vsp1"; 734 reg = <0 0xfe930000 0 0x8000>; 735 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; 737 738 renesas,has-lif; 739 renesas,has-lut; 740 renesas,#rpf = <4>; 741 renesas,#uds = <1>; 742 renesas,#wpf = <4>; 743 }; 744 745 vsp1@fe938000 { 746 compatible = "renesas,vsp1"; 747 reg = <0 0xfe938000 0 0x8000>; 748 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; 750 751 renesas,has-lif; 752 renesas,has-lut; 753 renesas,#rpf = <4>; 754 renesas,#uds = <1>; 755 renesas,#wpf = <4>; 756 }; 757 758 du: display@feb00000 { 759 compatible = "renesas,du-r8a7790"; 760 reg = <0 0xfeb00000 0 0x70000>, 761 <0 0xfeb90000 0 0x1c>, 762 <0 0xfeb94000 0 0x1c>; 763 reg-names = "du", "lvds.0", "lvds.1"; 764 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, 765 <0 268 IRQ_TYPE_LEVEL_HIGH>, 766 <0 269 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&mstp7_clks R8A7790_CLK_DU0>, 768 <&mstp7_clks R8A7790_CLK_DU1>, 769 <&mstp7_clks R8A7790_CLK_DU2>, 770 <&mstp7_clks R8A7790_CLK_LVDS0>, 771 <&mstp7_clks R8A7790_CLK_LVDS1>; 772 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; 773 status = "disabled"; 774 775 ports { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 779 port@0 { 780 reg = <0>; 781 du_out_rgb: endpoint { 782 }; 783 }; 784 port@1 { 785 reg = <1>; 786 du_out_lvds0: endpoint { 787 }; 788 }; 789 port@2 { 790 reg = <2>; 791 du_out_lvds1: endpoint { 792 }; 793 }; 794 }; 795 }; 796 797 can0: can@e6e80000 { 798 compatible = "renesas,can-r8a7790"; 799 reg = <0 0xe6e80000 0 0x1000>; 800 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, 802 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; 803 clock-names = "clkp1", "clkp2", "can_clk"; 804 status = "disabled"; 805 }; 806 807 can1: can@e6e88000 { 808 compatible = "renesas,can-r8a7790"; 809 reg = <0 0xe6e88000 0 0x1000>; 810 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, 812 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; 813 clock-names = "clkp1", "clkp2", "can_clk"; 814 status = "disabled"; 815 }; 816 817 clocks { 818 #address-cells = <2>; 819 #size-cells = <2>; 820 ranges; 821 822 /* External root clock */ 823 extal_clk: extal_clk { 824 compatible = "fixed-clock"; 825 #clock-cells = <0>; 826 /* This value must be overriden by the board. */ 827 clock-frequency = <0>; 828 clock-output-names = "extal"; 829 }; 830 831 /* External PCIe clock - can be overridden by the board */ 832 pcie_bus_clk: pcie_bus_clk { 833 compatible = "fixed-clock"; 834 #clock-cells = <0>; 835 clock-frequency = <100000000>; 836 clock-output-names = "pcie_bus"; 837 status = "disabled"; 838 }; 839 840 /* 841 * The external audio clocks are configured as 0 Hz fixed frequency clocks by 842 * default. Boards that provide audio clocks should override them. 843 */ 844 audio_clk_a: audio_clk_a { 845 compatible = "fixed-clock"; 846 #clock-cells = <0>; 847 clock-frequency = <0>; 848 clock-output-names = "audio_clk_a"; 849 }; 850 audio_clk_b: audio_clk_b { 851 compatible = "fixed-clock"; 852 #clock-cells = <0>; 853 clock-frequency = <0>; 854 clock-output-names = "audio_clk_b"; 855 }; 856 audio_clk_c: audio_clk_c { 857 compatible = "fixed-clock"; 858 #clock-cells = <0>; 859 clock-frequency = <0>; 860 clock-output-names = "audio_clk_c"; 861 }; 862 863 /* External USB clock - can be overridden by the board */ 864 usb_extal_clk: usb_extal_clk { 865 compatible = "fixed-clock"; 866 #clock-cells = <0>; 867 clock-frequency = <48000000>; 868 clock-output-names = "usb_extal"; 869 }; 870 871 /* External CAN clock */ 872 can_clk: can_clk { 873 compatible = "fixed-clock"; 874 #clock-cells = <0>; 875 /* This value must be overridden by the board. */ 876 clock-frequency = <0>; 877 clock-output-names = "can_clk"; 878 status = "disabled"; 879 }; 880 881 /* Special CPG clocks */ 882 cpg_clocks: cpg_clocks@e6150000 { 883 compatible = "renesas,r8a7790-cpg-clocks", 884 "renesas,rcar-gen2-cpg-clocks"; 885 reg = <0 0xe6150000 0 0x1000>; 886 clocks = <&extal_clk &usb_extal_clk>; 887 #clock-cells = <1>; 888 clock-output-names = "main", "pll0", "pll1", "pll3", 889 "lb", "qspi", "sdh", "sd0", "sd1", 890 "z", "rcan", "adsp"; 891 }; 892 893 /* Variable factor clocks */ 894 sd2_clk: sd2_clk@e6150078 { 895 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 896 reg = <0 0xe6150078 0 4>; 897 clocks = <&pll1_div2_clk>; 898 #clock-cells = <0>; 899 clock-output-names = "sd2"; 900 }; 901 sd3_clk: sd3_clk@e615026c { 902 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 903 reg = <0 0xe615026c 0 4>; 904 clocks = <&pll1_div2_clk>; 905 #clock-cells = <0>; 906 clock-output-names = "sd3"; 907 }; 908 mmc0_clk: mmc0_clk@e6150240 { 909 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 910 reg = <0 0xe6150240 0 4>; 911 clocks = <&pll1_div2_clk>; 912 #clock-cells = <0>; 913 clock-output-names = "mmc0"; 914 }; 915 mmc1_clk: mmc1_clk@e6150244 { 916 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 917 reg = <0 0xe6150244 0 4>; 918 clocks = <&pll1_div2_clk>; 919 #clock-cells = <0>; 920 clock-output-names = "mmc1"; 921 }; 922 ssp_clk: ssp_clk@e6150248 { 923 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 924 reg = <0 0xe6150248 0 4>; 925 clocks = <&pll1_div2_clk>; 926 #clock-cells = <0>; 927 clock-output-names = "ssp"; 928 }; 929 ssprs_clk: ssprs_clk@e615024c { 930 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 931 reg = <0 0xe615024c 0 4>; 932 clocks = <&pll1_div2_clk>; 933 #clock-cells = <0>; 934 clock-output-names = "ssprs"; 935 }; 936 937 /* Fixed factor clocks */ 938 pll1_div2_clk: pll1_div2_clk { 939 compatible = "fixed-factor-clock"; 940 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 941 #clock-cells = <0>; 942 clock-div = <2>; 943 clock-mult = <1>; 944 clock-output-names = "pll1_div2"; 945 }; 946 z2_clk: z2_clk { 947 compatible = "fixed-factor-clock"; 948 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 949 #clock-cells = <0>; 950 clock-div = <2>; 951 clock-mult = <1>; 952 clock-output-names = "z2"; 953 }; 954 zg_clk: zg_clk { 955 compatible = "fixed-factor-clock"; 956 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 957 #clock-cells = <0>; 958 clock-div = <3>; 959 clock-mult = <1>; 960 clock-output-names = "zg"; 961 }; 962 zx_clk: zx_clk { 963 compatible = "fixed-factor-clock"; 964 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 965 #clock-cells = <0>; 966 clock-div = <3>; 967 clock-mult = <1>; 968 clock-output-names = "zx"; 969 }; 970 zs_clk: zs_clk { 971 compatible = "fixed-factor-clock"; 972 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 973 #clock-cells = <0>; 974 clock-div = <6>; 975 clock-mult = <1>; 976 clock-output-names = "zs"; 977 }; 978 hp_clk: hp_clk { 979 compatible = "fixed-factor-clock"; 980 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 981 #clock-cells = <0>; 982 clock-div = <12>; 983 clock-mult = <1>; 984 clock-output-names = "hp"; 985 }; 986 i_clk: i_clk { 987 compatible = "fixed-factor-clock"; 988 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 989 #clock-cells = <0>; 990 clock-div = <2>; 991 clock-mult = <1>; 992 clock-output-names = "i"; 993 }; 994 b_clk: b_clk { 995 compatible = "fixed-factor-clock"; 996 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 997 #clock-cells = <0>; 998 clock-div = <12>; 999 clock-mult = <1>; 1000 clock-output-names = "b"; 1001 }; 1002 p_clk: p_clk { 1003 compatible = "fixed-factor-clock"; 1004 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 1005 #clock-cells = <0>; 1006 clock-div = <24>; 1007 clock-mult = <1>; 1008 clock-output-names = "p"; 1009 }; 1010 cl_clk: cl_clk { 1011 compatible = "fixed-factor-clock"; 1012 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 1013 #clock-cells = <0>; 1014 clock-div = <48>; 1015 clock-mult = <1>; 1016 clock-output-names = "cl"; 1017 }; 1018 m2_clk: m2_clk { 1019 compatible = "fixed-factor-clock"; 1020 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 1021 #clock-cells = <0>; 1022 clock-div = <8>; 1023 clock-mult = <1>; 1024 clock-output-names = "m2"; 1025 }; 1026 imp_clk: imp_clk { 1027 compatible = "fixed-factor-clock"; 1028 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 1029 #clock-cells = <0>; 1030 clock-div = <4>; 1031 clock-mult = <1>; 1032 clock-output-names = "imp"; 1033 }; 1034 rclk_clk: rclk_clk { 1035 compatible = "fixed-factor-clock"; 1036 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 1037 #clock-cells = <0>; 1038 clock-div = <(48 * 1024)>; 1039 clock-mult = <1>; 1040 clock-output-names = "rclk"; 1041 }; 1042 oscclk_clk: oscclk_clk { 1043 compatible = "fixed-factor-clock"; 1044 clocks = <&cpg_clocks R8A7790_CLK_PLL1>; 1045 #clock-cells = <0>; 1046 clock-div = <(12 * 1024)>; 1047 clock-mult = <1>; 1048 clock-output-names = "oscclk"; 1049 }; 1050 zb3_clk: zb3_clk { 1051 compatible = "fixed-factor-clock"; 1052 clocks = <&cpg_clocks R8A7790_CLK_PLL3>; 1053 #clock-cells = <0>; 1054 clock-div = <4>; 1055 clock-mult = <1>; 1056 clock-output-names = "zb3"; 1057 }; 1058 zb3d2_clk: zb3d2_clk { 1059 compatible = "fixed-factor-clock"; 1060 clocks = <&cpg_clocks R8A7790_CLK_PLL3>; 1061 #clock-cells = <0>; 1062 clock-div = <8>; 1063 clock-mult = <1>; 1064 clock-output-names = "zb3d2"; 1065 }; 1066 ddr_clk: ddr_clk { 1067 compatible = "fixed-factor-clock"; 1068 clocks = <&cpg_clocks R8A7790_CLK_PLL3>; 1069 #clock-cells = <0>; 1070 clock-div = <8>; 1071 clock-mult = <1>; 1072 clock-output-names = "ddr"; 1073 }; 1074 mp_clk: mp_clk { 1075 compatible = "fixed-factor-clock"; 1076 clocks = <&pll1_div2_clk>; 1077 #clock-cells = <0>; 1078 clock-div = <15>; 1079 clock-mult = <1>; 1080 clock-output-names = "mp"; 1081 }; 1082 cp_clk: cp_clk { 1083 compatible = "fixed-factor-clock"; 1084 clocks = <&extal_clk>; 1085 #clock-cells = <0>; 1086 clock-div = <2>; 1087 clock-mult = <1>; 1088 clock-output-names = "cp"; 1089 }; 1090 1091 /* Gate clocks */ 1092 mstp0_clks: mstp0_clks@e6150130 { 1093 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1094 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1095 clocks = <&mp_clk>; 1096 #clock-cells = <1>; 1097 clock-indices = <R8A7790_CLK_MSIOF0>; 1098 clock-output-names = "msiof0"; 1099 }; 1100 mstp1_clks: mstp1_clks@e6150134 { 1101 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1102 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1103 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, 1104 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, 1105 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 1106 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 1107 #clock-cells = <1>; 1108 clock-indices = < 1109 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 1110 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 1111 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC 1112 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 1113 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 1114 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 1115 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S 1116 >; 1117 clock-output-names = 1118 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", 1119 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", 1120 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", 1121 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; 1122 }; 1123 mstp2_clks: mstp2_clks@e6150138 { 1124 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1125 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 1126 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 1127 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, 1128 <&zs_clk>; 1129 #clock-cells = <1>; 1130 clock-indices = < 1131 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 1132 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 1133 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 1134 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 1135 >; 1136 clock-output-names = 1137 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 1138 "scifb1", "msiof1", "msiof3", "scifb2", 1139 "sys-dmac1", "sys-dmac0"; 1140 }; 1141 mstp3_clks: mstp3_clks@e615013c { 1142 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1143 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1144 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, 1145 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, 1146 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1147 <&hp_clk>, <&hp_clk>; 1148 #clock-cells = <1>; 1149 clock-indices = < 1150 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 1151 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 1152 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 1153 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 1154 >; 1155 clock-output-names = 1156 "iic2", "tpu0", "mmcif1", "sdhi3", 1157 "sdhi2", "sdhi1", "sdhi0", "mmcif0", 1158 "iic0", "pciec", "iic1", "ssusb", "cmt1", 1159 "usbdmac0", "usbdmac1"; 1160 }; 1161 mstp5_clks: mstp5_clks@e6150144 { 1162 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1163 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1164 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, 1165 <&extal_clk>, <&p_clk>; 1166 #clock-cells = <1>; 1167 clock-indices = < 1168 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 1169 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL 1170 R8A7790_CLK_PWM 1171 >; 1172 clock-output-names = "audmac0", "audmac1", "adsp_mod", 1173 "thermal", "pwm"; 1174 }; 1175 mstp7_clks: mstp7_clks@e615014c { 1176 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1177 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 1178 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, 1179 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, 1180 <&zx_clk>; 1181 #clock-cells = <1>; 1182 clock-indices = < 1183 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 1184 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 1185 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 1186 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 1187 >; 1188 clock-output-names = 1189 "ehci", "hsusb", "hscif1", "hscif0", "scif1", 1190 "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; 1191 }; 1192 mstp8_clks: mstp8_clks@e6150990 { 1193 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1194 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1195 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, 1196 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; 1197 #clock-cells = <1>; 1198 clock-indices = < 1199 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 1200 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER 1201 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 1202 >; 1203 clock-output-names = 1204 "mlb", "vin3", "vin2", "vin1", "vin0", "ether", 1205 "sata1", "sata0"; 1206 }; 1207 mstp9_clks: mstp9_clks@e6150994 { 1208 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1209 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 1210 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, 1211 <&cp_clk>, <&cp_clk>, <&cp_clk>, 1212 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, 1213 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; 1214 #clock-cells = <1>; 1215 clock-indices = < 1216 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 1217 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 1218 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS 1219 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 1220 >; 1221 clock-output-names = 1222 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", 1223 "rcan1", "rcan0", "qspi_mod", "iic3", 1224 "i2c3", "i2c2", "i2c1", "i2c0"; 1225 }; 1226 mstp10_clks: mstp10_clks@e6150998 { 1227 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1228 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; 1229 clocks = <&p_clk>, 1230 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1231 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1232 <&p_clk>, 1233 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, 1234 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, 1235 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, 1236 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, 1237 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, 1238 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; 1239 1240 #clock-cells = <1>; 1241 clock-indices = < 1242 R8A7790_CLK_SSI_ALL 1243 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 1244 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 1245 R8A7790_CLK_SCU_ALL 1246 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 1247 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 1248 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 1249 >; 1250 clock-output-names = 1251 "ssi-all", 1252 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", 1253 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", 1254 "scu-all", 1255 "scu-dvc1", "scu-dvc0", 1256 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", 1257 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; 1258 }; 1259 }; 1260 1261 qspi: spi@e6b10000 { 1262 compatible = "renesas,qspi-r8a7790", "renesas,qspi"; 1263 reg = <0 0xe6b10000 0 0x2c>; 1264 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; 1266 dmas = <&dmac0 0x17>, <&dmac0 0x18>; 1267 dma-names = "tx", "rx"; 1268 num-cs = <1>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 msiof0: spi@e6e20000 { 1275 compatible = "renesas,msiof-r8a7790"; 1276 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; 1277 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; 1279 dmas = <&dmac0 0x51>, <&dmac0 0x52>; 1280 dma-names = "tx", "rx"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 msiof1: spi@e6e10000 { 1287 compatible = "renesas,msiof-r8a7790"; 1288 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; 1289 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; 1290 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; 1291 dmas = <&dmac0 0x55>, <&dmac0 0x56>; 1292 dma-names = "tx", "rx"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 msiof2: spi@e6e00000 { 1299 compatible = "renesas,msiof-r8a7790"; 1300 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; 1301 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; 1303 dmas = <&dmac0 0x41>, <&dmac0 0x42>; 1304 dma-names = "tx", "rx"; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 1310 msiof3: spi@e6c90000 { 1311 compatible = "renesas,msiof-r8a7790"; 1312 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>; 1313 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; 1315 dmas = <&dmac0 0x45>, <&dmac0 0x46>; 1316 dma-names = "tx", "rx"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 status = "disabled"; 1320 }; 1321 1322 xhci: usb@ee000000 { 1323 compatible = "renesas,xhci-r8a7790"; 1324 reg = <0 0xee000000 0 0xc00>; 1325 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; 1327 phys = <&usb2 1>; 1328 phy-names = "usb"; 1329 status = "disabled"; 1330 }; 1331 1332 pci0: pci@ee090000 { 1333 compatible = "renesas,pci-r8a7790"; 1334 device_type = "pci"; 1335 clocks = <&mstp7_clks R8A7790_CLK_EHCI>; 1336 reg = <0 0xee090000 0 0xc00>, 1337 <0 0xee080000 0 0x1100>; 1338 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1339 status = "disabled"; 1340 1341 bus-range = <0 0>; 1342 #address-cells = <3>; 1343 #size-cells = <2>; 1344 #interrupt-cells = <1>; 1345 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; 1346 interrupt-map-mask = <0xff00 0 0 0x7>; 1347 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1348 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1349 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; 1350 1351 usb@0,1 { 1352 reg = <0x800 0 0 0 0>; 1353 device_type = "pci"; 1354 phys = <&usb0 0>; 1355 phy-names = "usb"; 1356 }; 1357 1358 usb@0,2 { 1359 reg = <0x1000 0 0 0 0>; 1360 device_type = "pci"; 1361 phys = <&usb0 0>; 1362 phy-names = "usb"; 1363 }; 1364 }; 1365 1366 pci1: pci@ee0b0000 { 1367 compatible = "renesas,pci-r8a7790"; 1368 device_type = "pci"; 1369 clocks = <&mstp7_clks R8A7790_CLK_EHCI>; 1370 reg = <0 0xee0b0000 0 0xc00>, 1371 <0 0xee0a0000 0 0x1100>; 1372 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; 1373 status = "disabled"; 1374 1375 bus-range = <1 1>; 1376 #address-cells = <3>; 1377 #size-cells = <2>; 1378 #interrupt-cells = <1>; 1379 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; 1380 interrupt-map-mask = <0xff00 0 0 0x7>; 1381 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH 1382 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH 1383 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>; 1384 }; 1385 1386 pci2: pci@ee0d0000 { 1387 compatible = "renesas,pci-r8a7790"; 1388 device_type = "pci"; 1389 clocks = <&mstp7_clks R8A7790_CLK_EHCI>; 1390 reg = <0 0xee0d0000 0 0xc00>, 1391 <0 0xee0c0000 0 0x1100>; 1392 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; 1393 status = "disabled"; 1394 1395 bus-range = <2 2>; 1396 #address-cells = <3>; 1397 #size-cells = <2>; 1398 #interrupt-cells = <1>; 1399 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; 1400 interrupt-map-mask = <0xff00 0 0 0x7>; 1401 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1402 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1403 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 1404 1405 usb@0,1 { 1406 reg = <0x800 0 0 0 0>; 1407 device_type = "pci"; 1408 phys = <&usb2 0>; 1409 phy-names = "usb"; 1410 }; 1411 1412 usb@0,2 { 1413 reg = <0x1000 0 0 0 0>; 1414 device_type = "pci"; 1415 phys = <&usb2 0>; 1416 phy-names = "usb"; 1417 }; 1418 }; 1419 1420 pciec: pcie@fe000000 { 1421 compatible = "renesas,pcie-r8a7790"; 1422 reg = <0 0xfe000000 0 0x80000>; 1423 #address-cells = <3>; 1424 #size-cells = <2>; 1425 bus-range = <0x00 0xff>; 1426 device_type = "pci"; 1427 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1428 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1429 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1430 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1431 /* Map all possible DDR as inbound ranges */ 1432 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 1433 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; 1434 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, 1435 <0 117 IRQ_TYPE_LEVEL_HIGH>, 1436 <0 118 IRQ_TYPE_LEVEL_HIGH>; 1437 #interrupt-cells = <1>; 1438 interrupt-map-mask = <0 0 0 0>; 1439 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; 1441 clock-names = "pcie", "pcie_bus"; 1442 status = "disabled"; 1443 }; 1444 1445 rcar_sound: rcar_sound@ec500000 { 1446 /* 1447 * #sound-dai-cells is required 1448 * 1449 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1450 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1451 */ 1452 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2"; 1453 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1454 <0 0xec5a0000 0 0x100>, /* ADG */ 1455 <0 0xec540000 0 0x1000>, /* SSIU */ 1456 <0 0xec541000 0 0x1280>, /* SSI */ 1457 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1458 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1459 1460 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, 1461 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, 1462 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, 1463 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, 1464 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, 1465 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, 1466 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, 1467 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, 1468 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, 1469 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, 1470 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, 1471 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, 1472 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; 1473 clock-names = "ssi-all", 1474 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", 1475 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", 1476 "src.9", "src.8", "src.7", "src.6", "src.5", 1477 "src.4", "src.3", "src.2", "src.1", "src.0", 1478 "dvc.0", "dvc.1", 1479 "clk_a", "clk_b", "clk_c", "clk_i"; 1480 1481 status = "disabled"; 1482 1483 rcar_sound,dvc { 1484 dvc0: dvc@0 { 1485 dmas = <&audma0 0xbc>; 1486 dma-names = "tx"; 1487 }; 1488 dvc1: dvc@1 { 1489 dmas = <&audma0 0xbe>; 1490 dma-names = "tx"; 1491 }; 1492 }; 1493 1494 rcar_sound,src { 1495 src0: src@0 { 1496 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; 1497 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1498 dma-names = "rx", "tx"; 1499 }; 1500 src1: src@1 { 1501 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; 1502 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1503 dma-names = "rx", "tx"; 1504 }; 1505 src2: src@2 { 1506 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; 1507 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1508 dma-names = "rx", "tx"; 1509 }; 1510 src3: src@3 { 1511 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; 1512 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1513 dma-names = "rx", "tx"; 1514 }; 1515 src4: src@4 { 1516 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; 1517 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1518 dma-names = "rx", "tx"; 1519 }; 1520 src5: src@5 { 1521 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; 1522 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1523 dma-names = "rx", "tx"; 1524 }; 1525 src6: src@6 { 1526 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; 1527 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1528 dma-names = "rx", "tx"; 1529 }; 1530 src7: src@7 { 1531 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; 1532 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1533 dma-names = "rx", "tx"; 1534 }; 1535 src8: src@8 { 1536 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; 1537 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1538 dma-names = "rx", "tx"; 1539 }; 1540 src9: src@9 { 1541 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; 1542 dmas = <&audma0 0x97>, <&audma1 0xba>; 1543 dma-names = "rx", "tx"; 1544 }; 1545 }; 1546 1547 rcar_sound,ssi { 1548 ssi0: ssi@0 { 1549 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; 1550 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1551 dma-names = "rx", "tx", "rxu", "txu"; 1552 }; 1553 ssi1: ssi@1 { 1554 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; 1555 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1556 dma-names = "rx", "tx", "rxu", "txu"; 1557 }; 1558 ssi2: ssi@2 { 1559 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; 1560 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1561 dma-names = "rx", "tx", "rxu", "txu"; 1562 }; 1563 ssi3: ssi@3 { 1564 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; 1565 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1566 dma-names = "rx", "tx", "rxu", "txu"; 1567 }; 1568 ssi4: ssi@4 { 1569 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; 1570 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1571 dma-names = "rx", "tx", "rxu", "txu"; 1572 }; 1573 ssi5: ssi@5 { 1574 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; 1575 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1576 dma-names = "rx", "tx", "rxu", "txu"; 1577 }; 1578 ssi6: ssi@6 { 1579 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; 1580 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1581 dma-names = "rx", "tx", "rxu", "txu"; 1582 }; 1583 ssi7: ssi@7 { 1584 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; 1585 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1586 dma-names = "rx", "tx", "rxu", "txu"; 1587 }; 1588 ssi8: ssi@8 { 1589 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; 1590 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1591 dma-names = "rx", "tx", "rxu", "txu"; 1592 }; 1593 ssi9: ssi@9 { 1594 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; 1595 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1596 dma-names = "rx", "tx", "rxu", "txu"; 1597 }; 1598 }; 1599 }; 1600 1601 ipmmu_sy0: mmu@e6280000 { 1602 compatible = "renesas,ipmmu-vmsa"; 1603 reg = <0 0xe6280000 0 0x1000>; 1604 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, 1605 <0 224 IRQ_TYPE_LEVEL_HIGH>; 1606 #iommu-cells = <1>; 1607 status = "disabled"; 1608 }; 1609 1610 ipmmu_sy1: mmu@e6290000 { 1611 compatible = "renesas,ipmmu-vmsa"; 1612 reg = <0 0xe6290000 0 0x1000>; 1613 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; 1614 #iommu-cells = <1>; 1615 status = "disabled"; 1616 }; 1617 1618 ipmmu_ds: mmu@e6740000 { 1619 compatible = "renesas,ipmmu-vmsa"; 1620 reg = <0 0xe6740000 0 0x1000>; 1621 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, 1622 <0 199 IRQ_TYPE_LEVEL_HIGH>; 1623 #iommu-cells = <1>; 1624 status = "disabled"; 1625 }; 1626 1627 ipmmu_mp: mmu@ec680000 { 1628 compatible = "renesas,ipmmu-vmsa"; 1629 reg = <0 0xec680000 0 0x1000>; 1630 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; 1631 #iommu-cells = <1>; 1632 status = "disabled"; 1633 }; 1634 1635 ipmmu_mx: mmu@fe951000 { 1636 compatible = "renesas,ipmmu-vmsa"; 1637 reg = <0 0xfe951000 0 0x1000>; 1638 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 1639 <0 221 IRQ_TYPE_LEVEL_HIGH>; 1640 #iommu-cells = <1>; 1641 status = "disabled"; 1642 }; 1643 1644 ipmmu_rt: mmu@ffc80000 { 1645 compatible = "renesas,ipmmu-vmsa"; 1646 reg = <0 0xffc80000 0 0x1000>; 1647 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; 1648 #iommu-cells = <1>; 1649 status = "disabled"; 1650 }; 1651}; 1652