1/* 2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC 3 * 4 * Copyright (C) 2012 Atmel, 5 * 2012 Hong Xu <hong.xu@atmel.com> 6 * 7 * Licensed under GPLv2 or later. 8 */ 9 10#include "skeleton.dtsi" 11#include <dt-bindings/dma/at91.h> 12#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/clock/at91.h> 16 17/ { 18 model = "Atmel AT91SAM9N12 SoC"; 19 compatible = "atmel,at91sam9n12"; 20 interrupt-parent = <&aic>; 21 22 aliases { 23 serial0 = &dbgu; 24 serial1 = &usart0; 25 serial2 = &usart1; 26 serial3 = &usart2; 27 serial4 = &usart3; 28 gpio0 = &pioA; 29 gpio1 = &pioB; 30 gpio2 = &pioC; 31 gpio3 = &pioD; 32 tcb0 = &tcb0; 33 tcb1 = &tcb1; 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 ssc0 = &ssc0; 37 pwm0 = &pwm0; 38 }; 39 cpus { 40 #address-cells = <0>; 41 #size-cells = <0>; 42 43 cpu { 44 compatible = "arm,arm926ej-s"; 45 device_type = "cpu"; 46 }; 47 }; 48 49 memory { 50 reg = <0x20000000 0x10000000>; 51 }; 52 53 clocks { 54 slow_xtal: slow_xtal { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <0>; 58 }; 59 60 main_xtal: main_xtal { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <0>; 64 }; 65 }; 66 67 sram: sram@00300000 { 68 compatible = "mmio-sram"; 69 reg = <0x00300000 0x8000>; 70 }; 71 72 ahb { 73 compatible = "simple-bus"; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 apb { 79 compatible = "simple-bus"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges; 83 84 aic: interrupt-controller@fffff000 { 85 #interrupt-cells = <3>; 86 compatible = "atmel,at91rm9200-aic"; 87 interrupt-controller; 88 reg = <0xfffff000 0x200>; 89 atmel,external-irqs = <31>; 90 }; 91 92 ramc0: ramc@ffffe800 { 93 compatible = "atmel,at91sam9g45-ddramc"; 94 reg = <0xffffe800 0x200>; 95 clocks = <&ddrck>; 96 clock-names = "ddrck"; 97 }; 98 99 pmc: pmc@fffffc00 { 100 compatible = "atmel,at91sam9n12-pmc"; 101 reg = <0xfffffc00 0x200>; 102 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 103 interrupt-controller; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 #interrupt-cells = <1>; 107 108 main_rc_osc: main_rc_osc { 109 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 110 #clock-cells = <0>; 111 interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; 112 clock-frequency = <12000000>; 113 clock-accuracy = <50000000>; 114 }; 115 116 main_osc: main_osc { 117 compatible = "atmel,at91rm9200-clk-main-osc"; 118 #clock-cells = <0>; 119 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 120 clocks = <&main_xtal>; 121 }; 122 123 main: mainck { 124 compatible = "atmel,at91sam9x5-clk-main"; 125 #clock-cells = <0>; 126 interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; 127 clocks = <&main_rc_osc>, <&main_osc>; 128 }; 129 130 plla: pllack { 131 compatible = "atmel,at91rm9200-clk-pll"; 132 #clock-cells = <0>; 133 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 134 clocks = <&main>; 135 reg = <0>; 136 atmel,clk-input-range = <2000000 32000000>; 137 #atmel,pll-clk-output-range-cells = <4>; 138 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, 139 <695000000 750000000 1 0>, 140 <645000000 700000000 2 0>, 141 <595000000 650000000 3 0>, 142 <545000000 600000000 0 1>, 143 <495000000 555000000 1 1>, 144 <445000000 500000000 2 1>, 145 <400000000 450000000 3 1>; 146 }; 147 148 plladiv: plladivck { 149 compatible = "atmel,at91sam9x5-clk-plldiv"; 150 #clock-cells = <0>; 151 clocks = <&plla>; 152 }; 153 154 pllb: pllbck { 155 compatible = "atmel,at91rm9200-clk-pll"; 156 #clock-cells = <0>; 157 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 158 clocks = <&main>; 159 reg = <1>; 160 atmel,clk-input-range = <2000000 32000000>; 161 #atmel,pll-clk-output-range-cells = <3>; 162 atmel,pll-clk-output-ranges = <30000000 100000000 0>; 163 }; 164 165 mck: masterck { 166 compatible = "atmel,at91sam9x5-clk-master"; 167 #clock-cells = <0>; 168 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 169 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; 170 atmel,clk-output-range = <0 133333333>; 171 atmel,clk-divisors = <1 2 4 3>; 172 atmel,master-clk-have-div3-pres; 173 }; 174 175 usb: usbck { 176 compatible = "atmel,at91sam9n12-clk-usb"; 177 #clock-cells = <0>; 178 clocks = <&pllb>; 179 }; 180 181 prog: progck { 182 compatible = "atmel,at91sam9x5-clk-programmable"; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 interrupt-parent = <&pmc>; 186 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; 187 188 prog0: prog0 { 189 #clock-cells = <0>; 190 reg = <0>; 191 interrupts = <AT91_PMC_PCKRDY(0)>; 192 }; 193 194 prog1: prog1 { 195 #clock-cells = <0>; 196 reg = <1>; 197 interrupts = <AT91_PMC_PCKRDY(1)>; 198 }; 199 }; 200 201 systemck { 202 compatible = "atmel,at91rm9200-clk-system"; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 206 ddrck: ddrck { 207 #clock-cells = <0>; 208 reg = <2>; 209 clocks = <&mck>; 210 }; 211 212 lcdck: lcdck { 213 #clock-cells = <0>; 214 reg = <3>; 215 clocks = <&mck>; 216 }; 217 218 uhpck: uhpck { 219 #clock-cells = <0>; 220 reg = <6>; 221 clocks = <&usb>; 222 }; 223 224 udpck: udpck { 225 #clock-cells = <0>; 226 reg = <7>; 227 clocks = <&usb>; 228 }; 229 230 pck0: pck0 { 231 #clock-cells = <0>; 232 reg = <8>; 233 clocks = <&prog0>; 234 }; 235 236 pck1: pck1 { 237 #clock-cells = <0>; 238 reg = <9>; 239 clocks = <&prog1>; 240 }; 241 }; 242 243 periphck { 244 compatible = "atmel,at91sam9x5-clk-peripheral"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 clocks = <&mck>; 248 249 pioAB_clk: pioAB_clk { 250 #clock-cells = <0>; 251 reg = <2>; 252 }; 253 254 pioCD_clk: pioCD_clk { 255 #clock-cells = <0>; 256 reg = <3>; 257 }; 258 259 fuse_clk: fuse_clk { 260 #clock-cells = <0>; 261 reg = <4>; 262 }; 263 264 usart0_clk: usart0_clk { 265 #clock-cells = <0>; 266 reg = <5>; 267 }; 268 269 usart1_clk: usart1_clk { 270 #clock-cells = <0>; 271 reg = <6>; 272 }; 273 274 usart2_clk: usart2_clk { 275 #clock-cells = <0>; 276 reg = <7>; 277 }; 278 279 usart3_clk: usart3_clk { 280 #clock-cells = <0>; 281 reg = <8>; 282 }; 283 284 twi0_clk: twi0_clk { 285 reg = <9>; 286 #clock-cells = <0>; 287 }; 288 289 twi1_clk: twi1_clk { 290 #clock-cells = <0>; 291 reg = <10>; 292 }; 293 294 mci0_clk: mci0_clk { 295 #clock-cells = <0>; 296 reg = <12>; 297 }; 298 299 spi0_clk: spi0_clk { 300 #clock-cells = <0>; 301 reg = <13>; 302 }; 303 304 spi1_clk: spi1_clk { 305 #clock-cells = <0>; 306 reg = <14>; 307 }; 308 309 uart0_clk: uart0_clk { 310 #clock-cells = <0>; 311 reg = <15>; 312 }; 313 314 uart1_clk: uart1_clk { 315 #clock-cells = <0>; 316 reg = <16>; 317 }; 318 319 tcb_clk: tcb_clk { 320 #clock-cells = <0>; 321 reg = <17>; 322 }; 323 324 pwm_clk: pwm_clk { 325 #clock-cells = <0>; 326 reg = <18>; 327 }; 328 329 adc_clk: adc_clk { 330 #clock-cells = <0>; 331 reg = <19>; 332 }; 333 334 dma0_clk: dma0_clk { 335 #clock-cells = <0>; 336 reg = <20>; 337 }; 338 339 uhphs_clk: uhphs_clk { 340 #clock-cells = <0>; 341 reg = <22>; 342 }; 343 344 udphs_clk: udphs_clk { 345 #clock-cells = <0>; 346 reg = <23>; 347 }; 348 349 lcdc_clk: lcdc_clk { 350 #clock-cells = <0>; 351 reg = <25>; 352 }; 353 354 sha_clk: sha_clk { 355 #clock-cells = <0>; 356 reg = <27>; 357 }; 358 359 ssc0_clk: ssc0_clk { 360 #clock-cells = <0>; 361 reg = <28>; 362 }; 363 364 aes_clk: aes_clk { 365 #clock-cells = <0>; 366 reg = <29>; 367 }; 368 369 trng_clk: trng_clk { 370 #clock-cells = <0>; 371 reg = <30>; 372 }; 373 }; 374 }; 375 376 rstc@fffffe00 { 377 compatible = "atmel,at91sam9g45-rstc"; 378 reg = <0xfffffe00 0x10>; 379 }; 380 381 pit: timer@fffffe30 { 382 compatible = "atmel,at91sam9260-pit"; 383 reg = <0xfffffe30 0xf>; 384 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 385 clocks = <&mck>; 386 }; 387 388 shdwc@fffffe10 { 389 compatible = "atmel,at91sam9x5-shdwc"; 390 reg = <0xfffffe10 0x10>; 391 }; 392 393 sckc@fffffe50 { 394 compatible = "atmel,at91sam9x5-sckc"; 395 reg = <0xfffffe50 0x4>; 396 397 slow_osc: slow_osc { 398 compatible = "atmel,at91sam9x5-clk-slow-osc"; 399 #clock-cells = <0>; 400 clocks = <&slow_xtal>; 401 }; 402 403 slow_rc_osc: slow_rc_osc { 404 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 405 #clock-cells = <0>; 406 clock-frequency = <32768>; 407 clock-accuracy = <50000000>; 408 }; 409 410 clk32k: slck { 411 compatible = "atmel,at91sam9x5-clk-slow"; 412 #clock-cells = <0>; 413 clocks = <&slow_rc_osc>, <&slow_osc>; 414 }; 415 }; 416 417 mmc0: mmc@f0008000 { 418 compatible = "atmel,hsmci"; 419 reg = <0xf0008000 0x600>; 420 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 421 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; 422 dma-names = "rxtx"; 423 clocks = <&mci0_clk>; 424 clock-names = "mci_clk"; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 status = "disabled"; 428 }; 429 430 tcb0: timer@f8008000 { 431 compatible = "atmel,at91sam9x5-tcb"; 432 reg = <0xf8008000 0x100>; 433 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 434 clocks = <&tcb_clk>; 435 clock-names = "t0_clk"; 436 }; 437 438 tcb1: timer@f800c000 { 439 compatible = "atmel,at91sam9x5-tcb"; 440 reg = <0xf800c000 0x100>; 441 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 442 clocks = <&tcb_clk>; 443 clock-names = "t0_clk"; 444 }; 445 446 dma: dma-controller@ffffec00 { 447 compatible = "atmel,at91sam9g45-dma"; 448 reg = <0xffffec00 0x200>; 449 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 450 #dma-cells = <2>; 451 clocks = <&dma0_clk>; 452 clock-names = "dma_clk"; 453 }; 454 455 pinctrl@fffff400 { 456 #address-cells = <1>; 457 #size-cells = <1>; 458 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 459 ranges = <0xfffff400 0xfffff400 0x800>; 460 461 atmel,mux-mask = < 462 /* A B C */ 463 0xffffffff 0xffe07983 0x00000000 /* pioA */ 464 0x00040000 0x00047e0f 0x00000000 /* pioB */ 465 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ 466 0x003fffff 0x003f8000 0x00000000 /* pioD */ 467 >; 468 469 /* shared pinctrl settings */ 470 dbgu { 471 pinctrl_dbgu: dbgu-0 { 472 atmel,pins = 473 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ 474 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ 475 }; 476 }; 477 478 usart0 { 479 pinctrl_usart0: usart0-0 { 480 atmel,pins = 481 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ 482 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ 483 }; 484 485 pinctrl_usart0_rts: usart0_rts-0 { 486 atmel,pins = 487 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ 488 }; 489 490 pinctrl_usart0_cts: usart0_cts-0 { 491 atmel,pins = 492 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ 493 }; 494 }; 495 496 usart1 { 497 pinctrl_usart1: usart1-0 { 498 atmel,pins = 499 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ 500 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ 501 }; 502 }; 503 504 usart2 { 505 pinctrl_usart2: usart2-0 { 506 atmel,pins = 507 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ 508 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ 509 }; 510 511 pinctrl_usart2_rts: usart2_rts-0 { 512 atmel,pins = 513 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ 514 }; 515 516 pinctrl_usart2_cts: usart2_cts-0 { 517 atmel,pins = 518 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ 519 }; 520 }; 521 522 usart3 { 523 pinctrl_usart3: usart3-0 { 524 atmel,pins = 525 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ 526 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ 527 }; 528 529 pinctrl_usart3_rts: usart3_rts-0 { 530 atmel,pins = 531 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ 532 }; 533 534 pinctrl_usart3_cts: usart3_cts-0 { 535 atmel,pins = 536 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ 537 }; 538 }; 539 540 uart0 { 541 pinctrl_uart0: uart0-0 { 542 atmel,pins = 543 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ 544 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ 545 }; 546 }; 547 548 uart1 { 549 pinctrl_uart1: uart1-0 { 550 atmel,pins = 551 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ 552 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ 553 }; 554 }; 555 556 nand { 557 pinctrl_nand: nand-0 { 558 atmel,pins = 559 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ 560 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ 561 }; 562 }; 563 564 mmc0 { 565 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { 566 atmel,pins = 567 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 568 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ 569 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ 570 }; 571 572 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 573 atmel,pins = 574 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ 575 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ 576 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ 577 }; 578 579 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { 580 atmel,pins = 581 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ 582 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ 583 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ 584 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ 585 }; 586 }; 587 588 ssc0 { 589 pinctrl_ssc0_tx: ssc0_tx-0 { 590 atmel,pins = 591 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ 592 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 593 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ 594 }; 595 596 pinctrl_ssc0_rx: ssc0_rx-0 { 597 atmel,pins = 598 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 599 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 600 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 601 }; 602 }; 603 604 spi0 { 605 pinctrl_spi0: spi0-0 { 606 atmel,pins = 607 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ 608 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ 609 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ 610 }; 611 }; 612 613 spi1 { 614 pinctrl_spi1: spi1-0 { 615 atmel,pins = 616 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ 617 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ 618 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ 619 }; 620 }; 621 622 i2c0 { 623 pinctrl_i2c0: i2c0-0 { 624 atmel,pins = 625 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE 626 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 627 }; 628 }; 629 630 i2c1 { 631 pinctrl_i2c1: i2c1-0 { 632 atmel,pins = 633 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE 634 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; 635 }; 636 }; 637 638 tcb0 { 639 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 640 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; 641 }; 642 643 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 644 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; 645 }; 646 647 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 648 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 649 }; 650 651 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 652 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 653 }; 654 655 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 656 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 657 }; 658 659 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 660 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 661 }; 662 663 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 664 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 665 }; 666 667 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 668 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 669 }; 670 671 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 672 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 673 }; 674 }; 675 676 tcb1 { 677 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 678 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; 679 }; 680 681 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 682 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; 683 }; 684 685 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 686 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; 687 }; 688 689 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 690 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; 691 }; 692 693 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 694 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; 695 }; 696 697 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 698 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; 699 }; 700 701 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 702 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; 703 }; 704 705 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 706 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; 707 }; 708 709 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 710 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; 711 }; 712 }; 713 714 pioA: gpio@fffff400 { 715 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 716 reg = <0xfffff400 0x200>; 717 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 718 #gpio-cells = <2>; 719 gpio-controller; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 clocks = <&pioAB_clk>; 723 }; 724 725 pioB: gpio@fffff600 { 726 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 727 reg = <0xfffff600 0x200>; 728 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 729 #gpio-cells = <2>; 730 gpio-controller; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 clocks = <&pioAB_clk>; 734 }; 735 736 pioC: gpio@fffff800 { 737 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 738 reg = <0xfffff800 0x200>; 739 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 740 #gpio-cells = <2>; 741 gpio-controller; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 clocks = <&pioCD_clk>; 745 }; 746 747 pioD: gpio@fffffa00 { 748 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 749 reg = <0xfffffa00 0x200>; 750 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 751 #gpio-cells = <2>; 752 gpio-controller; 753 interrupt-controller; 754 #interrupt-cells = <2>; 755 clocks = <&pioCD_clk>; 756 }; 757 }; 758 759 dbgu: serial@fffff200 { 760 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 761 reg = <0xfffff200 0x200>; 762 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_dbgu>; 765 clocks = <&mck>; 766 clock-names = "usart"; 767 status = "disabled"; 768 }; 769 770 ssc0: ssc@f0010000 { 771 compatible = "atmel,at91sam9g45-ssc"; 772 reg = <0xf0010000 0x4000>; 773 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 774 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, 775 <&dma 0 AT91_DMA_CFG_PER_ID(22)>; 776 dma-names = "tx", "rx"; 777 pinctrl-names = "default"; 778 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 779 clocks = <&ssc0_clk>; 780 clock-names = "pclk"; 781 status = "disabled"; 782 }; 783 784 usart0: serial@f801c000 { 785 compatible = "atmel,at91sam9260-usart"; 786 reg = <0xf801c000 0x4000>; 787 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; 788 pinctrl-names = "default"; 789 pinctrl-0 = <&pinctrl_usart0>; 790 clocks = <&usart0_clk>; 791 clock-names = "usart"; 792 status = "disabled"; 793 }; 794 795 usart1: serial@f8020000 { 796 compatible = "atmel,at91sam9260-usart"; 797 reg = <0xf8020000 0x4000>; 798 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&pinctrl_usart1>; 801 clocks = <&usart1_clk>; 802 clock-names = "usart"; 803 status = "disabled"; 804 }; 805 806 usart2: serial@f8024000 { 807 compatible = "atmel,at91sam9260-usart"; 808 reg = <0xf8024000 0x4000>; 809 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&pinctrl_usart2>; 812 clocks = <&usart2_clk>; 813 clock-names = "usart"; 814 status = "disabled"; 815 }; 816 817 usart3: serial@f8028000 { 818 compatible = "atmel,at91sam9260-usart"; 819 reg = <0xf8028000 0x4000>; 820 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&pinctrl_usart3>; 823 clocks = <&usart3_clk>; 824 clock-names = "usart"; 825 status = "disabled"; 826 }; 827 828 i2c0: i2c@f8010000 { 829 compatible = "atmel,at91sam9x5-i2c"; 830 reg = <0xf8010000 0x100>; 831 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; 832 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, 833 <&dma 1 AT91_DMA_CFG_PER_ID(14)>; 834 dma-names = "tx", "rx"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&pinctrl_i2c0>; 839 clocks = <&twi0_clk>; 840 status = "disabled"; 841 }; 842 843 i2c1: i2c@f8014000 { 844 compatible = "atmel,at91sam9x5-i2c"; 845 reg = <0xf8014000 0x100>; 846 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; 847 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, 848 <&dma 1 AT91_DMA_CFG_PER_ID(16)>; 849 dma-names = "tx", "rx"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&pinctrl_i2c1>; 854 clocks = <&twi1_clk>; 855 status = "disabled"; 856 }; 857 858 spi0: spi@f0000000 { 859 #address-cells = <1>; 860 #size-cells = <0>; 861 compatible = "atmel,at91rm9200-spi"; 862 reg = <0xf0000000 0x100>; 863 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 864 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, 865 <&dma 1 AT91_DMA_CFG_PER_ID(2)>; 866 dma-names = "tx", "rx"; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&pinctrl_spi0>; 869 clocks = <&spi0_clk>; 870 clock-names = "spi_clk"; 871 status = "disabled"; 872 }; 873 874 spi1: spi@f0004000 { 875 #address-cells = <1>; 876 #size-cells = <0>; 877 compatible = "atmel,at91rm9200-spi"; 878 reg = <0xf0004000 0x100>; 879 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; 880 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, 881 <&dma 1 AT91_DMA_CFG_PER_ID(4)>; 882 dma-names = "tx", "rx"; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&pinctrl_spi1>; 885 clocks = <&spi1_clk>; 886 clock-names = "spi_clk"; 887 status = "disabled"; 888 }; 889 890 watchdog@fffffe40 { 891 compatible = "atmel,at91sam9260-wdt"; 892 reg = <0xfffffe40 0x10>; 893 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 894 atmel,watchdog-type = "hardware"; 895 atmel,reset-type = "all"; 896 atmel,dbg-halt; 897 status = "disabled"; 898 }; 899 900 rtc@fffffeb0 { 901 compatible = "atmel,at91rm9200-rtc"; 902 reg = <0xfffffeb0 0x40>; 903 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 904 status = "disabled"; 905 }; 906 907 pwm0: pwm@f8034000 { 908 compatible = "atmel,at91sam9rl-pwm"; 909 reg = <0xf8034000 0x300>; 910 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 911 #pwm-cells = <3>; 912 clocks = <&pwm_clk>; 913 status = "disabled"; 914 }; 915 916 usb1: gadget@f803c000 { 917 compatible = "atmel,at91sam9260-udc"; 918 reg = <0xf803c000 0x4000>; 919 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 920 clocks = <&udphs_clk>, <&udpck>; 921 clock-names = "pclk", "hclk"; 922 status = "disabled"; 923 }; 924 }; 925 926 nand0: nand@40000000 { 927 compatible = "atmel,at91rm9200-nand"; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 reg = < 0x40000000 0x10000000 931 0xffffe000 0x00000600 932 0xffffe600 0x00000200 933 0x00108000 0x00018000 934 >; 935 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 936 atmel,nand-addr-offset = <21>; 937 atmel,nand-cmd-offset = <22>; 938 atmel,nand-has-dma; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&pinctrl_nand>; 941 gpios = <&pioD 5 GPIO_ACTIVE_HIGH 942 &pioD 4 GPIO_ACTIVE_HIGH 943 0 944 >; 945 status = "disabled"; 946 }; 947 948 usb0: ohci@00500000 { 949 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 950 reg = <0x00500000 0x00100000>; 951 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 952 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, 953 <&uhpck>; 954 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; 955 status = "disabled"; 956 }; 957 }; 958 959 i2c@0 { 960 compatible = "i2c-gpio"; 961 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ 962 &pioA 31 GPIO_ACTIVE_HIGH /* scl */ 963 >; 964 i2c-gpio,sda-open-drain; 965 i2c-gpio,scl-open-drain; 966 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971}; 972