Searched refs:state (Results 1 - 200 of 8170) sorted by relevance

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/linux-4.1.27/fs/nfsd/
H A Dtrace.c2 #include "state.h"
H A Dnfs4acl.c467 init_state(struct posix_acl_state *state, int cnt) init_state() argument
471 memset(state, 0, sizeof(struct posix_acl_state)); init_state()
472 state->empty = 1; init_state()
480 state->users = kzalloc(alloc, GFP_KERNEL); init_state()
481 if (!state->users) init_state()
483 state->groups = kzalloc(alloc, GFP_KERNEL); init_state()
484 if (!state->groups) { init_state()
485 kfree(state->users); init_state()
492 free_state(struct posix_acl_state *state) { free_state() argument
493 kfree(state->users); free_state()
494 kfree(state->groups); free_state()
497 static inline void add_to_mask(struct posix_acl_state *state, struct posix_ace_state *astate) add_to_mask() argument
499 state->mask.allow |= astate->allow; add_to_mask()
503 posix_state_to_acl(struct posix_acl_state *state, unsigned int flags) posix_state_to_acl() argument
515 if (state->empty && (flags & NFS4_ACL_TYPE_DEFAULT)) posix_state_to_acl()
523 if (!state->users->n && !state->groups->n) posix_state_to_acl()
526 nace = 4 + state->users->n + state->groups->n; posix_state_to_acl()
533 low_mode_from_nfs4(state->owner.allow, &pace->e_perm, flags); posix_state_to_acl()
535 for (i=0; i < state->users->n; i++) { posix_state_to_acl()
538 low_mode_from_nfs4(state->users->aces[i].perms.allow, posix_state_to_acl()
540 pace->e_uid = state->users->aces[i].uid; posix_state_to_acl()
541 add_to_mask(state, &state->users->aces[i].perms); posix_state_to_acl()
546 low_mode_from_nfs4(state->group.allow, &pace->e_perm, flags); posix_state_to_acl()
547 add_to_mask(state, &state->group); posix_state_to_acl()
549 for (i=0; i < state->groups->n; i++) { posix_state_to_acl()
552 low_mode_from_nfs4(state->groups->aces[i].perms.allow, posix_state_to_acl()
554 pace->e_gid = state->groups->aces[i].gid; posix_state_to_acl()
555 add_to_mask(state, &state->groups->aces[i].perms); posix_state_to_acl()
558 if (state->users->n || state->groups->n) { posix_state_to_acl()
561 low_mode_from_nfs4(state->mask.allow, &pace->e_perm, flags); posix_state_to_acl()
566 low_mode_from_nfs4(state->other.allow, &pace->e_perm, flags); posix_state_to_acl()
583 static int find_uid(struct posix_acl_state *state, kuid_t uid) find_uid() argument
585 struct posix_ace_state_array *a = state->users; find_uid()
594 a->aces[i].perms.allow = state->everyone.allow; find_uid()
595 a->aces[i].perms.deny = state->everyone.deny; find_uid()
600 static int find_gid(struct posix_acl_state *state, kgid_t gid) find_gid() argument
602 struct posix_ace_state_array *a = state->groups; find_gid()
611 a->aces[i].perms.allow = state->everyone.allow; find_gid()
612 a->aces[i].perms.deny = state->everyone.deny; find_gid()
633 static void process_one_v4_ace(struct posix_acl_state *state, process_one_v4_ace() argument
639 state->empty = 0; process_one_v4_ace()
644 allow_bits(&state->owner, mask); process_one_v4_ace()
646 deny_bits(&state->owner, mask); process_one_v4_ace()
650 i = find_uid(state, ace->who_uid); process_one_v4_ace()
652 allow_bits(&state->users->aces[i].perms, mask); process_one_v4_ace()
654 deny_bits(&state->users->aces[i].perms, mask); process_one_v4_ace()
655 mask = state->users->aces[i].perms.deny; process_one_v4_ace()
656 deny_bits(&state->owner, mask); process_one_v4_ace()
661 allow_bits(&state->group, mask); process_one_v4_ace()
663 deny_bits(&state->group, mask); process_one_v4_ace()
664 mask = state->group.deny; process_one_v4_ace()
665 deny_bits(&state->owner, mask); process_one_v4_ace()
666 deny_bits(&state->everyone, mask); process_one_v4_ace()
667 deny_bits_array(state->users, mask); process_one_v4_ace()
668 deny_bits_array(state->groups, mask); process_one_v4_ace()
672 i = find_gid(state, ace->who_gid); process_one_v4_ace()
674 allow_bits(&state->groups->aces[i].perms, mask); process_one_v4_ace()
676 deny_bits(&state->groups->aces[i].perms, mask); process_one_v4_ace()
677 mask = state->groups->aces[i].perms.deny; process_one_v4_ace()
678 deny_bits(&state->owner, mask); process_one_v4_ace()
679 deny_bits(&state->group, mask); process_one_v4_ace()
680 deny_bits(&state->everyone, mask); process_one_v4_ace()
681 deny_bits_array(state->users, mask); process_one_v4_ace()
682 deny_bits_array(state->groups, mask); process_one_v4_ace()
687 allow_bits(&state->owner, mask); process_one_v4_ace()
688 allow_bits(&state->group, mask); process_one_v4_ace()
689 allow_bits(&state->other, mask); process_one_v4_ace()
690 allow_bits(&state->everyone, mask); process_one_v4_ace()
691 allow_bits_array(state->users, mask); process_one_v4_ace()
692 allow_bits_array(state->groups, mask); process_one_v4_ace()
694 deny_bits(&state->owner, mask); process_one_v4_ace()
695 deny_bits(&state->group, mask); process_one_v4_ace()
696 deny_bits(&state->other, mask); process_one_v4_ace()
697 deny_bits(&state->everyone, mask); process_one_v4_ace()
698 deny_bits_array(state->users, mask); process_one_v4_ace()
699 deny_bits_array(state->groups, mask); process_one_v4_ace()
/linux-4.1.27/arch/arc/kernel/
H A Ddisasm.c22 * findings in *state
24 void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state, disasm_instr() argument
35 memset(state, 0, sizeof(struct disasm_state)); disasm_instr()
51 state->major_opcode = (word1 >> 11) & 0x1F; disasm_instr()
54 if (state->major_opcode < 0x0B) { disasm_instr()
57 state->instr_len = 4; disasm_instr()
59 state->words[0] = (word1 << 16) | word0; disasm_instr()
61 state->instr_len = 2; disasm_instr()
62 state->words[0] = word1; disasm_instr()
66 word1 = *((uint16_t *)(addr + state->instr_len)); disasm_instr()
67 word0 = *((uint16_t *)(addr + state->instr_len + 2)); disasm_instr()
68 state->words[1] = (word1 << 16) | word0; disasm_instr()
70 switch (state->major_opcode) { disasm_instr()
72 state->is_branch = 1; disasm_instr()
75 fieldA = (IS_BIT(state->words[0], 16)) ? disasm_instr()
76 FIELD_s25(state->words[0]) : disasm_instr()
77 FIELD_s21(state->words[0]); disasm_instr()
79 state->delay_slot = IS_BIT(state->words[0], 5); disasm_instr()
80 state->target = fieldA + (addr & ~0x3); disasm_instr()
81 state->flow = direct_jump; disasm_instr()
85 if (IS_BIT(state->words[0], 16)) { disasm_instr()
88 fieldA = (IS_BIT(state->words[0], 17)) ? disasm_instr()
89 (FIELD_s25(state->words[0]) & ~0x3) : disasm_instr()
90 FIELD_s21(state->words[0]); disasm_instr()
92 state->flow = direct_call; disasm_instr()
95 fieldA = FIELD_s9(state->words[0]) & ~0x3; disasm_instr()
96 state->flow = direct_jump; disasm_instr()
99 state->delay_slot = IS_BIT(state->words[0], 5); disasm_instr()
100 state->target = fieldA + (addr & ~0x3); disasm_instr()
101 state->is_branch = 1; disasm_instr()
105 state->write = 0; disasm_instr()
106 state->di = BITS(state->words[0], 11, 11); disasm_instr()
107 if (state->di) disasm_instr()
109 state->x = BITS(state->words[0], 6, 6); disasm_instr()
110 state->zz = BITS(state->words[0], 7, 8); disasm_instr()
111 state->aa = BITS(state->words[0], 9, 10); disasm_instr()
112 state->wb_reg = FIELD_B(state->words[0]); disasm_instr()
113 if (state->wb_reg == REG_LIMM) { disasm_instr()
114 state->instr_len += 4; disasm_instr()
115 state->aa = 0; disasm_instr()
116 state->src1 = state->words[1]; disasm_instr()
118 state->src1 = get_reg(state->wb_reg, regs, cregs); disasm_instr()
120 state->src2 = FIELD_s9(state->words[0]); disasm_instr()
121 state->dest = FIELD_A(state->words[0]); disasm_instr()
122 state->pref = (state->dest == REG_LIMM); disasm_instr()
126 state->write = 1; disasm_instr()
127 state->di = BITS(state->words[0], 5, 5); disasm_instr()
128 if (state->di) disasm_instr()
130 state->aa = BITS(state->words[0], 3, 4); disasm_instr()
131 state->zz = BITS(state->words[0], 1, 2); disasm_instr()
132 state->src1 = FIELD_C(state->words[0]); disasm_instr()
133 if (state->src1 == REG_LIMM) { disasm_instr()
134 state->instr_len += 4; disasm_instr()
135 state->src1 = state->words[1]; disasm_instr()
137 state->src1 = get_reg(state->src1, regs, cregs); disasm_instr()
139 state->wb_reg = FIELD_B(state->words[0]); disasm_instr()
140 if (state->wb_reg == REG_LIMM) { disasm_instr()
141 state->aa = 0; disasm_instr()
142 state->instr_len += 4; disasm_instr()
143 state->src2 = state->words[1]; disasm_instr()
145 state->src2 = get_reg(state->wb_reg, regs, cregs); disasm_instr()
147 state->src3 = FIELD_s9(state->words[0]); disasm_instr()
151 subopcode = MINOR_OPCODE(state->words[0]); disasm_instr()
160 state->delay_slot = 1; disasm_instr()
166 op_format = BITS(state->words[0], 22, 23); disasm_instr()
168 (!IS_BIT(state->words[0], 5)))) { disasm_instr()
169 fieldC = FIELD_C(state->words[0]); disasm_instr()
172 fieldC = state->words[1]; disasm_instr()
173 state->instr_len += 4; disasm_instr()
178 && (IS_BIT(state->words[0], 5)))) { disasm_instr()
179 fieldC = FIELD_C(state->words[0]); disasm_instr()
182 fieldC = FIELD_s12(state->words[0]); disasm_instr()
186 state->target = fieldC; disasm_instr()
187 state->flow = is_linked ? disasm_instr()
190 state->target = get_reg(fieldC, regs, cregs); disasm_instr()
191 state->flow = is_linked ? disasm_instr()
194 state->is_branch = 1; disasm_instr()
198 if (BITS(state->words[0], 22, 23) == 3) { disasm_instr()
200 fieldC = FIELD_C(state->words[0]); disasm_instr()
204 state->is_branch = 1; disasm_instr()
205 state->flow = direct_jump; disasm_instr()
206 state->target = fieldC; disasm_instr()
213 state->di = BITS(state->words[0], 15, 15); disasm_instr()
214 if (state->di) disasm_instr()
216 state->x = BITS(state->words[0], 16, 16); disasm_instr()
217 state->zz = BITS(state->words[0], 17, 18); disasm_instr()
218 state->aa = BITS(state->words[0], 22, 23); disasm_instr()
219 state->wb_reg = FIELD_B(state->words[0]); disasm_instr()
220 if (state->wb_reg == REG_LIMM) { disasm_instr()
221 state->instr_len += 4; disasm_instr()
222 state->src1 = state->words[1]; disasm_instr()
224 state->src1 = get_reg(state->wb_reg, regs, disasm_instr()
227 state->src2 = FIELD_C(state->words[0]); disasm_instr()
228 if (state->src2 == REG_LIMM) { disasm_instr()
229 state->instr_len += 4; disasm_instr()
230 state->src2 = state->words[1]; disasm_instr()
232 state->src2 = get_reg(state->src2, regs, disasm_instr()
235 state->dest = FIELD_A(state->words[0]); disasm_instr()
236 if (state->dest == REG_LIMM) disasm_instr()
237 state->pref = 1; disasm_instr()
243 switch (BITS(state->words[0], 22, 23)) { disasm_instr()
245 if (FIELD_C(state->words[0]) == REG_LIMM) disasm_instr()
246 state->instr_len += 4; disasm_instr()
253 if ((!IS_BIT(state->words[0], 5)) && disasm_instr()
254 (FIELD_C(state->words[0]) == REG_LIMM)) disasm_instr()
255 state->instr_len += 4; disasm_instr()
264 switch (BITS(state->words[0], 22, 23)) { disasm_instr()
266 if ((FIELD_B(state->words[0]) == REG_LIMM) || disasm_instr()
267 (FIELD_C(state->words[0]) == REG_LIMM)) disasm_instr()
268 state->instr_len += 4; disasm_instr()
275 if ((!IS_BIT(state->words[0], 5)) && disasm_instr()
276 ((FIELD_B(state->words[0]) == REG_LIMM) || disasm_instr()
277 (FIELD_C(state->words[0]) == REG_LIMM))) disasm_instr()
278 state->instr_len += 4; disasm_instr()
287 state->zz = BITS(state->words[0], 3, 4); disasm_instr()
288 state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); disasm_instr()
289 state->src2 = get_reg(FIELD_S_C(state->words[0]), regs, cregs); disasm_instr()
290 state->dest = FIELD_S_A(state->words[0]); disasm_instr()
295 if ((BITS(state->words[0], 3, 4) < 3) && disasm_instr()
296 (FIELD_S_H(state->words[0]) == REG_LIMM)) disasm_instr()
297 state->instr_len += 4; disasm_instr()
301 subopcode = BITS(state->words[0], 5, 7); disasm_instr()
307 state->target = get_reg(FIELD_S_B(state->words[0]), disasm_instr()
309 state->delay_slot = subopcode & 1; disasm_instr()
310 state->flow = (subopcode >= 2) ? disasm_instr()
314 switch (BITS(state->words[0], 8, 10)) { disasm_instr()
319 state->delay_slot = (subopcode == 7); disasm_instr()
320 state->flow = indirect_jump; disasm_instr()
321 state->target = get_reg(31, regs, cregs); disasm_instr()
331 state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); disasm_instr()
332 state->src2 = FIELD_S_u7(state->words[0]); disasm_instr()
333 state->dest = FIELD_S_C(state->words[0]); disasm_instr()
340 state->zz = 1; disasm_instr()
344 state->x = 1; disasm_instr()
348 state->zz = 2; disasm_instr()
349 state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); disasm_instr()
350 state->src2 = FIELD_S_u6(state->words[0]); disasm_instr()
351 state->dest = FIELD_S_C(state->words[0]); disasm_instr()
355 state->write = 1; disasm_instr()
356 state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs); disasm_instr()
357 state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); disasm_instr()
358 state->src3 = FIELD_S_u7(state->words[0]); disasm_instr()
362 state->write = 1; disasm_instr()
363 state->zz = 2; disasm_instr()
364 state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs); disasm_instr()
365 state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); disasm_instr()
366 state->src3 = FIELD_S_u6(state->words[0]); disasm_instr()
373 state->write = BITS(state->words[0], 6, 6); disasm_instr()
374 state->zz = BITS(state->words[0], 5, 5); disasm_instr()
375 if (state->zz) disasm_instr()
377 if (!state->write) { disasm_instr()
378 state->src1 = get_reg(28, regs, cregs); disasm_instr()
379 state->src2 = FIELD_S_u7(state->words[0]); disasm_instr()
380 state->dest = FIELD_S_B(state->words[0]); disasm_instr()
382 state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, disasm_instr()
384 state->src2 = get_reg(28, regs, cregs); disasm_instr()
385 state->src3 = FIELD_S_u7(state->words[0]); disasm_instr()
391 state->zz = BITS(state->words[0], 9, 10); disasm_instr()
392 state->src1 = get_reg(26, regs, cregs); disasm_instr()
393 state->src2 = state->zz ? FIELD_S_s10(state->words[0]) : disasm_instr()
394 FIELD_S_s11(state->words[0]); disasm_instr()
395 state->dest = 0; disasm_instr()
399 state->src1 = regs->ret & ~3; disasm_instr()
400 state->src2 = FIELD_S_u10(state->words[0]); disasm_instr()
401 state->dest = FIELD_S_B(state->words[0]); disasm_instr()
405 state->target = FIELD_S_s8(state->words[0]) + (addr & ~0x03); disasm_instr()
406 state->flow = direct_jump; disasm_instr()
407 state->is_branch = 1; disasm_instr()
411 fieldA = (BITS(state->words[0], 9, 10) == 3) ? disasm_instr()
412 FIELD_S_s7(state->words[0]) : disasm_instr()
413 FIELD_S_s10(state->words[0]); disasm_instr()
414 state->target = fieldA + (addr & ~0x03); disasm_instr()
415 state->flow = direct_jump; disasm_instr()
416 state->is_branch = 1; disasm_instr()
420 state->target = FIELD_S_s13(state->words[0]) + (addr & ~0x03); disasm_instr()
421 state->flow = direct_call; disasm_instr()
422 state->is_branch = 1; disasm_instr()
429 if (bytes_not_copied <= (8 - state->instr_len)) disasm_instr()
432 fault: state->fault = 1; disasm_instr()
H A Dunaligned.c136 static void fixup_load(struct disasm_state *state, struct pt_regs *regs, fixup_load() argument
142 if ((state->aa == 1) || (state->aa == 2)) { fixup_load()
143 set_reg(state->wb_reg, state->src1 + state->src2, regs, cregs); fixup_load()
145 if (state->aa == 2) fixup_load()
146 state->src2 = 0; fixup_load()
149 if (state->zz == 0) { fixup_load()
150 get32_unaligned_check(val, state->src1 + state->src2); fixup_load()
152 get16_unaligned_check(val, state->src1 + state->src2); fixup_load()
154 if (state->x) fixup_load()
158 if (state->pref == 0) fixup_load()
159 set_reg(state->dest, val, regs, cregs); fixup_load()
163 fault: state->fault = 1; fixup_load()
166 static void fixup_store(struct disasm_state *state, struct pt_regs *regs, fixup_store() argument
170 if ((state->aa == 1) || (state->aa == 2)) { fixup_store()
171 set_reg(state->wb_reg, state->src2 + state->src3, regs, cregs); fixup_store()
173 if (state->aa == 3) fixup_store()
174 state->src3 = 0; fixup_store()
175 } else if (state->aa == 3) { fixup_store()
176 if (state->zz == 2) { fixup_store()
177 set_reg(state->wb_reg, state->src2 + (state->src3 << 1), fixup_store()
179 } else if (!state->zz) { fixup_store()
180 set_reg(state->wb_reg, state->src2 + (state->src3 << 2), fixup_store()
188 if (!state->zz) fixup_store()
189 put32_unaligned_check(state->src1, state->src2 + state->src3); fixup_store()
191 put16_unaligned_check(state->src1, state->src2 + state->src3); fixup_store()
195 fault: state->fault = 1; fixup_store()
205 struct disasm_state state; misaligned_fixup() local
227 disasm_instr(regs->ret, &state, 1, regs, cregs); misaligned_fixup()
229 if (state.fault) misaligned_fixup()
233 if ((state.zz == 1) || (state.di)) misaligned_fixup()
236 if (!state.write) misaligned_fixup()
237 fixup_load(&state, regs, cregs); misaligned_fixup()
239 fixup_store(&state, regs, cregs); misaligned_fixup()
241 if (state.fault) misaligned_fixup()
248 regs->ret += state.instr_len; misaligned_fixup()
262 state.words[0], address); misaligned_fixup()
/linux-4.1.27/arch/arm64/include/asm/
H A Dfpsimdmacros.h2 * FP/SIMD state saving and restoring macros
20 .macro fpsimd_save state, tmpnr
21 stp q0, q1, [\state, #16 * 0]
22 stp q2, q3, [\state, #16 * 2]
23 stp q4, q5, [\state, #16 * 4]
24 stp q6, q7, [\state, #16 * 6]
25 stp q8, q9, [\state, #16 * 8]
26 stp q10, q11, [\state, #16 * 10]
27 stp q12, q13, [\state, #16 * 12]
28 stp q14, q15, [\state, #16 * 14]
29 stp q16, q17, [\state, #16 * 16]
30 stp q18, q19, [\state, #16 * 18]
31 stp q20, q21, [\state, #16 * 20]
32 stp q22, q23, [\state, #16 * 22]
33 stp q24, q25, [\state, #16 * 24]
34 stp q26, q27, [\state, #16 * 26]
35 stp q28, q29, [\state, #16 * 28]
36 stp q30, q31, [\state, #16 * 30]!
38 str w\tmpnr, [\state, #16 * 2]
40 str w\tmpnr, [\state, #16 * 2 + 4]
43 .macro fpsimd_restore_fpcr state, tmp
49 cmp \tmp, \state
51 msr fpcr, \state
55 /* Clobbers \state */
56 .macro fpsimd_restore state, tmpnr
57 ldp q0, q1, [\state, #16 * 0]
58 ldp q2, q3, [\state, #16 * 2]
59 ldp q4, q5, [\state, #16 * 4]
60 ldp q6, q7, [\state, #16 * 6]
61 ldp q8, q9, [\state, #16 * 8]
62 ldp q10, q11, [\state, #16 * 10]
63 ldp q12, q13, [\state, #16 * 12]
64 ldp q14, q15, [\state, #16 * 14]
65 ldp q16, q17, [\state, #16 * 16]
66 ldp q18, q19, [\state, #16 * 18]
67 ldp q20, q21, [\state, #16 * 20]
68 ldp q22, q23, [\state, #16 * 22]
69 ldp q24, q25, [\state, #16 * 24]
70 ldp q26, q27, [\state, #16 * 26]
71 ldp q28, q29, [\state, #16 * 28]
72 ldp q30, q31, [\state, #16 * 30]!
73 ldr w\tmpnr, [\state, #16 * 2]
75 ldr w\tmpnr, [\state, #16 * 2 + 4]
76 fpsimd_restore_fpcr x\tmpnr, \state
79 .macro fpsimd_save_partial state, numnr, tmpnr1, tmpnr2
81 str w\numnr, [\state, #8]
83 stp w\tmpnr1, w\tmpnr2, [\state]
85 add \state, \state, x\numnr, lsl #4 variable
88 stp q30, q31, [\state, #-16 * 30 - 16]
89 stp q28, q29, [\state, #-16 * 28 - 16]
90 stp q26, q27, [\state, #-16 * 26 - 16]
91 stp q24, q25, [\state, #-16 * 24 - 16]
92 stp q22, q23, [\state, #-16 * 22 - 16]
93 stp q20, q21, [\state, #-16 * 20 - 16]
94 stp q18, q19, [\state, #-16 * 18 - 16]
95 stp q16, q17, [\state, #-16 * 16 - 16]
96 stp q14, q15, [\state, #-16 * 14 - 16]
97 stp q12, q13, [\state, #-16 * 12 - 16]
98 stp q10, q11, [\state, #-16 * 10 - 16]
99 stp q8, q9, [\state, #-16 * 8 - 16]
100 stp q6, q7, [\state, #-16 * 6 - 16]
101 stp q4, q5, [\state, #-16 * 4 - 16]
102 stp q2, q3, [\state, #-16 * 2 - 16]
103 stp q0, q1, [\state, #-16 * 0 - 16]
107 .macro fpsimd_restore_partial state, tmpnr1, tmpnr2
108 ldp w\tmpnr1, w\tmpnr2, [\state]
112 ldr w\tmpnr2, [\state, #8]
113 add \state, \state, x\tmpnr2, lsl #4 variable
116 ldp q30, q31, [\state, #-16 * 30 - 16]
117 ldp q28, q29, [\state, #-16 * 28 - 16]
118 ldp q26, q27, [\state, #-16 * 26 - 16]
119 ldp q24, q25, [\state, #-16 * 24 - 16]
120 ldp q22, q23, [\state, #-16 * 22 - 16]
121 ldp q20, q21, [\state, #-16 * 20 - 16]
122 ldp q18, q19, [\state, #-16 * 18 - 16]
123 ldp q16, q17, [\state, #-16 * 16 - 16]
124 ldp q14, q15, [\state, #-16 * 14 - 16]
125 ldp q12, q13, [\state, #-16 * 12 - 16]
126 ldp q10, q11, [\state, #-16 * 10 - 16]
127 ldp q8, q9, [\state, #-16 * 8 - 16]
128 ldp q6, q7, [\state, #-16 * 6 - 16]
129 ldp q4, q5, [\state, #-16 * 4 - 16]
130 ldp q2, q3, [\state, #-16 * 2 - 16]
131 ldp q0, q1, [\state, #-16 * 0 - 16]
/linux-4.1.27/drivers/video/
H A Dvgastate.c2 * linux/drivers/video/vgastate.c -- VGA state save/restore
48 static void save_vga_text(struct vgastate *state, void __iomem *fbbase) save_vga_text() argument
50 struct regstate *saved = (struct regstate *) state->vidstate; save_vga_text()
56 misc = vga_r(state->vgabase, VGA_MIS_R); save_vga_text()
59 vga_r(state->vgabase, iobase + 0xa); save_vga_text()
60 vga_w(state->vgabase, VGA_ATT_W, 0x00); save_vga_text()
61 attr10 = vga_rattr(state->vgabase, 0x10); save_vga_text()
62 vga_r(state->vgabase, iobase + 0xa); save_vga_text()
63 vga_w(state->vgabase, VGA_ATT_W, 0x20); save_vga_text()
69 gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ); save_vga_text()
70 gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE); save_vga_text()
71 gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC); save_vga_text()
72 seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE); save_vga_text()
73 seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE); save_vga_text()
76 seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE); save_vga_text()
77 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); save_vga_text()
78 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 | 1 << 5); save_vga_text()
79 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3); save_vga_text()
82 if (state->flags & VGA_SAVE_FONT0) { save_vga_text()
83 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x4); save_vga_text()
84 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); save_vga_text()
85 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x2); save_vga_text()
86 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); save_vga_text()
87 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); save_vga_text()
93 if (state->flags & VGA_SAVE_FONT1) { save_vga_text()
94 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x8); save_vga_text()
95 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); save_vga_text()
96 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x3); save_vga_text()
97 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); save_vga_text()
98 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); save_vga_text()
99 for (i = 0; i < state->memsize; i++) save_vga_text()
104 if (state->flags & VGA_SAVE_TEXT) { save_vga_text()
105 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x1); save_vga_text()
106 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); save_vga_text()
107 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x0); save_vga_text()
108 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); save_vga_text()
109 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); save_vga_text()
113 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x2); save_vga_text()
114 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); save_vga_text()
115 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x1); save_vga_text()
116 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); save_vga_text()
117 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); save_vga_text()
123 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2); save_vga_text()
124 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4); save_vga_text()
126 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4); save_vga_text()
127 vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5); save_vga_text()
128 vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6); save_vga_text()
131 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); save_vga_text()
132 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 & ~(1 << 5)); save_vga_text()
133 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3); save_vga_text()
135 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1); save_vga_text()
138 static void restore_vga_text(struct vgastate *state, void __iomem *fbbase) restore_vga_text() argument
140 struct regstate *saved = (struct regstate *) state->vidstate; restore_vga_text()
146 gr1 = vga_rgfx(state->vgabase, VGA_GFX_SR_ENABLE); restore_vga_text()
147 gr3 = vga_rgfx(state->vgabase, VGA_GFX_DATA_ROTATE); restore_vga_text()
148 gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ); restore_vga_text()
149 gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE); restore_vga_text()
150 gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC); restore_vga_text()
151 gr8 = vga_rgfx(state->vgabase, VGA_GFX_BIT_MASK); restore_vga_text()
152 seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE); restore_vga_text()
153 seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE); restore_vga_text()
156 seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE); restore_vga_text()
157 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); restore_vga_text()
158 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 | 1 << 5); restore_vga_text()
159 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3); restore_vga_text()
161 if (state->depth == 4) { restore_vga_text()
162 vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, 0x0); restore_vga_text()
163 vga_wgfx(state->vgabase, VGA_GFX_BIT_MASK, 0xff); restore_vga_text()
164 vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, 0x00); restore_vga_text()
168 if (state->flags & VGA_SAVE_FONT0) { restore_vga_text()
169 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x4); restore_vga_text()
170 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); restore_vga_text()
171 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x2); restore_vga_text()
172 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); restore_vga_text()
173 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); restore_vga_text()
179 if (state->flags & VGA_SAVE_FONT1) { restore_vga_text()
180 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x8); restore_vga_text()
181 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); restore_vga_text()
182 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x3); restore_vga_text()
183 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); restore_vga_text()
184 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); restore_vga_text()
185 for (i = 0; i < state->memsize; i++) restore_vga_text()
190 if (state->flags & VGA_SAVE_TEXT) { restore_vga_text()
191 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x1); restore_vga_text()
192 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); restore_vga_text()
193 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x0); restore_vga_text()
194 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); restore_vga_text()
195 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); restore_vga_text()
199 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x2); restore_vga_text()
200 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6); restore_vga_text()
201 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x1); restore_vga_text()
202 vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0); restore_vga_text()
203 vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5); restore_vga_text()
209 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1); restore_vga_text()
210 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 & ~(1 << 5)); restore_vga_text()
211 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3); restore_vga_text()
214 vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, gr1); restore_vga_text()
215 vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, gr3); restore_vga_text()
216 vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4); restore_vga_text()
217 vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5); restore_vga_text()
218 vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6); restore_vga_text()
219 vga_wgfx(state->vgabase, VGA_GFX_BIT_MASK, gr8); restore_vga_text()
221 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1); restore_vga_text()
222 vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2); restore_vga_text()
223 vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4); restore_vga_text()
226 static void save_vga_mode(struct vgastate *state) save_vga_mode() argument
228 struct regstate *saved = (struct regstate *) state->vidstate; save_vga_mode()
232 saved->misc = vga_r(state->vgabase, VGA_MIS_R); save_vga_mode()
238 for (i = 0; i < state->num_crtc; i++) save_vga_mode()
239 saved->crtc[i] = vga_rcrtcs(state->vgabase, iobase, i); save_vga_mode()
241 vga_r(state->vgabase, iobase + 0xa); save_vga_mode()
242 vga_w(state->vgabase, VGA_ATT_W, 0x00); save_vga_mode()
243 for (i = 0; i < state->num_attr; i++) { save_vga_mode()
244 vga_r(state->vgabase, iobase + 0xa); save_vga_mode()
245 saved->attr[i] = vga_rattr(state->vgabase, i); save_vga_mode()
247 vga_r(state->vgabase, iobase + 0xa); save_vga_mode()
248 vga_w(state->vgabase, VGA_ATT_W, 0x20); save_vga_mode()
250 for (i = 0; i < state->num_gfx; i++) save_vga_mode()
251 saved->gfx[i] = vga_rgfx(state->vgabase, i); save_vga_mode()
253 for (i = 0; i < state->num_seq; i++) save_vga_mode()
254 saved->seq[i] = vga_rseq(state->vgabase, i); save_vga_mode()
257 static void restore_vga_mode(struct vgastate *state) restore_vga_mode() argument
259 struct regstate *saved = (struct regstate *) state->vidstate; restore_vga_mode()
263 vga_w(state->vgabase, VGA_MIS_W, saved->misc); restore_vga_mode()
271 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, restore_vga_mode()
275 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x01); restore_vga_mode()
278 vga_r(state->vgabase, iobase + 0xa); restore_vga_mode()
279 vga_w(state->vgabase, VGA_ATT_W, 0x00); restore_vga_mode()
281 for (i = 2; i < state->num_seq; i++) restore_vga_mode()
282 vga_wseq(state->vgabase, i, saved->seq[i]); restore_vga_mode()
286 vga_wcrtcs(state->vgabase, iobase, 17, saved->crtc[17] & ~0x80); restore_vga_mode()
287 for (i = 0; i < state->num_crtc; i++) restore_vga_mode()
288 vga_wcrtcs(state->vgabase, iobase, i, saved->crtc[i]); restore_vga_mode()
290 for (i = 0; i < state->num_gfx; i++) restore_vga_mode()
291 vga_wgfx(state->vgabase, i, saved->gfx[i]); restore_vga_mode()
293 for (i = 0; i < state->num_attr; i++) { restore_vga_mode()
294 vga_r(state->vgabase, iobase + 0xa); restore_vga_mode()
295 vga_wattr(state->vgabase, i, saved->attr[i]); restore_vga_mode()
299 vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x03); restore_vga_mode()
301 vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, restore_vga_mode()
305 vga_r(state->vgabase, iobase + 0xa); restore_vga_mode()
306 vga_w(state->vgabase, VGA_ATT_W, 0x20); restore_vga_mode()
309 static void save_vga_cmap(struct vgastate *state) save_vga_cmap() argument
311 struct regstate *saved = (struct regstate *) state->vidstate; save_vga_cmap()
314 vga_w(state->vgabase, VGA_PEL_MSK, 0xff); save_vga_cmap()
317 vga_w(state->vgabase, VGA_PEL_IR, 0x00); save_vga_cmap()
319 saved->vga_cmap[i] = vga_r(state->vgabase, VGA_PEL_D); save_vga_cmap()
322 static void restore_vga_cmap(struct vgastate *state) restore_vga_cmap() argument
324 struct regstate *saved = (struct regstate *) state->vidstate; restore_vga_cmap()
327 vga_w(state->vgabase, VGA_PEL_MSK, 0xff); restore_vga_cmap()
330 vga_w(state->vgabase, VGA_PEL_IW, 0x00); restore_vga_cmap()
332 vga_w(state->vgabase, VGA_PEL_D, saved->vga_cmap[i]); restore_vga_cmap()
335 static void vga_cleanup(struct vgastate *state) vga_cleanup() argument
337 if (state->vidstate != NULL) { vga_cleanup()
338 struct regstate *saved = (struct regstate *) state->vidstate; vga_cleanup()
346 state->vidstate = NULL; vga_cleanup()
350 int save_vga(struct vgastate *state) save_vga() argument
359 state->vidstate = (void *)saved; save_vga()
361 if (state->flags & VGA_SAVE_CMAP) { save_vga()
364 vga_cleanup(state); save_vga()
367 save_vga_cmap(state); save_vga()
370 if (state->flags & VGA_SAVE_MODE) { save_vga()
373 if (state->num_attr < 21) save_vga()
374 state->num_attr = 21; save_vga()
375 if (state->num_crtc < 25) save_vga()
376 state->num_crtc = 25; save_vga()
377 if (state->num_gfx < 9) save_vga()
378 state->num_gfx = 9; save_vga()
379 if (state->num_seq < 5) save_vga()
380 state->num_seq = 5; save_vga()
381 total = state->num_attr + state->num_crtc + save_vga()
382 state->num_gfx + state->num_seq; save_vga()
386 vga_cleanup(state); save_vga()
389 saved->crtc = saved->attr + state->num_attr; save_vga()
390 saved->gfx = saved->crtc + state->num_crtc; save_vga()
391 saved->seq = saved->gfx + state->num_gfx; save_vga()
393 save_vga_mode(state); save_vga()
396 if (state->flags & VGA_SAVE_FONTS) { save_vga()
400 if (state->memsize && state->memsize < 4 * 8192) { save_vga()
401 vga_cleanup(state); save_vga()
404 if (!state->memsize) save_vga()
405 state->memsize = 8 * 8192; save_vga()
407 if (!state->membase) save_vga()
408 state->membase = 0xA0000; save_vga()
410 fbbase = ioremap(state->membase, state->memsize); save_vga()
413 vga_cleanup(state); save_vga()
420 if (state->flags & VGA_SAVE_FONT0) { save_vga()
424 vga_cleanup(state); save_vga()
432 if (state->flags & VGA_SAVE_FONT1) { save_vga()
433 saved->vga_font1 = vmalloc(state->memsize); save_vga()
436 vga_cleanup(state); save_vga()
443 if (state->flags & VGA_SAVE_TEXT) { save_vga()
447 vga_cleanup(state); save_vga()
452 save_vga_text(state, fbbase); save_vga()
458 int restore_vga (struct vgastate *state) restore_vga() argument
460 if (state->vidstate == NULL) restore_vga()
463 if (state->flags & VGA_SAVE_MODE) restore_vga()
464 restore_vga_mode(state); restore_vga()
466 if (state->flags & VGA_SAVE_FONTS) { restore_vga()
467 void __iomem *fbbase = ioremap(state->membase, state->memsize); restore_vga()
470 vga_cleanup(state); restore_vga()
473 restore_vga_text(state, fbbase); restore_vga()
477 if (state->flags & VGA_SAVE_CMAP) restore_vga()
478 restore_vga_cmap(state); restore_vga()
480 vga_cleanup(state); restore_vga()
/linux-4.1.27/drivers/media/tuners/
H A Dmxl5005s.c298 static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
339 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_SetRfFreqHz() local
354 ByteTable[0] |= state->config->AgcMasterByte; mxl5005s_SetRfFreqHz()
371 state->config->AgcMasterByte; mxl5005s_SetRfFreqHz()
387 state->config->AgcMasterByte ; mxl5005s_SetRfFreqHz()
404 struct mxl5005s_state *state = fe->tuner_priv; MXL5005_RegisterInit() local
405 state->TunerRegs_Num = TUNER_REGS_NUM ; MXL5005_RegisterInit()
407 state->TunerRegs[0].Reg_Num = 9 ; MXL5005_RegisterInit()
408 state->TunerRegs[0].Reg_Val = 0x40 ; MXL5005_RegisterInit()
410 state->TunerRegs[1].Reg_Num = 11 ; MXL5005_RegisterInit()
411 state->TunerRegs[1].Reg_Val = 0x19 ; MXL5005_RegisterInit()
413 state->TunerRegs[2].Reg_Num = 12 ; MXL5005_RegisterInit()
414 state->TunerRegs[2].Reg_Val = 0x60 ; MXL5005_RegisterInit()
416 state->TunerRegs[3].Reg_Num = 13 ; MXL5005_RegisterInit()
417 state->TunerRegs[3].Reg_Val = 0x00 ; MXL5005_RegisterInit()
419 state->TunerRegs[4].Reg_Num = 14 ; MXL5005_RegisterInit()
420 state->TunerRegs[4].Reg_Val = 0x00 ; MXL5005_RegisterInit()
422 state->TunerRegs[5].Reg_Num = 15 ; MXL5005_RegisterInit()
423 state->TunerRegs[5].Reg_Val = 0xC0 ; MXL5005_RegisterInit()
425 state->TunerRegs[6].Reg_Num = 16 ; MXL5005_RegisterInit()
426 state->TunerRegs[6].Reg_Val = 0x00 ; MXL5005_RegisterInit()
428 state->TunerRegs[7].Reg_Num = 17 ; MXL5005_RegisterInit()
429 state->TunerRegs[7].Reg_Val = 0x00 ; MXL5005_RegisterInit()
431 state->TunerRegs[8].Reg_Num = 18 ; MXL5005_RegisterInit()
432 state->TunerRegs[8].Reg_Val = 0x00 ; MXL5005_RegisterInit()
434 state->TunerRegs[9].Reg_Num = 19 ; MXL5005_RegisterInit()
435 state->TunerRegs[9].Reg_Val = 0x34 ; MXL5005_RegisterInit()
437 state->TunerRegs[10].Reg_Num = 21 ; MXL5005_RegisterInit()
438 state->TunerRegs[10].Reg_Val = 0x00 ; MXL5005_RegisterInit()
440 state->TunerRegs[11].Reg_Num = 22 ; MXL5005_RegisterInit()
441 state->TunerRegs[11].Reg_Val = 0x6B ; MXL5005_RegisterInit()
443 state->TunerRegs[12].Reg_Num = 23 ; MXL5005_RegisterInit()
444 state->TunerRegs[12].Reg_Val = 0x35 ; MXL5005_RegisterInit()
446 state->TunerRegs[13].Reg_Num = 24 ; MXL5005_RegisterInit()
447 state->TunerRegs[13].Reg_Val = 0x70 ; MXL5005_RegisterInit()
449 state->TunerRegs[14].Reg_Num = 25 ; MXL5005_RegisterInit()
450 state->TunerRegs[14].Reg_Val = 0x3E ; MXL5005_RegisterInit()
452 state->TunerRegs[15].Reg_Num = 26 ; MXL5005_RegisterInit()
453 state->TunerRegs[15].Reg_Val = 0x82 ; MXL5005_RegisterInit()
455 state->TunerRegs[16].Reg_Num = 31 ; MXL5005_RegisterInit()
456 state->TunerRegs[16].Reg_Val = 0x00 ; MXL5005_RegisterInit()
458 state->TunerRegs[17].Reg_Num = 32 ; MXL5005_RegisterInit()
459 state->TunerRegs[17].Reg_Val = 0x40 ; MXL5005_RegisterInit()
461 state->TunerRegs[18].Reg_Num = 33 ; MXL5005_RegisterInit()
462 state->TunerRegs[18].Reg_Val = 0x53 ; MXL5005_RegisterInit()
464 state->TunerRegs[19].Reg_Num = 34 ; MXL5005_RegisterInit()
465 state->TunerRegs[19].Reg_Val = 0x81 ; MXL5005_RegisterInit()
467 state->TunerRegs[20].Reg_Num = 35 ; MXL5005_RegisterInit()
468 state->TunerRegs[20].Reg_Val = 0xC9 ; MXL5005_RegisterInit()
470 state->TunerRegs[21].Reg_Num = 36 ; MXL5005_RegisterInit()
471 state->TunerRegs[21].Reg_Val = 0x01 ; MXL5005_RegisterInit()
473 state->TunerRegs[22].Reg_Num = 37 ; MXL5005_RegisterInit()
474 state->TunerRegs[22].Reg_Val = 0x00 ; MXL5005_RegisterInit()
476 state->TunerRegs[23].Reg_Num = 41 ; MXL5005_RegisterInit()
477 state->TunerRegs[23].Reg_Val = 0x00 ; MXL5005_RegisterInit()
479 state->TunerRegs[24].Reg_Num = 42 ; MXL5005_RegisterInit()
480 state->TunerRegs[24].Reg_Val = 0xF8 ; MXL5005_RegisterInit()
482 state->TunerRegs[25].Reg_Num = 43 ; MXL5005_RegisterInit()
483 state->TunerRegs[25].Reg_Val = 0x43 ; MXL5005_RegisterInit()
485 state->TunerRegs[26].Reg_Num = 44 ; MXL5005_RegisterInit()
486 state->TunerRegs[26].Reg_Val = 0x20 ; MXL5005_RegisterInit()
488 state->TunerRegs[27].Reg_Num = 45 ; MXL5005_RegisterInit()
489 state->TunerRegs[27].Reg_Val = 0x80 ; MXL5005_RegisterInit()
491 state->TunerRegs[28].Reg_Num = 46 ; MXL5005_RegisterInit()
492 state->TunerRegs[28].Reg_Val = 0x88 ; MXL5005_RegisterInit()
494 state->TunerRegs[29].Reg_Num = 47 ; MXL5005_RegisterInit()
495 state->TunerRegs[29].Reg_Val = 0x86 ; MXL5005_RegisterInit()
497 state->TunerRegs[30].Reg_Num = 48 ; MXL5005_RegisterInit()
498 state->TunerRegs[30].Reg_Val = 0x00 ; MXL5005_RegisterInit()
500 state->TunerRegs[31].Reg_Num = 49 ; MXL5005_RegisterInit()
501 state->TunerRegs[31].Reg_Val = 0x00 ; MXL5005_RegisterInit()
503 state->TunerRegs[32].Reg_Num = 53 ; MXL5005_RegisterInit()
504 state->TunerRegs[32].Reg_Val = 0x94 ; MXL5005_RegisterInit()
506 state->TunerRegs[33].Reg_Num = 54 ; MXL5005_RegisterInit()
507 state->TunerRegs[33].Reg_Val = 0xFA ; MXL5005_RegisterInit()
509 state->TunerRegs[34].Reg_Num = 55 ; MXL5005_RegisterInit()
510 state->TunerRegs[34].Reg_Val = 0x92 ; MXL5005_RegisterInit()
512 state->TunerRegs[35].Reg_Num = 56 ; MXL5005_RegisterInit()
513 state->TunerRegs[35].Reg_Val = 0x80 ; MXL5005_RegisterInit()
515 state->TunerRegs[36].Reg_Num = 57 ; MXL5005_RegisterInit()
516 state->TunerRegs[36].Reg_Val = 0x41 ; MXL5005_RegisterInit()
518 state->TunerRegs[37].Reg_Num = 58 ; MXL5005_RegisterInit()
519 state->TunerRegs[37].Reg_Val = 0xDB ; MXL5005_RegisterInit()
521 state->TunerRegs[38].Reg_Num = 59 ; MXL5005_RegisterInit()
522 state->TunerRegs[38].Reg_Val = 0x00 ; MXL5005_RegisterInit()
524 state->TunerRegs[39].Reg_Num = 60 ; MXL5005_RegisterInit()
525 state->TunerRegs[39].Reg_Val = 0x00 ; MXL5005_RegisterInit()
527 state->TunerRegs[40].Reg_Num = 61 ; MXL5005_RegisterInit()
528 state->TunerRegs[40].Reg_Val = 0x00 ; MXL5005_RegisterInit()
530 state->TunerRegs[41].Reg_Num = 62 ; MXL5005_RegisterInit()
531 state->TunerRegs[41].Reg_Val = 0x00 ; MXL5005_RegisterInit()
533 state->TunerRegs[42].Reg_Num = 65 ; MXL5005_RegisterInit()
534 state->TunerRegs[42].Reg_Val = 0xF8 ; MXL5005_RegisterInit()
536 state->TunerRegs[43].Reg_Num = 66 ; MXL5005_RegisterInit()
537 state->TunerRegs[43].Reg_Val = 0xE4 ; MXL5005_RegisterInit()
539 state->TunerRegs[44].Reg_Num = 67 ; MXL5005_RegisterInit()
540 state->TunerRegs[44].Reg_Val = 0x90 ; MXL5005_RegisterInit()
542 state->TunerRegs[45].Reg_Num = 68 ; MXL5005_RegisterInit()
543 state->TunerRegs[45].Reg_Val = 0xC0 ; MXL5005_RegisterInit()
545 state->TunerRegs[46].Reg_Num = 69 ; MXL5005_RegisterInit()
546 state->TunerRegs[46].Reg_Val = 0x01 ; MXL5005_RegisterInit()
548 state->TunerRegs[47].Reg_Num = 70 ; MXL5005_RegisterInit()
549 state->TunerRegs[47].Reg_Val = 0x50 ; MXL5005_RegisterInit()
551 state->TunerRegs[48].Reg_Num = 71 ; MXL5005_RegisterInit()
552 state->TunerRegs[48].Reg_Val = 0x06 ; MXL5005_RegisterInit()
554 state->TunerRegs[49].Reg_Num = 72 ; MXL5005_RegisterInit()
555 state->TunerRegs[49].Reg_Val = 0x00 ; MXL5005_RegisterInit()
557 state->TunerRegs[50].Reg_Num = 73 ; MXL5005_RegisterInit()
558 state->TunerRegs[50].Reg_Val = 0x20 ; MXL5005_RegisterInit()
560 state->TunerRegs[51].Reg_Num = 76 ; MXL5005_RegisterInit()
561 state->TunerRegs[51].Reg_Val = 0xBB ; MXL5005_RegisterInit()
563 state->TunerRegs[52].Reg_Num = 77 ; MXL5005_RegisterInit()
564 state->TunerRegs[52].Reg_Val = 0x13 ; MXL5005_RegisterInit()
566 state->TunerRegs[53].Reg_Num = 81 ; MXL5005_RegisterInit()
567 state->TunerRegs[53].Reg_Val = 0x04 ; MXL5005_RegisterInit()
569 state->TunerRegs[54].Reg_Num = 82 ; MXL5005_RegisterInit()
570 state->TunerRegs[54].Reg_Val = 0x75 ; MXL5005_RegisterInit()
572 state->TunerRegs[55].Reg_Num = 83 ; MXL5005_RegisterInit()
573 state->TunerRegs[55].Reg_Val = 0x00 ; MXL5005_RegisterInit()
575 state->TunerRegs[56].Reg_Num = 84 ; MXL5005_RegisterInit()
576 state->TunerRegs[56].Reg_Val = 0x00 ; MXL5005_RegisterInit()
578 state->TunerRegs[57].Reg_Num = 85 ; MXL5005_RegisterInit()
579 state->TunerRegs[57].Reg_Val = 0x00 ; MXL5005_RegisterInit()
581 state->TunerRegs[58].Reg_Num = 91 ; MXL5005_RegisterInit()
582 state->TunerRegs[58].Reg_Val = 0x70 ; MXL5005_RegisterInit()
584 state->TunerRegs[59].Reg_Num = 92 ; MXL5005_RegisterInit()
585 state->TunerRegs[59].Reg_Val = 0x00 ; MXL5005_RegisterInit()
587 state->TunerRegs[60].Reg_Num = 93 ; MXL5005_RegisterInit()
588 state->TunerRegs[60].Reg_Val = 0x00 ; MXL5005_RegisterInit()
590 state->TunerRegs[61].Reg_Num = 94 ; MXL5005_RegisterInit()
591 state->TunerRegs[61].Reg_Val = 0x00 ; MXL5005_RegisterInit()
593 state->TunerRegs[62].Reg_Num = 95 ; MXL5005_RegisterInit()
594 state->TunerRegs[62].Reg_Val = 0x0C ; MXL5005_RegisterInit()
596 state->TunerRegs[63].Reg_Num = 96 ; MXL5005_RegisterInit()
597 state->TunerRegs[63].Reg_Val = 0x00 ; MXL5005_RegisterInit()
599 state->TunerRegs[64].Reg_Num = 97 ; MXL5005_RegisterInit()
600 state->TunerRegs[64].Reg_Val = 0x00 ; MXL5005_RegisterInit()
602 state->TunerRegs[65].Reg_Num = 98 ; MXL5005_RegisterInit()
603 state->TunerRegs[65].Reg_Val = 0xE2 ; MXL5005_RegisterInit()
605 state->TunerRegs[66].Reg_Num = 99 ; MXL5005_RegisterInit()
606 state->TunerRegs[66].Reg_Val = 0x00 ; MXL5005_RegisterInit()
608 state->TunerRegs[67].Reg_Num = 100 ; MXL5005_RegisterInit()
609 state->TunerRegs[67].Reg_Val = 0x00 ; MXL5005_RegisterInit()
611 state->TunerRegs[68].Reg_Num = 101 ; MXL5005_RegisterInit()
612 state->TunerRegs[68].Reg_Val = 0x12 ; MXL5005_RegisterInit()
614 state->TunerRegs[69].Reg_Num = 102 ; MXL5005_RegisterInit()
615 state->TunerRegs[69].Reg_Val = 0x80 ; MXL5005_RegisterInit()
617 state->TunerRegs[70].Reg_Num = 103 ; MXL5005_RegisterInit()
618 state->TunerRegs[70].Reg_Val = 0x32 ; MXL5005_RegisterInit()
620 state->TunerRegs[71].Reg_Num = 104 ; MXL5005_RegisterInit()
621 state->TunerRegs[71].Reg_Val = 0xB4 ; MXL5005_RegisterInit()
623 state->TunerRegs[72].Reg_Num = 105 ; MXL5005_RegisterInit()
624 state->TunerRegs[72].Reg_Val = 0x60 ; MXL5005_RegisterInit()
626 state->TunerRegs[73].Reg_Num = 106 ; MXL5005_RegisterInit()
627 state->TunerRegs[73].Reg_Val = 0x83 ; MXL5005_RegisterInit()
629 state->TunerRegs[74].Reg_Num = 107 ; MXL5005_RegisterInit()
630 state->TunerRegs[74].Reg_Val = 0x84 ; MXL5005_RegisterInit()
632 state->TunerRegs[75].Reg_Num = 108 ; MXL5005_RegisterInit()
633 state->TunerRegs[75].Reg_Val = 0x9C ; MXL5005_RegisterInit()
635 state->TunerRegs[76].Reg_Num = 109 ; MXL5005_RegisterInit()
636 state->TunerRegs[76].Reg_Val = 0x02 ; MXL5005_RegisterInit()
638 state->TunerRegs[77].Reg_Num = 110 ; MXL5005_RegisterInit()
639 state->TunerRegs[77].Reg_Val = 0x81 ; MXL5005_RegisterInit()
641 state->TunerRegs[78].Reg_Num = 111 ; MXL5005_RegisterInit()
642 state->TunerRegs[78].Reg_Val = 0xC0 ; MXL5005_RegisterInit()
644 state->TunerRegs[79].Reg_Num = 112 ; MXL5005_RegisterInit()
645 state->TunerRegs[79].Reg_Val = 0x10 ; MXL5005_RegisterInit()
647 state->TunerRegs[80].Reg_Num = 131 ; MXL5005_RegisterInit()
648 state->TunerRegs[80].Reg_Val = 0x8A ; MXL5005_RegisterInit()
650 state->TunerRegs[81].Reg_Num = 132 ; MXL5005_RegisterInit()
651 state->TunerRegs[81].Reg_Val = 0x10 ; MXL5005_RegisterInit()
653 state->TunerRegs[82].Reg_Num = 133 ; MXL5005_RegisterInit()
654 state->TunerRegs[82].Reg_Val = 0x24 ; MXL5005_RegisterInit()
656 state->TunerRegs[83].Reg_Num = 134 ; MXL5005_RegisterInit()
657 state->TunerRegs[83].Reg_Val = 0x00 ; MXL5005_RegisterInit()
659 state->TunerRegs[84].Reg_Num = 135 ; MXL5005_RegisterInit()
660 state->TunerRegs[84].Reg_Val = 0x00 ; MXL5005_RegisterInit()
662 state->TunerRegs[85].Reg_Num = 136 ; MXL5005_RegisterInit()
663 state->TunerRegs[85].Reg_Val = 0x7E ; MXL5005_RegisterInit()
665 state->TunerRegs[86].Reg_Num = 137 ; MXL5005_RegisterInit()
666 state->TunerRegs[86].Reg_Val = 0x40 ; MXL5005_RegisterInit()
668 state->TunerRegs[87].Reg_Num = 138 ; MXL5005_RegisterInit()
669 state->TunerRegs[87].Reg_Val = 0x38 ; MXL5005_RegisterInit()
671 state->TunerRegs[88].Reg_Num = 146 ; MXL5005_RegisterInit()
672 state->TunerRegs[88].Reg_Val = 0xF6 ; MXL5005_RegisterInit()
674 state->TunerRegs[89].Reg_Num = 147 ; MXL5005_RegisterInit()
675 state->TunerRegs[89].Reg_Val = 0x1A ; MXL5005_RegisterInit()
677 state->TunerRegs[90].Reg_Num = 148 ; MXL5005_RegisterInit()
678 state->TunerRegs[90].Reg_Val = 0x62 ; MXL5005_RegisterInit()
680 state->TunerRegs[91].Reg_Num = 149 ; MXL5005_RegisterInit()
681 state->TunerRegs[91].Reg_Val = 0x33 ; MXL5005_RegisterInit()
683 state->TunerRegs[92].Reg_Num = 150 ; MXL5005_RegisterInit()
684 state->TunerRegs[92].Reg_Val = 0x80 ; MXL5005_RegisterInit()
686 state->TunerRegs[93].Reg_Num = 156 ; MXL5005_RegisterInit()
687 state->TunerRegs[93].Reg_Val = 0x56 ; MXL5005_RegisterInit()
689 state->TunerRegs[94].Reg_Num = 157 ; MXL5005_RegisterInit()
690 state->TunerRegs[94].Reg_Val = 0x17 ; MXL5005_RegisterInit()
692 state->TunerRegs[95].Reg_Num = 158 ; MXL5005_RegisterInit()
693 state->TunerRegs[95].Reg_Val = 0xA9 ; MXL5005_RegisterInit()
695 state->TunerRegs[96].Reg_Num = 159 ; MXL5005_RegisterInit()
696 state->TunerRegs[96].Reg_Val = 0x00 ; MXL5005_RegisterInit()
698 state->TunerRegs[97].Reg_Num = 160 ; MXL5005_RegisterInit()
699 state->TunerRegs[97].Reg_Val = 0x00 ; MXL5005_RegisterInit()
701 state->TunerRegs[98].Reg_Num = 161 ; MXL5005_RegisterInit()
702 state->TunerRegs[98].Reg_Val = 0x00 ; MXL5005_RegisterInit()
704 state->TunerRegs[99].Reg_Num = 162 ; MXL5005_RegisterInit()
705 state->TunerRegs[99].Reg_Val = 0x40 ; MXL5005_RegisterInit()
707 state->TunerRegs[100].Reg_Num = 166 ; MXL5005_RegisterInit()
708 state->TunerRegs[100].Reg_Val = 0xAE ; MXL5005_RegisterInit()
710 state->TunerRegs[101].Reg_Num = 167 ; MXL5005_RegisterInit()
711 state->TunerRegs[101].Reg_Val = 0x1B ; MXL5005_RegisterInit()
713 state->TunerRegs[102].Reg_Num = 168 ; MXL5005_RegisterInit()
714 state->TunerRegs[102].Reg_Val = 0xF2 ; MXL5005_RegisterInit()
716 state->TunerRegs[103].Reg_Num = 195 ; MXL5005_RegisterInit()
717 state->TunerRegs[103].Reg_Val = 0x00 ; MXL5005_RegisterInit()
724 struct mxl5005s_state *state = fe->tuner_priv; MXL5005_ControlInit() local
725 state->Init_Ctrl_Num = INITCTRL_NUM; MXL5005_ControlInit()
727 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; MXL5005_ControlInit()
728 state->Init_Ctrl[0].size = 1 ; MXL5005_ControlInit()
729 state->Init_Ctrl[0].addr[0] = 73; MXL5005_ControlInit()
730 state->Init_Ctrl[0].bit[0] = 7; MXL5005_ControlInit()
731 state->Init_Ctrl[0].val[0] = 0; MXL5005_ControlInit()
733 state->Init_Ctrl[1].Ctrl_Num = BB_MODE ; MXL5005_ControlInit()
734 state->Init_Ctrl[1].size = 1 ; MXL5005_ControlInit()
735 state->Init_Ctrl[1].addr[0] = 53; MXL5005_ControlInit()
736 state->Init_Ctrl[1].bit[0] = 2; MXL5005_ControlInit()
737 state->Init_Ctrl[1].val[0] = 1; MXL5005_ControlInit()
739 state->Init_Ctrl[2].Ctrl_Num = BB_BUF ; MXL5005_ControlInit()
740 state->Init_Ctrl[2].size = 2 ; MXL5005_ControlInit()
741 state->Init_Ctrl[2].addr[0] = 53; MXL5005_ControlInit()
742 state->Init_Ctrl[2].bit[0] = 1; MXL5005_ControlInit()
743 state->Init_Ctrl[2].val[0] = 0; MXL5005_ControlInit()
744 state->Init_Ctrl[2].addr[1] = 57; MXL5005_ControlInit()
745 state->Init_Ctrl[2].bit[1] = 0; MXL5005_ControlInit()
746 state->Init_Ctrl[2].val[1] = 1; MXL5005_ControlInit()
748 state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; MXL5005_ControlInit()
749 state->Init_Ctrl[3].size = 1 ; MXL5005_ControlInit()
750 state->Init_Ctrl[3].addr[0] = 53; MXL5005_ControlInit()
751 state->Init_Ctrl[3].bit[0] = 0; MXL5005_ControlInit()
752 state->Init_Ctrl[3].val[0] = 0; MXL5005_ControlInit()
754 state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; MXL5005_ControlInit()
755 state->Init_Ctrl[4].size = 3 ; MXL5005_ControlInit()
756 state->Init_Ctrl[4].addr[0] = 53; MXL5005_ControlInit()
757 state->Init_Ctrl[4].bit[0] = 5; MXL5005_ControlInit()
758 state->Init_Ctrl[4].val[0] = 0; MXL5005_ControlInit()
759 state->Init_Ctrl[4].addr[1] = 53; MXL5005_ControlInit()
760 state->Init_Ctrl[4].bit[1] = 6; MXL5005_ControlInit()
761 state->Init_Ctrl[4].val[1] = 0; MXL5005_ControlInit()
762 state->Init_Ctrl[4].addr[2] = 53; MXL5005_ControlInit()
763 state->Init_Ctrl[4].bit[2] = 7; MXL5005_ControlInit()
764 state->Init_Ctrl[4].val[2] = 1; MXL5005_ControlInit()
766 state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; MXL5005_ControlInit()
767 state->Init_Ctrl[5].size = 1 ; MXL5005_ControlInit()
768 state->Init_Ctrl[5].addr[0] = 59; MXL5005_ControlInit()
769 state->Init_Ctrl[5].bit[0] = 0; MXL5005_ControlInit()
770 state->Init_Ctrl[5].val[0] = 0; MXL5005_ControlInit()
772 state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; MXL5005_ControlInit()
773 state->Init_Ctrl[6].size = 2 ; MXL5005_ControlInit()
774 state->Init_Ctrl[6].addr[0] = 53; MXL5005_ControlInit()
775 state->Init_Ctrl[6].bit[0] = 3; MXL5005_ControlInit()
776 state->Init_Ctrl[6].val[0] = 0; MXL5005_ControlInit()
777 state->Init_Ctrl[6].addr[1] = 53; MXL5005_ControlInit()
778 state->Init_Ctrl[6].bit[1] = 4; MXL5005_ControlInit()
779 state->Init_Ctrl[6].val[1] = 1; MXL5005_ControlInit()
781 state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; MXL5005_ControlInit()
782 state->Init_Ctrl[7].size = 4 ; MXL5005_ControlInit()
783 state->Init_Ctrl[7].addr[0] = 22; MXL5005_ControlInit()
784 state->Init_Ctrl[7].bit[0] = 4; MXL5005_ControlInit()
785 state->Init_Ctrl[7].val[0] = 0; MXL5005_ControlInit()
786 state->Init_Ctrl[7].addr[1] = 22; MXL5005_ControlInit()
787 state->Init_Ctrl[7].bit[1] = 5; MXL5005_ControlInit()
788 state->Init_Ctrl[7].val[1] = 1; MXL5005_ControlInit()
789 state->Init_Ctrl[7].addr[2] = 22; MXL5005_ControlInit()
790 state->Init_Ctrl[7].bit[2] = 6; MXL5005_ControlInit()
791 state->Init_Ctrl[7].val[2] = 1; MXL5005_ControlInit()
792 state->Init_Ctrl[7].addr[3] = 22; MXL5005_ControlInit()
793 state->Init_Ctrl[7].bit[3] = 7; MXL5005_ControlInit()
794 state->Init_Ctrl[7].val[3] = 0; MXL5005_ControlInit()
796 state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; MXL5005_ControlInit()
797 state->Init_Ctrl[8].size = 1 ; MXL5005_ControlInit()
798 state->Init_Ctrl[8].addr[0] = 22; MXL5005_ControlInit()
799 state->Init_Ctrl[8].bit[0] = 2; MXL5005_ControlInit()
800 state->Init_Ctrl[8].val[0] = 0; MXL5005_ControlInit()
802 state->Init_Ctrl[9].Ctrl_Num = AGC_IF ; MXL5005_ControlInit()
803 state->Init_Ctrl[9].size = 4 ; MXL5005_ControlInit()
804 state->Init_Ctrl[9].addr[0] = 76; MXL5005_ControlInit()
805 state->Init_Ctrl[9].bit[0] = 0; MXL5005_ControlInit()
806 state->Init_Ctrl[9].val[0] = 1; MXL5005_ControlInit()
807 state->Init_Ctrl[9].addr[1] = 76; MXL5005_ControlInit()
808 state->Init_Ctrl[9].bit[1] = 1; MXL5005_ControlInit()
809 state->Init_Ctrl[9].val[1] = 1; MXL5005_ControlInit()
810 state->Init_Ctrl[9].addr[2] = 76; MXL5005_ControlInit()
811 state->Init_Ctrl[9].bit[2] = 2; MXL5005_ControlInit()
812 state->Init_Ctrl[9].val[2] = 0; MXL5005_ControlInit()
813 state->Init_Ctrl[9].addr[3] = 76; MXL5005_ControlInit()
814 state->Init_Ctrl[9].bit[3] = 3; MXL5005_ControlInit()
815 state->Init_Ctrl[9].val[3] = 1; MXL5005_ControlInit()
817 state->Init_Ctrl[10].Ctrl_Num = AGC_RF ; MXL5005_ControlInit()
818 state->Init_Ctrl[10].size = 4 ; MXL5005_ControlInit()
819 state->Init_Ctrl[10].addr[0] = 76; MXL5005_ControlInit()
820 state->Init_Ctrl[10].bit[0] = 4; MXL5005_ControlInit()
821 state->Init_Ctrl[10].val[0] = 1; MXL5005_ControlInit()
822 state->Init_Ctrl[10].addr[1] = 76; MXL5005_ControlInit()
823 state->Init_Ctrl[10].bit[1] = 5; MXL5005_ControlInit()
824 state->Init_Ctrl[10].val[1] = 1; MXL5005_ControlInit()
825 state->Init_Ctrl[10].addr[2] = 76; MXL5005_ControlInit()
826 state->Init_Ctrl[10].bit[2] = 6; MXL5005_ControlInit()
827 state->Init_Ctrl[10].val[2] = 0; MXL5005_ControlInit()
828 state->Init_Ctrl[10].addr[3] = 76; MXL5005_ControlInit()
829 state->Init_Ctrl[10].bit[3] = 7; MXL5005_ControlInit()
830 state->Init_Ctrl[10].val[3] = 1; MXL5005_ControlInit()
832 state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; MXL5005_ControlInit()
833 state->Init_Ctrl[11].size = 5 ; MXL5005_ControlInit()
834 state->Init_Ctrl[11].addr[0] = 43; MXL5005_ControlInit()
835 state->Init_Ctrl[11].bit[0] = 3; MXL5005_ControlInit()
836 state->Init_Ctrl[11].val[0] = 0; MXL5005_ControlInit()
837 state->Init_Ctrl[11].addr[1] = 43; MXL5005_ControlInit()
838 state->Init_Ctrl[11].bit[1] = 4; MXL5005_ControlInit()
839 state->Init_Ctrl[11].val[1] = 0; MXL5005_ControlInit()
840 state->Init_Ctrl[11].addr[2] = 43; MXL5005_ControlInit()
841 state->Init_Ctrl[11].bit[2] = 5; MXL5005_ControlInit()
842 state->Init_Ctrl[11].val[2] = 0; MXL5005_ControlInit()
843 state->Init_Ctrl[11].addr[3] = 43; MXL5005_ControlInit()
844 state->Init_Ctrl[11].bit[3] = 6; MXL5005_ControlInit()
845 state->Init_Ctrl[11].val[3] = 1; MXL5005_ControlInit()
846 state->Init_Ctrl[11].addr[4] = 43; MXL5005_ControlInit()
847 state->Init_Ctrl[11].bit[4] = 7; MXL5005_ControlInit()
848 state->Init_Ctrl[11].val[4] = 0; MXL5005_ControlInit()
850 state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; MXL5005_ControlInit()
851 state->Init_Ctrl[12].size = 6 ; MXL5005_ControlInit()
852 state->Init_Ctrl[12].addr[0] = 44; MXL5005_ControlInit()
853 state->Init_Ctrl[12].bit[0] = 2; MXL5005_ControlInit()
854 state->Init_Ctrl[12].val[0] = 0; MXL5005_ControlInit()
855 state->Init_Ctrl[12].addr[1] = 44; MXL5005_ControlInit()
856 state->Init_Ctrl[12].bit[1] = 3; MXL5005_ControlInit()
857 state->Init_Ctrl[12].val[1] = 0; MXL5005_ControlInit()
858 state->Init_Ctrl[12].addr[2] = 44; MXL5005_ControlInit()
859 state->Init_Ctrl[12].bit[2] = 4; MXL5005_ControlInit()
860 state->Init_Ctrl[12].val[2] = 0; MXL5005_ControlInit()
861 state->Init_Ctrl[12].addr[3] = 44; MXL5005_ControlInit()
862 state->Init_Ctrl[12].bit[3] = 5; MXL5005_ControlInit()
863 state->Init_Ctrl[12].val[3] = 1; MXL5005_ControlInit()
864 state->Init_Ctrl[12].addr[4] = 44; MXL5005_ControlInit()
865 state->Init_Ctrl[12].bit[4] = 6; MXL5005_ControlInit()
866 state->Init_Ctrl[12].val[4] = 0; MXL5005_ControlInit()
867 state->Init_Ctrl[12].addr[5] = 44; MXL5005_ControlInit()
868 state->Init_Ctrl[12].bit[5] = 7; MXL5005_ControlInit()
869 state->Init_Ctrl[12].val[5] = 0; MXL5005_ControlInit()
871 state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; MXL5005_ControlInit()
872 state->Init_Ctrl[13].size = 7 ; MXL5005_ControlInit()
873 state->Init_Ctrl[13].addr[0] = 11; MXL5005_ControlInit()
874 state->Init_Ctrl[13].bit[0] = 0; MXL5005_ControlInit()
875 state->Init_Ctrl[13].val[0] = 1; MXL5005_ControlInit()
876 state->Init_Ctrl[13].addr[1] = 11; MXL5005_ControlInit()
877 state->Init_Ctrl[13].bit[1] = 1; MXL5005_ControlInit()
878 state->Init_Ctrl[13].val[1] = 0; MXL5005_ControlInit()
879 state->Init_Ctrl[13].addr[2] = 11; MXL5005_ControlInit()
880 state->Init_Ctrl[13].bit[2] = 2; MXL5005_ControlInit()
881 state->Init_Ctrl[13].val[2] = 0; MXL5005_ControlInit()
882 state->Init_Ctrl[13].addr[3] = 11; MXL5005_ControlInit()
883 state->Init_Ctrl[13].bit[3] = 3; MXL5005_ControlInit()
884 state->Init_Ctrl[13].val[3] = 1; MXL5005_ControlInit()
885 state->Init_Ctrl[13].addr[4] = 11; MXL5005_ControlInit()
886 state->Init_Ctrl[13].bit[4] = 4; MXL5005_ControlInit()
887 state->Init_Ctrl[13].val[4] = 1; MXL5005_ControlInit()
888 state->Init_Ctrl[13].addr[5] = 11; MXL5005_ControlInit()
889 state->Init_Ctrl[13].bit[5] = 5; MXL5005_ControlInit()
890 state->Init_Ctrl[13].val[5] = 0; MXL5005_ControlInit()
891 state->Init_Ctrl[13].addr[6] = 11; MXL5005_ControlInit()
892 state->Init_Ctrl[13].bit[6] = 6; MXL5005_ControlInit()
893 state->Init_Ctrl[13].val[6] = 0; MXL5005_ControlInit()
895 state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; MXL5005_ControlInit()
896 state->Init_Ctrl[14].size = 16 ; MXL5005_ControlInit()
897 state->Init_Ctrl[14].addr[0] = 13; MXL5005_ControlInit()
898 state->Init_Ctrl[14].bit[0] = 0; MXL5005_ControlInit()
899 state->Init_Ctrl[14].val[0] = 0; MXL5005_ControlInit()
900 state->Init_Ctrl[14].addr[1] = 13; MXL5005_ControlInit()
901 state->Init_Ctrl[14].bit[1] = 1; MXL5005_ControlInit()
902 state->Init_Ctrl[14].val[1] = 0; MXL5005_ControlInit()
903 state->Init_Ctrl[14].addr[2] = 13; MXL5005_ControlInit()
904 state->Init_Ctrl[14].bit[2] = 2; MXL5005_ControlInit()
905 state->Init_Ctrl[14].val[2] = 0; MXL5005_ControlInit()
906 state->Init_Ctrl[14].addr[3] = 13; MXL5005_ControlInit()
907 state->Init_Ctrl[14].bit[3] = 3; MXL5005_ControlInit()
908 state->Init_Ctrl[14].val[3] = 0; MXL5005_ControlInit()
909 state->Init_Ctrl[14].addr[4] = 13; MXL5005_ControlInit()
910 state->Init_Ctrl[14].bit[4] = 4; MXL5005_ControlInit()
911 state->Init_Ctrl[14].val[4] = 0; MXL5005_ControlInit()
912 state->Init_Ctrl[14].addr[5] = 13; MXL5005_ControlInit()
913 state->Init_Ctrl[14].bit[5] = 5; MXL5005_ControlInit()
914 state->Init_Ctrl[14].val[5] = 0; MXL5005_ControlInit()
915 state->Init_Ctrl[14].addr[6] = 13; MXL5005_ControlInit()
916 state->Init_Ctrl[14].bit[6] = 6; MXL5005_ControlInit()
917 state->Init_Ctrl[14].val[6] = 0; MXL5005_ControlInit()
918 state->Init_Ctrl[14].addr[7] = 13; MXL5005_ControlInit()
919 state->Init_Ctrl[14].bit[7] = 7; MXL5005_ControlInit()
920 state->Init_Ctrl[14].val[7] = 0; MXL5005_ControlInit()
921 state->Init_Ctrl[14].addr[8] = 12; MXL5005_ControlInit()
922 state->Init_Ctrl[14].bit[8] = 0; MXL5005_ControlInit()
923 state->Init_Ctrl[14].val[8] = 0; MXL5005_ControlInit()
924 state->Init_Ctrl[14].addr[9] = 12; MXL5005_ControlInit()
925 state->Init_Ctrl[14].bit[9] = 1; MXL5005_ControlInit()
926 state->Init_Ctrl[14].val[9] = 0; MXL5005_ControlInit()
927 state->Init_Ctrl[14].addr[10] = 12; MXL5005_ControlInit()
928 state->Init_Ctrl[14].bit[10] = 2; MXL5005_ControlInit()
929 state->Init_Ctrl[14].val[10] = 0; MXL5005_ControlInit()
930 state->Init_Ctrl[14].addr[11] = 12; MXL5005_ControlInit()
931 state->Init_Ctrl[14].bit[11] = 3; MXL5005_ControlInit()
932 state->Init_Ctrl[14].val[11] = 0; MXL5005_ControlInit()
933 state->Init_Ctrl[14].addr[12] = 12; MXL5005_ControlInit()
934 state->Init_Ctrl[14].bit[12] = 4; MXL5005_ControlInit()
935 state->Init_Ctrl[14].val[12] = 0; MXL5005_ControlInit()
936 state->Init_Ctrl[14].addr[13] = 12; MXL5005_ControlInit()
937 state->Init_Ctrl[14].bit[13] = 5; MXL5005_ControlInit()
938 state->Init_Ctrl[14].val[13] = 1; MXL5005_ControlInit()
939 state->Init_Ctrl[14].addr[14] = 12; MXL5005_ControlInit()
940 state->Init_Ctrl[14].bit[14] = 6; MXL5005_ControlInit()
941 state->Init_Ctrl[14].val[14] = 1; MXL5005_ControlInit()
942 state->Init_Ctrl[14].addr[15] = 12; MXL5005_ControlInit()
943 state->Init_Ctrl[14].bit[15] = 7; MXL5005_ControlInit()
944 state->Init_Ctrl[14].val[15] = 0; MXL5005_ControlInit()
946 state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; MXL5005_ControlInit()
947 state->Init_Ctrl[15].size = 3 ; MXL5005_ControlInit()
948 state->Init_Ctrl[15].addr[0] = 147; MXL5005_ControlInit()
949 state->Init_Ctrl[15].bit[0] = 2; MXL5005_ControlInit()
950 state->Init_Ctrl[15].val[0] = 0; MXL5005_ControlInit()
951 state->Init_Ctrl[15].addr[1] = 147; MXL5005_ControlInit()
952 state->Init_Ctrl[15].bit[1] = 3; MXL5005_ControlInit()
953 state->Init_Ctrl[15].val[1] = 1; MXL5005_ControlInit()
954 state->Init_Ctrl[15].addr[2] = 147; MXL5005_ControlInit()
955 state->Init_Ctrl[15].bit[2] = 4; MXL5005_ControlInit()
956 state->Init_Ctrl[15].val[2] = 1; MXL5005_ControlInit()
958 state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; MXL5005_ControlInit()
959 state->Init_Ctrl[16].size = 2 ; MXL5005_ControlInit()
960 state->Init_Ctrl[16].addr[0] = 147; MXL5005_ControlInit()
961 state->Init_Ctrl[16].bit[0] = 0; MXL5005_ControlInit()
962 state->Init_Ctrl[16].val[0] = 0; MXL5005_ControlInit()
963 state->Init_Ctrl[16].addr[1] = 147; MXL5005_ControlInit()
964 state->Init_Ctrl[16].bit[1] = 1; MXL5005_ControlInit()
965 state->Init_Ctrl[16].val[1] = 1; MXL5005_ControlInit()
967 state->Init_Ctrl[17].Ctrl_Num = EN_AAF ; MXL5005_ControlInit()
968 state->Init_Ctrl[17].size = 1 ; MXL5005_ControlInit()
969 state->Init_Ctrl[17].addr[0] = 147; MXL5005_ControlInit()
970 state->Init_Ctrl[17].bit[0] = 7; MXL5005_ControlInit()
971 state->Init_Ctrl[17].val[0] = 0; MXL5005_ControlInit()
973 state->Init_Ctrl[18].Ctrl_Num = EN_3P ; MXL5005_ControlInit()
974 state->Init_Ctrl[18].size = 1 ; MXL5005_ControlInit()
975 state->Init_Ctrl[18].addr[0] = 147; MXL5005_ControlInit()
976 state->Init_Ctrl[18].bit[0] = 6; MXL5005_ControlInit()
977 state->Init_Ctrl[18].val[0] = 0; MXL5005_ControlInit()
979 state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; MXL5005_ControlInit()
980 state->Init_Ctrl[19].size = 1 ; MXL5005_ControlInit()
981 state->Init_Ctrl[19].addr[0] = 156; MXL5005_ControlInit()
982 state->Init_Ctrl[19].bit[0] = 0; MXL5005_ControlInit()
983 state->Init_Ctrl[19].val[0] = 0; MXL5005_ControlInit()
985 state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; MXL5005_ControlInit()
986 state->Init_Ctrl[20].size = 1 ; MXL5005_ControlInit()
987 state->Init_Ctrl[20].addr[0] = 147; MXL5005_ControlInit()
988 state->Init_Ctrl[20].bit[0] = 5; MXL5005_ControlInit()
989 state->Init_Ctrl[20].val[0] = 0; MXL5005_ControlInit()
991 state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; MXL5005_ControlInit()
992 state->Init_Ctrl[21].size = 1 ; MXL5005_ControlInit()
993 state->Init_Ctrl[21].addr[0] = 137; MXL5005_ControlInit()
994 state->Init_Ctrl[21].bit[0] = 4; MXL5005_ControlInit()
995 state->Init_Ctrl[21].val[0] = 0; MXL5005_ControlInit()
997 state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; MXL5005_ControlInit()
998 state->Init_Ctrl[22].size = 1 ; MXL5005_ControlInit()
999 state->Init_Ctrl[22].addr[0] = 137; MXL5005_ControlInit()
1000 state->Init_Ctrl[22].bit[0] = 7; MXL5005_ControlInit()
1001 state->Init_Ctrl[22].val[0] = 0; MXL5005_ControlInit()
1003 state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; MXL5005_ControlInit()
1004 state->Init_Ctrl[23].size = 1 ; MXL5005_ControlInit()
1005 state->Init_Ctrl[23].addr[0] = 91; MXL5005_ControlInit()
1006 state->Init_Ctrl[23].bit[0] = 5; MXL5005_ControlInit()
1007 state->Init_Ctrl[23].val[0] = 1; MXL5005_ControlInit()
1009 state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; MXL5005_ControlInit()
1010 state->Init_Ctrl[24].size = 1 ; MXL5005_ControlInit()
1011 state->Init_Ctrl[24].addr[0] = 43; MXL5005_ControlInit()
1012 state->Init_Ctrl[24].bit[0] = 0; MXL5005_ControlInit()
1013 state->Init_Ctrl[24].val[0] = 1; MXL5005_ControlInit()
1015 state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; MXL5005_ControlInit()
1016 state->Init_Ctrl[25].size = 2 ; MXL5005_ControlInit()
1017 state->Init_Ctrl[25].addr[0] = 22; MXL5005_ControlInit()
1018 state->Init_Ctrl[25].bit[0] = 0; MXL5005_ControlInit()
1019 state->Init_Ctrl[25].val[0] = 1; MXL5005_ControlInit()
1020 state->Init_Ctrl[25].addr[1] = 22; MXL5005_ControlInit()
1021 state->Init_Ctrl[25].bit[1] = 1; MXL5005_ControlInit()
1022 state->Init_Ctrl[25].val[1] = 1; MXL5005_ControlInit()
1024 state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; MXL5005_ControlInit()
1025 state->Init_Ctrl[26].size = 1 ; MXL5005_ControlInit()
1026 state->Init_Ctrl[26].addr[0] = 134; MXL5005_ControlInit()
1027 state->Init_Ctrl[26].bit[0] = 2; MXL5005_ControlInit()
1028 state->Init_Ctrl[26].val[0] = 0; MXL5005_ControlInit()
1030 state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; MXL5005_ControlInit()
1031 state->Init_Ctrl[27].size = 1 ; MXL5005_ControlInit()
1032 state->Init_Ctrl[27].addr[0] = 137; MXL5005_ControlInit()
1033 state->Init_Ctrl[27].bit[0] = 3; MXL5005_ControlInit()
1034 state->Init_Ctrl[27].val[0] = 0; MXL5005_ControlInit()
1036 state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; MXL5005_ControlInit()
1037 state->Init_Ctrl[28].size = 1 ; MXL5005_ControlInit()
1038 state->Init_Ctrl[28].addr[0] = 77; MXL5005_ControlInit()
1039 state->Init_Ctrl[28].bit[0] = 7; MXL5005_ControlInit()
1040 state->Init_Ctrl[28].val[0] = 0; MXL5005_ControlInit()
1042 state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; MXL5005_ControlInit()
1043 state->Init_Ctrl[29].size = 1 ; MXL5005_ControlInit()
1044 state->Init_Ctrl[29].addr[0] = 166; MXL5005_ControlInit()
1045 state->Init_Ctrl[29].bit[0] = 7; MXL5005_ControlInit()
1046 state->Init_Ctrl[29].val[0] = 1; MXL5005_ControlInit()
1048 state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; MXL5005_ControlInit()
1049 state->Init_Ctrl[30].size = 3 ; MXL5005_ControlInit()
1050 state->Init_Ctrl[30].addr[0] = 166; MXL5005_ControlInit()
1051 state->Init_Ctrl[30].bit[0] = 0; MXL5005_ControlInit()
1052 state->Init_Ctrl[30].val[0] = 0; MXL5005_ControlInit()
1053 state->Init_Ctrl[30].addr[1] = 166; MXL5005_ControlInit()
1054 state->Init_Ctrl[30].bit[1] = 1; MXL5005_ControlInit()
1055 state->Init_Ctrl[30].val[1] = 1; MXL5005_ControlInit()
1056 state->Init_Ctrl[30].addr[2] = 166; MXL5005_ControlInit()
1057 state->Init_Ctrl[30].bit[2] = 2; MXL5005_ControlInit()
1058 state->Init_Ctrl[30].val[2] = 1; MXL5005_ControlInit()
1060 state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; MXL5005_ControlInit()
1061 state->Init_Ctrl[31].size = 3 ; MXL5005_ControlInit()
1062 state->Init_Ctrl[31].addr[0] = 166; MXL5005_ControlInit()
1063 state->Init_Ctrl[31].bit[0] = 3; MXL5005_ControlInit()
1064 state->Init_Ctrl[31].val[0] = 1; MXL5005_ControlInit()
1065 state->Init_Ctrl[31].addr[1] = 166; MXL5005_ControlInit()
1066 state->Init_Ctrl[31].bit[1] = 4; MXL5005_ControlInit()
1067 state->Init_Ctrl[31].val[1] = 0; MXL5005_ControlInit()
1068 state->Init_Ctrl[31].addr[2] = 166; MXL5005_ControlInit()
1069 state->Init_Ctrl[31].bit[2] = 5; MXL5005_ControlInit()
1070 state->Init_Ctrl[31].val[2] = 1; MXL5005_ControlInit()
1072 state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; MXL5005_ControlInit()
1073 state->Init_Ctrl[32].size = 3 ; MXL5005_ControlInit()
1074 state->Init_Ctrl[32].addr[0] = 167; MXL5005_ControlInit()
1075 state->Init_Ctrl[32].bit[0] = 0; MXL5005_ControlInit()
1076 state->Init_Ctrl[32].val[0] = 1; MXL5005_ControlInit()
1077 state->Init_Ctrl[32].addr[1] = 167; MXL5005_ControlInit()
1078 state->Init_Ctrl[32].bit[1] = 1; MXL5005_ControlInit()
1079 state->Init_Ctrl[32].val[1] = 1; MXL5005_ControlInit()
1080 state->Init_Ctrl[32].addr[2] = 167; MXL5005_ControlInit()
1081 state->Init_Ctrl[32].bit[2] = 2; MXL5005_ControlInit()
1082 state->Init_Ctrl[32].val[2] = 0; MXL5005_ControlInit()
1084 state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; MXL5005_ControlInit()
1085 state->Init_Ctrl[33].size = 4 ; MXL5005_ControlInit()
1086 state->Init_Ctrl[33].addr[0] = 168; MXL5005_ControlInit()
1087 state->Init_Ctrl[33].bit[0] = 0; MXL5005_ControlInit()
1088 state->Init_Ctrl[33].val[0] = 0; MXL5005_ControlInit()
1089 state->Init_Ctrl[33].addr[1] = 168; MXL5005_ControlInit()
1090 state->Init_Ctrl[33].bit[1] = 1; MXL5005_ControlInit()
1091 state->Init_Ctrl[33].val[1] = 1; MXL5005_ControlInit()
1092 state->Init_Ctrl[33].addr[2] = 168; MXL5005_ControlInit()
1093 state->Init_Ctrl[33].bit[2] = 2; MXL5005_ControlInit()
1094 state->Init_Ctrl[33].val[2] = 0; MXL5005_ControlInit()
1095 state->Init_Ctrl[33].addr[3] = 168; MXL5005_ControlInit()
1096 state->Init_Ctrl[33].bit[3] = 3; MXL5005_ControlInit()
1097 state->Init_Ctrl[33].val[3] = 0; MXL5005_ControlInit()
1099 state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; MXL5005_ControlInit()
1100 state->Init_Ctrl[34].size = 4 ; MXL5005_ControlInit()
1101 state->Init_Ctrl[34].addr[0] = 168; MXL5005_ControlInit()
1102 state->Init_Ctrl[34].bit[0] = 4; MXL5005_ControlInit()
1103 state->Init_Ctrl[34].val[0] = 1; MXL5005_ControlInit()
1104 state->Init_Ctrl[34].addr[1] = 168; MXL5005_ControlInit()
1105 state->Init_Ctrl[34].bit[1] = 5; MXL5005_ControlInit()
1106 state->Init_Ctrl[34].val[1] = 1; MXL5005_ControlInit()
1107 state->Init_Ctrl[34].addr[2] = 168; MXL5005_ControlInit()
1108 state->Init_Ctrl[34].bit[2] = 6; MXL5005_ControlInit()
1109 state->Init_Ctrl[34].val[2] = 1; MXL5005_ControlInit()
1110 state->Init_Ctrl[34].addr[3] = 168; MXL5005_ControlInit()
1111 state->Init_Ctrl[34].bit[3] = 7; MXL5005_ControlInit()
1112 state->Init_Ctrl[34].val[3] = 1; MXL5005_ControlInit()
1114 state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; MXL5005_ControlInit()
1115 state->Init_Ctrl[35].size = 1 ; MXL5005_ControlInit()
1116 state->Init_Ctrl[35].addr[0] = 135; MXL5005_ControlInit()
1117 state->Init_Ctrl[35].bit[0] = 0; MXL5005_ControlInit()
1118 state->Init_Ctrl[35].val[0] = 0; MXL5005_ControlInit()
1120 state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; MXL5005_ControlInit()
1121 state->Init_Ctrl[36].size = 1 ; MXL5005_ControlInit()
1122 state->Init_Ctrl[36].addr[0] = 56; MXL5005_ControlInit()
1123 state->Init_Ctrl[36].bit[0] = 3; MXL5005_ControlInit()
1124 state->Init_Ctrl[36].val[0] = 0; MXL5005_ControlInit()
1126 state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; MXL5005_ControlInit()
1127 state->Init_Ctrl[37].size = 7 ; MXL5005_ControlInit()
1128 state->Init_Ctrl[37].addr[0] = 59; MXL5005_ControlInit()
1129 state->Init_Ctrl[37].bit[0] = 1; MXL5005_ControlInit()
1130 state->Init_Ctrl[37].val[0] = 0; MXL5005_ControlInit()
1131 state->Init_Ctrl[37].addr[1] = 59; MXL5005_ControlInit()
1132 state->Init_Ctrl[37].bit[1] = 2; MXL5005_ControlInit()
1133 state->Init_Ctrl[37].val[1] = 0; MXL5005_ControlInit()
1134 state->Init_Ctrl[37].addr[2] = 59; MXL5005_ControlInit()
1135 state->Init_Ctrl[37].bit[2] = 3; MXL5005_ControlInit()
1136 state->Init_Ctrl[37].val[2] = 0; MXL5005_ControlInit()
1137 state->Init_Ctrl[37].addr[3] = 59; MXL5005_ControlInit()
1138 state->Init_Ctrl[37].bit[3] = 4; MXL5005_ControlInit()
1139 state->Init_Ctrl[37].val[3] = 0; MXL5005_ControlInit()
1140 state->Init_Ctrl[37].addr[4] = 59; MXL5005_ControlInit()
1141 state->Init_Ctrl[37].bit[4] = 5; MXL5005_ControlInit()
1142 state->Init_Ctrl[37].val[4] = 0; MXL5005_ControlInit()
1143 state->Init_Ctrl[37].addr[5] = 59; MXL5005_ControlInit()
1144 state->Init_Ctrl[37].bit[5] = 6; MXL5005_ControlInit()
1145 state->Init_Ctrl[37].val[5] = 0; MXL5005_ControlInit()
1146 state->Init_Ctrl[37].addr[6] = 59; MXL5005_ControlInit()
1147 state->Init_Ctrl[37].bit[6] = 7; MXL5005_ControlInit()
1148 state->Init_Ctrl[37].val[6] = 0; MXL5005_ControlInit()
1150 state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; MXL5005_ControlInit()
1151 state->Init_Ctrl[38].size = 6 ; MXL5005_ControlInit()
1152 state->Init_Ctrl[38].addr[0] = 32; MXL5005_ControlInit()
1153 state->Init_Ctrl[38].bit[0] = 2; MXL5005_ControlInit()
1154 state->Init_Ctrl[38].val[0] = 0; MXL5005_ControlInit()
1155 state->Init_Ctrl[38].addr[1] = 32; MXL5005_ControlInit()
1156 state->Init_Ctrl[38].bit[1] = 3; MXL5005_ControlInit()
1157 state->Init_Ctrl[38].val[1] = 0; MXL5005_ControlInit()
1158 state->Init_Ctrl[38].addr[2] = 32; MXL5005_ControlInit()
1159 state->Init_Ctrl[38].bit[2] = 4; MXL5005_ControlInit()
1160 state->Init_Ctrl[38].val[2] = 0; MXL5005_ControlInit()
1161 state->Init_Ctrl[38].addr[3] = 32; MXL5005_ControlInit()
1162 state->Init_Ctrl[38].bit[3] = 5; MXL5005_ControlInit()
1163 state->Init_Ctrl[38].val[3] = 0; MXL5005_ControlInit()
1164 state->Init_Ctrl[38].addr[4] = 32; MXL5005_ControlInit()
1165 state->Init_Ctrl[38].bit[4] = 6; MXL5005_ControlInit()
1166 state->Init_Ctrl[38].val[4] = 1; MXL5005_ControlInit()
1167 state->Init_Ctrl[38].addr[5] = 32; MXL5005_ControlInit()
1168 state->Init_Ctrl[38].bit[5] = 7; MXL5005_ControlInit()
1169 state->Init_Ctrl[38].val[5] = 0; MXL5005_ControlInit()
1171 state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; MXL5005_ControlInit()
1172 state->Init_Ctrl[39].size = 1 ; MXL5005_ControlInit()
1173 state->Init_Ctrl[39].addr[0] = 25; MXL5005_ControlInit()
1174 state->Init_Ctrl[39].bit[0] = 3; MXL5005_ControlInit()
1175 state->Init_Ctrl[39].val[0] = 1; MXL5005_ControlInit()
1178 state->CH_Ctrl_Num = CHCTRL_NUM ; MXL5005_ControlInit()
1180 state->CH_Ctrl[0].Ctrl_Num = DN_POLY ; MXL5005_ControlInit()
1181 state->CH_Ctrl[0].size = 2 ; MXL5005_ControlInit()
1182 state->CH_Ctrl[0].addr[0] = 68; MXL5005_ControlInit()
1183 state->CH_Ctrl[0].bit[0] = 6; MXL5005_ControlInit()
1184 state->CH_Ctrl[0].val[0] = 1; MXL5005_ControlInit()
1185 state->CH_Ctrl[0].addr[1] = 68; MXL5005_ControlInit()
1186 state->CH_Ctrl[0].bit[1] = 7; MXL5005_ControlInit()
1187 state->CH_Ctrl[0].val[1] = 1; MXL5005_ControlInit()
1189 state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; MXL5005_ControlInit()
1190 state->CH_Ctrl[1].size = 2 ; MXL5005_ControlInit()
1191 state->CH_Ctrl[1].addr[0] = 70; MXL5005_ControlInit()
1192 state->CH_Ctrl[1].bit[0] = 6; MXL5005_ControlInit()
1193 state->CH_Ctrl[1].val[0] = 1; MXL5005_ControlInit()
1194 state->CH_Ctrl[1].addr[1] = 70; MXL5005_ControlInit()
1195 state->CH_Ctrl[1].bit[1] = 7; MXL5005_ControlInit()
1196 state->CH_Ctrl[1].val[1] = 0; MXL5005_ControlInit()
1198 state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; MXL5005_ControlInit()
1199 state->CH_Ctrl[2].size = 9 ; MXL5005_ControlInit()
1200 state->CH_Ctrl[2].addr[0] = 69; MXL5005_ControlInit()
1201 state->CH_Ctrl[2].bit[0] = 5; MXL5005_ControlInit()
1202 state->CH_Ctrl[2].val[0] = 0; MXL5005_ControlInit()
1203 state->CH_Ctrl[2].addr[1] = 69; MXL5005_ControlInit()
1204 state->CH_Ctrl[2].bit[1] = 6; MXL5005_ControlInit()
1205 state->CH_Ctrl[2].val[1] = 0; MXL5005_ControlInit()
1206 state->CH_Ctrl[2].addr[2] = 69; MXL5005_ControlInit()
1207 state->CH_Ctrl[2].bit[2] = 7; MXL5005_ControlInit()
1208 state->CH_Ctrl[2].val[2] = 0; MXL5005_ControlInit()
1209 state->CH_Ctrl[2].addr[3] = 68; MXL5005_ControlInit()
1210 state->CH_Ctrl[2].bit[3] = 0; MXL5005_ControlInit()
1211 state->CH_Ctrl[2].val[3] = 0; MXL5005_ControlInit()
1212 state->CH_Ctrl[2].addr[4] = 68; MXL5005_ControlInit()
1213 state->CH_Ctrl[2].bit[4] = 1; MXL5005_ControlInit()
1214 state->CH_Ctrl[2].val[4] = 0; MXL5005_ControlInit()
1215 state->CH_Ctrl[2].addr[5] = 68; MXL5005_ControlInit()
1216 state->CH_Ctrl[2].bit[5] = 2; MXL5005_ControlInit()
1217 state->CH_Ctrl[2].val[5] = 0; MXL5005_ControlInit()
1218 state->CH_Ctrl[2].addr[6] = 68; MXL5005_ControlInit()
1219 state->CH_Ctrl[2].bit[6] = 3; MXL5005_ControlInit()
1220 state->CH_Ctrl[2].val[6] = 0; MXL5005_ControlInit()
1221 state->CH_Ctrl[2].addr[7] = 68; MXL5005_ControlInit()
1222 state->CH_Ctrl[2].bit[7] = 4; MXL5005_ControlInit()
1223 state->CH_Ctrl[2].val[7] = 0; MXL5005_ControlInit()
1224 state->CH_Ctrl[2].addr[8] = 68; MXL5005_ControlInit()
1225 state->CH_Ctrl[2].bit[8] = 5; MXL5005_ControlInit()
1226 state->CH_Ctrl[2].val[8] = 0; MXL5005_ControlInit()
1228 state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; MXL5005_ControlInit()
1229 state->CH_Ctrl[3].size = 1 ; MXL5005_ControlInit()
1230 state->CH_Ctrl[3].addr[0] = 70; MXL5005_ControlInit()
1231 state->CH_Ctrl[3].bit[0] = 5; MXL5005_ControlInit()
1232 state->CH_Ctrl[3].val[0] = 0; MXL5005_ControlInit()
1234 state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; MXL5005_ControlInit()
1235 state->CH_Ctrl[4].size = 3 ; MXL5005_ControlInit()
1236 state->CH_Ctrl[4].addr[0] = 73; MXL5005_ControlInit()
1237 state->CH_Ctrl[4].bit[0] = 4; MXL5005_ControlInit()
1238 state->CH_Ctrl[4].val[0] = 0; MXL5005_ControlInit()
1239 state->CH_Ctrl[4].addr[1] = 73; MXL5005_ControlInit()
1240 state->CH_Ctrl[4].bit[1] = 5; MXL5005_ControlInit()
1241 state->CH_Ctrl[4].val[1] = 1; MXL5005_ControlInit()
1242 state->CH_Ctrl[4].addr[2] = 73; MXL5005_ControlInit()
1243 state->CH_Ctrl[4].bit[2] = 6; MXL5005_ControlInit()
1244 state->CH_Ctrl[4].val[2] = 0; MXL5005_ControlInit()
1246 state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; MXL5005_ControlInit()
1247 state->CH_Ctrl[5].size = 4 ; MXL5005_ControlInit()
1248 state->CH_Ctrl[5].addr[0] = 70; MXL5005_ControlInit()
1249 state->CH_Ctrl[5].bit[0] = 0; MXL5005_ControlInit()
1250 state->CH_Ctrl[5].val[0] = 0; MXL5005_ControlInit()
1251 state->CH_Ctrl[5].addr[1] = 70; MXL5005_ControlInit()
1252 state->CH_Ctrl[5].bit[1] = 1; MXL5005_ControlInit()
1253 state->CH_Ctrl[5].val[1] = 0; MXL5005_ControlInit()
1254 state->CH_Ctrl[5].addr[2] = 70; MXL5005_ControlInit()
1255 state->CH_Ctrl[5].bit[2] = 2; MXL5005_ControlInit()
1256 state->CH_Ctrl[5].val[2] = 0; MXL5005_ControlInit()
1257 state->CH_Ctrl[5].addr[3] = 70; MXL5005_ControlInit()
1258 state->CH_Ctrl[5].bit[3] = 3; MXL5005_ControlInit()
1259 state->CH_Ctrl[5].val[3] = 0; MXL5005_ControlInit()
1261 state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; MXL5005_ControlInit()
1262 state->CH_Ctrl[6].size = 1 ; MXL5005_ControlInit()
1263 state->CH_Ctrl[6].addr[0] = 70; MXL5005_ControlInit()
1264 state->CH_Ctrl[6].bit[0] = 4; MXL5005_ControlInit()
1265 state->CH_Ctrl[6].val[0] = 1; MXL5005_ControlInit()
1267 state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; MXL5005_ControlInit()
1268 state->CH_Ctrl[7].size = 1 ; MXL5005_ControlInit()
1269 state->CH_Ctrl[7].addr[0] = 111; MXL5005_ControlInit()
1270 state->CH_Ctrl[7].bit[0] = 4; MXL5005_ControlInit()
1271 state->CH_Ctrl[7].val[0] = 0; MXL5005_ControlInit()
1273 state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; MXL5005_ControlInit()
1274 state->CH_Ctrl[8].size = 1 ; MXL5005_ControlInit()
1275 state->CH_Ctrl[8].addr[0] = 111; MXL5005_ControlInit()
1276 state->CH_Ctrl[8].bit[0] = 7; MXL5005_ControlInit()
1277 state->CH_Ctrl[8].val[0] = 1; MXL5005_ControlInit()
1279 state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; MXL5005_ControlInit()
1280 state->CH_Ctrl[9].size = 1 ; MXL5005_ControlInit()
1281 state->CH_Ctrl[9].addr[0] = 111; MXL5005_ControlInit()
1282 state->CH_Ctrl[9].bit[0] = 6; MXL5005_ControlInit()
1283 state->CH_Ctrl[9].val[0] = 1; MXL5005_ControlInit()
1285 state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; MXL5005_ControlInit()
1286 state->CH_Ctrl[10].size = 1 ; MXL5005_ControlInit()
1287 state->CH_Ctrl[10].addr[0] = 111; MXL5005_ControlInit()
1288 state->CH_Ctrl[10].bit[0] = 5; MXL5005_ControlInit()
1289 state->CH_Ctrl[10].val[0] = 0; MXL5005_ControlInit()
1291 state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; MXL5005_ControlInit()
1292 state->CH_Ctrl[11].size = 2 ; MXL5005_ControlInit()
1293 state->CH_Ctrl[11].addr[0] = 110; MXL5005_ControlInit()
1294 state->CH_Ctrl[11].bit[0] = 0; MXL5005_ControlInit()
1295 state->CH_Ctrl[11].val[0] = 1; MXL5005_ControlInit()
1296 state->CH_Ctrl[11].addr[1] = 110; MXL5005_ControlInit()
1297 state->CH_Ctrl[11].bit[1] = 1; MXL5005_ControlInit()
1298 state->CH_Ctrl[11].val[1] = 0; MXL5005_ControlInit()
1300 state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; MXL5005_ControlInit()
1301 state->CH_Ctrl[12].size = 3 ; MXL5005_ControlInit()
1302 state->CH_Ctrl[12].addr[0] = 69; MXL5005_ControlInit()
1303 state->CH_Ctrl[12].bit[0] = 2; MXL5005_ControlInit()
1304 state->CH_Ctrl[12].val[0] = 0; MXL5005_ControlInit()
1305 state->CH_Ctrl[12].addr[1] = 69; MXL5005_ControlInit()
1306 state->CH_Ctrl[12].bit[1] = 3; MXL5005_ControlInit()
1307 state->CH_Ctrl[12].val[1] = 0; MXL5005_ControlInit()
1308 state->CH_Ctrl[12].addr[2] = 69; MXL5005_ControlInit()
1309 state->CH_Ctrl[12].bit[2] = 4; MXL5005_ControlInit()
1310 state->CH_Ctrl[12].val[2] = 0; MXL5005_ControlInit()
1312 state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; MXL5005_ControlInit()
1313 state->CH_Ctrl[13].size = 6 ; MXL5005_ControlInit()
1314 state->CH_Ctrl[13].addr[0] = 110; MXL5005_ControlInit()
1315 state->CH_Ctrl[13].bit[0] = 2; MXL5005_ControlInit()
1316 state->CH_Ctrl[13].val[0] = 0; MXL5005_ControlInit()
1317 state->CH_Ctrl[13].addr[1] = 110; MXL5005_ControlInit()
1318 state->CH_Ctrl[13].bit[1] = 3; MXL5005_ControlInit()
1319 state->CH_Ctrl[13].val[1] = 0; MXL5005_ControlInit()
1320 state->CH_Ctrl[13].addr[2] = 110; MXL5005_ControlInit()
1321 state->CH_Ctrl[13].bit[2] = 4; MXL5005_ControlInit()
1322 state->CH_Ctrl[13].val[2] = 0; MXL5005_ControlInit()
1323 state->CH_Ctrl[13].addr[3] = 110; MXL5005_ControlInit()
1324 state->CH_Ctrl[13].bit[3] = 5; MXL5005_ControlInit()
1325 state->CH_Ctrl[13].val[3] = 0; MXL5005_ControlInit()
1326 state->CH_Ctrl[13].addr[4] = 110; MXL5005_ControlInit()
1327 state->CH_Ctrl[13].bit[4] = 6; MXL5005_ControlInit()
1328 state->CH_Ctrl[13].val[4] = 0; MXL5005_ControlInit()
1329 state->CH_Ctrl[13].addr[5] = 110; MXL5005_ControlInit()
1330 state->CH_Ctrl[13].bit[5] = 7; MXL5005_ControlInit()
1331 state->CH_Ctrl[13].val[5] = 1; MXL5005_ControlInit()
1333 state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; MXL5005_ControlInit()
1334 state->CH_Ctrl[14].size = 7 ; MXL5005_ControlInit()
1335 state->CH_Ctrl[14].addr[0] = 14; MXL5005_ControlInit()
1336 state->CH_Ctrl[14].bit[0] = 0; MXL5005_ControlInit()
1337 state->CH_Ctrl[14].val[0] = 0; MXL5005_ControlInit()
1338 state->CH_Ctrl[14].addr[1] = 14; MXL5005_ControlInit()
1339 state->CH_Ctrl[14].bit[1] = 1; MXL5005_ControlInit()
1340 state->CH_Ctrl[14].val[1] = 0; MXL5005_ControlInit()
1341 state->CH_Ctrl[14].addr[2] = 14; MXL5005_ControlInit()
1342 state->CH_Ctrl[14].bit[2] = 2; MXL5005_ControlInit()
1343 state->CH_Ctrl[14].val[2] = 0; MXL5005_ControlInit()
1344 state->CH_Ctrl[14].addr[3] = 14; MXL5005_ControlInit()
1345 state->CH_Ctrl[14].bit[3] = 3; MXL5005_ControlInit()
1346 state->CH_Ctrl[14].val[3] = 0; MXL5005_ControlInit()
1347 state->CH_Ctrl[14].addr[4] = 14; MXL5005_ControlInit()
1348 state->CH_Ctrl[14].bit[4] = 4; MXL5005_ControlInit()
1349 state->CH_Ctrl[14].val[4] = 0; MXL5005_ControlInit()
1350 state->CH_Ctrl[14].addr[5] = 14; MXL5005_ControlInit()
1351 state->CH_Ctrl[14].bit[5] = 5; MXL5005_ControlInit()
1352 state->CH_Ctrl[14].val[5] = 0; MXL5005_ControlInit()
1353 state->CH_Ctrl[14].addr[6] = 14; MXL5005_ControlInit()
1354 state->CH_Ctrl[14].bit[6] = 6; MXL5005_ControlInit()
1355 state->CH_Ctrl[14].val[6] = 0; MXL5005_ControlInit()
1357 state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; MXL5005_ControlInit()
1358 state->CH_Ctrl[15].size = 18 ; MXL5005_ControlInit()
1359 state->CH_Ctrl[15].addr[0] = 17; MXL5005_ControlInit()
1360 state->CH_Ctrl[15].bit[0] = 6; MXL5005_ControlInit()
1361 state->CH_Ctrl[15].val[0] = 0; MXL5005_ControlInit()
1362 state->CH_Ctrl[15].addr[1] = 17; MXL5005_ControlInit()
1363 state->CH_Ctrl[15].bit[1] = 7; MXL5005_ControlInit()
1364 state->CH_Ctrl[15].val[1] = 0; MXL5005_ControlInit()
1365 state->CH_Ctrl[15].addr[2] = 16; MXL5005_ControlInit()
1366 state->CH_Ctrl[15].bit[2] = 0; MXL5005_ControlInit()
1367 state->CH_Ctrl[15].val[2] = 0; MXL5005_ControlInit()
1368 state->CH_Ctrl[15].addr[3] = 16; MXL5005_ControlInit()
1369 state->CH_Ctrl[15].bit[3] = 1; MXL5005_ControlInit()
1370 state->CH_Ctrl[15].val[3] = 0; MXL5005_ControlInit()
1371 state->CH_Ctrl[15].addr[4] = 16; MXL5005_ControlInit()
1372 state->CH_Ctrl[15].bit[4] = 2; MXL5005_ControlInit()
1373 state->CH_Ctrl[15].val[4] = 0; MXL5005_ControlInit()
1374 state->CH_Ctrl[15].addr[5] = 16; MXL5005_ControlInit()
1375 state->CH_Ctrl[15].bit[5] = 3; MXL5005_ControlInit()
1376 state->CH_Ctrl[15].val[5] = 0; MXL5005_ControlInit()
1377 state->CH_Ctrl[15].addr[6] = 16; MXL5005_ControlInit()
1378 state->CH_Ctrl[15].bit[6] = 4; MXL5005_ControlInit()
1379 state->CH_Ctrl[15].val[6] = 0; MXL5005_ControlInit()
1380 state->CH_Ctrl[15].addr[7] = 16; MXL5005_ControlInit()
1381 state->CH_Ctrl[15].bit[7] = 5; MXL5005_ControlInit()
1382 state->CH_Ctrl[15].val[7] = 0; MXL5005_ControlInit()
1383 state->CH_Ctrl[15].addr[8] = 16; MXL5005_ControlInit()
1384 state->CH_Ctrl[15].bit[8] = 6; MXL5005_ControlInit()
1385 state->CH_Ctrl[15].val[8] = 0; MXL5005_ControlInit()
1386 state->CH_Ctrl[15].addr[9] = 16; MXL5005_ControlInit()
1387 state->CH_Ctrl[15].bit[9] = 7; MXL5005_ControlInit()
1388 state->CH_Ctrl[15].val[9] = 0; MXL5005_ControlInit()
1389 state->CH_Ctrl[15].addr[10] = 15; MXL5005_ControlInit()
1390 state->CH_Ctrl[15].bit[10] = 0; MXL5005_ControlInit()
1391 state->CH_Ctrl[15].val[10] = 0; MXL5005_ControlInit()
1392 state->CH_Ctrl[15].addr[11] = 15; MXL5005_ControlInit()
1393 state->CH_Ctrl[15].bit[11] = 1; MXL5005_ControlInit()
1394 state->CH_Ctrl[15].val[11] = 0; MXL5005_ControlInit()
1395 state->CH_Ctrl[15].addr[12] = 15; MXL5005_ControlInit()
1396 state->CH_Ctrl[15].bit[12] = 2; MXL5005_ControlInit()
1397 state->CH_Ctrl[15].val[12] = 0; MXL5005_ControlInit()
1398 state->CH_Ctrl[15].addr[13] = 15; MXL5005_ControlInit()
1399 state->CH_Ctrl[15].bit[13] = 3; MXL5005_ControlInit()
1400 state->CH_Ctrl[15].val[13] = 0; MXL5005_ControlInit()
1401 state->CH_Ctrl[15].addr[14] = 15; MXL5005_ControlInit()
1402 state->CH_Ctrl[15].bit[14] = 4; MXL5005_ControlInit()
1403 state->CH_Ctrl[15].val[14] = 0; MXL5005_ControlInit()
1404 state->CH_Ctrl[15].addr[15] = 15; MXL5005_ControlInit()
1405 state->CH_Ctrl[15].bit[15] = 5; MXL5005_ControlInit()
1406 state->CH_Ctrl[15].val[15] = 0; MXL5005_ControlInit()
1407 state->CH_Ctrl[15].addr[16] = 15; MXL5005_ControlInit()
1408 state->CH_Ctrl[15].bit[16] = 6; MXL5005_ControlInit()
1409 state->CH_Ctrl[15].val[16] = 1; MXL5005_ControlInit()
1410 state->CH_Ctrl[15].addr[17] = 15; MXL5005_ControlInit()
1411 state->CH_Ctrl[15].bit[17] = 7; MXL5005_ControlInit()
1412 state->CH_Ctrl[15].val[17] = 1; MXL5005_ControlInit()
1414 state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; MXL5005_ControlInit()
1415 state->CH_Ctrl[16].size = 5 ; MXL5005_ControlInit()
1416 state->CH_Ctrl[16].addr[0] = 112; MXL5005_ControlInit()
1417 state->CH_Ctrl[16].bit[0] = 0; MXL5005_ControlInit()
1418 state->CH_Ctrl[16].val[0] = 0; MXL5005_ControlInit()
1419 state->CH_Ctrl[16].addr[1] = 112; MXL5005_ControlInit()
1420 state->CH_Ctrl[16].bit[1] = 1; MXL5005_ControlInit()
1421 state->CH_Ctrl[16].val[1] = 0; MXL5005_ControlInit()
1422 state->CH_Ctrl[16].addr[2] = 112; MXL5005_ControlInit()
1423 state->CH_Ctrl[16].bit[2] = 2; MXL5005_ControlInit()
1424 state->CH_Ctrl[16].val[2] = 0; MXL5005_ControlInit()
1425 state->CH_Ctrl[16].addr[3] = 112; MXL5005_ControlInit()
1426 state->CH_Ctrl[16].bit[3] = 3; MXL5005_ControlInit()
1427 state->CH_Ctrl[16].val[3] = 0; MXL5005_ControlInit()
1428 state->CH_Ctrl[16].addr[4] = 112; MXL5005_ControlInit()
1429 state->CH_Ctrl[16].bit[4] = 4; MXL5005_ControlInit()
1430 state->CH_Ctrl[16].val[4] = 1; MXL5005_ControlInit()
1432 state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; MXL5005_ControlInit()
1433 state->CH_Ctrl[17].size = 1 ; MXL5005_ControlInit()
1434 state->CH_Ctrl[17].addr[0] = 14; MXL5005_ControlInit()
1435 state->CH_Ctrl[17].bit[0] = 7; MXL5005_ControlInit()
1436 state->CH_Ctrl[17].val[0] = 0; MXL5005_ControlInit()
1438 state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; MXL5005_ControlInit()
1439 state->CH_Ctrl[18].size = 4 ; MXL5005_ControlInit()
1440 state->CH_Ctrl[18].addr[0] = 107; MXL5005_ControlInit()
1441 state->CH_Ctrl[18].bit[0] = 3; MXL5005_ControlInit()
1442 state->CH_Ctrl[18].val[0] = 0; MXL5005_ControlInit()
1443 state->CH_Ctrl[18].addr[1] = 107; MXL5005_ControlInit()
1444 state->CH_Ctrl[18].bit[1] = 4; MXL5005_ControlInit()
1445 state->CH_Ctrl[18].val[1] = 0; MXL5005_ControlInit()
1446 state->CH_Ctrl[18].addr[2] = 107; MXL5005_ControlInit()
1447 state->CH_Ctrl[18].bit[2] = 5; MXL5005_ControlInit()
1448 state->CH_Ctrl[18].val[2] = 0; MXL5005_ControlInit()
1449 state->CH_Ctrl[18].addr[3] = 107; MXL5005_ControlInit()
1450 state->CH_Ctrl[18].bit[3] = 6; MXL5005_ControlInit()
1451 state->CH_Ctrl[18].val[3] = 0; MXL5005_ControlInit()
1453 state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; MXL5005_ControlInit()
1454 state->CH_Ctrl[19].size = 3 ; MXL5005_ControlInit()
1455 state->CH_Ctrl[19].addr[0] = 107; MXL5005_ControlInit()
1456 state->CH_Ctrl[19].bit[0] = 7; MXL5005_ControlInit()
1457 state->CH_Ctrl[19].val[0] = 1; MXL5005_ControlInit()
1458 state->CH_Ctrl[19].addr[1] = 106; MXL5005_ControlInit()
1459 state->CH_Ctrl[19].bit[1] = 0; MXL5005_ControlInit()
1460 state->CH_Ctrl[19].val[1] = 1; MXL5005_ControlInit()
1461 state->CH_Ctrl[19].addr[2] = 106; MXL5005_ControlInit()
1462 state->CH_Ctrl[19].bit[2] = 1; MXL5005_ControlInit()
1463 state->CH_Ctrl[19].val[2] = 1; MXL5005_ControlInit()
1465 state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; MXL5005_ControlInit()
1466 state->CH_Ctrl[20].size = 11 ; MXL5005_ControlInit()
1467 state->CH_Ctrl[20].addr[0] = 109; MXL5005_ControlInit()
1468 state->CH_Ctrl[20].bit[0] = 2; MXL5005_ControlInit()
1469 state->CH_Ctrl[20].val[0] = 0; MXL5005_ControlInit()
1470 state->CH_Ctrl[20].addr[1] = 109; MXL5005_ControlInit()
1471 state->CH_Ctrl[20].bit[1] = 3; MXL5005_ControlInit()
1472 state->CH_Ctrl[20].val[1] = 0; MXL5005_ControlInit()
1473 state->CH_Ctrl[20].addr[2] = 109; MXL5005_ControlInit()
1474 state->CH_Ctrl[20].bit[2] = 4; MXL5005_ControlInit()
1475 state->CH_Ctrl[20].val[2] = 0; MXL5005_ControlInit()
1476 state->CH_Ctrl[20].addr[3] = 109; MXL5005_ControlInit()
1477 state->CH_Ctrl[20].bit[3] = 5; MXL5005_ControlInit()
1478 state->CH_Ctrl[20].val[3] = 0; MXL5005_ControlInit()
1479 state->CH_Ctrl[20].addr[4] = 109; MXL5005_ControlInit()
1480 state->CH_Ctrl[20].bit[4] = 6; MXL5005_ControlInit()
1481 state->CH_Ctrl[20].val[4] = 0; MXL5005_ControlInit()
1482 state->CH_Ctrl[20].addr[5] = 109; MXL5005_ControlInit()
1483 state->CH_Ctrl[20].bit[5] = 7; MXL5005_ControlInit()
1484 state->CH_Ctrl[20].val[5] = 0; MXL5005_ControlInit()
1485 state->CH_Ctrl[20].addr[6] = 108; MXL5005_ControlInit()
1486 state->CH_Ctrl[20].bit[6] = 0; MXL5005_ControlInit()
1487 state->CH_Ctrl[20].val[6] = 0; MXL5005_ControlInit()
1488 state->CH_Ctrl[20].addr[7] = 108; MXL5005_ControlInit()
1489 state->CH_Ctrl[20].bit[7] = 1; MXL5005_ControlInit()
1490 state->CH_Ctrl[20].val[7] = 0; MXL5005_ControlInit()
1491 state->CH_Ctrl[20].addr[8] = 108; MXL5005_ControlInit()
1492 state->CH_Ctrl[20].bit[8] = 2; MXL5005_ControlInit()
1493 state->CH_Ctrl[20].val[8] = 1; MXL5005_ControlInit()
1494 state->CH_Ctrl[20].addr[9] = 108; MXL5005_ControlInit()
1495 state->CH_Ctrl[20].bit[9] = 3; MXL5005_ControlInit()
1496 state->CH_Ctrl[20].val[9] = 1; MXL5005_ControlInit()
1497 state->CH_Ctrl[20].addr[10] = 108; MXL5005_ControlInit()
1498 state->CH_Ctrl[20].bit[10] = 4; MXL5005_ControlInit()
1499 state->CH_Ctrl[20].val[10] = 1; MXL5005_ControlInit()
1501 state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; MXL5005_ControlInit()
1502 state->CH_Ctrl[21].size = 6 ; MXL5005_ControlInit()
1503 state->CH_Ctrl[21].addr[0] = 106; MXL5005_ControlInit()
1504 state->CH_Ctrl[21].bit[0] = 2; MXL5005_ControlInit()
1505 state->CH_Ctrl[21].val[0] = 0; MXL5005_ControlInit()
1506 state->CH_Ctrl[21].addr[1] = 106; MXL5005_ControlInit()
1507 state->CH_Ctrl[21].bit[1] = 3; MXL5005_ControlInit()
1508 state->CH_Ctrl[21].val[1] = 0; MXL5005_ControlInit()
1509 state->CH_Ctrl[21].addr[2] = 106; MXL5005_ControlInit()
1510 state->CH_Ctrl[21].bit[2] = 4; MXL5005_ControlInit()
1511 state->CH_Ctrl[21].val[2] = 0; MXL5005_ControlInit()
1512 state->CH_Ctrl[21].addr[3] = 106; MXL5005_ControlInit()
1513 state->CH_Ctrl[21].bit[3] = 5; MXL5005_ControlInit()
1514 state->CH_Ctrl[21].val[3] = 0; MXL5005_ControlInit()
1515 state->CH_Ctrl[21].addr[4] = 106; MXL5005_ControlInit()
1516 state->CH_Ctrl[21].bit[4] = 6; MXL5005_ControlInit()
1517 state->CH_Ctrl[21].val[4] = 0; MXL5005_ControlInit()
1518 state->CH_Ctrl[21].addr[5] = 106; MXL5005_ControlInit()
1519 state->CH_Ctrl[21].bit[5] = 7; MXL5005_ControlInit()
1520 state->CH_Ctrl[21].val[5] = 1; MXL5005_ControlInit()
1522 state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; MXL5005_ControlInit()
1523 state->CH_Ctrl[22].size = 1 ; MXL5005_ControlInit()
1524 state->CH_Ctrl[22].addr[0] = 138; MXL5005_ControlInit()
1525 state->CH_Ctrl[22].bit[0] = 4; MXL5005_ControlInit()
1526 state->CH_Ctrl[22].val[0] = 1; MXL5005_ControlInit()
1528 state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; MXL5005_ControlInit()
1529 state->CH_Ctrl[23].size = 1 ; MXL5005_ControlInit()
1530 state->CH_Ctrl[23].addr[0] = 17; MXL5005_ControlInit()
1531 state->CH_Ctrl[23].bit[0] = 5; MXL5005_ControlInit()
1532 state->CH_Ctrl[23].val[0] = 0; MXL5005_ControlInit()
1534 state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; MXL5005_ControlInit()
1535 state->CH_Ctrl[24].size = 1 ; MXL5005_ControlInit()
1536 state->CH_Ctrl[24].addr[0] = 111; MXL5005_ControlInit()
1537 state->CH_Ctrl[24].bit[0] = 3; MXL5005_ControlInit()
1538 state->CH_Ctrl[24].val[0] = 0; MXL5005_ControlInit()
1540 state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; MXL5005_ControlInit()
1541 state->CH_Ctrl[25].size = 1 ; MXL5005_ControlInit()
1542 state->CH_Ctrl[25].addr[0] = 112; MXL5005_ControlInit()
1543 state->CH_Ctrl[25].bit[0] = 7; MXL5005_ControlInit()
1544 state->CH_Ctrl[25].val[0] = 0; MXL5005_ControlInit()
1546 state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; MXL5005_ControlInit()
1547 state->CH_Ctrl[26].size = 1 ; MXL5005_ControlInit()
1548 state->CH_Ctrl[26].addr[0] = 136; MXL5005_ControlInit()
1549 state->CH_Ctrl[26].bit[0] = 7; MXL5005_ControlInit()
1550 state->CH_Ctrl[26].val[0] = 0; MXL5005_ControlInit()
1552 state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; MXL5005_ControlInit()
1553 state->CH_Ctrl[27].size = 1 ; MXL5005_ControlInit()
1554 state->CH_Ctrl[27].addr[0] = 149; MXL5005_ControlInit()
1555 state->CH_Ctrl[27].bit[0] = 7; MXL5005_ControlInit()
1556 state->CH_Ctrl[27].val[0] = 0; MXL5005_ControlInit()
1558 state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; MXL5005_ControlInit()
1559 state->CH_Ctrl[28].size = 1 ; MXL5005_ControlInit()
1560 state->CH_Ctrl[28].addr[0] = 149; MXL5005_ControlInit()
1561 state->CH_Ctrl[28].bit[0] = 6; MXL5005_ControlInit()
1562 state->CH_Ctrl[28].val[0] = 0; MXL5005_ControlInit()
1564 state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; MXL5005_ControlInit()
1565 state->CH_Ctrl[29].size = 1 ; MXL5005_ControlInit()
1566 state->CH_Ctrl[29].addr[0] = 149; MXL5005_ControlInit()
1567 state->CH_Ctrl[29].bit[0] = 5; MXL5005_ControlInit()
1568 state->CH_Ctrl[29].val[0] = 1; MXL5005_ControlInit()
1570 state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; MXL5005_ControlInit()
1571 state->CH_Ctrl[30].size = 1 ; MXL5005_ControlInit()
1572 state->CH_Ctrl[30].addr[0] = 149; MXL5005_ControlInit()
1573 state->CH_Ctrl[30].bit[0] = 4; MXL5005_ControlInit()
1574 state->CH_Ctrl[30].val[0] = 1; MXL5005_ControlInit()
1576 state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; MXL5005_ControlInit()
1577 state->CH_Ctrl[31].size = 1 ; MXL5005_ControlInit()
1578 state->CH_Ctrl[31].addr[0] = 149; MXL5005_ControlInit()
1579 state->CH_Ctrl[31].bit[0] = 3; MXL5005_ControlInit()
1580 state->CH_Ctrl[31].val[0] = 0; MXL5005_ControlInit()
1582 state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; MXL5005_ControlInit()
1583 state->CH_Ctrl[32].size = 1 ; MXL5005_ControlInit()
1584 state->CH_Ctrl[32].addr[0] = 93; MXL5005_ControlInit()
1585 state->CH_Ctrl[32].bit[0] = 1; MXL5005_ControlInit()
1586 state->CH_Ctrl[32].val[0] = 0; MXL5005_ControlInit()
1588 state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; MXL5005_ControlInit()
1589 state->CH_Ctrl[33].size = 1 ; MXL5005_ControlInit()
1590 state->CH_Ctrl[33].addr[0] = 93; MXL5005_ControlInit()
1591 state->CH_Ctrl[33].bit[0] = 0; MXL5005_ControlInit()
1592 state->CH_Ctrl[33].val[0] = 0; MXL5005_ControlInit()
1594 state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; MXL5005_ControlInit()
1595 state->CH_Ctrl[34].size = 6 ; MXL5005_ControlInit()
1596 state->CH_Ctrl[34].addr[0] = 92; MXL5005_ControlInit()
1597 state->CH_Ctrl[34].bit[0] = 2; MXL5005_ControlInit()
1598 state->CH_Ctrl[34].val[0] = 0; MXL5005_ControlInit()
1599 state->CH_Ctrl[34].addr[1] = 92; MXL5005_ControlInit()
1600 state->CH_Ctrl[34].bit[1] = 3; MXL5005_ControlInit()
1601 state->CH_Ctrl[34].val[1] = 0; MXL5005_ControlInit()
1602 state->CH_Ctrl[34].addr[2] = 92; MXL5005_ControlInit()
1603 state->CH_Ctrl[34].bit[2] = 4; MXL5005_ControlInit()
1604 state->CH_Ctrl[34].val[2] = 0; MXL5005_ControlInit()
1605 state->CH_Ctrl[34].addr[3] = 92; MXL5005_ControlInit()
1606 state->CH_Ctrl[34].bit[3] = 5; MXL5005_ControlInit()
1607 state->CH_Ctrl[34].val[3] = 0; MXL5005_ControlInit()
1608 state->CH_Ctrl[34].addr[4] = 92; MXL5005_ControlInit()
1609 state->CH_Ctrl[34].bit[4] = 6; MXL5005_ControlInit()
1610 state->CH_Ctrl[34].val[4] = 0; MXL5005_ControlInit()
1611 state->CH_Ctrl[34].addr[5] = 92; MXL5005_ControlInit()
1612 state->CH_Ctrl[34].bit[5] = 7; MXL5005_ControlInit()
1613 state->CH_Ctrl[34].val[5] = 0; MXL5005_ControlInit()
1615 state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; MXL5005_ControlInit()
1616 state->CH_Ctrl[35].size = 6 ; MXL5005_ControlInit()
1617 state->CH_Ctrl[35].addr[0] = 93; MXL5005_ControlInit()
1618 state->CH_Ctrl[35].bit[0] = 2; MXL5005_ControlInit()
1619 state->CH_Ctrl[35].val[0] = 0; MXL5005_ControlInit()
1620 state->CH_Ctrl[35].addr[1] = 93; MXL5005_ControlInit()
1621 state->CH_Ctrl[35].bit[1] = 3; MXL5005_ControlInit()
1622 state->CH_Ctrl[35].val[1] = 0; MXL5005_ControlInit()
1623 state->CH_Ctrl[35].addr[2] = 93; MXL5005_ControlInit()
1624 state->CH_Ctrl[35].bit[2] = 4; MXL5005_ControlInit()
1625 state->CH_Ctrl[35].val[2] = 0; MXL5005_ControlInit()
1626 state->CH_Ctrl[35].addr[3] = 93; MXL5005_ControlInit()
1627 state->CH_Ctrl[35].bit[3] = 5; MXL5005_ControlInit()
1628 state->CH_Ctrl[35].val[3] = 0; MXL5005_ControlInit()
1629 state->CH_Ctrl[35].addr[4] = 93; MXL5005_ControlInit()
1630 state->CH_Ctrl[35].bit[4] = 6; MXL5005_ControlInit()
1631 state->CH_Ctrl[35].val[4] = 0; MXL5005_ControlInit()
1632 state->CH_Ctrl[35].addr[5] = 93; MXL5005_ControlInit()
1633 state->CH_Ctrl[35].bit[5] = 7; MXL5005_ControlInit()
1634 state->CH_Ctrl[35].val[5] = 0; MXL5005_ControlInit()
1637 state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; MXL5005_ControlInit()
1638 state->CH_Ctrl[36].size = 1 ; MXL5005_ControlInit()
1639 state->CH_Ctrl[36].addr[0] = 109; MXL5005_ControlInit()
1640 state->CH_Ctrl[36].bit[0] = 1; MXL5005_ControlInit()
1641 state->CH_Ctrl[36].val[0] = 1; MXL5005_ControlInit()
1643 state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; MXL5005_ControlInit()
1644 state->CH_Ctrl[37].size = 2 ; MXL5005_ControlInit()
1645 state->CH_Ctrl[37].addr[0] = 112; MXL5005_ControlInit()
1646 state->CH_Ctrl[37].bit[0] = 5; MXL5005_ControlInit()
1647 state->CH_Ctrl[37].val[0] = 0; MXL5005_ControlInit()
1648 state->CH_Ctrl[37].addr[1] = 112; MXL5005_ControlInit()
1649 state->CH_Ctrl[37].bit[1] = 6; MXL5005_ControlInit()
1650 state->CH_Ctrl[37].val[1] = 0; MXL5005_ControlInit()
1652 state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; MXL5005_ControlInit()
1653 state->CH_Ctrl[38].size = 1 ; MXL5005_ControlInit()
1654 state->CH_Ctrl[38].addr[0] = 65; MXL5005_ControlInit()
1655 state->CH_Ctrl[38].bit[0] = 1; MXL5005_ControlInit()
1656 state->CH_Ctrl[38].val[0] = 0; MXL5005_ControlInit()
1694 struct mxl5005s_state *state = fe->tuner_priv; MXL5005_TunerConfig() local
1696 state->Mode = Mode; MXL5005_TunerConfig()
1697 state->IF_Mode = IF_mode; MXL5005_TunerConfig()
1698 state->Chan_Bandwidth = Bandwidth; MXL5005_TunerConfig()
1699 state->IF_OUT = IF_out; MXL5005_TunerConfig()
1700 state->Fxtal = Fxtal; MXL5005_TunerConfig()
1701 state->AGC_Mode = AGC_Mode; MXL5005_TunerConfig()
1702 state->TOP = TOP; MXL5005_TunerConfig()
1703 state->IF_OUT_LOAD = IF_OUT_LOAD; MXL5005_TunerConfig()
1704 state->CLOCK_OUT = CLOCK_OUT; MXL5005_TunerConfig()
1705 state->DIV_OUT = DIV_OUT; MXL5005_TunerConfig()
1706 state->CAPSELECT = CAPSELECT; MXL5005_TunerConfig()
1707 state->EN_RSSI = EN_RSSI; MXL5005_TunerConfig()
1708 state->Mod_Type = Mod_Type; MXL5005_TunerConfig()
1709 state->TF_Type = TF_Type; MXL5005_TunerConfig()
1722 struct mxl5005s_state *state = fe->tuner_priv; MXL_SynthIFLO_Calc() local
1723 if (state->Mode == 1) /* Digital Mode */ MXL_SynthIFLO_Calc()
1724 state->IF_LO = state->IF_OUT; MXL_SynthIFLO_Calc()
1726 if (state->IF_Mode == 0) /* Analog Zero IF mode */ MXL_SynthIFLO_Calc()
1727 state->IF_LO = state->IF_OUT + 400000; MXL_SynthIFLO_Calc()
1729 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; MXL_SynthIFLO_Calc()
1735 struct mxl5005s_state *state = fe->tuner_priv; MXL_SynthRFTGLO_Calc() local
1737 if (state->Mode == 1) /* Digital Mode */ { MXL_SynthRFTGLO_Calc()
1739 state->RF_LO = state->RF_IN; MXL_SynthRFTGLO_Calc()
1741 state->TG_LO = state->RF_IN - 750000; MXL_SynthRFTGLO_Calc()
1743 if (state->IF_Mode == 0) /* Analog Zero IF mode */ { MXL_SynthRFTGLO_Calc()
1744 state->RF_LO = state->RF_IN - 400000; MXL_SynthRFTGLO_Calc()
1745 state->TG_LO = state->RF_IN - 1750000; MXL_SynthRFTGLO_Calc()
1747 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; MXL_SynthRFTGLO_Calc()
1748 state->TG_LO = state->RF_IN - MXL_SynthRFTGLO_Calc()
1749 state->Chan_Bandwidth + 500000; MXL_SynthRFTGLO_Calc()
1768 struct mxl5005s_state *state = fe->tuner_priv; MXL_BlockInit() local
1774 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); MXL_BlockInit()
1777 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); MXL_BlockInit()
1778 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); MXL_BlockInit()
1779 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); MXL_BlockInit()
1780 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); MXL_BlockInit()
1784 if (state->Mode) { /* Digital Mode */ MXL_BlockInit()
1785 switch (state->Chan_Bandwidth) { MXL_BlockInit()
1798 switch (state->Chan_Bandwidth) { MXL_BlockInit()
1801 (state->IF_Mode ? 0 : 3)); MXL_BlockInit()
1805 (state->IF_Mode ? 1 : 4)); MXL_BlockInit()
1809 (state->IF_Mode ? 2 : 5)); MXL_BlockInit()
1815 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); MXL_BlockInit()
1817 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); MXL_BlockInit()
1818 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); MXL_BlockInit()
1821 if (state->AGC_Mode == 0) /* Dual AGC */ { MXL_BlockInit()
1825 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); MXL_BlockInit()
1827 if (state->TOP == 55) /* TOP == 5.5 */ MXL_BlockInit()
1830 if (state->TOP == 72) /* TOP == 7.2 */ MXL_BlockInit()
1833 if (state->TOP == 92) /* TOP == 9.2 */ MXL_BlockInit()
1836 if (state->TOP == 110) /* TOP == 11.0 */ MXL_BlockInit()
1839 if (state->TOP == 129) /* TOP == 12.9 */ MXL_BlockInit()
1842 if (state->TOP == 147) /* TOP == 14.7 */ MXL_BlockInit()
1845 if (state->TOP == 168) /* TOP == 16.8 */ MXL_BlockInit()
1848 if (state->TOP == 194) /* TOP == 19.4 */ MXL_BlockInit()
1851 if (state->TOP == 212) /* TOP == 21.2 */ MXL_BlockInit()
1854 if (state->TOP == 232) /* TOP == 23.2 */ MXL_BlockInit()
1857 if (state->TOP == 252) /* TOP == 25.2 */ MXL_BlockInit()
1860 if (state->TOP == 271) /* TOP == 27.1 */ MXL_BlockInit()
1863 if (state->TOP == 292) /* TOP == 29.2 */ MXL_BlockInit()
1866 if (state->TOP == 317) /* TOP == 31.7 */ MXL_BlockInit()
1869 if (state->TOP == 349) /* TOP == 34.9 */ MXL_BlockInit()
1876 if (state->IF_OUT_LOAD == 200) { MXL_BlockInit()
1880 if (state->IF_OUT_LOAD == 300) { MXL_BlockInit()
1888 if (state->Mode) { /* Digital Mode */ MXL_BlockInit()
1889 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) { MXL_BlockInit()
1895 if ((state->IF_OUT == 36125000UL) || MXL_BlockInit()
1896 (state->IF_OUT == 36150000UL)) { MXL_BlockInit()
1902 if (state->IF_OUT > 36150000UL) { MXL_BlockInit()
1909 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { MXL_BlockInit()
1915 if (state->IF_OUT > 5000000UL) { MXL_BlockInit()
1924 if (state->CLOCK_OUT) MXL_BlockInit()
1929 if (state->DIV_OUT == 1) MXL_BlockInit()
1931 if (state->DIV_OUT == 0) MXL_BlockInit()
1935 if (state->CAPSELECT) MXL_BlockInit()
1940 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) MXL_BlockInit()
1942 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) MXL_BlockInit()
1945 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) MXL_BlockInit()
1947 if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL) MXL_BlockInit()
1951 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ MXL_BlockInit()
1960 MXL_Ceiling(state->Fxtal, 1000000)); MXL_BlockInit()
1965 if (state->EN_RSSI) { MXL_BlockInit()
1984 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { MXL_BlockInit()
1985 state->AGC_Mode = 1; /* Single AGC Mode */ MXL_BlockInit()
2001 if (state->IF_OUT <= 6280000UL) /* Low IF */ MXL_BlockInit()
2007 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { MXL_BlockInit()
2008 state->AGC_Mode = 1; /* Single AGC Mode */ MXL_BlockInit()
2028 if (state->IF_OUT <= 6280000UL) /* Low IF */ MXL_BlockInit()
2033 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { MXL_BlockInit()
2034 state->Mode = MXL_DIGITAL_MODE; MXL_BlockInit()
2036 /* state->AGC_Mode = 1; */ /* Single AGC Mode */ MXL_BlockInit()
2051 if (state->IF_OUT <= 6280000UL) /* Low IF */ MXL_BlockInit()
2058 if (state->Mod_Type == MXL_ANALOG_CABLE) { MXL_BlockInit()
2060 /* state->Mode = MXL_DIGITAL_MODE; */ MXL_BlockInit()
2062 state->AGC_Mode = 1; /* Single AGC Mode */ MXL_BlockInit()
2075 if (state->Mod_Type == MXL_ANALOG_OTA) { MXL_BlockInit()
2077 /* state->Mode = MXL_ANALOG_MODE; */ MXL_BlockInit()
2094 if (state->EN_RSSI == 0) { MXL_BlockInit()
2106 struct mxl5005s_state *state = fe->tuner_priv; MXL_IFSynthInit() local
2113 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) MXL_IFSynthInit()
2115 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) MXL_IFSynthInit()
2119 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { MXL_IFSynthInit()
2120 if (state->IF_LO == 41000000UL) { MXL_IFSynthInit()
2125 if (state->IF_LO == 47000000UL) { MXL_IFSynthInit()
2130 if (state->IF_LO == 54000000UL) { MXL_IFSynthInit()
2135 if (state->IF_LO == 60000000UL) { MXL_IFSynthInit()
2140 if (state->IF_LO == 39250000UL) { MXL_IFSynthInit()
2145 if (state->IF_LO == 39650000UL) { MXL_IFSynthInit()
2150 if (state->IF_LO == 40150000UL) { MXL_IFSynthInit()
2155 if (state->IF_LO == 40650000UL) { MXL_IFSynthInit()
2162 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { MXL_IFSynthInit()
2163 if (state->IF_LO == 57000000UL) { MXL_IFSynthInit()
2168 if (state->IF_LO == 44000000UL) { MXL_IFSynthInit()
2173 if (state->IF_LO == 43750000UL) { MXL_IFSynthInit()
2178 if (state->IF_LO == 36650000UL) { MXL_IFSynthInit()
2183 if (state->IF_LO == 36150000UL) { MXL_IFSynthInit()
2188 if (state->IF_LO == 36000000UL) { MXL_IFSynthInit()
2193 if (state->IF_LO == 35250000UL) { MXL_IFSynthInit()
2198 if (state->IF_LO == 34750000UL) { MXL_IFSynthInit()
2203 if (state->IF_LO == 6280000UL) { MXL_IFSynthInit()
2208 if (state->IF_LO == 5000000UL) { MXL_IFSynthInit()
2213 if (state->IF_LO == 4500000UL) { MXL_IFSynthInit()
2218 if (state->IF_LO == 4570000UL) { MXL_IFSynthInit()
2223 if (state->IF_LO == 4000000UL) { MXL_IFSynthInit()
2228 if (state->IF_LO == 57400000UL) { MXL_IFSynthInit()
2233 if (state->IF_LO == 44400000UL) { MXL_IFSynthInit()
2238 if (state->IF_LO == 44150000UL) { MXL_IFSynthInit()
2243 if (state->IF_LO == 37050000UL) { MXL_IFSynthInit()
2248 if (state->IF_LO == 36550000UL) { MXL_IFSynthInit()
2253 if (state->IF_LO == 36125000UL) { MXL_IFSynthInit()
2258 if (state->IF_LO == 6000000UL) { MXL_IFSynthInit()
2263 if (state->IF_LO == 5400000UL) { MXL_IFSynthInit()
2268 if (state->IF_LO == 5380000UL) { MXL_IFSynthInit()
2273 if (state->IF_LO == 5200000UL) { MXL_IFSynthInit()
2278 if (state->IF_LO == 4900000UL) { MXL_IFSynthInit()
2283 if (state->IF_LO == 4400000UL) { MXL_IFSynthInit()
2288 if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ { MXL_IFSynthInit()
2296 intModVal = Fref / (state->Fxtal * Kdbl/2); MXL_IFSynthInit()
2299 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * MXL_IFSynthInit()
2302 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000); MXL_IFSynthInit()
2310 struct mxl5005s_state *state = fe->tuner_priv; MXL_TuneRF() local
2321 state->RF_IN = RF_Freq; MXL_TuneRF()
2325 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) MXL_TuneRF()
2327 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) MXL_TuneRF()
2339 if (state->RF_LO < 40000000UL) MXL_TuneRF()
2342 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { MXL_TuneRF()
2349 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { MXL_TuneRF()
2356 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { MXL_TuneRF()
2363 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { MXL_TuneRF()
2370 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { MXL_TuneRF()
2377 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { MXL_TuneRF()
2384 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { MXL_TuneRF()
2391 if (state->RF_LO > 900000000UL) MXL_TuneRF()
2396 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { MXL_TuneRF()
2400 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { MXL_TuneRF()
2404 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { MXL_TuneRF()
2408 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { MXL_TuneRF()
2412 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { MXL_TuneRF()
2416 if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) { MXL_TuneRF()
2420 if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) { MXL_TuneRF()
2424 if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) { MXL_TuneRF()
2428 if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) { MXL_TuneRF()
2432 if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) { MXL_TuneRF()
2436 if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) { MXL_TuneRF()
2440 if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) { MXL_TuneRF()
2444 if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) { MXL_TuneRF()
2448 if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) { MXL_TuneRF()
2452 if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) { MXL_TuneRF()
2456 if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) { MXL_TuneRF()
2476 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2489 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2502 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2515 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2528 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2541 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2554 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2567 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2580 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2593 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2606 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { MXL_TuneRF()
2624 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; MXL_TuneRF()
2628 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000); MXL_TuneRF()
2632 E5 = ((2<<17)*(state->RF_LO/10000*divider_val - MXL_TuneRF()
2633 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) / MXL_TuneRF()
2634 (2*state->Fxtal*Kdbl_RF/10000); MXL_TuneRF()
2639 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; MXL_TuneRF()
2659 if (state->TG_LO < 33000000UL) MXL_TuneRF()
2664 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2673 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2682 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2691 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2700 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2709 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2718 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2727 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2736 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { MXL_TuneRF()
2745 tg_divval = (state->TG_LO*divider_val/100000) * MXL_TuneRF()
2746 (MXL_Ceiling(state->Fxtal, 1000000) * 100) / MXL_TuneRF()
2747 (state->Fxtal/1000); MXL_TuneRF()
2751 if (state->TG_LO > 600000000UL) MXL_TuneRF()
2761 Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000); MXL_TuneRF()
2764 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; MXL_TuneRF()
2778 * u32 Xtal_Int = MXL_GetXtalInt(state->Fxtal); MXL_TuneRF()
2780 * ((state->TG_LO/10000)*divider_val * MXL_TuneRF()
2781 * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * MXL_TuneRF()
2788 if (state->Mod_Type == MXL_QAM) { MXL_TuneRF()
2789 if (state->config->qam_gain != 0) MXL_TuneRF()
2791 state->config->qam_gain); MXL_TuneRF()
2792 else if (state->RF_IN < 680000000) MXL_TuneRF()
2799 if (state->TF_Type == MXL_TF_OFF) { MXL_TuneRF()
2808 if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ { MXL_TuneRF()
2812 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { MXL_TuneRF()
2819 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { MXL_TuneRF()
2826 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { MXL_TuneRF()
2833 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { MXL_TuneRF()
2840 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { MXL_TuneRF()
2847 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { MXL_TuneRF()
2854 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { MXL_TuneRF()
2861 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { MXL_TuneRF()
2868 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
2877 if (state->TF_Type == MXL_TF_C_H) { MXL_TuneRF()
2882 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { MXL_TuneRF()
2888 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { MXL_TuneRF()
2894 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { MXL_TuneRF()
2900 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { MXL_TuneRF()
2906 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { MXL_TuneRF()
2912 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { MXL_TuneRF()
2918 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { MXL_TuneRF()
2924 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { MXL_TuneRF()
2930 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
2938 if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */ MXL_TuneRF()
2942 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { MXL_TuneRF()
2948 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { MXL_TuneRF()
2954 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { MXL_TuneRF()
2960 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { MXL_TuneRF()
2966 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { MXL_TuneRF()
2972 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { MXL_TuneRF()
2978 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
2986 if (state->TF_Type == MXL_TF_D_L) { MXL_TuneRF()
2992 if (state->RF_IN >= 471000000 && MXL_TuneRF()
2993 (state->RF_IN - 471000000)%6000000 != 0) { MXL_TuneRF()
3002 if (state->RF_IN >= 43000000 && MXL_TuneRF()
3003 state->RF_IN < 140000000) { MXL_TuneRF()
3010 if (state->RF_IN >= 140000000 && MXL_TuneRF()
3011 state->RF_IN < 240000000) { MXL_TuneRF()
3017 if (state->RF_IN >= 240000000 && MXL_TuneRF()
3018 state->RF_IN < 340000000) { MXL_TuneRF()
3024 if (state->RF_IN >= 340000000 && MXL_TuneRF()
3025 state->RF_IN < 430000000) { MXL_TuneRF()
3031 if (state->RF_IN >= 430000000 && MXL_TuneRF()
3032 state->RF_IN < 470000000) { MXL_TuneRF()
3038 if (state->RF_IN >= 470000000 && MXL_TuneRF()
3039 state->RF_IN < 570000000) { MXL_TuneRF()
3045 if (state->RF_IN >= 570000000 && MXL_TuneRF()
3046 state->RF_IN < 620000000) { MXL_TuneRF()
3052 if (state->RF_IN >= 620000000 && MXL_TuneRF()
3053 state->RF_IN < 760000000) { MXL_TuneRF()
3059 if (state->RF_IN >= 760000000 && MXL_TuneRF()
3060 state->RF_IN <= 900000000) { MXL_TuneRF()
3069 if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ { MXL_TuneRF()
3073 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { MXL_TuneRF()
3079 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { MXL_TuneRF()
3085 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { MXL_TuneRF()
3091 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { MXL_TuneRF()
3097 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { MXL_TuneRF()
3103 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { MXL_TuneRF()
3109 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
3117 if (state->TF_Type == MXL_TF_F) { MXL_TuneRF()
3122 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { MXL_TuneRF()
3128 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { MXL_TuneRF()
3134 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { MXL_TuneRF()
3140 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { MXL_TuneRF()
3146 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { MXL_TuneRF()
3152 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { MXL_TuneRF()
3158 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
3166 if (state->TF_Type == MXL_TF_E_2) { MXL_TuneRF()
3171 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { MXL_TuneRF()
3177 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { MXL_TuneRF()
3183 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { MXL_TuneRF()
3189 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { MXL_TuneRF()
3195 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { MXL_TuneRF()
3201 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { MXL_TuneRF()
3207 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
3215 if (state->TF_Type == MXL_TF_G) { MXL_TuneRF()
3220 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { MXL_TuneRF()
3227 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { MXL_TuneRF()
3233 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { MXL_TuneRF()
3239 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { MXL_TuneRF()
3245 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) { MXL_TuneRF()
3251 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { MXL_TuneRF()
3257 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { MXL_TuneRF()
3263 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
3271 if (state->TF_Type == MXL_TF_E_NA) { MXL_TuneRF()
3277 if (state->RF_IN >= 471000000 && MXL_TuneRF()
3278 (state->RF_IN - 471000000)%6000000 != 0) { MXL_TuneRF()
3310 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { MXL_TuneRF()
3317 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { MXL_TuneRF()
3323 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { MXL_TuneRF()
3329 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { MXL_TuneRF()
3335 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { MXL_TuneRF()
3341 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { MXL_TuneRF()
3347 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { MXL_TuneRF()
3376 if (GPIO_Val == 3) { /* tri-state */ MXL_SetGPIO()
3390 if (GPIO_Val == 3) { /* tri-state */ MXL_SetGPIO()
3418 struct mxl5005s_state *state = fe->tuner_priv; MXL_ControlWrite_Group() local
3425 for (i = 0; i < state->Init_Ctrl_Num; i++) { MXL_ControlWrite_Group()
3427 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { MXL_ControlWrite_Group()
3429 highLimit = 1 << state->Init_Ctrl[i].size; MXL_ControlWrite_Group()
3431 for (j = 0; j < state->Init_Ctrl[i].size; j++) { MXL_ControlWrite_Group()
3432 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_ControlWrite_Group()
3433 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), MXL_ControlWrite_Group()
3434 (u8)(state->Init_Ctrl[i].bit[j]), MXL_ControlWrite_Group()
3438 for (k = 0; k < state->Init_Ctrl[i].size; k++) MXL_ControlWrite_Group()
3439 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); MXL_ControlWrite_Group()
3447 for (i = 0; i < state->CH_Ctrl_Num; i++) { MXL_ControlWrite_Group()
3449 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { MXL_ControlWrite_Group()
3451 highLimit = 1 << state->CH_Ctrl[i].size; MXL_ControlWrite_Group()
3453 for (j = 0; j < state->CH_Ctrl[i].size; j++) { MXL_ControlWrite_Group()
3454 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_ControlWrite_Group()
3455 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), MXL_ControlWrite_Group()
3456 (u8)(state->CH_Ctrl[i].bit[j]), MXL_ControlWrite_Group()
3460 for (k = 0; k < state->CH_Ctrl[i].size; k++) MXL_ControlWrite_Group()
3461 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); MXL_ControlWrite_Group()
3470 for (i = 0; i < state->MXL_Ctrl_Num; i++) { MXL_ControlWrite_Group()
3472 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { MXL_ControlWrite_Group()
3474 highLimit = (1 << state->MXL_Ctrl[i].size); MXL_ControlWrite_Group()
3476 for (j = 0; j < state->MXL_Ctrl[i].size; j++) { MXL_ControlWrite_Group()
3477 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_ControlWrite_Group()
3478 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), MXL_ControlWrite_Group()
3479 (u8)(state->MXL_Ctrl[i].bit[j]), MXL_ControlWrite_Group()
3483 for (k = 0; k < state->MXL_Ctrl[i].size; k++) MXL_ControlWrite_Group()
3484 ctrlVal += state-> MXL_ControlWrite_Group()
3498 struct mxl5005s_state *state = fe->tuner_priv; MXL_RegRead() local
3502 if (RegNum == state->TunerRegs[i].Reg_Num) { MXL_RegRead()
3503 *RegVal = (u8)(state->TunerRegs[i].Reg_Val); MXL_RegRead()
3513 struct mxl5005s_state *state = fe->tuner_priv; MXL_ControlRead() local
3517 for (i = 0; i < state->Init_Ctrl_Num ; i++) { MXL_ControlRead()
3519 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { MXL_ControlRead()
3522 for (k = 0; k < state->Init_Ctrl[i].size; k++) MXL_ControlRead()
3523 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k); MXL_ControlRead()
3529 for (i = 0; i < state->CH_Ctrl_Num ; i++) { MXL_ControlRead()
3531 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { MXL_ControlRead()
3534 for (k = 0; k < state->CH_Ctrl[i].size; k++) MXL_ControlRead()
3535 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); MXL_ControlRead()
3543 for (i = 0; i < state->MXL_Ctrl_Num ; i++) { MXL_ControlRead()
3545 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { MXL_ControlRead()
3548 for (k = 0; k < state->MXL_Ctrl[i].size; k++) MXL_ControlRead()
3549 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k); MXL_ControlRead()
3562 struct mxl5005s_state *state = fe->tuner_priv; MXL_RegWriteBit() local
3573 for (i = 0; i < state->TunerRegs_Num; i++) { MXL_RegWriteBit()
3574 if (state->TunerRegs[i].Reg_Num == address) { MXL_RegWriteBit()
3576 state->TunerRegs[i].Reg_Val |= OR_MAP[bit]; MXL_RegWriteBit()
3578 state->TunerRegs[i].Reg_Val &= AND_MAP[bit]; MXL_RegWriteBit()
3661 static u16 MXL_GetMasterControl(u8 *MasterReg, int state) MXL_GetMasterControl() argument
3663 if (state == 1) /* Load_Start */ MXL_GetMasterControl()
3665 if (state == 2) /* Power_Down */ MXL_GetMasterControl()
3667 if (state == 3) /* Synth_Reset */ MXL_GetMasterControl()
3669 if (state == 4) /* Seq_Off */ MXL_GetMasterControl()
3678 struct mxl5005s_state *state = fe->tuner_priv; MXL_VCORange_Test() local
3689 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3697 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3705 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
3725 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3733 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3741 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
3761 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3769 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3777 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
3797 if (state->Mode == 0 && state->IF_Mode == 1) { MXL_VCORange_Test()
3805 if (state->Mode == 0 && state->IF_Mode == 0) { MXL_VCORange_Test()
3813 if (state->Mode == 1) /* Digital Mode */ { MXL_VCORange_Test()
3827 struct mxl5005s_state *state = fe->tuner_priv; MXL_Hystersis_Test() local
3846 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_reset() local
3850 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, mxl5005s_reset()
3858 if (i2c_transfer(state->i2c, &msg, 1) != 1) { mxl5005s_reset()
3874 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_writereg() local
3876 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, mxl5005s_writereg()
3884 if (i2c_transfer(state->i2c, &msg, 1) != 1) { mxl5005s_writereg()
3915 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_init() local
3918 state->current_mode = MXL_QAM; mxl5005s_init()
3925 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_reconfigure() local
3938 ByteTable[0] |= state->config->AgcMasterByte; mxl5005s_reconfigure()
3955 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_AssignTunerMode() local
3956 struct mxl5005s_config *c = state->config; mxl5005s_AssignTunerMode()
3983 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_set_params() local
4020 if (req_mode != state->current_mode || mxl5005s_set_params()
4021 req_bw != state->Chan_Bandwidth) { mxl5005s_set_params()
4022 state->current_mode = req_mode; mxl5005s_set_params()
4038 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_get_frequency() local
4041 *frequency = state->RF_IN; mxl5005s_get_frequency()
4048 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_get_bandwidth() local
4051 *bandwidth = state->Chan_Bandwidth; mxl5005s_get_bandwidth()
4058 struct mxl5005s_state *state = fe->tuner_priv; mxl5005s_get_if_frequency() local
4061 *frequency = state->IF_OUT; mxl5005s_get_if_frequency()
4095 struct mxl5005s_state *state = NULL; mxl5005s_attach() local
4098 state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL); mxl5005s_attach()
4099 if (state == NULL) mxl5005s_attach()
4102 state->frontend = fe; mxl5005s_attach()
4103 state->config = config; mxl5005s_attach()
4104 state->i2c = i2c; mxl5005s_attach()
4112 fe->tuner_priv = state; mxl5005s_attach()
H A Dqm1d1c0042.c63 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) reg_write() argument
68 ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf)); reg_write()
74 static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val) reg_read() argument
78 .addr = state->i2c->addr, reg_read()
84 .addr = state->i2c->addr, reg_read()
92 ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs)); reg_read()
99 static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast) qm1d1c0042_set_srch_mode() argument
102 state->regs[0x03] |= 0x01; /* set fast search mode */ qm1d1c0042_set_srch_mode()
104 state->regs[0x03] &= ~0x01 & 0xff; qm1d1c0042_set_srch_mode()
106 return reg_write(state, 0x03, state->regs[0x03]); qm1d1c0042_set_srch_mode()
109 static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state) qm1d1c0042_wakeup() argument
113 state->regs[0x01] |= 1 << 3; /* BB_Reg_enable */ qm1d1c0042_wakeup()
114 state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */ qm1d1c0042_wakeup()
115 state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */ qm1d1c0042_wakeup()
116 ret = reg_write(state, 0x01, state->regs[0x01]); qm1d1c0042_wakeup()
118 ret = reg_write(state, 0x05, state->regs[0x05]); qm1d1c0042_wakeup()
121 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", qm1d1c0042_wakeup()
122 __func__, state->cfg.fe->dvb->num, state->cfg.fe->id); qm1d1c0042_wakeup()
130 struct qm1d1c0042_state *state; qm1d1c0042_set_config() local
133 state = fe->tuner_priv; qm1d1c0042_set_config()
137 state->cfg.fe = cfg->fe; qm1d1c0042_set_config()
140 dev_warn(&state->i2c->dev, qm1d1c0042_set_config()
142 state->cfg.xtal_freq = default_cfg.xtal_freq; qm1d1c0042_set_config()
144 state->cfg.lpf = cfg->lpf; qm1d1c0042_set_config()
145 state->cfg.fast_srch = cfg->fast_srch; qm1d1c0042_set_config()
148 state->cfg.lpf_wait = cfg->lpf_wait; qm1d1c0042_set_config()
150 state->cfg.lpf_wait = default_cfg.lpf_wait; qm1d1c0042_set_config()
153 state->cfg.fast_srch_wait = cfg->fast_srch_wait; qm1d1c0042_set_config()
155 state->cfg.fast_srch_wait = default_cfg.fast_srch_wait; qm1d1c0042_set_config()
158 state->cfg.normal_srch_wait = cfg->normal_srch_wait; qm1d1c0042_set_config()
160 state->cfg.normal_srch_wait = default_cfg.normal_srch_wait; qm1d1c0042_set_config()
180 struct qm1d1c0042_state *state; qm1d1c0042_set_params() local
187 state = fe->tuner_priv; qm1d1c0042_set_params()
190 state->regs[0x08] &= 0xf0; qm1d1c0042_set_params()
191 state->regs[0x08] |= 0x09; qm1d1c0042_set_params()
193 state->regs[0x13] &= 0x9f; qm1d1c0042_set_params()
194 state->regs[0x13] |= 0x20; qm1d1c0042_set_params()
197 val = state->regs[0x02] & 0x0f; qm1d1c0042_set_params()
204 ret = reg_write(state, 0x02, val); qm1d1c0042_set_params()
208 a = (freq + state->cfg.xtal_freq / 2) / state->cfg.xtal_freq; qm1d1c0042_set_params()
210 state->regs[0x06] &= 0x40; qm1d1c0042_set_params()
211 state->regs[0x06] |= (a - 12) / 4; qm1d1c0042_set_params()
212 ret = reg_write(state, 0x06, state->regs[0x06]); qm1d1c0042_set_params()
216 state->regs[0x07] &= 0xf0; qm1d1c0042_set_params()
217 state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f; qm1d1c0042_set_params()
218 ret = reg_write(state, 0x07, state->regs[0x07]); qm1d1c0042_set_params()
223 val = state->regs[0x08]; qm1d1c0042_set_params()
224 if (state->cfg.lpf) { qm1d1c0042_set_params()
229 ret = reg_write(state, 0x08, val); qm1d1c0042_set_params()
234 * b = (freq / state->cfg.xtal_freq - a) << 20; qm1d1c0042_set_params()
238 b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq) qm1d1c0042_set_params()
246 state->regs[0x09] &= 0xc0; qm1d1c0042_set_params()
247 state->regs[0x09] |= (sd >> 16) & 0x3f; qm1d1c0042_set_params()
248 state->regs[0x0a] = (sd >> 8) & 0xff; qm1d1c0042_set_params()
249 state->regs[0x0b] = sd & 0xff; qm1d1c0042_set_params()
250 ret = reg_write(state, 0x09, state->regs[0x09]); qm1d1c0042_set_params()
252 ret = reg_write(state, 0x0a, state->regs[0x0a]); qm1d1c0042_set_params()
254 ret = reg_write(state, 0x0b, state->regs[0x0b]); qm1d1c0042_set_params()
258 if (!state->cfg.lpf) { qm1d1c0042_set_params()
260 ret = reg_write(state, 0x13, state->regs[0x13]); qm1d1c0042_set_params()
266 mask = state->cfg.lpf ? 0x3f : 0x7f; qm1d1c0042_set_params()
267 val = state->regs[0x0c] & mask; qm1d1c0042_set_params()
268 ret = reg_write(state, 0x0c, val); qm1d1c0042_set_params()
272 val = state->regs[0x0c] | ~mask; qm1d1c0042_set_params()
273 ret = reg_write(state, 0x0c, val); qm1d1c0042_set_params()
277 if (state->cfg.lpf) qm1d1c0042_set_params()
278 msleep(state->cfg.lpf_wait); qm1d1c0042_set_params()
279 else if (state->regs[0x03] & 0x01) qm1d1c0042_set_params()
280 msleep(state->cfg.fast_srch_wait); qm1d1c0042_set_params()
282 msleep(state->cfg.normal_srch_wait); qm1d1c0042_set_params()
284 if (state->cfg.lpf) { qm1d1c0042_set_params()
286 ret = reg_write(state, 0x08, 0x09); qm1d1c0042_set_params()
291 ret = reg_write(state, 0x13, state->regs[0x13]); qm1d1c0042_set_params()
300 struct qm1d1c0042_state *state; qm1d1c0042_sleep() local
303 state = fe->tuner_priv; qm1d1c0042_sleep()
304 state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */ qm1d1c0042_sleep()
305 state->regs[0x01] |= 1 << 0; /* STDBY */ qm1d1c0042_sleep()
306 state->regs[0x05] |= 1 << 3; /* pfd_rst STANDBY */ qm1d1c0042_sleep()
307 ret = reg_write(state, 0x05, state->regs[0x05]); qm1d1c0042_sleep()
309 ret = reg_write(state, 0x01, state->regs[0x01]); qm1d1c0042_sleep()
311 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", qm1d1c0042_sleep()
318 struct qm1d1c0042_state *state; qm1d1c0042_init() local
322 state = fe->tuner_priv; qm1d1c0042_init()
323 memcpy(state->regs, reg_initval, sizeof(reg_initval)); qm1d1c0042_init()
325 reg_write(state, 0x01, 0x0c); qm1d1c0042_init()
326 reg_write(state, 0x01, 0x0c); qm1d1c0042_init()
328 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */ qm1d1c0042_init()
333 val = state->regs[0x01] | 0x10; qm1d1c0042_init()
334 ret = reg_write(state, 0x01, val); /* soft reset off */ qm1d1c0042_init()
339 ret = reg_read(state, 0x00, &val); qm1d1c0042_init()
344 state->regs[0x0c] |= 0x40; qm1d1c0042_init()
345 ret = reg_write(state, 0x0c, state->regs[0x0c]); qm1d1c0042_init()
348 msleep(state->cfg.lpf_wait); qm1d1c0042_init()
352 ret = reg_write(state, i, state->regs[i]); qm1d1c0042_init()
357 ret = reg_write(state, i, state->regs[i]); qm1d1c0042_init()
362 ret = qm1d1c0042_wakeup(state); qm1d1c0042_init()
366 ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch); qm1d1c0042_init()
373 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", qm1d1c0042_init()
398 struct qm1d1c0042_state *state; qm1d1c0042_probe() local
402 state = kzalloc(sizeof(*state), GFP_KERNEL); qm1d1c0042_probe()
403 if (!state) qm1d1c0042_probe()
405 state->i2c = client; qm1d1c0042_probe()
409 fe->tuner_priv = state; qm1d1c0042_probe()
413 i2c_set_clientdata(client, &state->cfg); qm1d1c0042_probe()
420 struct qm1d1c0042_state *state; qm1d1c0042_remove() local
422 state = cfg_to_state(i2c_get_clientdata(client)); qm1d1c0042_remove()
423 state->cfg.fe->tuner_priv = NULL; qm1d1c0042_remove()
424 kfree(state); qm1d1c0042_remove()
H A Dmt2063.c248 static int mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len) mt2063_write() argument
250 struct dvb_frontend *fe = state->frontend; mt2063_write()
254 .addr = state->config->tuner_address, mt2063_write()
267 ret = i2c_transfer(state->i2c, &msg, 1); mt2063_write()
280 static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val) mt2063_setreg() argument
289 status = mt2063_write(state, reg, &val, 1); mt2063_setreg()
293 state->reg[reg] = val; mt2063_setreg()
301 static int mt2063_read(struct mt2063_state *state, mt2063_read() argument
305 struct dvb_frontend *fe = state->frontend; mt2063_read()
317 .addr = state->config->tuner_address, mt2063_read()
322 .addr = state->config->tuner_address, mt2063_read()
329 status = i2c_transfer(state->i2c, msg, 2); mt2063_read()
934 * @state: struct mt2063_state pointer
938 static int mt2063_lockStatus(struct mt2063_state *state) mt2063_lockStatus() argument
951 if (state->tuner_id == MT2063_B0) mt2063_lockStatus()
955 status = mt2063_read(state, MT2063_REG_LO_STATUS, mt2063_lockStatus()
956 &state->reg[MT2063_REG_LO_STATUS], 1); mt2063_lockStatus()
961 if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) == mt2063_lockStatus()
1047 static u32 mt2063_get_dnc_output_enable(struct mt2063_state *state, mt2063_get_dnc_output_enable() argument
1052 if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */ mt2063_get_dnc_output_enable()
1053 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ mt2063_get_dnc_output_enable()
1058 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ mt2063_get_dnc_output_enable()
1069 static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state, mt2063_set_dnc_output_enable() argument
1080 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ mt2063_set_dnc_output_enable()
1081 if (state->reg[MT2063_REG_DNC_GAIN] != mt2063_set_dnc_output_enable()
1084 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1088 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ mt2063_set_dnc_output_enable()
1089 if (state->reg[MT2063_REG_VGA_GAIN] != mt2063_set_dnc_output_enable()
1092 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1096 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ mt2063_set_dnc_output_enable()
1097 if (state->reg[MT2063_REG_RSVD_20] != mt2063_set_dnc_output_enable()
1100 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1106 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */ mt2063_set_dnc_output_enable()
1107 if (state->reg[MT2063_REG_DNC_GAIN] != mt2063_set_dnc_output_enable()
1110 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1114 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ mt2063_set_dnc_output_enable()
1115 if (state->reg[MT2063_REG_VGA_GAIN] != mt2063_set_dnc_output_enable()
1118 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1122 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ mt2063_set_dnc_output_enable()
1123 if (state->reg[MT2063_REG_RSVD_20] != mt2063_set_dnc_output_enable()
1126 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1132 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ mt2063_set_dnc_output_enable()
1133 if (state->reg[MT2063_REG_DNC_GAIN] != mt2063_set_dnc_output_enable()
1136 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1140 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */ mt2063_set_dnc_output_enable()
1141 if (state->reg[MT2063_REG_VGA_GAIN] != mt2063_set_dnc_output_enable()
1144 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1148 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ mt2063_set_dnc_output_enable()
1149 if (state->reg[MT2063_REG_RSVD_20] != mt2063_set_dnc_output_enable()
1152 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1158 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */ mt2063_set_dnc_output_enable()
1159 if (state->reg[MT2063_REG_DNC_GAIN] != mt2063_set_dnc_output_enable()
1162 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1166 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */ mt2063_set_dnc_output_enable()
1167 if (state->reg[MT2063_REG_VGA_GAIN] != mt2063_set_dnc_output_enable()
1170 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1174 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ mt2063_set_dnc_output_enable()
1175 if (state->reg[MT2063_REG_RSVD_20] != mt2063_set_dnc_output_enable()
1178 mt2063_setreg(state, mt2063_set_dnc_output_enable()
1197 * @state: ptr to mt2063_state structure
1203 static u32 MT2063_SetReceiverMode(struct mt2063_state *state, MT2063_SetReceiverMode() argument
1218 (state-> MT2063_SetReceiverMode()
1222 if (state->reg[MT2063_REG_PD1_TGT] != val) MT2063_SetReceiverMode()
1223 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); MT2063_SetReceiverMode()
1228 u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) | MT2063_SetReceiverMode()
1230 if (state->reg[MT2063_REG_CTRL_2C] != val) MT2063_SetReceiverMode()
1231 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val); MT2063_SetReceiverMode()
1237 (state-> MT2063_SetReceiverMode()
1240 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) { MT2063_SetReceiverMode()
1242 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val); MT2063_SetReceiverMode()
1245 (state->reg[MT2063_REG_FIFF_CTRL] | 0x01); MT2063_SetReceiverMode()
1247 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); MT2063_SetReceiverMode()
1249 (state-> MT2063_SetReceiverMode()
1252 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); MT2063_SetReceiverMode()
1257 status |= mt2063_get_dnc_output_enable(state, &longval); MT2063_SetReceiverMode()
1258 status |= mt2063_set_dnc_output_enable(state, longval); MT2063_SetReceiverMode()
1262 u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) | MT2063_SetReceiverMode()
1264 if (state->reg[MT2063_REG_LNA_OV] != val) MT2063_SetReceiverMode()
1265 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val); MT2063_SetReceiverMode()
1270 u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) | MT2063_SetReceiverMode()
1272 if (state->reg[MT2063_REG_LNA_TGT] != val) MT2063_SetReceiverMode()
1273 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); MT2063_SetReceiverMode()
1278 u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) | MT2063_SetReceiverMode()
1280 if (state->reg[MT2063_REG_RF_OV] != val) MT2063_SetReceiverMode()
1281 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val); MT2063_SetReceiverMode()
1286 u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) | MT2063_SetReceiverMode()
1288 if (state->reg[MT2063_REG_PD1_TGT] != val) MT2063_SetReceiverMode()
1289 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); MT2063_SetReceiverMode()
1295 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5) MT2063_SetReceiverMode()
1297 val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) | MT2063_SetReceiverMode()
1299 if (state->reg[MT2063_REG_FIF_OV] != val) MT2063_SetReceiverMode()
1300 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val); MT2063_SetReceiverMode()
1305 u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) | MT2063_SetReceiverMode()
1307 if (state->reg[MT2063_REG_PD2_TGT] != val) MT2063_SetReceiverMode()
1308 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val); MT2063_SetReceiverMode()
1313 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) | MT2063_SetReceiverMode()
1315 if (state->reg[MT2063_REG_LNA_TGT] != val) MT2063_SetReceiverMode()
1316 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); MT2063_SetReceiverMode()
1321 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) | MT2063_SetReceiverMode()
1323 if (state->reg[MT2063_REG_PD1_TGT] != val) MT2063_SetReceiverMode()
1324 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); MT2063_SetReceiverMode()
1328 state->rcvr_mode = Mode; MT2063_SetReceiverMode()
1330 mt2063_mode_name[state->rcvr_mode]); MT2063_SetReceiverMode()
1345 static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state, MT2063_ClearPowerMaskBits() argument
1353 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); MT2063_ClearPowerMaskBits()
1355 mt2063_write(state, MT2063_ClearPowerMaskBits()
1357 &state->reg[MT2063_REG_PWR_2], 1); MT2063_ClearPowerMaskBits()
1360 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); MT2063_ClearPowerMaskBits()
1362 mt2063_write(state, MT2063_ClearPowerMaskBits()
1364 &state->reg[MT2063_REG_PWR_1], 1); MT2063_ClearPowerMaskBits()
1375 static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown) MT2063_SoftwareShutdown() argument
1381 state->reg[MT2063_REG_PWR_1] |= 0x04; MT2063_SoftwareShutdown()
1383 state->reg[MT2063_REG_PWR_1] &= ~0x04; MT2063_SoftwareShutdown()
1385 status = mt2063_write(state, MT2063_SoftwareShutdown()
1387 &state->reg[MT2063_REG_PWR_1], 1); MT2063_SoftwareShutdown()
1390 state->reg[MT2063_REG_BYP_CTRL] = MT2063_SoftwareShutdown()
1391 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; MT2063_SoftwareShutdown()
1393 mt2063_write(state, MT2063_SoftwareShutdown()
1395 &state->reg[MT2063_REG_BYP_CTRL], MT2063_SoftwareShutdown()
1397 state->reg[MT2063_REG_BYP_CTRL] = MT2063_SoftwareShutdown()
1398 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F); MT2063_SoftwareShutdown()
1400 mt2063_write(state, MT2063_SoftwareShutdown()
1402 &state->reg[MT2063_REG_BYP_CTRL], MT2063_SoftwareShutdown()
1514 * @state: ptr to tuner data structure
1519 static u32 FindClearTuneFilter(struct mt2063_state *state, u32 f_in) FindClearTuneFilter() argument
1529 if (state->CTFiltMax[idx] >= f_in) { FindClearTuneFilter()
1540 static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in) MT2063_Tune() argument
1562 if ((state->AS_Data.f_out < MT2063_MIN_FOUT_FREQ) MT2063_Tune()
1563 || (state->AS_Data.f_out > MT2063_MAX_FOUT_FREQ)) MT2063_Tune()
1569 ofLO1 = state->AS_Data.f_LO1; MT2063_Tune()
1570 ofLO2 = state->AS_Data.f_LO2; MT2063_Tune()
1575 if (state->ctfilt_sw == 1) { MT2063_Tune()
1576 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08); MT2063_Tune()
1577 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) { MT2063_Tune()
1579 mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val); MT2063_Tune()
1581 val = state->reg[MT2063_REG_CTUNE_OV]; MT2063_Tune()
1582 RFBand = FindClearTuneFilter(state, f_in); MT2063_Tune()
1583 state->reg[MT2063_REG_CTUNE_OV] = MT2063_Tune()
1584 (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F) MT2063_Tune()
1586 if (state->reg[MT2063_REG_CTUNE_OV] != val) { MT2063_Tune()
1588 mt2063_setreg(state, MT2063_REG_CTUNE_OV, val); MT2063_Tune()
1597 mt2063_read(state, MT2063_Tune()
1599 &state->reg[MT2063_REG_FIFFC], 1); MT2063_Tune()
1600 fiffc = state->reg[MT2063_REG_FIFFC]; MT2063_Tune()
1605 state->AS_Data.f_in = f_in; MT2063_Tune()
1607 state->AS_Data.f_if1_Request = MT2063_Tune()
1608 MT2063_Round_fLO(state->AS_Data.f_if1_Request + f_in, MT2063_Tune()
1609 state->AS_Data.f_LO1_Step, MT2063_Tune()
1610 state->AS_Data.f_ref) - f_in; MT2063_Tune()
1616 MT2063_ResetExclZones(&state->AS_Data); MT2063_Tune()
1618 f_IF1 = MT2063_ChooseFirstIF(&state->AS_Data); MT2063_Tune()
1620 state->AS_Data.f_LO1 = MT2063_Tune()
1621 MT2063_Round_fLO(f_IF1 + f_in, state->AS_Data.f_LO1_Step, MT2063_Tune()
1622 state->AS_Data.f_ref); MT2063_Tune()
1624 state->AS_Data.f_LO2 = MT2063_Tune()
1625 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in, MT2063_Tune()
1626 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref); MT2063_Tune()
1632 status |= MT2063_AvoidSpurs(&state->AS_Data); MT2063_Tune()
1638 state->AS_Data.f_LO1 = MT2063_Tune()
1639 MT2063_CalcLO1Mult(&LO1, &Num1, state->AS_Data.f_LO1, MT2063_Tune()
1640 state->AS_Data.f_LO1_Step, state->AS_Data.f_ref); MT2063_Tune()
1641 state->AS_Data.f_LO2 = MT2063_Tune()
1642 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in, MT2063_Tune()
1643 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref); MT2063_Tune()
1644 state->AS_Data.f_LO2 = MT2063_Tune()
1645 MT2063_CalcLO2Mult(&LO2, &Num2, state->AS_Data.f_LO2, MT2063_Tune()
1646 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref); MT2063_Tune()
1651 if ((state->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ) MT2063_Tune()
1652 || (state->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ)) MT2063_Tune()
1654 if ((state->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ) MT2063_Tune()
1655 || (state->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ)) MT2063_Tune()
1658 if (state->tuner_id == MT2063_B0) MT2063_Tune()
1665 if ((ofLO1 != state->AS_Data.f_LO1) MT2063_Tune()
1666 || (ofLO2 != state->AS_Data.f_LO2) MT2063_Tune()
1667 || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) != MT2063_Tune()
1677 (state->AS_Data.f_LO1 - MT2063_Tune()
1678 f_in) / (state->AS_Data.f_ref / 64) - 8 * (u32) fiffc - MT2063_Tune()
1688 state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */ MT2063_Tune()
1689 state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */ MT2063_Tune()
1690 state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */ MT2063_Tune()
1692 state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */ MT2063_Tune()
1693 state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */ MT2063_Tune()
1700 status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */ MT2063_Tune()
1701 if (state->tuner_id == MT2063_B0) { MT2063_Tune()
1703 status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */ MT2063_Tune()
1706 if (state->reg[MT2063_REG_FIFF_OFFSET] != MT2063_Tune()
1708 state->reg[MT2063_REG_FIFF_OFFSET] = MT2063_Tune()
1711 mt2063_write(state, MT2063_Tune()
1713 &state-> MT2063_Tune()
1726 status = mt2063_lockStatus(state); MT2063_Tune()
1735 state->f_IF1_actual = state->AS_Data.f_LO1 - f_in; MT2063_Tune()
1807 struct mt2063_state *state = fe->tuner_priv; mt2063_init() local
1818 state->rcvr_mode = MT2063_CABLE_QAM; mt2063_init()
1821 status = mt2063_read(state, MT2063_REG_PART_REV, mt2063_init()
1822 &state->reg[MT2063_REG_PART_REV], 1); mt2063_init()
1829 switch (state->reg[MT2063_REG_PART_REV]) { mt2063_init()
1844 state->reg[MT2063_REG_PART_REV]); mt2063_init()
1849 status = mt2063_read(state, MT2063_REG_RSVD_3B, mt2063_init()
1850 &state->reg[MT2063_REG_RSVD_3B], 1); mt2063_init()
1853 if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) { mt2063_init()
1855 state->reg[MT2063_REG_PART_REV], mt2063_init()
1856 state->reg[MT2063_REG_RSVD_3B]); mt2063_init()
1863 status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1); mt2063_init()
1868 /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */ mt2063_init()
1869 switch (state->reg[MT2063_REG_PART_REV]) { mt2063_init()
1890 status = mt2063_write(state, reg, &val, 1); mt2063_init()
1900 status = mt2063_read(state, mt2063_init()
1902 &state-> mt2063_init()
1904 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6; mt2063_init()
1910 status = mt2063_read(state, mt2063_init()
1912 &state->reg[MT2063_REG_FIFFC], 1); mt2063_init()
1917 status = mt2063_read(state, mt2063_init()
1919 state->reg, MT2063_REG_END_REGS); mt2063_init()
1923 /* Initialize the tuner state. */ mt2063_init()
1924 state->tuner_id = state->reg[MT2063_REG_PART_REV]; mt2063_init()
1925 state->AS_Data.f_ref = MT2063_REF_FREQ; mt2063_init()
1926 state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) * mt2063_init()
1927 ((u32) state->reg[MT2063_REG_FIFFC] + 640); mt2063_init()
1928 state->AS_Data.f_if1_bw = MT2063_IF1_BW; mt2063_init()
1929 state->AS_Data.f_out = 43750000UL; mt2063_init()
1930 state->AS_Data.f_out_bw = 6750000UL; mt2063_init()
1931 state->AS_Data.f_zif_bw = MT2063_ZIF_BW; mt2063_init()
1932 state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64; mt2063_init()
1933 state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE; mt2063_init()
1934 state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1; mt2063_init()
1935 state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2; mt2063_init()
1936 state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP; mt2063_init()
1937 state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center; mt2063_init()
1938 state->AS_Data.f_LO1 = 2181000000UL; mt2063_init()
1939 state->AS_Data.f_LO2 = 1486249786UL; mt2063_init()
1940 state->f_IF1_actual = state->AS_Data.f_if1_Center; mt2063_init()
1941 state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual; mt2063_init()
1942 state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID; mt2063_init()
1943 state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID; mt2063_init()
1944 state->num_regs = MT2063_REG_END_REGS; mt2063_init()
1945 state->AS_Data.avoidDECT = MT2063_AVOID_BOTH; mt2063_init()
1946 state->ctfilt_sw = 0; mt2063_init()
1948 state->CTFiltMax[0] = 69230000; mt2063_init()
1949 state->CTFiltMax[1] = 105770000; mt2063_init()
1950 state->CTFiltMax[2] = 140350000; mt2063_init()
1951 state->CTFiltMax[3] = 177110000; mt2063_init()
1952 state->CTFiltMax[4] = 212860000; mt2063_init()
1953 state->CTFiltMax[5] = 241130000; mt2063_init()
1954 state->CTFiltMax[6] = 274370000; mt2063_init()
1955 state->CTFiltMax[7] = 309820000; mt2063_init()
1956 state->CTFiltMax[8] = 342450000; mt2063_init()
1957 state->CTFiltMax[9] = 378870000; mt2063_init()
1958 state->CTFiltMax[10] = 416210000; mt2063_init()
1959 state->CTFiltMax[11] = 456500000; mt2063_init()
1960 state->CTFiltMax[12] = 495790000; mt2063_init()
1961 state->CTFiltMax[13] = 534530000; mt2063_init()
1962 state->CTFiltMax[14] = 572610000; mt2063_init()
1963 state->CTFiltMax[15] = 598970000; mt2063_init()
1964 state->CTFiltMax[16] = 635910000; mt2063_init()
1965 state->CTFiltMax[17] = 672130000; mt2063_init()
1966 state->CTFiltMax[18] = 714840000; mt2063_init()
1967 state->CTFiltMax[19] = 739660000; mt2063_init()
1968 state->CTFiltMax[20] = 770410000; mt2063_init()
1969 state->CTFiltMax[21] = 814660000; mt2063_init()
1970 state->CTFiltMax[22] = 846950000; mt2063_init()
1971 state->CTFiltMax[23] = 867820000; mt2063_init()
1972 state->CTFiltMax[24] = 915980000; mt2063_init()
1973 state->CTFiltMax[25] = 947450000; mt2063_init()
1974 state->CTFiltMax[26] = 983110000; mt2063_init()
1975 state->CTFiltMax[27] = 1021630000; mt2063_init()
1976 state->CTFiltMax[28] = 1061870000; mt2063_init()
1977 state->CTFiltMax[29] = 1098330000; mt2063_init()
1978 state->CTFiltMax[30] = 1138990000; mt2063_init()
1985 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; mt2063_init()
1986 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL, mt2063_init()
1987 &state->reg[MT2063_REG_CTUNE_CTRL], 1); mt2063_init()
1992 status = mt2063_read(state, MT2063_REG_FIFFC, mt2063_init()
1993 &state->reg[MT2063_REG_FIFFC], 1); mt2063_init()
1997 fcu_osc = state->reg[MT2063_REG_FIFFC]; mt2063_init()
1999 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00; mt2063_init()
2000 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL, mt2063_init()
2001 &state->reg[MT2063_REG_CTUNE_CTRL], 1); mt2063_init()
2007 state->CTFiltMax[i] = (state->CTFiltMax[i] / 768) * (fcu_osc + 640); mt2063_init()
2009 status = MT2063_SoftwareShutdown(state, 1); mt2063_init()
2012 status = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD); mt2063_init()
2016 state->init = true; mt2063_init()
2023 struct mt2063_state *state = fe->tuner_priv; mt2063_get_status() local
2028 if (!state->init) mt2063_get_status()
2032 status = mt2063_lockStatus(state); mt2063_get_status()
2045 struct mt2063_state *state = fe->tuner_priv; mt2063_release() local
2050 kfree(state); mt2063_release()
2058 struct mt2063_state *state = fe->tuner_priv; mt2063_set_analog_params() local
2068 if (!state->init) { mt2063_set_analog_params()
2102 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */ mt2063_set_analog_params()
2103 state->AS_Data.f_out = if_mid; mt2063_set_analog_params()
2104 state->AS_Data.f_out_bw = ch_bw + 750000; mt2063_set_analog_params()
2105 status = MT2063_SetReceiverMode(state, rcvr_mode); mt2063_set_analog_params()
2112 status = MT2063_Tune(state, (params->frequency + (pict2chanb_vsb + (ch_bw / 2)))); mt2063_set_analog_params()
2116 state->frequency = params->frequency; mt2063_set_analog_params()
2132 struct mt2063_state *state = fe->tuner_priv; mt2063_set_params() local
2140 if (!state->init) { mt2063_set_params()
2174 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */ mt2063_set_params()
2175 state->AS_Data.f_out = if_mid; mt2063_set_params()
2176 state->AS_Data.f_out_bw = ch_bw + 750000; mt2063_set_params()
2177 status = MT2063_SetReceiverMode(state, rcvr_mode); mt2063_set_params()
2184 status = MT2063_Tune(state, (c->frequency + (pict2chanb_vsb + (ch_bw / 2)))); mt2063_set_params()
2189 state->frequency = c->frequency; mt2063_set_params()
2195 struct mt2063_state *state = fe->tuner_priv; mt2063_get_if_frequency() local
2199 if (!state->init) mt2063_get_if_frequency()
2202 *freq = state->AS_Data.f_out; mt2063_get_if_frequency()
2211 struct mt2063_state *state = fe->tuner_priv; mt2063_get_bandwidth() local
2215 if (!state->init) mt2063_get_bandwidth()
2218 *bw = state->AS_Data.f_out_bw - 750000; mt2063_get_bandwidth()
2247 struct mt2063_state *state = NULL; mt2063_attach() local
2251 state = kzalloc(sizeof(struct mt2063_state), GFP_KERNEL); mt2063_attach()
2252 if (!state) mt2063_attach()
2255 state->config = config; mt2063_attach()
2256 state->i2c = i2c; mt2063_attach()
2257 state->frontend = fe; mt2063_attach()
2258 state->reference = config->refclock / 1000; /* kHz */ mt2063_attach()
2259 fe->tuner_priv = state; mt2063_attach()
2274 struct mt2063_state *state = fe->tuner_priv;
2279 err = MT2063_SoftwareShutdown(state, 1);
2288 struct mt2063_state *state = fe->tuner_priv;
2293 err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
H A Dmxl5007t.c216 static void mxl5007t_set_mode_bits(struct mxl5007t_state *state, mxl5007t_set_mode_bits() argument
222 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12); mxl5007t_set_mode_bits()
225 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11); mxl5007t_set_mode_bits()
228 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10); mxl5007t_set_mode_bits()
231 set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1); mxl5007t_set_mode_bits()
232 set_reg_bits(state->tab_init_cable, 0x0a, 0xff, mxl5007t_set_mode_bits()
234 set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17); mxl5007t_set_mode_bits()
242 static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state, mxl5007t_set_if_freq_bits() argument
286 set_reg_bits(state->tab_init, 0x02, 0x0f, val); mxl5007t_set_if_freq_bits()
289 set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00); mxl5007t_set_if_freq_bits()
291 state->if_freq = if_freq; mxl5007t_set_if_freq_bits()
296 static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state, mxl5007t_set_xtal_freq_bits() argument
302 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00); mxl5007t_set_xtal_freq_bits()
303 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00); mxl5007t_set_xtal_freq_bits()
306 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10); mxl5007t_set_xtal_freq_bits()
307 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01); mxl5007t_set_xtal_freq_bits()
310 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20); mxl5007t_set_xtal_freq_bits()
311 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02); mxl5007t_set_xtal_freq_bits()
314 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30); mxl5007t_set_xtal_freq_bits()
315 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03); mxl5007t_set_xtal_freq_bits()
318 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40); mxl5007t_set_xtal_freq_bits()
319 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04); mxl5007t_set_xtal_freq_bits()
322 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50); mxl5007t_set_xtal_freq_bits()
323 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05); mxl5007t_set_xtal_freq_bits()
326 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60); mxl5007t_set_xtal_freq_bits()
327 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06); mxl5007t_set_xtal_freq_bits()
330 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70); mxl5007t_set_xtal_freq_bits()
331 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07); mxl5007t_set_xtal_freq_bits()
334 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80); mxl5007t_set_xtal_freq_bits()
335 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08); mxl5007t_set_xtal_freq_bits()
338 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90); mxl5007t_set_xtal_freq_bits()
339 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09); mxl5007t_set_xtal_freq_bits()
342 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0); mxl5007t_set_xtal_freq_bits()
343 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a); mxl5007t_set_xtal_freq_bits()
346 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0); mxl5007t_set_xtal_freq_bits()
347 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b); mxl5007t_set_xtal_freq_bits()
350 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0); mxl5007t_set_xtal_freq_bits()
351 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c); mxl5007t_set_xtal_freq_bits()
354 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0); mxl5007t_set_xtal_freq_bits()
355 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d); mxl5007t_set_xtal_freq_bits()
365 static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state, mxl5007t_calc_init_regs() argument
368 struct mxl5007t_config *cfg = state->config; mxl5007t_calc_init_regs()
370 memcpy(&state->tab_init, &init_tab, sizeof(init_tab)); mxl5007t_calc_init_regs()
371 memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable)); mxl5007t_calc_init_regs()
373 mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level); mxl5007t_calc_init_regs()
374 mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); mxl5007t_calc_init_regs()
375 mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); mxl5007t_calc_init_regs()
377 set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3); mxl5007t_calc_init_regs()
378 set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp); mxl5007t_calc_init_regs()
381 copy_reg_bits(state->tab_init, state->tab_init_cable); mxl5007t_calc_init_regs()
382 return state->tab_init_cable; mxl5007t_calc_init_regs()
384 return state->tab_init; mxl5007t_calc_init_regs()
395 static void mxl5007t_set_bw_bits(struct mxl5007t_state *state, mxl5007t_set_bw_bits() argument
415 set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val); mxl5007t_set_bw_bits()
421 reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state, mxl5007t_calc_rf_tune_regs() argument
429 memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune)); mxl5007t_calc_rf_tune_regs()
431 mxl5007t_set_bw_bits(state, bw); mxl5007t_calc_rf_tune_regs()
452 set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq); mxl5007t_calc_rf_tune_regs()
453 set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8)); mxl5007t_calc_rf_tune_regs()
456 set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40); mxl5007t_calc_rf_tune_regs()
458 return state->tab_rftune; mxl5007t_calc_rf_tune_regs()
463 static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val) mxl5007t_write_reg() argument
466 struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0, mxl5007t_write_reg()
470 ret = i2c_transfer(state->i2c_props.adap, &msg, 1); mxl5007t_write_reg()
478 static int mxl5007t_write_regs(struct mxl5007t_state *state, mxl5007t_write_regs() argument
485 ret = mxl5007t_write_reg(state, mxl5007t_write_regs()
492 static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val) mxl5007t_read_reg() argument
496 { .addr = state->i2c_props.addr, .flags = 0, mxl5007t_read_reg()
498 { .addr = state->i2c_props.addr, .flags = I2C_M_RD, mxl5007t_read_reg()
503 ret = i2c_transfer(state->i2c_props.adap, msg, 2); mxl5007t_read_reg()
511 static int mxl5007t_soft_reset(struct mxl5007t_state *state) mxl5007t_soft_reset() argument
515 .addr = state->i2c_props.addr, .flags = 0, mxl5007t_soft_reset()
518 int ret = i2c_transfer(state->i2c_props.adap, &msg, 1); mxl5007t_soft_reset()
527 static int mxl5007t_tuner_init(struct mxl5007t_state *state, mxl5007t_tuner_init() argument
534 init_regs = mxl5007t_calc_init_regs(state, mode); mxl5007t_tuner_init()
536 ret = mxl5007t_write_regs(state, init_regs); mxl5007t_tuner_init()
544 static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz, mxl5007t_tuner_rf_tune() argument
551 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw); mxl5007t_tuner_rf_tune()
553 ret = mxl5007t_write_regs(state, rf_tune_regs); mxl5007t_tuner_rf_tune()
563 static int mxl5007t_synth_lock_status(struct mxl5007t_state *state, mxl5007t_synth_lock_status() argument
572 ret = mxl5007t_read_reg(state, 0xd8, &d); mxl5007t_synth_lock_status()
589 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_get_status() local
597 ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked); mxl5007t_get_status()
618 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_set_params() local
658 mutex_lock(&state->lock); mxl5007t_set_params()
660 ret = mxl5007t_tuner_init(state, mode); mxl5007t_set_params()
664 ret = mxl5007t_tuner_rf_tune(state, freq, bw); mxl5007t_set_params()
668 state->frequency = freq; mxl5007t_set_params()
669 state->bandwidth = c->bandwidth_hz; mxl5007t_set_params()
671 mutex_unlock(&state->lock); mxl5007t_set_params()
683 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_init() local
690 ret = mxl5007t_write_reg(state, 0x01, 0x01); mxl5007t_init()
701 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_sleep() local
708 ret = mxl5007t_write_reg(state, 0x01, 0x00); mxl5007t_sleep()
710 ret = mxl5007t_write_reg(state, 0x0f, 0x00); mxl5007t_sleep()
723 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_get_frequency() local
724 *frequency = state->frequency; mxl5007t_get_frequency()
730 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_get_bandwidth() local
731 *bandwidth = state->bandwidth; mxl5007t_get_bandwidth()
737 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_get_if_frequency() local
741 switch (state->if_freq) { mxl5007t_get_if_frequency()
781 struct mxl5007t_state *state = fe->tuner_priv; mxl5007t_release() local
785 if (state) mxl5007t_release()
786 hybrid_tuner_release_state(state); mxl5007t_release()
811 static int mxl5007t_get_chip_id(struct mxl5007t_state *state) mxl5007t_get_chip_id() argument
817 ret = mxl5007t_read_reg(state, 0xd9, &id); mxl5007t_get_chip_id()
848 state->chip_id = id; mxl5007t_get_chip_id()
850 i2c_adapter_id(state->i2c_props.adap), mxl5007t_get_chip_id()
851 state->i2c_props.addr); mxl5007t_get_chip_id()
855 i2c_adapter_id(state->i2c_props.adap), mxl5007t_get_chip_id()
856 state->i2c_props.addr); mxl5007t_get_chip_id()
858 state->chip_id = MxL_UNKNOWN_ID; mxl5007t_get_chip_id()
866 struct mxl5007t_state *state = NULL; mxl5007t_attach() local
870 instance = hybrid_tuner_request_state(struct mxl5007t_state, state, mxl5007t_attach()
878 state->config = cfg; mxl5007t_attach()
880 mutex_init(&state->lock); mxl5007t_attach()
885 ret = mxl5007t_get_chip_id(state); mxl5007t_attach()
902 ret = mxl5007t_soft_reset(state); mxl5007t_attach()
913 ret = mxl5007t_write_reg(state, 0x04, mxl5007t_attach()
914 state->config->loop_thru_enable); mxl5007t_attach()
922 fe->tuner_priv = state; mxl5007t_attach()
H A Dtuner-i2c.h74 * state structure must contain the following:
79 * hybrid_tuner_instance_list (both within state structure and globally)
81 * and hybrid_tuner_release_state to manage state sharing between
129 #define hybrid_tuner_request_state(type, state, list, i2cadap, i2caddr, devname)\
132 list_for_each_entry(state, &list, hybrid_tuner_instance_list) { \
133 if (((i2cadap) && (state->i2c_props.adap)) && \
134 ((i2c_adapter_id(state->i2c_props.adap) == \
136 (i2caddr == state->i2c_props.addr))) { \
137 __tuner_info(state->i2c_props, \
139 state->i2c_props.count++; \
140 __ret = state->i2c_props.count; \
145 state = kzalloc(sizeof(type), GFP_KERNEL); \
146 if (NULL == state) \
148 state->i2c_props.addr = i2caddr; \
149 state->i2c_props.adap = i2cadap; \
150 state->i2c_props.name = devname; \
151 __tuner_info(state->i2c_props, \
153 list_add_tail(&state->hybrid_tuner_instance_list, &list);\
154 state->i2c_props.count++; \
155 __ret = state->i2c_props.count; \
161 #define hybrid_tuner_release_state(state) \
164 state->i2c_props.count--; \
165 __ret = state->i2c_props.count; \
166 if (!state->i2c_props.count) { \
167 __tuner_info(state->i2c_props, "destroying instance\n");\
168 list_del(&state->hybrid_tuner_instance_list); \
169 kfree(state); \
174 #define hybrid_tuner_report_instance_count(state) \
177 if (state) \
178 __ret = state->i2c_props.count; \
H A Dmxl301rf.c44 static int raw_write(struct mxl301rf_state *state, const u8 *buf, int len) raw_write() argument
48 ret = i2c_master_send(state->i2c, buf, len); raw_write()
54 static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val) reg_write() argument
58 return raw_write(state, buf, 2); reg_write()
61 static int reg_read(struct mxl301rf_state *state, u8 reg, u8 *val) reg_read() argument
66 ret = raw_write(state, wbuf, sizeof(wbuf)); reg_read()
68 ret = i2c_master_recv(state->i2c, val, 1); reg_read()
79 struct mxl301rf_state *state; mxl301rf_get_rf_strength() local
91 state = fe->tuner_priv; mxl301rf_get_rf_strength()
92 ret = reg_write(state, 0x14, 0x01); mxl301rf_get_rf_strength()
97 ret = reg_read(state, 0x18, &rf_in1); mxl301rf_get_rf_strength()
99 ret = reg_read(state, 0x19, &rf_in2); mxl301rf_get_rf_strength()
101 ret = reg_read(state, 0xd6, &rf_off1); mxl301rf_get_rf_strength()
103 ret = reg_read(state, 0xd7, &rf_off2); mxl301rf_get_rf_strength()
180 struct mxl301rf_state *state; mxl301rf_set_params() local
186 state = fe->tuner_priv; mxl301rf_set_params()
198 ret = raw_write(state, (u8 *) tune0, sizeof(tune0)); mxl301rf_set_params()
219 ret = raw_write(state, (u8 *) tune1, sizeof(tune1)); mxl301rf_set_params()
224 ret = reg_write(state, 0x1a, 0x0d); mxl301rf_set_params()
227 ret = raw_write(state, (u8 *) set_idac, sizeof(set_idac)); mxl301rf_set_params()
233 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", mxl301rf_set_params()
245 struct mxl301rf_state *state; mxl301rf_sleep() local
248 state = fe->tuner_priv; mxl301rf_sleep()
249 ret = raw_write(state, (u8 *)standby_data, sizeof(standby_data)); mxl301rf_sleep()
251 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", mxl301rf_sleep()
263 struct mxl301rf_state *state; mxl301rf_init() local
266 state = fe->tuner_priv; mxl301rf_init()
268 ret = reg_write(state, 0x01, 0x01); mxl301rf_init()
270 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", mxl301rf_init()
298 struct mxl301rf_state *state; mxl301rf_probe() local
302 state = kzalloc(sizeof(*state), GFP_KERNEL); mxl301rf_probe()
303 if (!state) mxl301rf_probe()
306 state->i2c = client; mxl301rf_probe()
309 memcpy(&state->cfg, cfg, sizeof(state->cfg)); mxl301rf_probe()
311 fe->tuner_priv = state; mxl301rf_probe()
314 i2c_set_clientdata(client, &state->cfg); mxl301rf_probe()
321 struct mxl301rf_state *state; mxl301rf_remove() local
323 state = cfg_to_state(i2c_get_clientdata(client)); mxl301rf_remove()
324 state->cfg.fe->tuner_priv = NULL; mxl301rf_remove()
325 kfree(state); mxl301rf_remove()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dcx24113.c104 static int cx24113_writereg(struct cx24113_state *state, int reg, int data) cx24113_writereg() argument
107 struct i2c_msg msg = { .addr = state->config->i2c_addr, cx24113_writereg()
109 int err = i2c_transfer(state->i2c, &msg, 1); cx24113_writereg()
119 static int cx24113_readreg(struct cx24113_state *state, u8 reg) cx24113_readreg() argument
124 { .addr = state->config->i2c_addr, cx24113_readreg()
126 { .addr = state->config->i2c_addr, cx24113_readreg()
130 ret = i2c_transfer(state->i2c, msg, 2); cx24113_readreg()
141 static void cx24113_set_parameters(struct cx24113_state *state) cx24113_set_parameters() argument
145 r = cx24113_readreg(state, 0x10) & 0x82; cx24113_set_parameters()
146 r |= state->icp_mode; cx24113_set_parameters()
147 r |= state->icp_man << 4; cx24113_set_parameters()
148 r |= state->icp_dig << 2; cx24113_set_parameters()
149 r |= state->prescaler_mode << 5; cx24113_set_parameters()
150 cx24113_writereg(state, 0x10, r); cx24113_set_parameters()
152 r = (state->icp_auto_low << 0) | (state->icp_auto_mlow << 2) cx24113_set_parameters()
153 | (state->icp_auto_mhi << 4) | (state->icp_auto_hi << 6); cx24113_set_parameters()
154 cx24113_writereg(state, 0x11, r); cx24113_set_parameters()
156 if (state->rev == REV_CX24113) { cx24113_set_parameters()
157 r = cx24113_readreg(state, 0x20) & 0xec; cx24113_set_parameters()
158 r |= state->lna_gain; cx24113_set_parameters()
159 r |= state->rfvga_bias_ctrl << 4; cx24113_set_parameters()
160 cx24113_writereg(state, 0x20, r); cx24113_set_parameters()
163 r = cx24113_readreg(state, 0x12) & 0x03; cx24113_set_parameters()
164 r |= state->acp_on << 2; cx24113_set_parameters()
165 r |= state->bs_delay << 4; cx24113_set_parameters()
166 cx24113_writereg(state, 0x12, r); cx24113_set_parameters()
168 r = cx24113_readreg(state, 0x18) & 0x40; cx24113_set_parameters()
169 r |= state->vco_shift; cx24113_set_parameters()
170 if (state->vco_band == VCOBANDSEL_6) cx24113_set_parameters()
173 r |= (state->vco_band << 1); cx24113_set_parameters()
174 cx24113_writereg(state, 0x18, r); cx24113_set_parameters()
176 r = cx24113_readreg(state, 0x14) & 0x20; cx24113_set_parameters()
177 r |= (state->vco_mode << 6) | ((state->bs_freqcnt >> 8) & 0x1f); cx24113_set_parameters()
178 cx24113_writereg(state, 0x14, r); cx24113_set_parameters()
179 cx24113_writereg(state, 0x15, (state->bs_freqcnt & 0xff)); cx24113_set_parameters()
181 cx24113_writereg(state, 0x16, (state->bs_rdiv >> 4) & 0xff); cx24113_set_parameters()
182 r = (cx24113_readreg(state, 0x17) & 0x0f) | cx24113_set_parameters()
183 ((state->bs_rdiv & 0x0f) << 4); cx24113_set_parameters()
184 cx24113_writereg(state, 0x17, r); cx24113_set_parameters()
201 static int cx24113_set_gain_settings(struct cx24113_state *state, cx24113_set_gain_settings() argument
204 u8 ampout = cx24113_readreg(state, 0x1d) & 0xf0, cx24113_set_gain_settings()
205 vga = cx24113_readreg(state, 0x1f) & 0x3f, cx24113_set_gain_settings()
206 rfvga = cx24113_readreg(state, 0x20) & 0xf3; cx24113_set_gain_settings()
207 u8 gain_level = power_estimation >= state->tuner_gain_thres; cx24113_set_gain_settings()
210 power_estimation, state->tuner_gain_thres, cx24113_set_gain_settings()
211 state->gain_level, gain_level); cx24113_set_gain_settings()
213 if (gain_level == state->gain_level) cx24113_set_gain_settings()
225 state->gain_level = gain_level; cx24113_set_gain_settings()
227 cx24113_writereg(state, 0x1d, ampout); cx24113_set_gain_settings()
228 cx24113_writereg(state, 0x1f, vga); cx24113_set_gain_settings()
229 cx24113_writereg(state, 0x20, rfvga); cx24113_set_gain_settings()
234 static int cx24113_set_Fref(struct cx24113_state *state, u8 high) cx24113_set_Fref() argument
236 u8 xtal = cx24113_readreg(state, 0x02); cx24113_set_Fref()
237 if (state->rev == 0x43 && state->vcodiv == VCODIV4) cx24113_set_Fref()
243 return cx24113_writereg(state, 0x02, xtal); cx24113_set_Fref()
246 static int cx24113_enable(struct cx24113_state *state, u8 enable) cx24113_enable() argument
248 u8 r21 = (cx24113_readreg(state, 0x21) & 0xc0) | enable; cx24113_enable()
249 if (state->rev == REV_CX24113) cx24113_enable()
251 return cx24113_writereg(state, 0x21, r21); cx24113_enable()
254 static int cx24113_set_bandwidth(struct cx24113_state *state, u32 bandwidth_khz) cx24113_set_bandwidth() argument
276 return cx24113_writereg(state, 0x1e, r); cx24113_set_bandwidth()
279 static int cx24113_set_clk_inversion(struct cx24113_state *state, u8 on) cx24113_set_clk_inversion() argument
281 u8 r = (cx24113_readreg(state, 0x10) & 0x7f) | ((on & 0x1) << 7); cx24113_set_clk_inversion()
282 return cx24113_writereg(state, 0x10, r); cx24113_set_clk_inversion()
287 struct cx24113_state *state = fe->tuner_priv; cx24113_get_status() local
288 u8 r = (cx24113_readreg(state, 0x10) & 0x02) >> 1; cx24113_get_status()
295 static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv) cx24113_set_ref_div() argument
297 if (state->rev == 0x43 && state->vcodiv == VCODIV4) cx24113_set_ref_div()
299 return state->refdiv = refdiv; cx24113_set_ref_div()
302 static void cx24113_calc_pll_nf(struct cx24113_state *state, u16 *n, s32 *f) cx24113_calc_pll_nf() argument
310 s32 freq_hz = state->frequency * 1000; cx24113_calc_pll_nf()
312 if (state->config->xtal_khz < 20000) cx24113_calc_pll_nf()
317 if (state->rev == REV_CX24113) { cx24113_calc_pll_nf()
318 if (state->frequency >= 1100000) cx24113_calc_pll_nf()
323 if (state->frequency >= 1165000) cx24113_calc_pll_nf()
328 state->vcodiv = vcodiv; cx24113_calc_pll_nf()
333 R = cx24113_set_ref_div(state, R + 1); cx24113_calc_pll_nf()
337 N /= (state->config->xtal_khz) * factor * 2; cx24113_calc_pll_nf()
352 do_div(dividend, state->config->xtal_khz * 1000 * factor * 2); cx24113_calc_pll_nf()
359 if (state->Fwindow_enabled) { cx24113_calc_pll_nf()
366 r = cx24113_readreg(state, 0x10); cx24113_calc_pll_nf()
367 cx24113_writereg(state, 0x10, r | (1 << 6)); cx24113_calc_pll_nf()
377 static void cx24113_set_nfr(struct cx24113_state *state, u16 n, s32 f, u8 r) cx24113_set_nfr() argument
380 cx24113_writereg(state, 0x19, (n >> 1) & 0xff); cx24113_set_nfr()
383 cx24113_writereg(state, 0x1a, reg); cx24113_set_nfr()
385 cx24113_writereg(state, 0x1b, (f >> 3) & 0xff); cx24113_set_nfr()
387 reg = cx24113_readreg(state, 0x1c) & 0x1f; cx24113_set_nfr()
388 cx24113_writereg(state, 0x1c, reg | ((f & 0x7) << 5)); cx24113_set_nfr()
390 cx24113_set_Fref(state, r - 1); cx24113_set_nfr()
393 static int cx24113_set_frequency(struct cx24113_state *state, u32 frequency) cx24113_set_frequency() argument
399 r = cx24113_readreg(state, 0x14); cx24113_set_frequency()
400 cx24113_writereg(state, 0x14, r & 0x3f); cx24113_set_frequency()
402 r = cx24113_readreg(state, 0x10); cx24113_set_frequency()
403 cx24113_writereg(state, 0x10, r & 0xbf); cx24113_set_frequency()
405 state->frequency = frequency; cx24113_set_frequency()
409 cx24113_calc_pll_nf(state, &n, &f); cx24113_set_frequency()
410 cx24113_set_nfr(state, n, f, state->refdiv); cx24113_set_frequency()
412 r = cx24113_readreg(state, 0x18) & 0xbf; cx24113_set_frequency()
413 if (state->vcodiv != VCODIV2) cx24113_set_frequency()
415 cx24113_writereg(state, 0x18, r); cx24113_set_frequency()
420 r = cx24113_readreg(state, 0x1c) & 0xef; cx24113_set_frequency()
421 cx24113_writereg(state, 0x1c, r | (1 << 4)); cx24113_set_frequency()
427 struct cx24113_state *state = fe->tuner_priv; cx24113_init() local
430 state->tuner_gain_thres = -50; cx24113_init()
431 state->gain_level = 255; /* to force a gain-setting initialization */ cx24113_init()
432 state->icp_mode = 0; cx24113_init()
434 if (state->config->xtal_khz < 11000) { cx24113_init()
435 state->icp_auto_hi = ICP_LEVEL4; cx24113_init()
436 state->icp_auto_mhi = ICP_LEVEL4; cx24113_init()
437 state->icp_auto_mlow = ICP_LEVEL3; cx24113_init()
438 state->icp_auto_low = ICP_LEVEL3; cx24113_init()
440 state->icp_auto_hi = ICP_LEVEL4; cx24113_init()
441 state->icp_auto_mhi = ICP_LEVEL4; cx24113_init()
442 state->icp_auto_mlow = ICP_LEVEL3; cx24113_init()
443 state->icp_auto_low = ICP_LEVEL2; cx24113_init()
446 state->icp_dig = ICP_LEVEL3; cx24113_init()
447 state->icp_man = ICP_LEVEL1; cx24113_init()
448 state->acp_on = 1; cx24113_init()
449 state->vco_mode = 0; cx24113_init()
450 state->vco_shift = 0; cx24113_init()
451 state->vco_band = VCOBANDSEL_1; cx24113_init()
452 state->bs_delay = 8; cx24113_init()
453 state->bs_freqcnt = 0x0fff; cx24113_init()
454 state->bs_rdiv = 0x0fff; cx24113_init()
455 state->prescaler_mode = 0; cx24113_init()
456 state->lna_gain = LNA_MAX_GAIN; cx24113_init()
457 state->rfvga_bias_ctrl = 1; cx24113_init()
458 state->Fwindow_enabled = 1; cx24113_init()
460 cx24113_set_Fref(state, 0); cx24113_init()
461 cx24113_enable(state, 0x3d); cx24113_init()
462 cx24113_set_parameters(state); cx24113_init()
464 cx24113_set_gain_settings(state, -30); cx24113_init()
466 cx24113_set_bandwidth(state, 18025); cx24113_init()
467 cx24113_set_clk_inversion(state, 1); cx24113_init()
469 if (state->config->xtal_khz >= 40000) cx24113_init()
470 ret = cx24113_writereg(state, 0x02, cx24113_init()
471 (cx24113_readreg(state, 0x02) & 0xfb) | (1 << 2)); cx24113_init()
473 ret = cx24113_writereg(state, 0x02, cx24113_init()
474 (cx24113_readreg(state, 0x02) & 0xfb) | (0 << 2)); cx24113_init()
482 struct cx24113_state *state = fe->tuner_priv; cx24113_set_params() local
491 cx24113_set_bandwidth(state, bw); cx24113_set_params()
493 cx24113_set_frequency(state, c->frequency); cx24113_set_params()
505 struct cx24113_state *state = fe->tuner_priv; cx24113_agc_callback() local
516 if (cx24113_agc_table[state->gain_level][i] > s) cx24113_agc_callback()
519 } while (cx24113_set_gain_settings(state, s)); cx24113_agc_callback()
525 struct cx24113_state *state = fe->tuner_priv; cx24113_get_frequency() local
526 *frequency = state->frequency; cx24113_get_frequency()
532 struct cx24113_state *state = fe->tuner_priv; cx24113_release() local
535 kfree(state); cx24113_release()
559 /* allocate memory for the internal state */ cx24113_attach()
560 struct cx24113_state *state = cx24113_attach() local
563 if (state == NULL) { cx24113_attach()
568 /* setup the state */ cx24113_attach()
569 state->config = config; cx24113_attach()
570 state->i2c = i2c; cx24113_attach()
576 cx24113_readreg(state, 0x00); cx24113_attach()
578 rc = cx24113_readreg(state, 0x00); cx24113_attach()
583 state->rev = rc; cx24113_attach()
593 cx_err("unsupported device id: %x\n", state->rev); cx24113_attach()
596 state->ver = cx24113_readreg(state, 0x01); cx24113_attach()
597 cx_info("version: %x\n", state->ver); cx24113_attach()
602 fe->tuner_priv = state; cx24113_attach()
606 kfree(state); cx24113_attach()
H A Dstv0297.c51 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data) stv0297_writereg() argument
55 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 }; stv0297_writereg()
57 ret = i2c_transfer(state->i2c, &msg, 1); stv0297_writereg()
66 static int stv0297_readreg(struct stv0297_state *state, u8 reg) stv0297_readreg() argument
71 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1}, stv0297_readreg()
72 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1} stv0297_readreg()
76 if (state->config->stop_during_read) { stv0297_readreg()
77 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) { stv0297_readreg()
81 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) { stv0297_readreg()
86 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) { stv0297_readreg()
95 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data) stv0297_writereg_mask() argument
99 val = stv0297_readreg(state, reg); stv0297_writereg_mask()
102 stv0297_writereg(state, reg, val); stv0297_writereg_mask()
107 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len) stv0297_readregs() argument
110 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = stv0297_readregs()
112 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len} stv0297_readregs()
116 if (state->config->stop_during_read) { stv0297_readregs()
117 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) { stv0297_readregs()
121 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) { stv0297_readregs()
126 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) { stv0297_readregs()
135 static u32 stv0297_get_symbolrate(struct stv0297_state *state) stv0297_get_symbolrate() argument
139 tmp = stv0297_readreg(state, 0x55); stv0297_get_symbolrate()
140 tmp |= stv0297_readreg(state, 0x56) << 8; stv0297_get_symbolrate()
141 tmp |= stv0297_readreg(state, 0x57) << 16; stv0297_get_symbolrate()
142 tmp |= stv0297_readreg(state, 0x58) << 24; stv0297_get_symbolrate()
150 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate) stv0297_set_symbolrate() argument
158 stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF)); stv0297_set_symbolrate()
159 stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8)); stv0297_set_symbolrate()
160 stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16)); stv0297_set_symbolrate()
161 stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24)); stv0297_set_symbolrate()
164 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate) stv0297_set_sweeprate() argument
180 stv0297_writereg(state, 0x60, tmp & 0xFF); stv0297_set_sweeprate()
181 stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0); stv0297_set_sweeprate()
184 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset) stv0297_set_carrieroffset() argument
194 stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF)); stv0297_set_carrieroffset()
195 stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8)); stv0297_set_carrieroffset()
196 stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16)); stv0297_set_carrieroffset()
197 stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f); stv0297_set_carrieroffset()
201 static long stv0297_get_carrieroffset(struct stv0297_state *state)
205 stv0297_writereg(state, 0x6B, 0x00);
207 tmp = stv0297_readreg(state, 0x66);
208 tmp |= (stv0297_readreg(state, 0x67) << 8);
209 tmp |= (stv0297_readreg(state, 0x68) << 16);
210 tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
212 tmp *= stv0297_get_symbolrate(state);
219 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq) stv0297_set_initialdemodfreq() argument
231 stv0297_writereg_mask(state, 0x25, 0x80, 0x80); stv0297_set_initialdemodfreq()
232 stv0297_writereg(state, 0x21, tmp >> 8); stv0297_set_initialdemodfreq()
233 stv0297_writereg(state, 0x20, tmp); stv0297_set_initialdemodfreq()
236 static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation) stv0297_set_qam() argument
265 stv0297_writereg_mask(state, 0x00, 0x70, val << 4); stv0297_set_qam()
270 static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion) stv0297_set_inversion() argument
287 stv0297_writereg_mask(state, 0x83, 0x08, val << 3); stv0297_set_inversion()
294 struct stv0297_state *state = fe->demodulator_priv; stv0297_i2c_gate_ctrl() local
297 stv0297_writereg(state, 0x87, 0x78); stv0297_i2c_gate_ctrl()
298 stv0297_writereg(state, 0x86, 0xc8); stv0297_i2c_gate_ctrl()
306 struct stv0297_state *state = fe->demodulator_priv; stv0297_init() local
310 for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2) stv0297_init()
311 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]); stv0297_init()
314 state->last_ber = 0; stv0297_init()
321 struct stv0297_state *state = fe->demodulator_priv; stv0297_sleep() local
323 stv0297_writereg_mask(state, 0x80, 1, 1); stv0297_sleep()
330 struct stv0297_state *state = fe->demodulator_priv; stv0297_read_status() local
332 u8 sync = stv0297_readreg(state, 0xDF); stv0297_read_status()
343 struct stv0297_state *state = fe->demodulator_priv; stv0297_read_ber() local
346 stv0297_readregs(state, 0xA0, BER, 3); stv0297_read_ber()
348 state->last_ber = BER[2] << 8 | BER[1]; stv0297_read_ber()
349 stv0297_writereg_mask(state, 0xA0, 0x80, 0x80); stv0297_read_ber()
352 *ber = state->last_ber; stv0297_read_ber()
360 struct stv0297_state *state = fe->demodulator_priv; stv0297_read_signal_strength() local
364 stv0297_readregs(state, 0x41, STRENGTH, 3); stv0297_read_signal_strength()
383 struct stv0297_state *state = fe->demodulator_priv; stv0297_read_snr() local
386 stv0297_readregs(state, 0x07, SNR, 2); stv0297_read_snr()
394 struct stv0297_state *state = fe->demodulator_priv; stv0297_read_ucblocks() local
396 stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */ stv0297_read_ucblocks()
398 *ucblocks = (stv0297_readreg(state, 0xD5) << 8) stv0297_read_ucblocks()
399 | stv0297_readreg(state, 0xD4); stv0297_read_ucblocks()
401 stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */ stv0297_read_ucblocks()
402 stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */ stv0297_read_ucblocks()
410 struct stv0297_state *state = fe->demodulator_priv; stv0297_set_frontend() local
440 if (state->config->invert) stv0297_set_frontend()
463 stv0297_writereg(state, 0x82, 0x0); stv0297_set_frontend()
466 stv0297_set_initialdemodfreq(state, 7250); stv0297_set_frontend()
469 stv0297_writereg_mask(state, 0x43, 0x10, 0x00); stv0297_set_frontend()
470 stv0297_writereg(state, 0x41, 0x00); stv0297_set_frontend()
471 stv0297_writereg_mask(state, 0x42, 0x03, 0x01); stv0297_set_frontend()
472 stv0297_writereg_mask(state, 0x36, 0x60, 0x00); stv0297_set_frontend()
473 stv0297_writereg_mask(state, 0x36, 0x18, 0x00); stv0297_set_frontend()
474 stv0297_writereg_mask(state, 0x71, 0x80, 0x80); stv0297_set_frontend()
475 stv0297_writereg(state, 0x72, 0x00); stv0297_set_frontend()
476 stv0297_writereg(state, 0x73, 0x00); stv0297_set_frontend()
477 stv0297_writereg_mask(state, 0x74, 0x0F, 0x00); stv0297_set_frontend()
478 stv0297_writereg_mask(state, 0x43, 0x08, 0x00); stv0297_set_frontend()
479 stv0297_writereg_mask(state, 0x71, 0x80, 0x00); stv0297_set_frontend()
482 stv0297_writereg_mask(state, 0x5a, 0x20, 0x20); stv0297_set_frontend()
483 stv0297_writereg_mask(state, 0x5b, 0x02, 0x02); stv0297_set_frontend()
484 stv0297_writereg_mask(state, 0x5b, 0x02, 0x00); stv0297_set_frontend()
485 stv0297_writereg_mask(state, 0x5b, 0x01, 0x00); stv0297_set_frontend()
486 stv0297_writereg_mask(state, 0x5a, 0x40, 0x40); stv0297_set_frontend()
489 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00); stv0297_set_frontend()
492 stv0297_writereg_mask(state, 0x81, 0x01, 0x01); stv0297_set_frontend()
493 stv0297_writereg_mask(state, 0x81, 0x01, 0x00); stv0297_set_frontend()
496 stv0297_writereg_mask(state, 0x83, 0x20, 0x20); stv0297_set_frontend()
497 stv0297_writereg_mask(state, 0x83, 0x20, 0x00); stv0297_set_frontend()
500 u_threshold = stv0297_readreg(state, 0x00) & 0xf; stv0297_set_frontend()
501 initial_u = stv0297_readreg(state, 0x01) >> 4; stv0297_set_frontend()
502 blind_u = stv0297_readreg(state, 0x01) & 0xf; stv0297_set_frontend()
503 stv0297_writereg_mask(state, 0x84, 0x01, 0x01); stv0297_set_frontend()
504 stv0297_writereg_mask(state, 0x84, 0x01, 0x00); stv0297_set_frontend()
505 stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold); stv0297_set_frontend()
506 stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4); stv0297_set_frontend()
507 stv0297_writereg_mask(state, 0x01, 0x0f, blind_u); stv0297_set_frontend()
510 stv0297_writereg_mask(state, 0x87, 0x80, 0x00); stv0297_set_frontend()
513 stv0297_writereg(state, 0x63, 0x00); stv0297_set_frontend()
514 stv0297_writereg(state, 0x64, 0x00); stv0297_set_frontend()
515 stv0297_writereg(state, 0x65, 0x00); stv0297_set_frontend()
516 stv0297_writereg(state, 0x66, 0x00); stv0297_set_frontend()
517 stv0297_writereg(state, 0x67, 0x00); stv0297_set_frontend()
518 stv0297_writereg(state, 0x68, 0x00); stv0297_set_frontend()
519 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00); stv0297_set_frontend()
522 stv0297_set_qam(state, p->modulation); stv0297_set_frontend()
523 stv0297_set_symbolrate(state, p->symbol_rate / 1000); stv0297_set_frontend()
524 stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000); stv0297_set_frontend()
525 stv0297_set_carrieroffset(state, carrieroffset); stv0297_set_frontend()
526 stv0297_set_inversion(state, inversion); stv0297_set_frontend()
532 stv0297_writereg_mask(state, 0x88, 0x08, 0x00); stv0297_set_frontend()
534 stv0297_writereg_mask(state, 0x88, 0x08, 0x08); stv0297_set_frontend()
536 stv0297_writereg_mask(state, 0x5a, 0x20, 0x00); stv0297_set_frontend()
537 stv0297_writereg_mask(state, 0x6a, 0x01, 0x01); stv0297_set_frontend()
538 stv0297_writereg_mask(state, 0x43, 0x40, 0x40); stv0297_set_frontend()
539 stv0297_writereg_mask(state, 0x5b, 0x30, 0x00); stv0297_set_frontend()
540 stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c); stv0297_set_frontend()
541 stv0297_writereg_mask(state, 0x03, 0x03, 0x03); stv0297_set_frontend()
542 stv0297_writereg_mask(state, 0x43, 0x10, 0x10); stv0297_set_frontend()
548 if (stv0297_readreg(state, 0x43) & 0x08) stv0297_set_frontend()
561 if (stv0297_readreg(state, 0x82) & 0x04) { stv0297_set_frontend()
574 if (stv0297_readreg(state, 0x82) & 0x08) { stv0297_set_frontend()
583 stv0297_writereg_mask(state, 0x6a, 1, 0); stv0297_set_frontend()
584 stv0297_writereg_mask(state, 0x88, 8, 0); stv0297_set_frontend()
591 if (stv0297_readreg(state, 0xDF) & 0x80) { stv0297_set_frontend()
601 if (!(stv0297_readreg(state, 0xDF) & 0x80)) { stv0297_set_frontend()
606 stv0297_writereg_mask(state, 0x5a, 0x40, 0x00); stv0297_set_frontend()
607 state->base_freq = p->frequency; stv0297_set_frontend()
611 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00); stv0297_set_frontend()
618 struct stv0297_state *state = fe->demodulator_priv; stv0297_get_frontend() local
621 reg_00 = stv0297_readreg(state, 0x00); stv0297_get_frontend()
622 reg_83 = stv0297_readreg(state, 0x83); stv0297_get_frontend()
624 p->frequency = state->base_freq; stv0297_get_frontend()
626 if (state->config->invert) stv0297_get_frontend()
628 p->symbol_rate = stv0297_get_symbolrate(state) * 1000; stv0297_get_frontend()
654 struct stv0297_state *state = fe->demodulator_priv; stv0297_release() local
655 kfree(state); stv0297_release()
663 struct stv0297_state *state = NULL; stv0297_attach() local
665 /* allocate memory for the internal state */ stv0297_attach()
666 state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL); stv0297_attach()
667 if (state == NULL) stv0297_attach()
670 /* setup the state */ stv0297_attach()
671 state->config = config; stv0297_attach()
672 state->i2c = i2c; stv0297_attach()
673 state->last_ber = 0; stv0297_attach()
674 state->base_freq = 0; stv0297_attach()
677 if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20) stv0297_attach()
681 memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops)); stv0297_attach()
682 state->frontend.demodulator_priv = state; stv0297_attach()
683 return &state->frontend; stv0297_attach()
686 kfree(state); stv0297_attach()
H A Ds5h1420.c65 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
79 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg) s5h1420_readreg() argument
84 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 }, s5h1420_readreg()
85 { .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 }, s5h1420_readreg()
86 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 }, s5h1420_readreg()
90 b[1] = state->shadow[(reg - 1) & 0xff]; s5h1420_readreg()
92 if (state->config->repeated_start_workaround) { s5h1420_readreg()
93 ret = i2c_transfer(state->i2c, msg, 3); s5h1420_readreg()
97 ret = i2c_transfer(state->i2c, &msg[1], 1); s5h1420_readreg()
100 ret = i2c_transfer(state->i2c, &msg[2], 1); s5h1420_readreg()
105 /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */ s5h1420_readreg()
110 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data) s5h1420_writereg() argument
113 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; s5h1420_writereg()
116 /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */ s5h1420_writereg()
117 err = i2c_transfer(state->i2c, &msg, 1); s5h1420_writereg()
122 state->shadow[reg] = data; s5h1420_writereg()
129 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_set_voltage() local
135 s5h1420_writereg(state, 0x3c, s5h1420_set_voltage()
136 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02); s5h1420_set_voltage()
140 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03); s5h1420_set_voltage()
144 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd); s5h1420_set_voltage()
154 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_set_tone() local
159 s5h1420_writereg(state, 0x3b, s5h1420_set_tone()
160 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08); s5h1420_set_tone()
164 s5h1420_writereg(state, 0x3b, s5h1420_set_tone()
165 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01); s5h1420_set_tone()
176 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_send_master_cmd() local
187 val = s5h1420_readreg(state, 0x3b); s5h1420_send_master_cmd()
188 s5h1420_writereg(state, 0x3b, 0x02); s5h1420_send_master_cmd()
193 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]); s5h1420_send_master_cmd()
197 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | s5h1420_send_master_cmd()
203 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) s5h1420_send_master_cmd()
212 s5h1420_writereg(state, 0x3b, val); s5h1420_send_master_cmd()
221 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_recv_slave_reply() local
229 val = s5h1420_readreg(state, 0x3b); s5h1420_recv_slave_reply()
230 s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */ s5h1420_recv_slave_reply()
236 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */ s5h1420_recv_slave_reply()
248 if (s5h1420_readreg(state, 0x49)) { s5h1420_recv_slave_reply()
254 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4; s5h1420_recv_slave_reply()
263 reply->msg[i] = s5h1420_readreg(state, 0x3d + i); s5h1420_recv_slave_reply()
268 s5h1420_writereg(state, 0x3b, val); s5h1420_recv_slave_reply()
275 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_send_burst() local
281 val = s5h1420_readreg(state, 0x3b); s5h1420_send_burst()
282 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01); s5h1420_send_burst()
286 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04); s5h1420_send_burst()
291 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08); s5h1420_send_burst()
296 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) s5h1420_send_burst()
305 s5h1420_writereg(state, 0x3b, val); s5h1420_send_burst()
310 static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state) s5h1420_get_status_bits() argument
315 val = s5h1420_readreg(state, 0x14); s5h1420_get_status_bits()
320 val = s5h1420_readreg(state, 0x36); s5h1420_get_status_bits()
333 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_read_status() local
341 /* determine lock state */ s5h1420_read_status()
342 *status = s5h1420_get_status_bits(state); s5h1420_read_status()
347 val = s5h1420_readreg(state, Vit10); s5h1420_read_status()
350 s5h1420_writereg(state, Vit09, 0x13); s5h1420_read_status()
352 s5h1420_writereg(state, Vit09, 0x1b); s5h1420_read_status()
356 *status = s5h1420_get_status_bits(state); s5h1420_read_status()
361 if ((*status & FE_HAS_LOCK) && !state->postlocked) { s5h1420_read_status()
364 u32 tmp = s5h1420_getsymbolrate(state); s5h1420_read_status()
365 switch (s5h1420_readreg(state, Vit10) & 0x07) { s5h1420_read_status()
378 tmp = state->fclk / tmp; s5h1420_read_status()
400 s5h1420_writereg(state, FEC01, 0x18); s5h1420_read_status()
401 s5h1420_writereg(state, FEC01, 0x10); s5h1420_read_status()
402 s5h1420_writereg(state, FEC01, val); s5h1420_read_status()
405 val = s5h1420_readreg(state, Mpeg02); s5h1420_read_status()
406 s5h1420_writereg(state, Mpeg02, val | (1 << 6)); s5h1420_read_status()
409 val = s5h1420_readreg(state, QPSK01) & 0x7f; s5h1420_read_status()
410 s5h1420_writereg(state, QPSK01, val); s5h1420_read_status()
414 if (s5h1420_getsymbolrate(state) >= 20000000) { s5h1420_read_status()
415 s5h1420_writereg(state, Loop04, 0x8a); s5h1420_read_status()
416 s5h1420_writereg(state, Loop05, 0x6a); s5h1420_read_status()
418 s5h1420_writereg(state, Loop04, 0x58); s5h1420_read_status()
419 s5h1420_writereg(state, Loop05, 0x27); s5h1420_read_status()
423 state->postlocked = 1; s5h1420_read_status()
433 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_read_ber() local
435 s5h1420_writereg(state, 0x46, 0x1d); s5h1420_read_ber()
438 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); s5h1420_read_ber()
445 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_read_signal_strength() local
447 u8 val = s5h1420_readreg(state, 0x15); s5h1420_read_signal_strength()
456 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_read_ucblocks() local
458 s5h1420_writereg(state, 0x46, 0x1f); s5h1420_read_ucblocks()
461 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); s5h1420_read_ucblocks()
466 static void s5h1420_reset(struct s5h1420_state* state) s5h1420_reset() argument
469 s5h1420_writereg (state, 0x01, 0x08); s5h1420_reset()
470 s5h1420_writereg (state, 0x01, 0x00); s5h1420_reset()
474 static void s5h1420_setsymbolrate(struct s5h1420_state* state, s5h1420_setsymbolrate() argument
485 do_div(val, (state->fclk / 1000)); s5h1420_setsymbolrate()
489 v = s5h1420_readreg(state, Loop01); s5h1420_setsymbolrate()
490 s5h1420_writereg(state, Loop01, v & 0x7f); s5h1420_setsymbolrate()
491 s5h1420_writereg(state, Tnco01, val >> 16); s5h1420_setsymbolrate()
492 s5h1420_writereg(state, Tnco02, val >> 8); s5h1420_setsymbolrate()
493 s5h1420_writereg(state, Tnco03, val & 0xff); s5h1420_setsymbolrate()
494 s5h1420_writereg(state, Loop01, v | 0x80); s5h1420_setsymbolrate()
498 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state) s5h1420_getsymbolrate() argument
500 return state->symbol_rate; s5h1420_getsymbolrate()
503 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset) s5h1420_setfreqoffset() argument
512 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); s5h1420_setfreqoffset()
516 v = s5h1420_readreg(state, Loop01); s5h1420_setfreqoffset()
517 s5h1420_writereg(state, Loop01, v & 0xbf); s5h1420_setfreqoffset()
518 s5h1420_writereg(state, Pnco01, val >> 16); s5h1420_setfreqoffset()
519 s5h1420_writereg(state, Pnco02, val >> 8); s5h1420_setfreqoffset()
520 s5h1420_writereg(state, Pnco03, val & 0xff); s5h1420_setfreqoffset()
521 s5h1420_writereg(state, Loop01, v | 0x40); s5h1420_setfreqoffset()
525 static int s5h1420_getfreqoffset(struct s5h1420_state* state) s5h1420_getfreqoffset() argument
529 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08); s5h1420_getfreqoffset()
530 val = s5h1420_readreg(state, 0x0e) << 16; s5h1420_getfreqoffset()
531 val |= s5h1420_readreg(state, 0x0f) << 8; s5h1420_getfreqoffset()
532 val |= s5h1420_readreg(state, 0x10); s5h1420_getfreqoffset()
533 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7); s5h1420_getfreqoffset()
540 val = (((-val) * (state->fclk/1000000)) / (1<<24)); s5h1420_getfreqoffset()
545 static void s5h1420_setfec_inversion(struct s5h1420_state* state, s5h1420_setfec_inversion() argument
554 inversion = state->config->invert ? 0x08 : 0; s5h1420_setfec_inversion()
556 inversion = state->config->invert ? 0 : 0x08; s5h1420_setfec_inversion()
593 s5h1420_writereg(state, Vit08, vit08); s5h1420_setfec_inversion()
594 s5h1420_writereg(state, Vit09, vit09); s5h1420_setfec_inversion()
598 static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state) s5h1420_getfec() argument
600 switch(s5h1420_readreg(state, 0x32) & 0x07) { s5h1420_getfec()
623 static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state) s5h1420_getinversion() argument
625 if (s5h1420_readreg(state, 0x32) & 0x08) s5h1420_getinversion()
634 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_set_frontend() local
642 frequency_delta = p->frequency - state->tunedfreq; s5h1420_set_frontend()
646 (state->fec_inner == p->fec_inner) && s5h1420_set_frontend()
647 (state->symbol_rate == p->symbol_rate)) { s5h1420_set_frontend()
657 s5h1420_setfreqoffset(state, p->frequency - tmp); s5h1420_set_frontend()
659 s5h1420_setfreqoffset(state, 0); s5h1420_set_frontend()
667 s5h1420_reset(state); s5h1420_set_frontend()
671 state->fclk = 80000000; s5h1420_set_frontend()
673 state->fclk = 59000000; s5h1420_set_frontend()
675 state->fclk = 86000000; s5h1420_set_frontend()
677 state->fclk = 88000000; s5h1420_set_frontend()
679 state->fclk = 44000000; s5h1420_set_frontend()
681 dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); s5h1420_set_frontend()
682 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8); s5h1420_set_frontend()
683 s5h1420_writereg(state, PLL02, 0x40); s5h1420_set_frontend()
684 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); s5h1420_set_frontend()
688 s5h1420_writereg(state, QPSK01, 0xae | 0x10); s5h1420_set_frontend()
690 s5h1420_writereg(state, QPSK01, 0xac | 0x10); s5h1420_set_frontend()
693 s5h1420_writereg(state, CON_1, 0x00); s5h1420_set_frontend()
694 s5h1420_writereg(state, QPSK02, 0x00); s5h1420_set_frontend()
695 s5h1420_writereg(state, Pre01, 0xb0); s5h1420_set_frontend()
697 s5h1420_writereg(state, Loop01, 0xF0); s5h1420_set_frontend()
698 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */ s5h1420_set_frontend()
699 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */ s5h1420_set_frontend()
701 s5h1420_writereg(state, Loop04, 0x79); s5h1420_set_frontend()
703 s5h1420_writereg(state, Loop04, 0x58); s5h1420_set_frontend()
704 s5h1420_writereg(state, Loop05, 0x6b); s5h1420_set_frontend()
707 s5h1420_writereg(state, Post01, (0 << 6) | 0x10); s5h1420_set_frontend()
709 s5h1420_writereg(state, Post01, (1 << 6) | 0x10); s5h1420_set_frontend()
711 s5h1420_writereg(state, Post01, (3 << 6) | 0x10); s5h1420_set_frontend()
713 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */ s5h1420_set_frontend()
715 s5h1420_writereg(state, Sync01, 0x33); s5h1420_set_frontend()
716 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity); s5h1420_set_frontend()
717 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */ s5h1420_set_frontend()
718 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */ s5h1420_set_frontend()
720 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */ s5h1420_set_frontend()
721 s5h1420_writereg(state, DiS03, 0x00); s5h1420_set_frontend()
722 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */ s5h1420_set_frontend()
729 s5h1420_setfreqoffset(state, 0); s5h1420_set_frontend()
733 s5h1420_setsymbolrate(state, p); s5h1420_set_frontend()
734 s5h1420_setfec_inversion(state, p); s5h1420_set_frontend()
737 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1); s5h1420_set_frontend()
739 state->fec_inner = p->fec_inner; s5h1420_set_frontend()
740 state->symbol_rate = p->symbol_rate; s5h1420_set_frontend()
741 state->postlocked = 0; s5h1420_set_frontend()
742 state->tunedfreq = p->frequency; s5h1420_set_frontend()
751 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_get_frontend() local
753 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state); s5h1420_get_frontend()
754 p->inversion = s5h1420_getinversion(state); s5h1420_get_frontend()
755 p->symbol_rate = s5h1420_getsymbolrate(state); s5h1420_get_frontend()
756 p->fec_inner = s5h1420_getfec(state); s5h1420_get_frontend()
796 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_i2c_gate_ctrl() local
799 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1); s5h1420_i2c_gate_ctrl()
801 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe); s5h1420_i2c_gate_ctrl()
806 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_init() local
809 state->CON_1_val = state->config->serial_mpeg << 4; s5h1420_init()
810 s5h1420_writereg(state, 0x02, state->CON_1_val); s5h1420_init()
812 s5h1420_reset(state); s5h1420_init()
819 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_sleep() local
820 state->CON_1_val = 0x12; s5h1420_sleep()
821 return s5h1420_writereg(state, 0x02, state->CON_1_val); s5h1420_sleep()
826 struct s5h1420_state* state = fe->demodulator_priv; s5h1420_release() local
827 i2c_del_adapter(&state->tuner_i2c_adapter); s5h1420_release()
828 kfree(state); s5h1420_release()
838 struct s5h1420_state *state = i2c_get_adapdata(i2c_adap); s5h1420_tuner_i2c_tuner_xfer() local
840 u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */ s5h1420_tuner_i2c_tuner_xfer()
851 m[0].addr = state->config->demod_address; s5h1420_tuner_i2c_tuner_xfer()
857 return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO; s5h1420_tuner_i2c_tuner_xfer()
867 struct s5h1420_state *state = fe->demodulator_priv; s5h1420_get_tuner_i2c_adapter() local
868 return &state->tuner_i2c_adapter; s5h1420_get_tuner_i2c_adapter()
877 /* allocate memory for the internal state */ s5h1420_attach()
878 struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL); s5h1420_attach() local
881 if (state == NULL) s5h1420_attach()
884 /* setup the state */ s5h1420_attach()
885 state->config = config; s5h1420_attach()
886 state->i2c = i2c; s5h1420_attach()
887 state->postlocked = 0; s5h1420_attach()
888 state->fclk = 88000000; s5h1420_attach()
889 state->tunedfreq = 0; s5h1420_attach()
890 state->fec_inner = FEC_NONE; s5h1420_attach()
891 state->symbol_rate = 0; s5h1420_attach()
894 i = s5h1420_readreg(state, ID01); s5h1420_attach()
898 memset(state->shadow, 0xff, sizeof(state->shadow)); s5h1420_attach()
901 state->shadow[i] = s5h1420_readreg(state, i); s5h1420_attach()
904 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops)); s5h1420_attach()
905 state->frontend.demodulator_priv = state; s5h1420_attach()
908 strlcpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus", s5h1420_attach()
909 sizeof(state->tuner_i2c_adapter.name)); s5h1420_attach()
910 state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo; s5h1420_attach()
911 state->tuner_i2c_adapter.algo_data = NULL; s5h1420_attach()
912 i2c_set_adapdata(&state->tuner_i2c_adapter, state); s5h1420_attach()
913 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { s5h1420_attach()
918 return &state->frontend; s5h1420_attach()
921 kfree(state); s5h1420_attach()
H A Ddrxd_hard.c241 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) Read16() argument
243 u8 adr = state->config.demod_address; Read16()
248 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) Read16()
255 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) Read32() argument
257 u8 adr = state->config.demod_address; Read32()
263 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) Read32()
271 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) Write16() argument
273 u8 adr = state->config.demod_address; Write16()
279 if (i2c_write(state->i2c, adr, mm, 6) < 0) Write16()
284 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) Write32() argument
286 u8 adr = state->config.demod_address; Write32()
293 if (i2c_write(state->i2c, adr, mm, 8) < 0) Write32()
298 static int write_chunk(struct drxd_state *state, write_chunk() argument
301 u8 adr = state->config.demod_address; write_chunk()
309 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { write_chunk()
316 static int WriteBlock(struct drxd_state *state, WriteBlock() argument
322 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) WriteBlock()
331 static int WriteTable(struct drxd_state *state, u8 * pTable) WriteTable() argument
351 status = WriteBlock(state, Address, Length * 2, pTable, 0); WriteTable()
361 static int ResetCEFR(struct drxd_state *state) ResetCEFR() argument
363 return WriteTable(state, state->m_ResetCEFR); ResetCEFR()
366 static int InitCP(struct drxd_state *state) InitCP() argument
368 return WriteTable(state, state->m_InitCP); InitCP()
371 static int InitCE(struct drxd_state *state) InitCE() argument
374 enum app_env AppEnv = state->app_env_default; InitCE()
377 status = WriteTable(state, state->m_InitCE); InitCE()
381 if (state->operation_mode == OM_DVBT_Diversity_Front || InitCE()
382 state->operation_mode == OM_DVBT_Diversity_End) { InitCE()
383 AppEnv = state->app_env_diversity; InitCE()
386 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); InitCE()
390 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); InitCE()
393 } else if (AppEnv == APPENV_MOBILE && state->type_A) { InitCE()
394 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); InitCE()
397 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { InitCE()
398 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); InitCE()
404 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); InitCE()
411 static int StopOC(struct drxd_state *state) StopOC() argument
415 u16 ocModeLop = state->m_EcOcRegOcModeLop; StopOC()
421 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); StopOC()
425 state->m_EcOcRegSncSncLvl = ocSyncLvl; StopOC()
429 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); StopOC()
432 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); StopOC()
435 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); StopOC()
438 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); StopOC()
443 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); StopOC()
446 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); StopOC()
452 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); StopOC()
458 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); StopOC()
464 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); StopOC()
467 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); StopOC()
470 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); StopOC()
478 static int StartOC(struct drxd_state *state) StartOC() argument
484 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); StartOC()
489 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); StartOC()
492 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); StartOC()
497 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); StartOC()
502 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); StartOC()
509 static int InitEQ(struct drxd_state *state) InitEQ() argument
511 return WriteTable(state, state->m_InitEQ); InitEQ()
514 static int InitEC(struct drxd_state *state) InitEC() argument
516 return WriteTable(state, state->m_InitEC); InitEC()
519 static int InitSC(struct drxd_state *state) InitSC() argument
521 return WriteTable(state, state->m_InitSC); InitSC()
524 static int InitAtomicRead(struct drxd_state *state) InitAtomicRead() argument
526 return WriteTable(state, state->m_InitAtomicRead); InitAtomicRead()
529 static int CorrectSysClockDeviation(struct drxd_state *state);
531 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) DRX_GetLockStatus() argument
545 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); DRX_GetLockStatus()
551 if (state->drxd_state != DRXD_STARTED) DRX_GetLockStatus()
556 CorrectSysClockDeviation(state); DRX_GetLockStatus()
569 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) SetCfgIfAgc() argument
581 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); SetCfgIfAgc()
586 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); SetCfgIfAgc()
592 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); SetCfgIfAgc()
610 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); SetCfgIfAgc()
616 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); SetCfgIfAgc()
624 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); SetCfgIfAgc()
635 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); SetCfgIfAgc()
638 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); SetCfgIfAgc()
686 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); SetCfgIfAgc()
689 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); SetCfgIfAgc()
692 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); SetCfgIfAgc()
695 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); SetCfgIfAgc()
698 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); SetCfgIfAgc()
712 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) SetCfgRfAgc() argument
727 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); SetCfgRfAgc()
734 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); SetCfgRfAgc()
735 state->m_FeAgRegAgPwd |= SetCfgRfAgc()
737 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); SetCfgRfAgc()
741 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); SetCfgRfAgc()
748 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); SetCfgRfAgc()
755 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); SetCfgRfAgc()
762 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); SetCfgRfAgc()
775 (state->m_FeAgRegAgPwd) &= SetCfgRfAgc()
777 (state->m_FeAgRegAgPwd) |= SetCfgRfAgc()
779 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); SetCfgRfAgc()
783 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); SetCfgRfAgc()
790 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); SetCfgRfAgc()
796 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); SetCfgRfAgc()
807 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); SetCfgRfAgc()
814 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); SetCfgRfAgc()
826 (state->m_FeAgRegAgPwd) &= SetCfgRfAgc()
828 (state->m_FeAgRegAgPwd) |= SetCfgRfAgc()
830 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); SetCfgRfAgc()
834 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); SetCfgRfAgc()
841 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); SetCfgRfAgc()
848 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); SetCfgRfAgc()
855 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); SetCfgRfAgc()
864 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) ReadIFAgc() argument
869 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { ReadIFAgc()
871 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); ReadIFAgc()
884 u32 R1 = state->if_agc_cfg.R1; ReadIFAgc()
885 u32 R2 = state->if_agc_cfg.R2; ReadIFAgc()
886 u32 R3 = state->if_agc_cfg.R3; ReadIFAgc()
904 static int load_firmware(struct drxd_state *state, const char *fw_name) load_firmware() argument
908 if (request_firmware(&fw, fw_name, state->dev) < 0) { load_firmware()
913 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); load_firmware()
914 if (state->microcode == NULL) { load_firmware()
920 state->microcode_length = fw->size; load_firmware()
925 static int DownloadMicrocode(struct drxd_state *state, DownloadMicrocode() argument
964 status = WriteBlock(state, Address, BlockSize, DownloadMicrocode()
975 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) HI_Command() argument
981 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); HI_Command()
991 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); HI_Command()
995 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); HI_Command()
999 static int HI_CfgCommand(struct drxd_state *state) HI_CfgCommand() argument
1003 mutex_lock(&state->mutex); HI_CfgCommand()
1004 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); HI_CfgCommand()
1005 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); HI_CfgCommand()
1006 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); HI_CfgCommand()
1007 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); HI_CfgCommand()
1008 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); HI_CfgCommand()
1010 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); HI_CfgCommand()
1012 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == HI_CfgCommand()
1014 status = Write16(state, HI_RA_RAM_SRV_CMD__A, HI_CfgCommand()
1017 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); HI_CfgCommand()
1018 mutex_unlock(&state->mutex); HI_CfgCommand()
1022 static int InitHI(struct drxd_state *state) InitHI() argument
1024 state->hi_cfg_wakeup_key = (state->chip_adr); InitHI()
1026 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; InitHI()
1027 return HI_CfgCommand(state); InitHI()
1030 static int HI_ResetCommand(struct drxd_state *state) HI_ResetCommand() argument
1034 mutex_lock(&state->mutex); HI_ResetCommand()
1035 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, HI_ResetCommand()
1038 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); HI_ResetCommand()
1039 mutex_unlock(&state->mutex); HI_ResetCommand()
1044 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) DRX_ConfigureI2CBridge() argument
1046 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); DRX_ConfigureI2CBridge()
1048 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; DRX_ConfigureI2CBridge()
1050 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; DRX_ConfigureI2CBridge()
1052 return HI_CfgCommand(state); DRX_ConfigureI2CBridge()
1061 static int AtomicReadBlock(struct drxd_state *state,
1071 mutex_lock(&state->mutex);
1076 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1079 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1082 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1085 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1088 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1092 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1102 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1110 mutex_unlock(&state->mutex);
1114 static int AtomicReadReg32(struct drxd_state *state,
1122 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1130 static int StopAllProcessors(struct drxd_state *state) StopAllProcessors() argument
1132 return Write16(state, HI_COMM_EXEC__A, StopAllProcessors()
1136 static int EnableAndResetMB(struct drxd_state *state) EnableAndResetMB() argument
1138 if (state->type_A) { EnableAndResetMB()
1140 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); EnableAndResetMB()
1144 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); EnableAndResetMB()
1145 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); EnableAndResetMB()
1149 static int InitCC(struct drxd_state *state) InitCC() argument
1151 if (state->osc_clock_freq == 0 || InitCC()
1152 state->osc_clock_freq > 20000 || InitCC()
1153 (state->osc_clock_freq % 4000) != 0) { InitCC()
1154 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); InitCC()
1158 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); InitCC()
1159 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | InitCC()
1161 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); InitCC()
1162 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); InitCC()
1163 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); InitCC()
1168 static int ResetECOD(struct drxd_state *state) ResetECOD() argument
1172 if (state->type_A) ResetECOD()
1173 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); ResetECOD()
1175 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); ResetECOD()
1178 status = WriteTable(state, state->m_ResetECRAM); ResetECOD()
1180 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); ResetECOD()
1186 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) SetCfgPga() argument
1195 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); SetCfgPga()
1200 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); SetCfgPga()
1205 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); SetCfgPga()
1210 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); SetCfgPga()
1216 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000); SetCfgPga()
1223 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); SetCfgPga()
1228 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); SetCfgPga()
1233 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); SetCfgPga()
1238 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); SetCfgPga()
1244 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000); SetCfgPga()
1252 static int InitFE(struct drxd_state *state) InitFE() argument
1257 status = WriteTable(state, state->m_InitFE_1); InitFE()
1261 if (state->type_A) { InitFE()
1262 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, InitFE()
1266 if (state->PGA) InitFE()
1267 status = SetCfgPga(state, 0); InitFE()
1270 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, InitFE()
1277 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); InitFE()
1280 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); InitFE()
1284 status = WriteTable(state, state->m_InitFE_2); InitFE()
1293 static int InitFT(struct drxd_state *state) InitFT() argument
1299 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); InitFT()
1302 static int SC_WaitForReady(struct drxd_state *state) SC_WaitForReady() argument
1308 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); SC_WaitForReady()
1315 static int SC_SendCommand(struct drxd_state *state, u16 cmd) SC_SendCommand() argument
1320 Write16(state, SC_RA_RAM_CMD__A, cmd, 0); SC_SendCommand()
1321 SC_WaitForReady(state); SC_SendCommand()
1323 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); SC_SendCommand()
1333 static int SC_ProcStartCommand(struct drxd_state *state, SC_ProcStartCommand() argument
1339 mutex_lock(&state->mutex); SC_ProcStartCommand()
1341 Read16(state, SC_COMM_EXEC__A, &scExec, 0); SC_ProcStartCommand()
1346 SC_WaitForReady(state); SC_ProcStartCommand()
1347 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); SC_ProcStartCommand()
1348 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); SC_ProcStartCommand()
1349 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); SC_ProcStartCommand()
1351 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); SC_ProcStartCommand()
1353 mutex_unlock(&state->mutex); SC_ProcStartCommand()
1357 static int SC_SetPrefParamCommand(struct drxd_state *state, SC_SetPrefParamCommand() argument
1362 mutex_lock(&state->mutex); SC_SetPrefParamCommand()
1364 status = SC_WaitForReady(state); SC_SetPrefParamCommand()
1367 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); SC_SetPrefParamCommand()
1370 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); SC_SetPrefParamCommand()
1373 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); SC_SetPrefParamCommand()
1377 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); SC_SetPrefParamCommand()
1381 mutex_unlock(&state->mutex); SC_SetPrefParamCommand()
1386 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1390 mutex_lock(&state->mutex);
1392 status = SC_WaitForReady(state);
1395 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1398 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1402 mutex_unlock(&state->mutex);
1407 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) ConfigureMPEGOutput() argument
1417 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */ ConfigureMPEGOutput()
1419 if (state->operation_mode == OM_DVBT_Diversity_Front) { ConfigureMPEGOutput()
1428 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; ConfigureMPEGOutput()
1436 if (state->insert_rs_byte) { ConfigureMPEGOutput()
1453 if (state->enable_parallel) ConfigureMPEGOutput()
1481 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); ConfigureMPEGOutput()
1484 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); ConfigureMPEGOutput()
1487 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); ConfigureMPEGOutput()
1490 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); ConfigureMPEGOutput()
1497 static int SetDeviceTypeId(struct drxd_state *state) SetDeviceTypeId() argument
1503 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); SetDeviceTypeId()
1507 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); SetDeviceTypeId()
1512 state->type_A = 0; SetDeviceTypeId()
1513 state->PGA = 0; SetDeviceTypeId()
1514 state->diversity = 0; SetDeviceTypeId()
1516 state->type_A = 1; SetDeviceTypeId()
1523 state->diversity = 1; SetDeviceTypeId()
1526 state->PGA = 1; SetDeviceTypeId()
1529 state->diversity = 1; SetDeviceTypeId()
1544 state->m_InitAtomicRead = DRXD_InitAtomicRead; SetDeviceTypeId()
1545 state->m_InitSC = DRXD_InitSC; SetDeviceTypeId()
1546 state->m_ResetECRAM = DRXD_ResetECRAM; SetDeviceTypeId()
1547 if (state->type_A) { SetDeviceTypeId()
1548 state->m_ResetCEFR = DRXD_ResetCEFR; SetDeviceTypeId()
1549 state->m_InitFE_1 = DRXD_InitFEA2_1; SetDeviceTypeId()
1550 state->m_InitFE_2 = DRXD_InitFEA2_2; SetDeviceTypeId()
1551 state->m_InitCP = DRXD_InitCPA2; SetDeviceTypeId()
1552 state->m_InitCE = DRXD_InitCEA2; SetDeviceTypeId()
1553 state->m_InitEQ = DRXD_InitEQA2; SetDeviceTypeId()
1554 state->m_InitEC = DRXD_InitECA2; SetDeviceTypeId()
1555 if (load_firmware(state, DRX_FW_FILENAME_A2)) SetDeviceTypeId()
1558 state->m_ResetCEFR = NULL; SetDeviceTypeId()
1559 state->m_InitFE_1 = DRXD_InitFEB1_1; SetDeviceTypeId()
1560 state->m_InitFE_2 = DRXD_InitFEB1_2; SetDeviceTypeId()
1561 state->m_InitCP = DRXD_InitCPB1; SetDeviceTypeId()
1562 state->m_InitCE = DRXD_InitCEB1; SetDeviceTypeId()
1563 state->m_InitEQ = DRXD_InitEQB1; SetDeviceTypeId()
1564 state->m_InitEC = DRXD_InitECB1; SetDeviceTypeId()
1565 if (load_firmware(state, DRX_FW_FILENAME_B1)) SetDeviceTypeId()
1568 if (state->diversity) { SetDeviceTypeId()
1569 state->m_InitDiversityFront = DRXD_InitDiversityFront; SetDeviceTypeId()
1570 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; SetDeviceTypeId()
1571 state->m_DisableDiversity = DRXD_DisableDiversity; SetDeviceTypeId()
1572 state->m_StartDiversityFront = DRXD_StartDiversityFront; SetDeviceTypeId()
1573 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; SetDeviceTypeId()
1574 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; SetDeviceTypeId()
1575 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; SetDeviceTypeId()
1577 state->m_InitDiversityFront = NULL; SetDeviceTypeId()
1578 state->m_InitDiversityEnd = NULL; SetDeviceTypeId()
1579 state->m_DisableDiversity = NULL; SetDeviceTypeId()
1580 state->m_StartDiversityFront = NULL; SetDeviceTypeId()
1581 state->m_StartDiversityEnd = NULL; SetDeviceTypeId()
1582 state->m_DiversityDelay8MHZ = NULL; SetDeviceTypeId()
1583 state->m_DiversityDelay6MHZ = NULL; SetDeviceTypeId()
1589 static int CorrectSysClockDeviation(struct drxd_state *state) CorrectSysClockDeviation() argument
1605 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); CorrectSysClockDeviation()
1608 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); CorrectSysClockDeviation()
1612 if (state->type_A) { CorrectSysClockDeviation()
1620 switch (state->props.bandwidth_hz) { CorrectSysClockDeviation()
1647 (state->expected_sys_clock_freq)) * CorrectSysClockDeviation()
1650 (state->expected_sys_clock_freq)); CorrectSysClockDeviation()
1652 Diff = oscClockDeviation - state->osc_clock_deviation; CorrectSysClockDeviation()
1655 state->sys_clock_freq = (u16) sysClockFreq; CorrectSysClockDeviation()
1656 if (oscClockDeviation != state->osc_clock_deviation) { CorrectSysClockDeviation()
1657 if (state->config.osc_deviation) { CorrectSysClockDeviation()
1658 state->config.osc_deviation(state->priv, CorrectSysClockDeviation()
1661 state->osc_clock_deviation = CorrectSysClockDeviation()
1666 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); CorrectSysClockDeviation()
1671 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); CorrectSysClockDeviation()
1674 state->cscd_state = CSCD_SAVED; CorrectSysClockDeviation()
1681 static int DRX_Stop(struct drxd_state *state) DRX_Stop() argument
1685 if (state->drxd_state != DRXD_STARTED) DRX_Stop()
1689 if (state->cscd_state != CSCD_SAVED) { DRX_Stop()
1691 status = DRX_GetLockStatus(state, &lock); DRX_Stop()
1696 status = StopOC(state); DRX_Stop()
1700 state->drxd_state = DRXD_STOPPED; DRX_Stop()
1702 status = ConfigureMPEGOutput(state, 0); DRX_Stop()
1706 if (state->type_A) { DRX_Stop()
1708 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); DRX_Stop()
1712 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1715 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1720 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1723 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1726 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1729 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1732 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1735 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRX_Stop()
1738 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); DRX_Stop()
1748 static int SetOperationMode(struct drxd_state *state, int oMode)
1753 if (state->drxd_state != DRXD_STOPPED) {
1758 if (oMode == state->operation_mode) {
1763 if (oMode != OM_Default && !state->diversity) {
1770 status = WriteTable(state, state->m_InitDiversityFront);
1773 status = WriteTable(state, state->m_InitDiversityEnd);
1779 status = WriteTable(state, state->m_DisableDiversity);
1785 state->operation_mode = oMode;
1790 static int StartDiversity(struct drxd_state *state) StartDiversity() argument
1796 if (state->operation_mode == OM_DVBT_Diversity_Front) { StartDiversity()
1797 status = WriteTable(state, state->m_StartDiversityFront); StartDiversity()
1800 } else if (state->operation_mode == OM_DVBT_Diversity_End) { StartDiversity()
1801 status = WriteTable(state, state->m_StartDiversityEnd); StartDiversity()
1804 if (state->props.bandwidth_hz == 8000000) { StartDiversity()
1805 status = WriteTable(state, state->m_DiversityDelay8MHZ); StartDiversity()
1809 status = WriteTable(state, state->m_DiversityDelay6MHZ); StartDiversity()
1814 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); StartDiversity()
1823 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); StartDiversity()
1831 static int SetFrequencyShift(struct drxd_state *state, SetFrequencyShift() argument
1834 int negativeShift = (state->tuner_mirrors == channelMirrored); SetFrequencyShift()
1847 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + SetFrequencyShift()
1849 1 << 28, state->sys_clock_freq); SetFrequencyShift()
1851 state->fe_fs_add_incr &= 0x0FFFFFFFL; SetFrequencyShift()
1853 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); SetFrequencyShift()
1857 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, SetFrequencyShift()
1858 1 << 28, state->sys_clock_freq); SetFrequencyShift()
1860 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; SetFrequencyShift()
1862 state->org_fe_fs_add_incr = ((1L << 28) - SetFrequencyShift()
1863 state->org_fe_fs_add_incr); SetFrequencyShift()
1865 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, SetFrequencyShift()
1866 state->fe_fs_add_incr, 0); SetFrequencyShift()
1869 static int SetCfgNoiseCalibration(struct drxd_state *state, SetCfgNoiseCalibration() argument
1876 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); SetCfgNoiseCalibration()
1883 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); SetCfgNoiseCalibration()
1887 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); SetCfgNoiseCalibration()
1891 if (!state->type_A) { SetCfgNoiseCalibration()
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); SetCfgNoiseCalibration()
1895 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); SetCfgNoiseCalibration()
1904 static int DRX_Start(struct drxd_state *state, s32 off) DRX_Start() argument
1906 struct dtv_frontend_properties *p = &state->props; DRX_Start()
1935 if (state->drxd_state != DRXD_STOPPED) DRX_Start()
1937 status = ResetECOD(state); DRX_Start()
1940 if (state->type_A) { DRX_Start()
1941 status = InitSC(state); DRX_Start()
1945 status = InitFT(state); DRX_Start()
1948 status = InitCP(state); DRX_Start()
1951 status = InitCE(state); DRX_Start()
1954 status = InitEQ(state); DRX_Start()
1957 status = InitSC(state); DRX_Start()
1964 status = SetCfgIfAgc(state, &state->if_agc_cfg); DRX_Start()
1967 status = SetCfgRfAgc(state, &state->rf_agc_cfg); DRX_Start()
1971 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); DRX_Start()
1979 if (state->type_A) { DRX_Start()
1980 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); DRX_Start()
1990 if (state->type_A) { DRX_Start()
1991 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); DRX_Start()
2024 if (state->type_A) { DRX_Start()
2025 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); DRX_Start()
2028 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); DRX_Start()
2054 if (state->type_A) { DRX_Start()
2055 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); DRX_Start()
2058 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); DRX_Start()
2083 if (state->type_A) { DRX_Start()
2084 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); DRX_Start()
2087 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); DRX_Start()
2115 if (state->type_A) { DRX_Start()
2116 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); DRX_Start()
2119 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); DRX_Start()
2154 if (state->type_A) { DRX_Start()
2155 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); DRX_Start()
2158 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); DRX_Start()
2161 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); DRX_Start()
2164 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); DRX_Start()
2167 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); DRX_Start()
2171 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); DRX_Start()
2174 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); DRX_Start()
2177 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); DRX_Start()
2180 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); DRX_Start()
2187 if (state->type_A) { DRX_Start()
2188 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); DRX_Start()
2191 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); DRX_Start()
2194 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); DRX_Start()
2197 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); DRX_Start()
2200 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); DRX_Start()
2204 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); DRX_Start()
2207 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); DRX_Start()
2210 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); DRX_Start()
2213 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); DRX_Start()
2221 if (state->type_A) { DRX_Start()
2222 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); DRX_Start()
2225 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); DRX_Start()
2228 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); DRX_Start()
2231 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); DRX_Start()
2234 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); DRX_Start()
2238 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); DRX_Start()
2241 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); DRX_Start()
2244 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); DRX_Start()
2247 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); DRX_Start()
2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); DRX_Start()
2269 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); DRX_Start()
2279 if (state->type_A) { DRX_Start()
2280 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); DRX_Start()
2289 if (state->type_A) { DRX_Start()
2290 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); DRX_Start()
2297 if (state->type_A) { DRX_Start()
2298 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); DRX_Start()
2305 if (state->type_A) { DRX_Start()
2306 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); DRX_Start()
2313 if (state->type_A) { DRX_Start()
2314 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); DRX_Start()
2340 status = Write16(state, DRX_Start()
2347 status = Write16(state, DRX_Start()
2354 status = Write16(state, DRX_Start()
2363 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); DRX_Start()
2369 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); DRX_Start()
2383 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); DRX_Start()
2388 status = SetCfgNoiseCalibration(state, &state->noise_cal); DRX_Start()
2392 if (state->cscd_state == CSCD_INIT) { DRX_Start()
2394 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); DRX_Start()
2398 state->cscd_state = CSCD_SET; DRX_Start()
2404 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, DRX_Start()
2406 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); DRX_Start()
2409 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000); DRX_Start()
2415 SetFrequencyShift(state, off, mirrorFreqSpect); DRX_Start()
2420 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); DRX_Start()
2423 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); DRX_Start()
2435 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); DRX_Start()
2440 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN); DRX_Start()
2444 status = StartOC(state); DRX_Start()
2448 if (state->operation_mode != OM_Default) { DRX_Start()
2449 status = StartDiversity(state); DRX_Start()
2454 state->drxd_state = DRXD_STARTED; DRX_Start()
2460 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) CDRXD() argument
2480 u32 ulClock = state->config.clock; CDRXD()
2490 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; CDRXD()
2491 state->if_agc_cfg.outputLevel = 0; CDRXD()
2492 state->if_agc_cfg.settleLevel = 140; CDRXD()
2493 state->if_agc_cfg.minOutputLevel = 0; CDRXD()
2494 state->if_agc_cfg.maxOutputLevel = 1023; CDRXD()
2495 state->if_agc_cfg.speed = 904; CDRXD()
2498 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; CDRXD()
2499 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); CDRXD()
2507 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; CDRXD()
2508 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); CDRXD()
2509 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); CDRXD()
2510 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); CDRXD()
2511 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); CDRXD()
2514 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); CDRXD()
2515 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); CDRXD()
2516 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); CDRXD()
2518 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); CDRXD()
2519 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); CDRXD()
2520 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); CDRXD()
2522 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; CDRXD()
2525 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; CDRXD()
2526 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); CDRXD()
2534 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; CDRXD()
2535 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); CDRXD()
2536 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); CDRXD()
2537 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); CDRXD()
2538 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); CDRXD()
2542 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; CDRXD()
2545 state->app_env_default = (enum app_env) CDRXD()
2548 state->app_env_diversity = (enum app_env) CDRXD()
2553 state->noise_cal.cpOpt = 0; CDRXD()
2554 state->noise_cal.cpNexpOfs = 40; CDRXD()
2555 state->noise_cal.tdCal2k = -40; CDRXD()
2556 state->noise_cal.tdCal8k = -24; CDRXD()
2559 state->noise_cal.cpOpt = 1; CDRXD()
2560 state->noise_cal.cpNexpOfs = 0; CDRXD()
2561 state->noise_cal.tdCal2k = -21; CDRXD()
2562 state->noise_cal.tdCal8k = -24; CDRXD()
2564 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); CDRXD()
2566 state->chip_adr = (state->config.demod_address << 1) | 1; CDRXD()
2569 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; CDRXD()
2572 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; CDRXD()
2575 state->m_HiI2cPatch = NULL; CDRXD()
2579 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); CDRXD()
2581 state->expected_sys_clock_freq = 48000; CDRXD()
2583 state->sys_clock_freq = 48000; CDRXD()
2584 state->osc_clock_freq = (u16) ulClock; CDRXD()
2585 state->osc_clock_deviation = 0; CDRXD()
2586 state->cscd_state = CSCD_INIT; CDRXD()
2587 state->drxd_state = DRXD_UNINITIALIZED; CDRXD()
2589 state->PGA = 0; CDRXD()
2590 state->type_A = 0; CDRXD()
2591 state->tuner_mirrors = 0; CDRXD()
2594 state->insert_rs_byte = state->config.insert_rs_byte; CDRXD()
2595 state->enable_parallel = (ulSerialMode != 1); CDRXD()
2600 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * CDRXD()
2604 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * CDRXD()
2607 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; CDRXD()
2608 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ CDRXD()
2609 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; CDRXD()
2613 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) DRXD_init() argument
2618 if (state->init_done) DRXD_init()
2621 CDRXD(state, state->config.IF ? state->config.IF : 36000000); DRXD_init()
2624 state->operation_mode = OM_Default; DRXD_init()
2626 status = SetDeviceTypeId(state); DRXD_init()
2631 if (!state->type_A && state->m_HiI2cPatch != NULL) { DRXD_init()
2632 status = WriteTable(state, state->m_HiI2cPatch); DRXD_init()
2637 if (state->type_A) { DRXD_init()
2640 status = Write16(state, 0x43012D, 0x047f, 0); DRXD_init()
2645 status = HI_ResetCommand(state); DRXD_init()
2649 status = StopAllProcessors(state); DRXD_init()
2652 status = InitCC(state); DRXD_init()
2656 state->osc_clock_deviation = 0; DRXD_init()
2658 if (state->config.osc_deviation) DRXD_init()
2659 state->osc_clock_deviation = DRXD_init()
2660 state->config.osc_deviation(state->priv, 0, 0); DRXD_init()
2664 s32 devA = (s32) (state->osc_clock_deviation) * DRXD_init()
2665 (s32) (state->expected_sys_clock_freq); DRXD_init()
2678 state->sys_clock_freq = DRXD_init()
2679 (u16) ((state->expected_sys_clock_freq) + DRXD_init()
2682 status = InitHI(state); DRXD_init()
2685 status = InitAtomicRead(state); DRXD_init()
2689 status = EnableAndResetMB(state); DRXD_init()
2692 if (state->type_A) { DRXD_init()
2693 status = ResetCEFR(state); DRXD_init()
2698 status = DownloadMicrocode(state, fw, fw_size); DRXD_init()
2702 status = DownloadMicrocode(state, state->microcode, state->microcode_length); DRXD_init()
2707 if (state->PGA) { DRXD_init()
2708 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; DRXD_init()
2709 SetCfgPga(state, 0); /* PGA = 0 dB */ DRXD_init()
2711 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; DRXD_init()
2714 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; DRXD_init()
2716 status = InitFE(state); DRXD_init()
2719 status = InitFT(state); DRXD_init()
2722 status = InitCP(state); DRXD_init()
2725 status = InitCE(state); DRXD_init()
2728 status = InitEQ(state); DRXD_init()
2731 status = InitEC(state); DRXD_init()
2734 status = InitSC(state); DRXD_init()
2738 status = SetCfgIfAgc(state, &state->if_agc_cfg); DRXD_init()
2741 status = SetCfgRfAgc(state, &state->rf_agc_cfg); DRXD_init()
2745 state->cscd_state = CSCD_INIT; DRXD_init()
2746 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRXD_init()
2749 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); DRXD_init()
2761 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); DRXD_init()
2765 status = StopOC(state); DRXD_init()
2769 state->drxd_state = DRXD_STOPPED; DRXD_init()
2770 state->init_done = 1; DRXD_init()
2776 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) DRXD_status() argument
2778 DRX_GetLockStatus(state, pLockStatus); DRXD_status()
2782 ConfigureMPEGOutput(state, 1); DRXD_status()
2784 /*DRX_GetLockStatus(state, pLockStatus); */ DRXD_status()
2796 struct drxd_state *state = fe->demodulator_priv; drxd_read_signal_strength() local
2800 res = ReadIFAgc(state, &value); drxd_read_signal_strength()
2810 struct drxd_state *state = fe->demodulator_priv; drxd_read_status() local
2813 DRXD_status(state, &lock); drxd_read_status()
2833 struct drxd_state *state = fe->demodulator_priv; drxd_init() local
2835 return DRXD_init(state, NULL, 0); drxd_init()
2840 struct drxd_state *state = fe->demodulator_priv; drxd_config_i2c() local
2842 if (state->config.disable_i2c_gate_ctrl == 1) drxd_config_i2c()
2845 return DRX_ConfigureI2CBridge(state, onoff); drxd_config_i2c()
2877 struct drxd_state *state = fe->demodulator_priv; drxd_sleep() local
2879 ConfigureMPEGOutput(state, 0); drxd_sleep()
2891 struct drxd_state *state = fe->demodulator_priv; drxd_set_frontend() local
2894 state->props = *p; drxd_set_frontend()
2895 DRX_Stop(state); drxd_set_frontend()
2905 return DRX_Start(state, off); drxd_set_frontend()
2910 struct drxd_state *state = fe->demodulator_priv; drxd_release() local
2912 kfree(state); drxd_release()
2951 struct drxd_state *state = NULL; drxd_attach() local
2953 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL); drxd_attach()
2954 if (!state) drxd_attach()
2956 memset(state, 0, sizeof(*state)); drxd_attach()
2958 state->ops = drxd_ops; drxd_attach()
2959 state->dev = dev; drxd_attach()
2960 state->config = *config; drxd_attach()
2961 state->i2c = i2c; drxd_attach()
2962 state->priv = priv; drxd_attach()
2964 mutex_init(&state->mutex); drxd_attach()
2966 if (Read16(state, 0, NULL, 0) < 0) drxd_attach()
2969 state->frontend.ops = drxd_ops; drxd_attach()
2970 state->frontend.demodulator_priv = state; drxd_attach()
2971 ConfigureMPEGOutput(state, 0); drxd_attach()
2973 CDRXD(state, state->config.IF ? state->config.IF : 36000000); drxd_attach()
2974 InitHI(state); drxd_attach()
2976 return &state->frontend; drxd_attach()
2980 kfree(state); drxd_attach()
H A Ddib7000m.c72 static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg) dib7000m_read_word() argument
76 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib7000m_read_word()
81 state->i2c_write_buffer[0] = (reg >> 8) | 0x80; dib7000m_read_word()
82 state->i2c_write_buffer[1] = reg & 0xff; dib7000m_read_word()
84 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); dib7000m_read_word()
85 state->msg[0].addr = state->i2c_addr >> 1; dib7000m_read_word()
86 state->msg[0].flags = 0; dib7000m_read_word()
87 state->msg[0].buf = state->i2c_write_buffer; dib7000m_read_word()
88 state->msg[0].len = 2; dib7000m_read_word()
89 state->msg[1].addr = state->i2c_addr >> 1; dib7000m_read_word()
90 state->msg[1].flags = I2C_M_RD; dib7000m_read_word()
91 state->msg[1].buf = state->i2c_read_buffer; dib7000m_read_word()
92 state->msg[1].len = 2; dib7000m_read_word()
94 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2) dib7000m_read_word()
97 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; dib7000m_read_word()
98 mutex_unlock(&state->i2c_buffer_lock); dib7000m_read_word()
103 static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val) dib7000m_write_word() argument
107 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib7000m_write_word()
112 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; dib7000m_write_word()
113 state->i2c_write_buffer[1] = reg & 0xff; dib7000m_write_word()
114 state->i2c_write_buffer[2] = (val >> 8) & 0xff; dib7000m_write_word()
115 state->i2c_write_buffer[3] = val & 0xff; dib7000m_write_word()
117 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); dib7000m_write_word()
118 state->msg[0].addr = state->i2c_addr >> 1; dib7000m_write_word()
119 state->msg[0].flags = 0; dib7000m_write_word()
120 state->msg[0].buf = state->i2c_write_buffer; dib7000m_write_word()
121 state->msg[0].len = 4; dib7000m_write_word()
123 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? dib7000m_write_word()
125 mutex_unlock(&state->i2c_buffer_lock); dib7000m_write_word()
128 static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf) dib7000m_write_tab() argument
136 if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC dib7000m_write_tab()
140 dib7000m_write_word(state, r, *n++); dib7000m_write_tab()
147 static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode) dib7000m_set_output_mode() argument
155 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1); dib7000m_set_output_mode()
157 dprintk( "setting output mode for demod %p to %d", &state->demod, mode); dib7000m_set_output_mode()
170 if (state->cfg.hostbus_diversity) dib7000m_set_output_mode()
184 dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod); dib7000m_set_output_mode()
188 if (state->cfg.output_mpeg2_in_188_bytes) dib7000m_set_output_mode()
191 ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode); dib7000m_set_output_mode()
192 ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */ dib7000m_set_output_mode()
193 ret |= dib7000m_write_word(state, 1795, outreg); dib7000m_set_output_mode()
194 ret |= dib7000m_write_word(state, 1805, sram); dib7000m_set_output_mode()
196 if (state->revision == 0x4003) { dib7000m_set_output_mode()
197 u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd; dib7000m_set_output_mode()
200 dib7000m_write_word(state, 909, clk_cfg1); dib7000m_set_output_mode()
205 static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode) dib7000m_set_power_mode() argument
241 if (!state->cfg.mobile_mode) dib7000m_set_power_mode()
245 if (state->revision != 0x4000) dib7000m_set_power_mode()
248 if (state->revision == 0x4003) dib7000m_set_power_mode()
251 dib7000m_write_word(state, 903 + offset, reg_903); dib7000m_set_power_mode()
252 dib7000m_write_word(state, 904 + offset, reg_904); dib7000m_set_power_mode()
253 dib7000m_write_word(state, 905 + offset, reg_905); dib7000m_set_power_mode()
254 dib7000m_write_word(state, 906 + offset, reg_906); dib7000m_set_power_mode()
257 static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no) dib7000m_set_adc_state() argument
260 u16 reg_913 = dib7000m_read_word(state, 913), dib7000m_set_adc_state()
261 reg_914 = dib7000m_read_word(state, 914); dib7000m_set_adc_state()
266 ret |= dib7000m_write_word(state, 914, reg_914); dib7000m_set_adc_state()
275 if (state->revision == 0x4000) { // workaround for PA/MA dib7000m_set_adc_state()
277 dib7000m_write_word(state, 913, 0); dib7000m_set_adc_state()
278 dib7000m_write_word(state, 914, reg_914 & 0x3); dib7000m_set_adc_state()
280 dib7000m_write_word(state, 913, (1 << 15)); dib7000m_set_adc_state()
281 dib7000m_write_word(state, 914, reg_914 & 0x3); dib7000m_set_adc_state()
306 ret |= dib7000m_write_word(state, 913, reg_913); dib7000m_set_adc_state()
307 ret |= dib7000m_write_word(state, 914, reg_914); dib7000m_set_adc_state()
312 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw) dib7000m_set_bandwidth() argument
320 state->current_bandwidth = bw; dib7000m_set_bandwidth()
322 if (state->timf == 0) { dib7000m_set_bandwidth()
324 timf = state->timf_default; dib7000m_set_bandwidth()
327 timf = state->timf; dib7000m_set_bandwidth()
332 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); dib7000m_set_bandwidth()
333 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff)); dib7000m_set_bandwidth()
340 struct dib7000m_state *state = demod->demodulator_priv; dib7000m_set_diversity_in() local
342 if (state->div_force_off) { dib7000m_set_diversity_in()
346 state->div_state = (u8)onoff; dib7000m_set_diversity_in()
349 dib7000m_write_word(state, 263 + state->reg_offs, 6); dib7000m_set_diversity_in()
350 dib7000m_write_word(state, 264 + state->reg_offs, 6); dib7000m_set_diversity_in()
351 dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0)); dib7000m_set_diversity_in()
353 dib7000m_write_word(state, 263 + state->reg_offs, 1); dib7000m_set_diversity_in()
354 dib7000m_write_word(state, 264 + state->reg_offs, 0); dib7000m_set_diversity_in()
355 dib7000m_write_word(state, 266 + state->reg_offs, 0); dib7000m_set_diversity_in()
361 static int dib7000m_sad_calib(struct dib7000m_state *state) dib7000m_sad_calib() argument
365 // dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth dib7000m_sad_calib()
366 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0)); dib7000m_sad_calib()
367 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096 dib7000m_sad_calib()
370 dib7000m_write_word(state, 929, (1 << 0)); dib7000m_sad_calib()
371 dib7000m_write_word(state, 929, (0 << 0)); dib7000m_sad_calib()
378 static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw) dib7000m_reset_pll_common() argument
380 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); dib7000m_reset_pll_common()
381 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); dib7000m_reset_pll_common()
382 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); dib7000m_reset_pll_common()
383 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 928, bw->sad_cfg); dib7000m_reset_pll_common()
388 static void dib7000m_reset_pll(struct dib7000m_state *state) dib7000m_reset_pll() argument
390 const struct dibx000_bandwidth_config *bw = state->cfg.bw; dib7000m_reset_pll()
401 if (!state->cfg.quartz_direct) { dib7000m_reset_pll()
405 if(state->cfg.input_clk_is_div_2) dib7000m_reset_pll()
414 dib7000m_write_word(state, 910, reg_910); // pll cfg dib7000m_reset_pll()
415 dib7000m_write_word(state, 907, reg_907); // clk cfg0 dib7000m_reset_pll()
416 dib7000m_write_word(state, 908, 0x0006); // clk_cfg1 dib7000m_reset_pll()
418 dib7000m_reset_pll_common(state, bw); dib7000m_reset_pll()
421 static void dib7000mc_reset_pll(struct dib7000m_state *state) dib7000mc_reset_pll() argument
423 const struct dibx000_bandwidth_config *bw = state->cfg.bw; dib7000mc_reset_pll()
427 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); dib7000mc_reset_pll()
430 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) | dib7000mc_reset_pll()
434 dib7000m_write_word(state, 908, clk_cfg1); dib7000mc_reset_pll()
436 dib7000m_write_word(state, 908, clk_cfg1); dib7000mc_reset_pll()
439 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7)); dib7000mc_reset_pll()
441 dib7000m_reset_pll_common(state, bw); dib7000mc_reset_pll()
559 static int dib7000m_demod_reset(struct dib7000m_state *state) dib7000m_demod_reset() argument
561 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); dib7000m_demod_reset()
564 dib7000m_set_adc_state(state, DIBX000_VBG_ENABLE); dib7000m_demod_reset()
567 dib7000m_write_word(state, 898, 0xffff); dib7000m_demod_reset()
568 dib7000m_write_word(state, 899, 0xffff); dib7000m_demod_reset()
569 dib7000m_write_word(state, 900, 0xff0f); dib7000m_demod_reset()
570 dib7000m_write_word(state, 901, 0xfffc); dib7000m_demod_reset()
572 dib7000m_write_word(state, 898, 0); dib7000m_demod_reset()
573 dib7000m_write_word(state, 899, 0); dib7000m_demod_reset()
574 dib7000m_write_word(state, 900, 0); dib7000m_demod_reset()
575 dib7000m_write_word(state, 901, 0); dib7000m_demod_reset()
577 if (state->revision == 0x4000) dib7000m_demod_reset()
578 dib7000m_reset_pll(state); dib7000m_demod_reset()
580 dib7000mc_reset_pll(state); dib7000m_demod_reset()
582 if (dib7000m_reset_gpio(state) != 0) dib7000m_demod_reset()
585 if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0) dib7000m_demod_reset()
589 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) ); dib7000m_demod_reset()
591 dib7000m_set_bandwidth(state, 8000); dib7000m_demod_reset()
593 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON); dib7000m_demod_reset()
594 dib7000m_sad_calib(state); dib7000m_demod_reset()
595 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF); dib7000m_demod_reset()
597 if (state->cfg.dvbt_mode) dib7000m_demod_reset()
598 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output dib7000m_demod_reset()
600 if (state->cfg.mobile_mode) dib7000m_demod_reset()
601 dib7000m_write_word(state, 261 + state->reg_offs, 2); dib7000m_demod_reset()
603 dib7000m_write_word(state, 224 + state->reg_offs, 1); dib7000m_demod_reset()
606 if(state->cfg.tuner_is_baseband) dib7000m_demod_reset()
607 dib7000m_write_word(state, 36, 0x0755); dib7000m_demod_reset()
609 dib7000m_write_word(state, 36, 0x1f55); dib7000m_demod_reset()
612 if (state->revision == 0x4000) dib7000m_demod_reset()
613 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6)); dib7000m_demod_reset()
615 dib7000m_write_word(state, 909, (3 << 4) | 1); dib7000m_demod_reset()
617 dib7000m_write_tab(state, dib7000m_defaults_common); dib7000m_demod_reset()
618 dib7000m_write_tab(state, dib7000m_defaults); dib7000m_demod_reset()
620 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY); dib7000m_demod_reset()
622 state->internal_clk = state->cfg.bw->internal; dib7000m_demod_reset()
627 static void dib7000m_restart_agc(struct dib7000m_state *state) dib7000m_restart_agc() argument
630 dib7000m_write_word(state, 898, 0x0c00); dib7000m_restart_agc()
631 dib7000m_write_word(state, 898, 0x0000); dib7000m_restart_agc()
634 static int dib7000m_agc_soft_split(struct dib7000m_state *state) dib7000m_agc_soft_split() argument
638 if(!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0) dib7000m_agc_soft_split()
642 agc = dib7000m_read_word(state, 390); dib7000m_agc_soft_split()
644 if (agc > state->current_agc->split.min_thres) dib7000m_agc_soft_split()
645 split_offset = state->current_agc->split.min; dib7000m_agc_soft_split()
646 else if (agc < state->current_agc->split.max_thres) dib7000m_agc_soft_split()
647 split_offset = state->current_agc->split.max; dib7000m_agc_soft_split()
649 split_offset = state->current_agc->split.max * dib7000m_agc_soft_split()
650 (agc - state->current_agc->split.min_thres) / dib7000m_agc_soft_split()
651 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); dib7000m_agc_soft_split()
656 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset); dib7000m_agc_soft_split()
659 static int dib7000m_update_lna(struct dib7000m_state *state) dib7000m_update_lna() argument
663 if (state->cfg.update_lna) { dib7000m_update_lna()
665 dyn_gain = dib7000m_read_word(state, 390); dib7000m_update_lna()
667 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed dib7000m_update_lna()
668 dib7000m_restart_agc(state); dib7000m_update_lna()
675 static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band) dib7000m_set_agc_config() argument
679 if (state->current_band == band && state->current_agc != NULL) dib7000m_set_agc_config()
681 state->current_band = band; dib7000m_set_agc_config()
683 for (i = 0; i < state->cfg.agc_config_count; i++) dib7000m_set_agc_config()
684 if (state->cfg.agc[i].band_caps & band) { dib7000m_set_agc_config()
685 agc = &state->cfg.agc[i]; dib7000m_set_agc_config()
694 state->current_agc = agc; dib7000m_set_agc_config()
697 dib7000m_write_word(state, 72 , agc->setup); dib7000m_set_agc_config()
698 dib7000m_write_word(state, 73 , agc->inv_gain); dib7000m_set_agc_config()
699 dib7000m_write_word(state, 74 , agc->time_stabiliz); dib7000m_set_agc_config()
700 dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock); dib7000m_set_agc_config()
703 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp); dib7000m_set_agc_config()
704 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp); dib7000m_set_agc_config()
707 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); dib7000m_set_agc_config()
710 if (state->wbd_ref != 0) dib7000m_set_agc_config()
711 dib7000m_write_word(state, 102, state->wbd_ref); dib7000m_set_agc_config()
713 dib7000m_write_word(state, 102, agc->wbd_ref); dib7000m_set_agc_config()
715 dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) ); dib7000m_set_agc_config()
716 dib7000m_write_word(state, 104, agc->agc1_max); dib7000m_set_agc_config()
717 dib7000m_write_word(state, 105, agc->agc1_min); dib7000m_set_agc_config()
718 dib7000m_write_word(state, 106, agc->agc2_max); dib7000m_set_agc_config()
719 dib7000m_write_word(state, 107, agc->agc2_min); dib7000m_set_agc_config()
720 dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 ); dib7000m_set_agc_config()
721 dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2); dib7000m_set_agc_config()
722 dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2); dib7000m_set_agc_config()
723 dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2); dib7000m_set_agc_config()
725 if (state->revision > 0x4000) { // settings for the MC dib7000m_set_agc_config()
726 dib7000m_write_word(state, 71, agc->agc1_pt3); dib7000m_set_agc_config()
728 // (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel); dib7000m_set_agc_config()
729 dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2)); dib7000m_set_agc_config()
734 dib7000m_write_word(state, 88 + i, b[i]); dib7000m_set_agc_config()
739 static void dib7000m_update_timf(struct dib7000m_state *state) dib7000m_update_timf() argument
741 u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437); dib7000m_update_timf()
742 state->timf = timf * 160 / (state->current_bandwidth / 50); dib7000m_update_timf()
743 dib7000m_write_word(state, 23, (u16) (timf >> 16)); dib7000m_update_timf()
744 dib7000m_write_word(state, 24, (u16) (timf & 0xffff)); dib7000m_update_timf()
745 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->timf_default); dib7000m_update_timf()
751 struct dib7000m_state *state = demod->demodulator_priv; dib7000m_agc_startup() local
752 u16 cfg_72 = dib7000m_read_word(state, 72); dib7000m_agc_startup()
754 u8 *agc_state = &state->agc_state; dib7000m_agc_startup()
757 switch (state->agc_state) { dib7000m_agc_startup()
760 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC); dib7000m_agc_startup()
761 dib7000m_set_adc_state(state, DIBX000_ADC_ON); dib7000m_agc_startup()
763 if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0) dib7000m_agc_startup()
772 if (state->cfg.agc_control) dib7000m_agc_startup()
773 state->cfg.agc_control(&state->demod, 1); dib7000m_agc_startup()
775 dib7000m_write_word(state, 75, 32768); dib7000m_agc_startup()
776 if (!state->current_agc->perform_agc_softsplit) { dib7000m_agc_startup()
778 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */ dib7000m_agc_startup()
788 dib7000m_restart_agc(state); dib7000m_agc_startup()
792 dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */ dib7000m_agc_startup()
793 dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */ dib7000m_agc_startup()
799 agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */ dib7000m_agc_startup()
800 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */ dib7000m_agc_startup()
802 dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */ dib7000m_agc_startup()
803 dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */ dib7000m_agc_startup()
805 dib7000m_restart_agc(state); dib7000m_agc_startup()
817 if (dib7000m_update_lna(state)) dib7000m_agc_startup()
825 dib7000m_agc_soft_split(state); dib7000m_agc_startup()
827 if (state->cfg.agc_control) dib7000m_agc_startup()
828 state->cfg.agc_control(&state->demod, 0); dib7000m_agc_startup()
839 static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch, dib7000m_set_channel() argument
844 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); dib7000m_set_channel()
873 dib7000m_write_word(state, 0, value); dib7000m_set_channel()
874 dib7000m_write_word(state, 5, (seq << 4)); dib7000m_set_channel()
892 dib7000m_write_word(state, 267 + state->reg_offs, value); dib7000m_set_channel()
897 dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80); dib7000m_set_channel()
900 dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3)); dib7000m_set_channel()
903 dib7000m_write_word(state, 32, (0 << 4) | 0x3); dib7000m_set_channel()
906 dib7000m_write_word(state, 33, (0 << 4) | 0x5); dib7000m_set_channel()
922 state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo TODO dib7000m_set_channel()
926 if (1 == 1 || state->revision > 0x4000) dib7000m_set_channel()
927 state->div_force_off = 0; dib7000m_set_channel()
929 state->div_force_off = 1; dib7000m_set_channel()
930 dib7000m_set_diversity_in(&state->demod, state->div_state); dib7000m_set_channel()
954 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]); dib7000m_set_channel()
957 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD); dib7000m_set_channel()
963 struct dib7000m_state *state = demod->demodulator_priv; dib7000m_autosearch_start() local
977 dib7000m_set_channel(state, &schan, 7); dib7000m_autosearch_start()
986 value = 30 * state->internal_clk * factor; dib7000m_autosearch_start()
987 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time dib7000m_autosearch_start()
988 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time dib7000m_autosearch_start()
989 value = 100 * state->internal_clk * factor; dib7000m_autosearch_start()
990 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time dib7000m_autosearch_start()
991 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time dib7000m_autosearch_start()
992 value = 500 * state->internal_clk * factor; dib7000m_autosearch_start()
993 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time dib7000m_autosearch_start()
994 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time dib7000m_autosearch_start()
997 value = dib7000m_read_word(state, 0); dib7000m_autosearch_start()
998 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9))); dib7000m_autosearch_start()
1001 if (state->revision == 0x4000) dib7000m_autosearch_start()
1002 dib7000m_write_word(state, 1793, 0); dib7000m_autosearch_start()
1004 dib7000m_read_word(state, 537); dib7000m_autosearch_start()
1006 ret |= dib7000m_write_word(state, 0, (u16) value); dib7000m_autosearch_start()
1011 static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg) dib7000m_autosearch_irq() argument
1013 u16 irq_pending = dib7000m_read_word(state, reg); dib7000m_autosearch_irq()
1029 struct dib7000m_state *state = demod->demodulator_priv; dib7000m_autosearch_is_irq() local
1030 if (state->revision == 0x4000) dib7000m_autosearch_is_irq()
1031 return dib7000m_autosearch_irq(state, 1793); dib7000m_autosearch_is_irq()
1033 return dib7000m_autosearch_irq(state, 537); dib7000m_autosearch_is_irq()
1039 struct dib7000m_state *state = demod->demodulator_priv; dib7000m_tune() local
1044 dib7000m_set_channel(state, ch, 0); dib7000m_tune()
1047 ret |= dib7000m_write_word(state, 898, 0x4000); dib7000m_tune()
1048 ret |= dib7000m_write_word(state, 898, 0x0000); dib7000m_tune()
1051 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD); dib7000m_tune()
1053 ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3)); dib7000m_tune()
1056 if (state->timf == 0) dib7000m_tune()
1059 //dump_reg(state); dib7000m_tune()
1068 ret |= dib7000m_write_word(state, 26, value); dib7000m_tune()
1078 ret |= dib7000m_write_word(state, 32, value); dib7000m_tune()
1088 ret |= dib7000m_write_word(state, 33, value); dib7000m_tune()
1091 if ((dib7000m_read_word(state, 535) >> 6) & 0x1) dib7000m_tune()
1092 dib7000m_update_timf(state); dib7000m_tune()
1094 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); dib7000m_tune()
1100 struct dib7000m_state *state = demod->demodulator_priv; dib7000m_wakeup() local
1102 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); dib7000m_wakeup()
1104 if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) dib7000m_wakeup()
1119 static int dib7000m_identify(struct dib7000m_state *state) dib7000m_identify() argument
1123 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) { dib7000m_identify()
1128 state->revision = dib7000m_read_word(state, 897); dib7000m_identify()
1129 if (state->revision != 0x4000 && dib7000m_identify()
1130 state->revision != 0x4001 && dib7000m_identify()
1131 state->revision != 0x4002 && dib7000m_identify()
1132 state->revision != 0x4003) { dib7000m_identify()
1138 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) { dib7000m_identify()
1143 switch (state->revision) { dib7000m_identify()
1145 case 0x4001: state->reg_offs = 1; dprintk( "found DiB7000HC"); break; dib7000m_identify()
1146 case 0x4002: state->reg_offs = 1; dprintk( "found DiB7000MC"); break; dib7000m_identify()
1147 case 0x4003: state->reg_offs = 1; dprintk( "found DiB9000"); break; dib7000m_identify()
1157 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_get_frontend() local
1158 u16 tps = dib7000m_read_word(state,480); dib7000m_get_frontend()
1162 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth); dib7000m_get_frontend()
1207 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */ dib7000m_get_frontend()
1215 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_set_frontend() local
1218 dib7000m_set_output_mode(state, OUTMODE_HIGH_Z); dib7000m_set_frontend()
1220 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz)); dib7000m_set_frontend()
1226 state->agc_state = 0; dib7000m_set_frontend()
1255 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO); dib7000m_set_frontend()
1261 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_read_status() local
1262 u16 lock = dib7000m_read_word(state, 535); dib7000m_read_status()
1282 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_read_ber() local
1283 *ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527); dib7000m_read_ber()
1289 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_read_unc_blocks() local
1290 *unc = dib7000m_read_word(state, 534); dib7000m_read_unc_blocks()
1296 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_read_signal_strength() local
1297 u16 val = dib7000m_read_word(state, 390); dib7000m_read_signal_strength()
1330 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_pid_filter_ctrl() local
1331 u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef; dib7000m_pid_filter_ctrl()
1334 return dib7000m_write_word(state, 294 + state->reg_offs, val); dib7000m_pid_filter_ctrl()
1340 struct dib7000m_state *state = fe->demodulator_priv; dib7000m_pid_filter() local
1342 return dib7000m_write_word(state, 300 + state->reg_offs + id, dib7000m_pid_filter()
H A Ddrxk_hard.c41 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
42 static int power_down_qam(struct drxk_state *state);
43 static int set_dvbt_standard(struct drxk_state *state,
45 static int set_qam_standard(struct drxk_state *state,
47 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
49 static int set_dvbt_standard(struct drxk_state *state,
51 static int dvbt_start(struct drxk_state *state);
52 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
54 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
55 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
56 static int switch_antenna_to_qam(struct drxk_state *state);
57 static int switch_antenna_to_dvbt(struct drxk_state *state);
59 static bool is_dvbt(struct drxk_state *state) is_dvbt() argument
61 return state->m_operation_mode == OM_DVBT; is_dvbt()
64 static bool is_qam(struct drxk_state *state) is_qam() argument
66 return state->m_operation_mode == OM_QAM_ITU_A || is_qam()
67 state->m_operation_mode == OM_QAM_ITU_B || is_qam()
68 state->m_operation_mode == OM_QAM_ITU_C; is_qam()
110 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
113 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
116 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
218 static int drxk_i2c_lock(struct drxk_state *state) drxk_i2c_lock() argument
220 i2c_lock_adapter(state->i2c); drxk_i2c_lock()
221 state->drxk_i2c_exclusive_lock = true; drxk_i2c_lock()
226 static void drxk_i2c_unlock(struct drxk_state *state) drxk_i2c_unlock() argument
228 if (!state->drxk_i2c_exclusive_lock) drxk_i2c_unlock()
231 i2c_unlock_adapter(state->i2c); drxk_i2c_unlock()
232 state->drxk_i2c_exclusive_lock = false; drxk_i2c_unlock()
235 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, drxk_i2c_transfer() argument
238 if (state->drxk_i2c_exclusive_lock) drxk_i2c_transfer()
239 return __i2c_transfer(state->i2c, msgs, len); drxk_i2c_transfer()
241 return i2c_transfer(state->i2c, msgs, len); drxk_i2c_transfer()
244 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) i2c_read1() argument
250 return drxk_i2c_transfer(state, msgs, 1); i2c_read1()
253 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) i2c_write() argument
266 status = drxk_i2c_transfer(state, &msg, 1); i2c_write()
276 static int i2c_read(struct drxk_state *state, i2c_read() argument
287 status = drxk_i2c_transfer(state, msgs, 2); i2c_read()
310 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) read16_flags() argument
313 u8 adr = state->demod_address, mm1[4], mm2[2], len; read16_flags()
315 if (state->single_master) read16_flags()
330 status = i2c_read(state, adr, mm1, len, mm2, 2); read16_flags()
339 static int read16(struct drxk_state *state, u32 reg, u16 *data) read16() argument
341 return read16_flags(state, reg, data, 0); read16()
344 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) read32_flags() argument
347 u8 adr = state->demod_address, mm1[4], mm2[4], len; read32_flags()
349 if (state->single_master) read32_flags()
364 status = i2c_read(state, adr, mm1, len, mm2, 4); read32_flags()
374 static int read32(struct drxk_state *state, u32 reg, u32 *data) read32() argument
376 return read32_flags(state, reg, data, 0); read32()
379 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) write16_flags() argument
381 u8 adr = state->demod_address, mm[6], len; write16_flags()
383 if (state->single_master) write16_flags()
400 return i2c_write(state, adr, mm, len + 2); write16_flags()
403 static int write16(struct drxk_state *state, u32 reg, u16 data) write16() argument
405 return write16_flags(state, reg, data, 0); write16()
408 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) write32_flags() argument
410 u8 adr = state->demod_address, mm[8], len; write32_flags()
412 if (state->single_master) write32_flags()
431 return i2c_write(state, adr, mm, len + 4); write32_flags()
434 static int write32(struct drxk_state *state, u32 reg, u32 data) write32() argument
436 return write32_flags(state, reg, data, 0); write32()
439 static int write_block(struct drxk_state *state, u32 address, write_block() argument
445 if (state->single_master) write_block()
449 int chunk = blk_size > state->m_chunk_size ? write_block()
450 state->m_chunk_size : blk_size; write_block()
451 u8 *adr_buf = &state->chunk[0]; write_block()
461 if (chunk == state->m_chunk_size) write_block()
469 memcpy(&state->chunk[adr_length], p_block, chunk); write_block()
478 status = i2c_write(state, state->demod_address, write_block()
479 &state->chunk[0], chunk + adr_length); write_block()
496 static int power_up_device(struct drxk_state *state) power_up_device() argument
504 status = i2c_read1(state, state->demod_address, &data); power_up_device()
508 status = i2c_write(state, state->demod_address, power_up_device()
514 status = i2c_read1(state, state->demod_address, power_up_device()
523 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); power_up_device()
526 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); power_up_device()
530 status = write16(state, SIO_CC_PLL_LOCK__A, 1); power_up_device()
534 state->m_current_power_mode = DRX_POWER_UP; power_up_device()
544 static int init_state(struct drxk_state *state) init_state() argument
600 state->m_has_lna = false; init_state()
601 state->m_has_dvbt = false; init_state()
602 state->m_has_dvbc = false; init_state()
603 state->m_has_atv = false; init_state()
604 state->m_has_oob = false; init_state()
605 state->m_has_audio = false; init_state()
607 if (!state->m_chunk_size) init_state()
608 state->m_chunk_size = 124; init_state()
610 state->m_osc_clock_freq = 0; init_state()
611 state->m_smart_ant_inverted = false; init_state()
612 state->m_b_p_down_open_bridge = false; init_state()
615 state->m_sys_clock_freq = 151875; init_state()
618 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * init_state()
621 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) init_state()
622 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; init_state()
623 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); init_state()
625 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; init_state()
627 state->m_b_power_down = (ul_power_down != 0); init_state()
629 state->m_drxk_a3_patch_code = false; init_state()
633 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; init_state()
634 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; init_state()
635 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; init_state()
636 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; init_state()
637 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; init_state()
638 state->m_vsb_pga_cfg = 140; init_state()
641 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; init_state()
642 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; init_state()
643 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; init_state()
644 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; init_state()
645 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; init_state()
646 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; init_state()
647 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; init_state()
648 state->m_vsb_pre_saw_cfg.reference = 0x07; init_state()
649 state->m_vsb_pre_saw_cfg.use_pre_saw = true; init_state()
651 state->m_Quality83percent = DEFAULT_MER_83; init_state()
652 state->m_Quality93percent = DEFAULT_MER_93; init_state()
654 state->m_Quality83percent = ulQual83; init_state()
655 state->m_Quality93percent = ulQual93; init_state()
659 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; init_state()
660 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; init_state()
661 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; init_state()
662 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; init_state()
663 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; init_state()
666 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; init_state()
667 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; init_state()
668 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; init_state()
669 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; init_state()
670 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; init_state()
671 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; init_state()
672 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; init_state()
673 state->m_atv_pre_saw_cfg.reference = 0x04; init_state()
674 state->m_atv_pre_saw_cfg.use_pre_saw = true; init_state()
678 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; init_state()
679 state->m_dvbt_rf_agc_cfg.output_level = 0; init_state()
680 state->m_dvbt_rf_agc_cfg.min_output_level = 0; init_state()
681 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; init_state()
682 state->m_dvbt_rf_agc_cfg.top = 0x2100; init_state()
683 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; init_state()
684 state->m_dvbt_rf_agc_cfg.speed = 1; init_state()
688 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; init_state()
689 state->m_dvbt_if_agc_cfg.output_level = 0; init_state()
690 state->m_dvbt_if_agc_cfg.min_output_level = 0; init_state()
691 state->m_dvbt_if_agc_cfg.max_output_level = 9000; init_state()
692 state->m_dvbt_if_agc_cfg.top = 13424; init_state()
693 state->m_dvbt_if_agc_cfg.cut_off_current = 0; init_state()
694 state->m_dvbt_if_agc_cfg.speed = 3; init_state()
695 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; init_state()
696 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; init_state()
697 /* state->m_dvbtPgaCfg = 140; */ init_state()
699 state->m_dvbt_pre_saw_cfg.reference = 4; init_state()
700 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; init_state()
703 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; init_state()
704 state->m_qam_rf_agc_cfg.output_level = 0; init_state()
705 state->m_qam_rf_agc_cfg.min_output_level = 6023; init_state()
706 state->m_qam_rf_agc_cfg.max_output_level = 27000; init_state()
707 state->m_qam_rf_agc_cfg.top = 0x2380; init_state()
708 state->m_qam_rf_agc_cfg.cut_off_current = 4000; init_state()
709 state->m_qam_rf_agc_cfg.speed = 3; init_state()
712 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; init_state()
713 state->m_qam_if_agc_cfg.output_level = 0; init_state()
714 state->m_qam_if_agc_cfg.min_output_level = 0; init_state()
715 state->m_qam_if_agc_cfg.max_output_level = 9000; init_state()
716 state->m_qam_if_agc_cfg.top = 0x0511; init_state()
717 state->m_qam_if_agc_cfg.cut_off_current = 0; init_state()
718 state->m_qam_if_agc_cfg.speed = 3; init_state()
719 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; init_state()
720 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; init_state()
722 state->m_qam_pga_cfg = 140; init_state()
723 state->m_qam_pre_saw_cfg.reference = 4; init_state()
724 state->m_qam_pre_saw_cfg.use_pre_saw = false; init_state()
726 state->m_operation_mode = OM_NONE; init_state()
727 state->m_drxk_state = DRXK_UNINITIALIZED; init_state()
730 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG ouput */ init_state()
731 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ init_state()
732 state->m_invert_data = false; /* If TRUE; invert DATA signals */ init_state()
733 state->m_invert_err = false; /* If TRUE; invert ERR signal */ init_state()
734 state->m_invert_str = false; /* If TRUE; invert STR signals */ init_state()
735 state->m_invert_val = false; /* If TRUE; invert VAL signals */ init_state()
736 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ init_state()
741 state->m_dvbt_bitrate = ul_dvbt_bitrate; init_state()
742 state->m_dvbc_bitrate = ul_dvbc_bitrate; init_state()
744 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); init_state()
747 state->m_mpeg_ts_static_bitrate = 19392658; init_state()
748 state->m_disable_te_ihandling = false; init_state()
751 state->m_insert_rs_byte = true; init_state()
753 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; init_state()
755 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; init_state()
756 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; init_state()
758 state->m_demod_lock_time_out = ul_demod_lock_time_out; init_state()
761 state->m_constellation = DRX_CONSTELLATION_AUTO; init_state()
762 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; init_state()
763 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ init_state()
764 state->m_fec_rs_prescale = 1; init_state()
766 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; init_state()
767 state->m_agcfast_clip_ctrl_delay = 0; init_state()
769 state->m_gpio_cfg = ul_gpio_cfg; init_state()
771 state->m_b_power_down = false; init_state()
772 state->m_current_power_mode = DRX_POWER_DOWN; init_state()
774 state->m_rfmirror = (ul_rf_mirror == 0); init_state()
775 state->m_if_agc_pol = false; init_state()
779 static int drxx_open(struct drxk_state *state) drxx_open() argument
788 status = write16(state, SCU_RAM_GPIO__A, drxx_open()
793 status = read16(state, SIO_TOP_COMM_KEY__A, &key); drxx_open()
796 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); drxx_open()
799 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); drxx_open()
802 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); drxx_open()
805 status = write16(state, SIO_TOP_COMM_KEY__A, key); drxx_open()
812 static int get_device_capabilities(struct drxk_state *state) get_device_capabilities() argument
823 status = write16(state, SCU_RAM_GPIO__A, get_device_capabilities()
827 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); get_device_capabilities()
830 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); get_device_capabilities()
833 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); get_device_capabilities()
843 state->m_osc_clock_freq = 27000; get_device_capabilities()
847 state->m_osc_clock_freq = 20250; get_device_capabilities()
851 state->m_osc_clock_freq = 20250; get_device_capabilities()
861 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); get_device_capabilities()
870 state->m_device_spin = DRXK_SPIN_A1; get_device_capabilities()
874 state->m_device_spin = DRXK_SPIN_A2; get_device_capabilities()
878 state->m_device_spin = DRXK_SPIN_A3; get_device_capabilities()
882 state->m_device_spin = DRXK_SPIN_UNKNOWN; get_device_capabilities()
890 state->m_has_lna = false; get_device_capabilities()
891 state->m_has_oob = false; get_device_capabilities()
892 state->m_has_atv = false; get_device_capabilities()
893 state->m_has_audio = false; get_device_capabilities()
894 state->m_has_dvbt = true; get_device_capabilities()
895 state->m_has_dvbc = true; get_device_capabilities()
896 state->m_has_sawsw = true; get_device_capabilities()
897 state->m_has_gpio2 = false; get_device_capabilities()
898 state->m_has_gpio1 = false; get_device_capabilities()
899 state->m_has_irqn = false; get_device_capabilities()
903 state->m_has_lna = false; get_device_capabilities()
904 state->m_has_oob = false; get_device_capabilities()
905 state->m_has_atv = true; get_device_capabilities()
906 state->m_has_audio = false; get_device_capabilities()
907 state->m_has_dvbt = true; get_device_capabilities()
908 state->m_has_dvbc = false; get_device_capabilities()
909 state->m_has_sawsw = true; get_device_capabilities()
910 state->m_has_gpio2 = true; get_device_capabilities()
911 state->m_has_gpio1 = true; get_device_capabilities()
912 state->m_has_irqn = false; get_device_capabilities()
916 state->m_has_lna = false; get_device_capabilities()
917 state->m_has_oob = false; get_device_capabilities()
918 state->m_has_atv = true; get_device_capabilities()
919 state->m_has_audio = false; get_device_capabilities()
920 state->m_has_dvbt = true; get_device_capabilities()
921 state->m_has_dvbc = false; get_device_capabilities()
922 state->m_has_sawsw = true; get_device_capabilities()
923 state->m_has_gpio2 = true; get_device_capabilities()
924 state->m_has_gpio1 = true; get_device_capabilities()
925 state->m_has_irqn = false; get_device_capabilities()
929 state->m_has_lna = false; get_device_capabilities()
930 state->m_has_oob = false; get_device_capabilities()
931 state->m_has_atv = true; get_device_capabilities()
932 state->m_has_audio = true; get_device_capabilities()
933 state->m_has_dvbt = true; get_device_capabilities()
934 state->m_has_dvbc = false; get_device_capabilities()
935 state->m_has_sawsw = true; get_device_capabilities()
936 state->m_has_gpio2 = true; get_device_capabilities()
937 state->m_has_gpio1 = true; get_device_capabilities()
938 state->m_has_irqn = false; get_device_capabilities()
942 state->m_has_lna = false; get_device_capabilities()
943 state->m_has_oob = false; get_device_capabilities()
944 state->m_has_atv = true; get_device_capabilities()
945 state->m_has_audio = true; get_device_capabilities()
946 state->m_has_dvbt = true; get_device_capabilities()
947 state->m_has_dvbc = true; get_device_capabilities()
948 state->m_has_sawsw = true; get_device_capabilities()
949 state->m_has_gpio2 = true; get_device_capabilities()
950 state->m_has_gpio1 = true; get_device_capabilities()
951 state->m_has_irqn = false; get_device_capabilities()
955 state->m_has_lna = false; get_device_capabilities()
956 state->m_has_oob = false; get_device_capabilities()
957 state->m_has_atv = true; get_device_capabilities()
958 state->m_has_audio = true; get_device_capabilities()
959 state->m_has_dvbt = true; get_device_capabilities()
960 state->m_has_dvbc = true; get_device_capabilities()
961 state->m_has_sawsw = true; get_device_capabilities()
962 state->m_has_gpio2 = true; get_device_capabilities()
963 state->m_has_gpio1 = true; get_device_capabilities()
964 state->m_has_irqn = false; get_device_capabilities()
968 state->m_has_lna = false; get_device_capabilities()
969 state->m_has_oob = false; get_device_capabilities()
970 state->m_has_atv = true; get_device_capabilities()
971 state->m_has_audio = true; get_device_capabilities()
972 state->m_has_dvbt = true; get_device_capabilities()
973 state->m_has_dvbc = true; get_device_capabilities()
974 state->m_has_sawsw = true; get_device_capabilities()
975 state->m_has_gpio2 = true; get_device_capabilities()
976 state->m_has_gpio1 = true; get_device_capabilities()
977 state->m_has_irqn = false; get_device_capabilities()
981 state->m_has_lna = false; get_device_capabilities()
982 state->m_has_oob = false; get_device_capabilities()
983 state->m_has_atv = true; get_device_capabilities()
984 state->m_has_audio = false; get_device_capabilities()
985 state->m_has_dvbt = true; get_device_capabilities()
986 state->m_has_dvbc = true; get_device_capabilities()
987 state->m_has_sawsw = true; get_device_capabilities()
988 state->m_has_gpio2 = true; get_device_capabilities()
989 state->m_has_gpio1 = true; get_device_capabilities()
990 state->m_has_irqn = false; get_device_capabilities()
1001 state->m_osc_clock_freq / 1000, get_device_capabilities()
1002 state->m_osc_clock_freq % 1000); get_device_capabilities()
1012 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) hi_command() argument
1020 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); hi_command()
1028 ((state->m_hi_cfg_ctrl) & hi_command()
1039 status = read16(state, SIO_HI_RA_RAM_CMD__A, hi_command()
1045 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); hi_command()
1054 static int hi_cfg_command(struct drxk_state *state) hi_cfg_command() argument
1060 mutex_lock(&state->mutex); hi_cfg_command()
1062 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, hi_cfg_command()
1063 state->m_hi_cfg_timeout); hi_cfg_command()
1066 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, hi_cfg_command()
1067 state->m_hi_cfg_ctrl); hi_cfg_command()
1070 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, hi_cfg_command()
1071 state->m_hi_cfg_wake_up_key); hi_cfg_command()
1074 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, hi_cfg_command()
1075 state->m_hi_cfg_bridge_delay); hi_cfg_command()
1078 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, hi_cfg_command()
1079 state->m_hi_cfg_timing_div); hi_cfg_command()
1082 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, hi_cfg_command()
1086 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); hi_cfg_command()
1090 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; hi_cfg_command()
1092 mutex_unlock(&state->mutex); hi_cfg_command()
1098 static int init_hi(struct drxk_state *state) init_hi() argument
1102 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); init_hi()
1103 state->m_hi_cfg_timeout = 0x96FF; init_hi()
1105 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; init_hi()
1107 return hi_cfg_command(state); init_hi()
1110 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) mpegts_configure_pins() argument
1119 state->m_enable_parallel ? "parallel" : "serial"); mpegts_configure_pins()
1122 status = write16(state, SCU_RAM_GPIO__A, mpegts_configure_pins()
1128 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); mpegts_configure_pins()
1134 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); mpegts_configure_pins()
1137 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); mpegts_configure_pins()
1140 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); mpegts_configure_pins()
1143 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); mpegts_configure_pins()
1146 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); mpegts_configure_pins()
1149 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); mpegts_configure_pins()
1152 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); mpegts_configure_pins()
1155 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); mpegts_configure_pins()
1158 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); mpegts_configure_pins()
1161 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); mpegts_configure_pins()
1164 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); mpegts_configure_pins()
1167 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); mpegts_configure_pins()
1173 ((state->m_ts_data_strength << mpegts_configure_pins()
1175 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << mpegts_configure_pins()
1179 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); mpegts_configure_pins()
1183 if (state->enable_merr_cfg) mpegts_configure_pins()
1186 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); mpegts_configure_pins()
1189 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); mpegts_configure_pins()
1193 if (state->m_enable_parallel) { mpegts_configure_pins()
1195 status = write16(state, SIO_PDR_MD1_CFG__A, mpegts_configure_pins()
1199 status = write16(state, SIO_PDR_MD2_CFG__A, mpegts_configure_pins()
1203 status = write16(state, SIO_PDR_MD3_CFG__A, mpegts_configure_pins()
1207 status = write16(state, SIO_PDR_MD4_CFG__A, mpegts_configure_pins()
1211 status = write16(state, SIO_PDR_MD5_CFG__A, mpegts_configure_pins()
1215 status = write16(state, SIO_PDR_MD6_CFG__A, mpegts_configure_pins()
1219 status = write16(state, SIO_PDR_MD7_CFG__A, mpegts_configure_pins()
1224 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << mpegts_configure_pins()
1228 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); mpegts_configure_pins()
1231 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); mpegts_configure_pins()
1234 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); mpegts_configure_pins()
1237 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); mpegts_configure_pins()
1240 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); mpegts_configure_pins()
1243 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); mpegts_configure_pins()
1246 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); mpegts_configure_pins()
1250 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); mpegts_configure_pins()
1253 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); mpegts_configure_pins()
1258 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); mpegts_configure_pins()
1262 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); mpegts_configure_pins()
1269 static int mpegts_disable(struct drxk_state *state) mpegts_disable() argument
1273 return mpegts_configure_pins(state, false); mpegts_disable()
1276 static int bl_chain_cmd(struct drxk_state *state, bl_chain_cmd() argument
1284 mutex_lock(&state->mutex); bl_chain_cmd()
1285 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); bl_chain_cmd()
1288 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); bl_chain_cmd()
1291 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); bl_chain_cmd()
1294 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); bl_chain_cmd()
1301 status = read16(state, SIO_BL_STATUS__A, &bl_status); bl_chain_cmd()
1316 mutex_unlock(&state->mutex); bl_chain_cmd()
1321 static int download_microcode(struct drxk_state *state, download_microcode() argument
1374 status = write_block(state, address, block_size, p_src); download_microcode()
1385 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) dvbt_enable_ofdm_token_ring() argument
1400 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); dvbt_enable_ofdm_token_ring()
1406 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); dvbt_enable_ofdm_token_ring()
1410 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); dvbt_enable_ofdm_token_ring()
1423 static int mpegts_stop(struct drxk_state *state) mpegts_stop() argument
1432 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); mpegts_stop()
1436 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); mpegts_stop()
1441 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); mpegts_stop()
1445 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); mpegts_stop()
1454 static int scu_command(struct drxk_state *state, scu_command() argument
1477 mutex_lock(&state->mutex); scu_command()
1488 write_block(state, SCU_RAM_PARAM_0__A - scu_command()
1494 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); scu_command()
1509 status = read16(state, SCU_RAM_PARAM_0__A - ii, scu_command()
1548 mutex_unlock(&state->mutex); scu_command()
1552 static int set_iqm_af(struct drxk_state *state, bool active) set_iqm_af() argument
1560 status = read16(state, IQM_AF_STDBY__A, &data); set_iqm_af()
1578 status = write16(state, IQM_AF_STDBY__A, data); set_iqm_af()
1586 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) ctrl_power_mode() argument
1619 if (state->m_current_power_mode == *mode) ctrl_power_mode()
1623 if (state->m_current_power_mode != DRX_POWER_UP) { ctrl_power_mode()
1624 status = power_up_device(state); ctrl_power_mode()
1627 status = dvbt_enable_ofdm_token_ring(state, true); ctrl_power_mode()
1644 switch (state->m_operation_mode) { ctrl_power_mode()
1646 status = mpegts_stop(state); ctrl_power_mode()
1649 status = power_down_dvbt(state, false); ctrl_power_mode()
1655 status = mpegts_stop(state); ctrl_power_mode()
1658 status = power_down_qam(state); ctrl_power_mode()
1665 status = dvbt_enable_ofdm_token_ring(state, false); ctrl_power_mode()
1668 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); ctrl_power_mode()
1671 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); ctrl_power_mode()
1676 state->m_hi_cfg_ctrl |= ctrl_power_mode()
1678 status = hi_cfg_command(state); ctrl_power_mode()
1683 state->m_current_power_mode = *mode; ctrl_power_mode()
1692 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) power_down_dvbt() argument
1701 status = read16(state, SCU_COMM_EXEC__A, &data); power_down_dvbt()
1706 status = scu_command(state, power_down_dvbt()
1713 status = scu_command(state, power_down_dvbt()
1722 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); power_down_dvbt()
1725 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); power_down_dvbt()
1728 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); power_down_dvbt()
1733 status = set_iqm_af(state, false); power_down_dvbt()
1739 status = ctrl_power_mode(state, &power_mode); power_down_dvbt()
1749 static int setoperation_mode(struct drxk_state *state, setoperation_mode() argument
1762 status = write16(state, SCU_RAM_GPIO__A, setoperation_mode()
1768 if (state->m_operation_mode == o_mode) setoperation_mode()
1771 switch (state->m_operation_mode) { setoperation_mode()
1776 status = mpegts_stop(state); setoperation_mode()
1779 status = power_down_dvbt(state, true); setoperation_mode()
1782 state->m_operation_mode = OM_NONE; setoperation_mode()
1786 status = mpegts_stop(state); setoperation_mode()
1789 status = power_down_qam(state); setoperation_mode()
1792 state->m_operation_mode = OM_NONE; setoperation_mode()
1806 state->m_operation_mode = o_mode; setoperation_mode()
1807 status = set_dvbt_standard(state, o_mode); setoperation_mode()
1814 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); setoperation_mode()
1815 state->m_operation_mode = o_mode; setoperation_mode()
1816 status = set_qam_standard(state, o_mode); setoperation_mode()
1830 static int start(struct drxk_state *state, s32 offset_freq, start() argument
1839 if (state->m_drxk_state != DRXK_STOPPED && start()
1840 state->m_drxk_state != DRXK_DTV_STARTED) start()
1843 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); start()
1846 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; start()
1850 switch (state->m_operation_mode) { start()
1854 status = set_qam(state, i_freqk_hz, offsetk_hz); start()
1857 state->m_drxk_state = DRXK_DTV_STARTED; start()
1861 status = mpegts_stop(state); start()
1864 status = set_dvbt(state, i_freqk_hz, offsetk_hz); start()
1867 status = dvbt_start(state); start()
1870 state->m_drxk_state = DRXK_DTV_STARTED; start()
1881 static int shut_down(struct drxk_state *state) shut_down() argument
1885 mpegts_stop(state); shut_down()
1889 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) get_lock_status() argument
1901 switch (state->m_operation_mode) { get_lock_status()
1905 status = get_qam_lock_status(state, p_lock_status); get_lock_status()
1908 status = get_dvbt_lock_status(state, p_lock_status); get_lock_status()
1919 static int mpegts_start(struct drxk_state *state) mpegts_start() argument
1926 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); mpegts_start()
1930 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); mpegts_start()
1933 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); mpegts_start()
1940 static int mpegts_dto_init(struct drxk_state *state) mpegts_dto_init() argument
1947 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); mpegts_dto_init()
1950 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); mpegts_dto_init()
1953 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); mpegts_dto_init()
1956 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); mpegts_dto_init()
1959 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); mpegts_dto_init()
1962 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); mpegts_dto_init()
1965 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); mpegts_dto_init()
1968 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); mpegts_dto_init()
1973 status = write16(state, FEC_OC_OCR_INVERT__A, 0); mpegts_dto_init()
1976 status = write16(state, FEC_OC_SNC_LWM__A, 2); mpegts_dto_init()
1979 status = write16(state, FEC_OC_SNC_HWM__A, 12); mpegts_dto_init()
1987 static int mpegts_dto_setup(struct drxk_state *state, mpegts_dto_setup() argument
2007 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); mpegts_dto_setup()
2010 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); mpegts_dto_setup()
2015 if (state->m_insert_rs_byte) { mpegts_dto_setup()
2026 if (!state->m_enable_parallel) { mpegts_dto_setup()
2033 max_bit_rate = state->m_dvbt_bitrate; mpegts_dto_setup()
2036 static_clk = state->m_dvbt_static_clk; mpegts_dto_setup()
2042 max_bit_rate = state->m_dvbc_bitrate; mpegts_dto_setup()
2043 static_clk = state->m_dvbc_static_clk; mpegts_dto_setup()
2075 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) mpegts_dto_setup()
2090 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); mpegts_dto_setup()
2093 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); mpegts_dto_setup()
2096 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); mpegts_dto_setup()
2099 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); mpegts_dto_setup()
2102 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); mpegts_dto_setup()
2105 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); mpegts_dto_setup()
2110 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); mpegts_dto_setup()
2113 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, mpegts_dto_setup()
2117 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); mpegts_dto_setup()
2124 static int mpegts_configure_polarity(struct drxk_state *state) mpegts_configure_polarity() argument
2139 if (state->m_invert_data) mpegts_configure_polarity()
2142 if (state->m_invert_err) mpegts_configure_polarity()
2145 if (state->m_invert_str) mpegts_configure_polarity()
2148 if (state->m_invert_val) mpegts_configure_polarity()
2151 if (state->m_invert_clk) mpegts_configure_polarity()
2154 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); mpegts_configure_polarity()
2159 static int set_agc_rf(struct drxk_state *state, set_agc_rf() argument
2174 status = read16(state, IQM_AF_STDBY__A, &data); set_agc_rf()
2178 status = write16(state, IQM_AF_STDBY__A, data); set_agc_rf()
2181 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); set_agc_rf()
2189 if (state->m_rf_agc_pol) set_agc_rf()
2193 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); set_agc_rf()
2198 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); set_agc_rf()
2207 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); set_agc_rf()
2211 if (is_dvbt(state)) set_agc_rf()
2212 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; set_agc_rf()
2213 else if (is_qam(state)) set_agc_rf()
2214 p_if_agc_settings = &state->m_qam_if_agc_cfg; set_agc_rf()
2216 p_if_agc_settings = &state->m_atv_if_agc_cfg; set_agc_rf()
2224 status = write16(state, set_agc_rf()
2232 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, set_agc_rf()
2238 status = write16(state, SCU_RAM_AGC_RF_MAX__A, set_agc_rf()
2247 status = read16(state, IQM_AF_STDBY__A, &data); set_agc_rf()
2251 status = write16(state, IQM_AF_STDBY__A, data); set_agc_rf()
2256 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); set_agc_rf()
2260 if (state->m_rf_agc_pol) set_agc_rf()
2264 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); set_agc_rf()
2269 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); set_agc_rf()
2274 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, set_agc_rf()
2282 status = read16(state, IQM_AF_STDBY__A, &data); set_agc_rf()
2286 status = write16(state, IQM_AF_STDBY__A, data); set_agc_rf()
2291 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); set_agc_rf()
2295 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); set_agc_rf()
2312 static int set_agc_if(struct drxk_state *state, set_agc_if() argument
2325 status = read16(state, IQM_AF_STDBY__A, &data); set_agc_if()
2329 status = write16(state, IQM_AF_STDBY__A, data); set_agc_if()
2333 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); set_agc_if()
2341 if (state->m_if_agc_pol) set_agc_if()
2345 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); set_agc_if()
2350 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); set_agc_if()
2358 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); set_agc_if()
2362 if (is_qam(state)) set_agc_if()
2363 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; set_agc_if()
2365 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; set_agc_if()
2369 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, set_agc_if()
2378 status = read16(state, IQM_AF_STDBY__A, &data); set_agc_if()
2382 status = write16(state, IQM_AF_STDBY__A, data); set_agc_if()
2386 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); set_agc_if()
2394 if (state->m_if_agc_pol) set_agc_if()
2398 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); set_agc_if()
2403 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, set_agc_if()
2412 status = read16(state, IQM_AF_STDBY__A, &data); set_agc_if()
2416 status = write16(state, IQM_AF_STDBY__A, data); set_agc_if()
2421 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); set_agc_if()
2425 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); set_agc_if()
2433 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); set_agc_if()
2440 static int get_qam_signal_to_noise(struct drxk_state *state, get_qam_signal_to_noise() argument
2455 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); get_qam_signal_to_noise()
2461 switch (state->props.modulation) { get_qam_signal_to_noise()
2489 static int get_dvbt_signal_to_noise(struct drxk_state *state, get_dvbt_signal_to_noise() argument
2509 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, get_dvbt_signal_to_noise()
2513 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, get_dvbt_signal_to_noise()
2517 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, get_dvbt_signal_to_noise()
2521 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, get_dvbt_signal_to_noise()
2531 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data); get_dvbt_signal_to_noise()
2540 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, get_dvbt_signal_to_noise()
2593 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) get_signal_to_noise() argument
2598 switch (state->m_operation_mode) { get_signal_to_noise()
2600 return get_dvbt_signal_to_noise(state, p_signal_to_noise); get_signal_to_noise()
2603 return get_qam_signal_to_noise(state, p_signal_to_noise); get_signal_to_noise()
2611 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2645 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2648 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2654 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2678 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2690 status = get_qam_signal_to_noise(state, &signal_to_noise);
2694 switch (state->props.modulation) {
2725 static int get_quality(struct drxk_state *state, s32 *p_quality)
2729 switch (state->m_operation_mode) {
2731 return get_dvbt_quality(state, p_quality);
2733 return get_dvbc_quality(state, p_quality);
2755 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) ConfigureI2CBridge() argument
2761 if (state->m_drxk_state == DRXK_UNINITIALIZED) ConfigureI2CBridge()
2763 if (state->m_drxk_state == DRXK_POWERED_DOWN) ConfigureI2CBridge()
2766 if (state->no_i2c_bridge) ConfigureI2CBridge()
2769 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, ConfigureI2CBridge()
2774 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, ConfigureI2CBridge()
2779 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, ConfigureI2CBridge()
2785 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); ConfigureI2CBridge()
2793 static int set_pre_saw(struct drxk_state *state, set_pre_saw() argument
2804 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); set_pre_saw()
2811 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, bl_direct_cmd() argument
2822 mutex_lock(&state->mutex); bl_direct_cmd()
2823 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); bl_direct_cmd()
2826 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); bl_direct_cmd()
2829 status = write16(state, SIO_BL_TGT_ADDR__A, offset); bl_direct_cmd()
2832 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); bl_direct_cmd()
2835 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); bl_direct_cmd()
2838 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); bl_direct_cmd()
2844 status = read16(state, SIO_BL_STATUS__A, &bl_status); bl_direct_cmd()
2857 mutex_unlock(&state->mutex); bl_direct_cmd()
2862 static int adc_sync_measurement(struct drxk_state *state, u16 *count) adc_sync_measurement() argument
2870 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); adc_sync_measurement()
2873 status = write16(state, IQM_AF_START_LOCK__A, 1); adc_sync_measurement()
2878 status = read16(state, IQM_AF_PHASE0__A, &data); adc_sync_measurement()
2883 status = read16(state, IQM_AF_PHASE1__A, &data); adc_sync_measurement()
2888 status = read16(state, IQM_AF_PHASE2__A, &data); adc_sync_measurement()
2900 static int adc_synchronization(struct drxk_state *state) adc_synchronization() argument
2907 status = adc_sync_measurement(state, &count); adc_synchronization()
2915 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); adc_synchronization()
2928 status = write16(state, IQM_AF_CLKNEG__A, clk_neg); adc_synchronization()
2931 status = adc_sync_measurement(state, &count); adc_synchronization()
2944 static int set_frequency_shifter(struct drxk_state *state, set_frequency_shifter() argument
2951 bool tuner_mirror = !state->m_b_mirror_freq_spect; set_frequency_shifter()
2956 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); set_frequency_shifter()
2967 if ((state->m_operation_mode == OM_QAM_ITU_A) || set_frequency_shifter()
2968 (state->m_operation_mode == OM_QAM_ITU_C) || set_frequency_shifter()
2969 (state->m_operation_mode == OM_DVBT)) set_frequency_shifter()
2993 image_to_select = state->m_rfmirror ^ tuner_mirror ^ set_frequency_shifter()
2995 state->m_iqm_fs_rate_ofs = set_frequency_shifter()
2999 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; set_frequency_shifter()
3003 status = write32(state, IQM_FS_RATE_OFS_LO__A, set_frequency_shifter()
3004 state->m_iqm_fs_rate_ofs); set_frequency_shifter()
3010 static int init_agc(struct drxk_state *state, bool is_dtv) init_agc() argument
3040 if (!is_qam(state)) { init_agc()
3042 __func__, state->m_operation_mode); init_agc()
3060 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; init_agc()
3062 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, init_agc()
3067 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); init_agc()
3070 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); init_agc()
3073 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); init_agc()
3076 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); init_agc()
3079 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, init_agc()
3083 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, init_agc()
3087 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); init_agc()
3090 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); init_agc()
3093 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); init_agc()
3096 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); init_agc()
3099 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); init_agc()
3102 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); init_agc()
3106 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, init_agc()
3110 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, init_agc()
3114 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); init_agc()
3118 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); init_agc()
3121 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); init_agc()
3124 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); init_agc()
3128 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); init_agc()
3131 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); init_agc()
3134 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); init_agc()
3137 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); init_agc()
3140 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); init_agc()
3143 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); init_agc()
3146 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); init_agc()
3149 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); init_agc()
3152 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); init_agc()
3155 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); init_agc()
3158 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); init_agc()
3161 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); init_agc()
3164 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); init_agc()
3167 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); init_agc()
3170 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); init_agc()
3173 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); init_agc()
3176 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); init_agc()
3179 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); init_agc()
3182 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); init_agc()
3187 status = read16(state, SCU_RAM_AGC_KI__A, &data); init_agc()
3197 status = write16(state, SCU_RAM_AGC_KI__A, data); init_agc()
3204 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) dvbtqam_get_acc_pkt_err() argument
3210 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); dvbtqam_get_acc_pkt_err()
3212 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, dvbtqam_get_acc_pkt_err()
3219 static int dvbt_sc_command(struct drxk_state *state, dvbt_sc_command() argument
3231 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); dvbt_sc_command()
3243 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); dvbt_sc_command()
3255 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); dvbt_sc_command()
3273 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); dvbt_sc_command()
3277 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); dvbt_sc_command()
3282 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); dvbt_sc_command()
3295 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); dvbt_sc_command()
3302 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); dvbt_sc_command()
3319 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); dvbt_sc_command()
3339 static int power_up_dvbt(struct drxk_state *state) power_up_dvbt() argument
3345 status = ctrl_power_mode(state, &power_mode); power_up_dvbt()
3351 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) dvbt_ctrl_set_inc_enable() argument
3357 status = write16(state, IQM_CF_BYPASSDET__A, 0); dvbt_ctrl_set_inc_enable()
3359 status = write16(state, IQM_CF_BYPASSDET__A, 1); dvbt_ctrl_set_inc_enable()
3366 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) dvbt_ctrl_set_fr_enable() argument
3374 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, dvbt_ctrl_set_fr_enable()
3378 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); dvbt_ctrl_set_fr_enable()
3386 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, dvbt_ctrl_set_echo_threshold() argument
3393 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); dvbt_ctrl_set_echo_threshold()
3414 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); dvbt_ctrl_set_echo_threshold()
3421 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, dvbt_ctrl_set_sqi_speed() argument
3436 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, dvbt_ctrl_set_sqi_speed()
3454 static int dvbt_activate_presets(struct drxk_state *state) dvbt_activate_presets() argument
3464 status = dvbt_ctrl_set_inc_enable(state, &setincenable); dvbt_activate_presets()
3467 status = dvbt_ctrl_set_fr_enable(state, &setfrenable); dvbt_activate_presets()
3470 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); dvbt_activate_presets()
3473 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); dvbt_activate_presets()
3476 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, dvbt_activate_presets()
3477 state->m_dvbt_if_agc_cfg.ingain_tgt_max); dvbt_activate_presets()
3494 static int set_dvbt_standard(struct drxk_state *state, set_dvbt_standard() argument
3503 power_up_dvbt(state); set_dvbt_standard()
3505 switch_antenna_to_dvbt(state); set_dvbt_standard()
3507 status = scu_command(state, set_dvbt_standard()
3515 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM set_dvbt_standard()
3522 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); set_dvbt_standard()
3525 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); set_dvbt_standard()
3528 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); set_dvbt_standard()
3534 status = write16(state, IQM_AF_UPD_SEL__A, 1); set_dvbt_standard()
3538 status = write16(state, IQM_AF_CLP_LEN__A, 0); set_dvbt_standard()
3542 status = write16(state, IQM_AF_SNS_LEN__A, 0); set_dvbt_standard()
3546 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); set_dvbt_standard()
3549 status = set_iqm_af(state, true); set_dvbt_standard()
3553 status = write16(state, IQM_AF_AGC_RF__A, 0); set_dvbt_standard()
3558 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ set_dvbt_standard()
3561 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ set_dvbt_standard()
3564 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ set_dvbt_standard()
3568 status = write16(state, IQM_RC_STRETCH__A, 16); set_dvbt_standard()
3571 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ set_dvbt_standard()
3574 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ set_dvbt_standard()
3577 status = write16(state, IQM_CF_SCALE__A, 1600); set_dvbt_standard()
3580 status = write16(state, IQM_CF_SCALE_SH__A, 0); set_dvbt_standard()
3585 status = write16(state, IQM_AF_CLP_TH__A, 448); set_dvbt_standard()
3588 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ set_dvbt_standard()
3592 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, set_dvbt_standard()
3597 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ set_dvbt_standard()
3600 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); set_dvbt_standard()
3604 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); set_dvbt_standard()
3607 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); set_dvbt_standard()
3612 status = adc_synchronization(state); set_dvbt_standard()
3615 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); set_dvbt_standard()
3620 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); set_dvbt_standard()
3624 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); set_dvbt_standard()
3627 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); set_dvbt_standard()
3632 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); set_dvbt_standard()
3636 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); set_dvbt_standard()
3641 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); set_dvbt_standard()
3645 if (!state->m_drxk_a3_rom_code) { set_dvbt_standard()
3647 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, set_dvbt_standard()
3648 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); set_dvbt_standard()
3655 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); set_dvbt_standard()
3658 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); set_dvbt_standard()
3664 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ set_dvbt_standard()
3670 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); set_dvbt_standard()
3674 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); set_dvbt_standard()
3678 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); set_dvbt_standard()
3683 status = mpegts_dto_setup(state, OM_DVBT); set_dvbt_standard()
3687 status = dvbt_activate_presets(state); set_dvbt_standard()
3703 static int dvbt_start(struct drxk_state *state) dvbt_start() argument
3713 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, dvbt_start()
3719 status = mpegts_start(state); dvbt_start()
3722 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); dvbt_start()
3740 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, set_dvbt() argument
3754 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM set_dvbt()
3761 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); set_dvbt()
3766 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); set_dvbt()
3769 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); set_dvbt()
3775 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); set_dvbt()
3782 switch (state->props.transmission_mode) { set_dvbt()
3796 switch (state->props.guard_interval) { set_dvbt()
3816 switch (state->props.hierarchy) { set_dvbt()
3837 switch (state->props.modulation) { set_dvbt()
3874 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); set_dvbt()
3880 switch (state->props.code_rate_HP) { set_dvbt()
3915 switch (state->props.bandwidth_hz) { set_dvbt()
3917 state->props.bandwidth_hz = 8000000; set_dvbt()
3921 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, set_dvbt()
3926 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, set_dvbt()
3930 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, set_dvbt()
3934 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, set_dvbt()
3938 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, set_dvbt()
3945 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, set_dvbt()
3950 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, set_dvbt()
3954 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, set_dvbt()
3958 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, set_dvbt()
3962 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, set_dvbt()
3969 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, set_dvbt()
3974 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, set_dvbt()
3978 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, set_dvbt()
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, set_dvbt()
3986 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, set_dvbt()
4010 ((state->m_sys_clock_freq * set_dvbt()
4023 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); set_dvbt()
4034 status = set_frequency_shifter(state, intermediate_freqk_hz, set_dvbt()
4042 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); set_dvbt()
4047 status = write16(state, OFDM_SC_COMM_STATE__A, 0); set_dvbt()
4050 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); set_dvbt()
4055 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM set_dvbt()
4067 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, set_dvbt()
4072 if (!state->m_drxk_a3_rom_code) set_dvbt()
4073 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); set_dvbt()
4091 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) get_dvbt_lock_status() argument
4107 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); get_dvbt_lock_status()
4113 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); get_dvbt_lock_status()
4132 static int power_up_qam(struct drxk_state *state) power_up_qam() argument
4138 status = ctrl_power_mode(state, &power_mode); power_up_qam()
4147 static int power_down_qam(struct drxk_state *state) power_down_qam() argument
4154 status = read16(state, SCU_COMM_EXEC__A, &data); power_down_qam()
4163 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); power_down_qam()
4166 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM power_down_qam()
4173 status = set_iqm_af(state, false); power_down_qam()
4195 static int set_qam_measurement(struct drxk_state *state, set_qam_measurement() argument
4256 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); set_qam_measurement()
4259 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, set_qam_measurement()
4263 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); set_qam_measurement()
4270 static int set_qam16(struct drxk_state *state) set_qam16() argument
4277 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); set_qam16()
4280 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); set_qam16()
4283 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); set_qam16()
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); set_qam16()
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); set_qam16()
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); set_qam16()
4296 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); set_qam16()
4299 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); set_qam16()
4302 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); set_qam16()
4305 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); set_qam16()
4308 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); set_qam16()
4311 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); set_qam16()
4315 status = write16(state, QAM_SY_SYNC_HWM__A, 5); set_qam16()
4318 status = write16(state, QAM_SY_SYNC_AWM__A, 4); set_qam16()
4321 status = write16(state, QAM_SY_SYNC_LWM__A, 3); set_qam16()
4326 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, set_qam16()
4332 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); set_qam16()
4335 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); set_qam16()
4338 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); set_qam16()
4341 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); set_qam16()
4344 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); set_qam16()
4347 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); set_qam16()
4350 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); set_qam16()
4353 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); set_qam16()
4357 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); set_qam16()
4360 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); set_qam16()
4363 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); set_qam16()
4366 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); set_qam16()
4369 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); set_qam16()
4372 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); set_qam16()
4375 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); set_qam16()
4378 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); set_qam16()
4381 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); set_qam16()
4384 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); set_qam16()
4387 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); set_qam16()
4390 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); set_qam16()
4397 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); set_qam16()
4400 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); set_qam16()
4403 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); set_qam16()
4406 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); set_qam16()
4409 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); set_qam16()
4412 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); set_qam16()
4416 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); set_qam16()
4419 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); set_qam16()
4422 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); set_qam16()
4429 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); set_qam16()
4432 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); set_qam16()
4435 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); set_qam16()
4438 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); set_qam16()
4441 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); set_qam16()
4444 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); set_qam16()
4447 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); set_qam16()
4464 static int set_qam32(struct drxk_state *state) set_qam32() argument
4472 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); set_qam32()
4475 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); set_qam32()
4478 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); set_qam32()
4481 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); set_qam32()
4484 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); set_qam32()
4487 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); set_qam32()
4492 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); set_qam32()
4495 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); set_qam32()
4498 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); set_qam32()
4501 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); set_qam32()
4504 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); set_qam32()
4507 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); set_qam32()
4511 status = write16(state, QAM_SY_SYNC_HWM__A, 6); set_qam32()
4514 status = write16(state, QAM_SY_SYNC_AWM__A, 5); set_qam32()
4517 status = write16(state, QAM_SY_SYNC_LWM__A, 3); set_qam32()
4523 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, set_qam32()
4531 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); set_qam32()
4534 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); set_qam32()
4537 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); set_qam32()
4540 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); set_qam32()
4543 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); set_qam32()
4546 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); set_qam32()
4549 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); set_qam32()
4552 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); set_qam32()
4556 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); set_qam32()
4559 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); set_qam32()
4562 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); set_qam32()
4565 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); set_qam32()
4568 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); set_qam32()
4571 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); set_qam32()
4574 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); set_qam32()
4577 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); set_qam32()
4580 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); set_qam32()
4583 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); set_qam32()
4586 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); set_qam32()
4589 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); set_qam32()
4596 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); set_qam32()
4599 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); set_qam32()
4602 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); set_qam32()
4605 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); set_qam32()
4608 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); set_qam32()
4611 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); set_qam32()
4615 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); set_qam32()
4618 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); set_qam32()
4621 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); set_qam32()
4628 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); set_qam32()
4631 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); set_qam32()
4634 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); set_qam32()
4637 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); set_qam32()
4640 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); set_qam32()
4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); set_qam32()
4646 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); set_qam32()
4660 static int set_qam64(struct drxk_state *state) set_qam64() argument
4667 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); set_qam64()
4670 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); set_qam64()
4673 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); set_qam64()
4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); set_qam64()
4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); set_qam64()
4682 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); set_qam64()
4687 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); set_qam64()
4690 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); set_qam64()
4693 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); set_qam64()
4696 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); set_qam64()
4699 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); set_qam64()
4702 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); set_qam64()
4706 status = write16(state, QAM_SY_SYNC_HWM__A, 5); set_qam64()
4709 status = write16(state, QAM_SY_SYNC_AWM__A, 4); set_qam64()
4712 status = write16(state, QAM_SY_SYNC_LWM__A, 3); set_qam64()
4717 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, set_qam64()
4725 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); set_qam64()
4728 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); set_qam64()
4731 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); set_qam64()
4734 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); set_qam64()
4737 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); set_qam64()
4740 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); set_qam64()
4743 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); set_qam64()
4746 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); set_qam64()
4750 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); set_qam64()
4753 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); set_qam64()
4756 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); set_qam64()
4759 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); set_qam64()
4762 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); set_qam64()
4765 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); set_qam64()
4768 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); set_qam64()
4771 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); set_qam64()
4774 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); set_qam64()
4777 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); set_qam64()
4780 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); set_qam64()
4783 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); set_qam64()
4790 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); set_qam64()
4793 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); set_qam64()
4796 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); set_qam64()
4799 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); set_qam64()
4802 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); set_qam64()
4805 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); set_qam64()
4809 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); set_qam64()
4812 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); set_qam64()
4815 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); set_qam64()
4822 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); set_qam64()
4825 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); set_qam64()
4828 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); set_qam64()
4831 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); set_qam64()
4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); set_qam64()
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); set_qam64()
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); set_qam64()
4855 static int set_qam128(struct drxk_state *state) set_qam128() argument
4862 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); set_qam128()
4865 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); set_qam128()
4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); set_qam128()
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); set_qam128()
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); set_qam128()
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); set_qam128()
4882 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); set_qam128()
4885 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); set_qam128()
4888 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); set_qam128()
4891 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); set_qam128()
4894 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); set_qam128()
4897 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); set_qam128()
4901 status = write16(state, QAM_SY_SYNC_HWM__A, 6); set_qam128()
4904 status = write16(state, QAM_SY_SYNC_AWM__A, 5); set_qam128()
4907 status = write16(state, QAM_SY_SYNC_LWM__A, 3); set_qam128()
4914 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, set_qam128()
4922 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); set_qam128()
4925 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); set_qam128()
4928 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); set_qam128()
4931 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); set_qam128()
4934 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); set_qam128()
4937 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); set_qam128()
4940 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); set_qam128()
4943 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); set_qam128()
4947 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); set_qam128()
4950 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); set_qam128()
4953 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); set_qam128()
4956 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); set_qam128()
4959 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); set_qam128()
4962 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); set_qam128()
4965 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); set_qam128()
4968 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); set_qam128()
4971 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); set_qam128()
4974 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); set_qam128()
4977 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); set_qam128()
4980 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); set_qam128()
4987 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); set_qam128()
4990 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); set_qam128()
4993 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); set_qam128()
4996 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); set_qam128()
4999 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); set_qam128()
5002 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); set_qam128()
5006 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); set_qam128()
5009 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); set_qam128()
5013 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); set_qam128()
5019 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); set_qam128()
5022 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); set_qam128()
5025 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); set_qam128()
5028 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); set_qam128()
5031 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); set_qam128()
5034 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); set_qam128()
5037 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); set_qam128()
5052 static int set_qam256(struct drxk_state *state) set_qam256() argument
5059 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); set_qam256()
5062 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); set_qam256()
5065 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); set_qam256()
5068 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); set_qam256()
5071 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); set_qam256()
5074 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); set_qam256()
5079 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); set_qam256()
5082 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); set_qam256()
5085 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); set_qam256()
5088 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); set_qam256()
5091 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); set_qam256()
5094 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); set_qam256()
5098 status = write16(state, QAM_SY_SYNC_HWM__A, 5); set_qam256()
5101 status = write16(state, QAM_SY_SYNC_AWM__A, 4); set_qam256()
5104 status = write16(state, QAM_SY_SYNC_LWM__A, 3); set_qam256()
5110 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, set_qam256()
5118 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); set_qam256()
5121 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); set_qam256()
5124 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); set_qam256()
5127 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); set_qam256()
5130 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); set_qam256()
5133 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); set_qam256()
5136 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); set_qam256()
5139 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); set_qam256()
5143 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); set_qam256()
5146 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); set_qam256()
5149 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); set_qam256()
5152 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); set_qam256()
5155 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); set_qam256()
5158 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); set_qam256()
5161 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); set_qam256()
5164 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); set_qam256()
5167 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); set_qam256()
5170 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); set_qam256()
5173 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); set_qam256()
5176 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); set_qam256()
5183 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); set_qam256()
5186 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); set_qam256()
5189 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); set_qam256()
5192 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); set_qam256()
5195 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); set_qam256()
5198 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); set_qam256()
5202 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); set_qam256()
5205 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); set_qam256()
5208 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); set_qam256()
5215 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); set_qam256()
5218 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); set_qam256()
5221 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); set_qam256()
5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); set_qam256()
5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); set_qam256()
5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); set_qam256()
5233 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); set_qam256()
5248 static int qam_reset_qam(struct drxk_state *state) qam_reset_qam() argument
5255 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); qam_reset_qam()
5259 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM qam_reset_qam()
5276 static int qam_set_symbolrate(struct drxk_state *state) qam_set_symbolrate() argument
5287 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; qam_set_symbolrate()
5289 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ qam_set_symbolrate()
5290 if (state->props.symbol_rate <= 1188750) qam_set_symbolrate()
5292 else if (state->props.symbol_rate <= 2377500) qam_set_symbolrate()
5294 else if (state->props.symbol_rate <= 4755000) qam_set_symbolrate()
5296 status = write16(state, IQM_FD_RATESEL__A, ratesel); qam_set_symbolrate()
5303 symb_freq = state->props.symbol_rate * (1 << ratesel); qam_set_symbolrate()
5312 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); qam_set_symbolrate()
5315 state->m_iqm_rc_rate = iqm_rc_rate; qam_set_symbolrate()
5319 symb_freq = state->props.symbol_rate; qam_set_symbolrate()
5330 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); qam_set_symbolrate()
5347 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) get_qam_lock_status() argument
5354 status = scu_command(state, get_qam_lock_status()
5388 static int qam_demodulator_command(struct drxk_state *state, qam_demodulator_command() argument
5395 set_param_parameters[0] = state->m_constellation; /* modulation */ qam_demodulator_command()
5401 if (state->m_operation_mode == OM_QAM_ITU_C) qam_demodulator_command()
5406 status = scu_command(state, qam_demodulator_command()
5413 status = scu_command(state, qam_demodulator_command()
5419 if (state->m_operation_mode == OM_QAM_ITU_C) qam_demodulator_command()
5429 status = scu_command(state, qam_demodulator_command()
5446 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, set_qam() argument
5451 int qam_demod_param_count = state->qam_demod_parameter_count; set_qam()
5460 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); set_qam()
5463 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); set_qam()
5466 status = qam_reset_qam(state); set_qam()
5475 status = qam_set_symbolrate(state); set_qam()
5480 switch (state->props.modulation) { set_qam()
5482 state->m_constellation = DRX_CONSTELLATION_QAM256; set_qam()
5486 state->m_constellation = DRX_CONSTELLATION_QAM64; set_qam()
5489 state->m_constellation = DRX_CONSTELLATION_QAM16; set_qam()
5492 state->m_constellation = DRX_CONSTELLATION_QAM32; set_qam()
5495 state->m_constellation = DRX_CONSTELLATION_QAM128; set_qam()
5506 if (state->qam_demod_parameter_count == 4 set_qam()
5507 || !state->qam_demod_parameter_count) { set_qam()
5509 status = qam_demodulator_command(state, qam_demod_param_count); set_qam()
5515 if (state->qam_demod_parameter_count == 2 set_qam()
5516 || (!state->qam_demod_parameter_count && status < 0)) { set_qam()
5518 status = qam_demodulator_command(state, qam_demod_param_count); set_qam()
5525 state->qam_demod_parameter_count, set_qam()
5526 state->microcode_name); set_qam()
5528 } else if (!state->qam_demod_parameter_count) { set_qam()
5537 state->qam_demod_parameter_count = qam_demod_param_count; set_qam()
5549 status = set_frequency_shifter(state, intermediate_freqk_hz, set_qam()
5555 status = set_qam_measurement(state, state->m_constellation, set_qam()
5556 state->props.symbol_rate); set_qam()
5561 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); set_qam()
5564 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); set_qam()
5569 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); set_qam()
5572 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); set_qam()
5575 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); set_qam()
5578 status = write16(state, QAM_LC_MODE__A, 7); set_qam()
5582 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); set_qam()
5585 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); set_qam()
5588 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); set_qam()
5591 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); set_qam()
5594 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); set_qam()
5597 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); set_qam()
5600 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); set_qam()
5603 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); set_qam()
5606 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); set_qam()
5609 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); set_qam()
5612 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); set_qam()
5615 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); set_qam()
5618 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); set_qam()
5621 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); set_qam()
5624 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); set_qam()
5629 status = write16(state, QAM_SY_SP_INV__A, set_qam()
5635 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); set_qam()
5640 switch (state->props.modulation) { set_qam()
5642 status = set_qam16(state); set_qam()
5645 status = set_qam32(state); set_qam()
5649 status = set_qam64(state); set_qam()
5652 status = set_qam128(state); set_qam()
5655 status = set_qam256(state); set_qam()
5665 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); set_qam()
5672 status = mpegts_dto_setup(state, state->m_operation_mode); set_qam()
5677 status = mpegts_start(state); set_qam()
5680 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); set_qam()
5683 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); set_qam()
5686 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); set_qam()
5691 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM set_qam()
5706 static int set_qam_standard(struct drxk_state *state, set_qam_standard() argument
5719 switch_antenna_to_qam(state); set_qam_standard()
5722 status = power_up_qam(state); set_qam_standard()
5726 status = qam_reset_qam(state); set_qam_standard()
5732 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); set_qam_standard()
5735 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); set_qam_standard()
5743 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, set_qam_standard()
5748 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, set_qam_standard()
5754 status = bl_direct_cmd(state, set_qam_standard()
5766 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); set_qam_standard()
5769 status = write16(state, IQM_CF_SYMMETRIC__A, 0); set_qam_standard()
5772 status = write16(state, IQM_CF_MIDTAP__A, set_qam_standard()
5777 status = write16(state, IQM_RC_STRETCH__A, 21); set_qam_standard()
5780 status = write16(state, IQM_AF_CLP_LEN__A, 0); set_qam_standard()
5783 status = write16(state, IQM_AF_CLP_TH__A, 448); set_qam_standard()
5786 status = write16(state, IQM_AF_SNS_LEN__A, 0); set_qam_standard()
5789 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); set_qam_standard()
5793 status = write16(state, IQM_FS_ADJ_SEL__A, 1); set_qam_standard()
5796 status = write16(state, IQM_RC_ADJ_SEL__A, 1); set_qam_standard()
5799 status = write16(state, IQM_CF_ADJ_SEL__A, 1); set_qam_standard()
5802 status = write16(state, IQM_AF_UPD_SEL__A, 0); set_qam_standard()
5807 status = write16(state, IQM_CF_CLP_VAL__A, 500); set_qam_standard()
5810 status = write16(state, IQM_CF_DATATH__A, 1000); set_qam_standard()
5813 status = write16(state, IQM_CF_BYPASSDET__A, 1); set_qam_standard()
5816 status = write16(state, IQM_CF_DET_LCT__A, 0); set_qam_standard()
5819 status = write16(state, IQM_CF_WND_LEN__A, 1); set_qam_standard()
5822 status = write16(state, IQM_CF_PKDTH__A, 1); set_qam_standard()
5825 status = write16(state, IQM_AF_INC_BYPASS__A, 1); set_qam_standard()
5830 status = set_iqm_af(state, true); set_qam_standard()
5833 status = write16(state, IQM_AF_START_LOCK__A, 0x01); set_qam_standard()
5838 status = adc_synchronization(state); set_qam_standard()
5843 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); set_qam_standard()
5848 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); set_qam_standard()
5855 status = init_agc(state, true); set_qam_standard()
5858 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); set_qam_standard()
5863 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); set_qam_standard()
5866 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); set_qam_standard()
5871 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); set_qam_standard()
5878 static int write_gpio(struct drxk_state *state) write_gpio() argument
5885 status = write16(state, SCU_RAM_GPIO__A, write_gpio()
5891 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); write_gpio()
5895 if (state->m_has_sawsw) { write_gpio()
5896 if (state->uio_mask & 0x0001) { /* UIO-1 */ write_gpio()
5898 status = write16(state, SIO_PDR_SMA_TX_CFG__A, write_gpio()
5899 state->m_gpio_cfg); write_gpio()
5904 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); write_gpio()
5907 if ((state->m_gpio & 0x0001) == 0) write_gpio()
5912 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); write_gpio()
5916 if (state->uio_mask & 0x0002) { /* UIO-2 */ write_gpio()
5918 status = write16(state, SIO_PDR_SMA_RX_CFG__A, write_gpio()
5919 state->m_gpio_cfg); write_gpio()
5924 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); write_gpio()
5927 if ((state->m_gpio & 0x0002) == 0) write_gpio()
5932 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); write_gpio()
5936 if (state->uio_mask & 0x0004) { /* UIO-3 */ write_gpio()
5938 status = write16(state, SIO_PDR_GPIO_CFG__A, write_gpio()
5939 state->m_gpio_cfg); write_gpio()
5944 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); write_gpio()
5947 if ((state->m_gpio & 0x0004) == 0) write_gpio()
5952 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); write_gpio()
5958 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); write_gpio()
5965 static int switch_antenna_to_qam(struct drxk_state *state) switch_antenna_to_qam() argument
5972 if (!state->antenna_gpio) switch_antenna_to_qam()
5975 gpio_state = state->m_gpio & state->antenna_gpio; switch_antenna_to_qam()
5977 if (state->antenna_dvbt ^ gpio_state) { switch_antenna_to_qam()
5979 if (state->antenna_dvbt) switch_antenna_to_qam()
5980 state->m_gpio &= ~state->antenna_gpio; switch_antenna_to_qam()
5982 state->m_gpio |= state->antenna_gpio; switch_antenna_to_qam()
5983 status = write_gpio(state); switch_antenna_to_qam()
5990 static int switch_antenna_to_dvbt(struct drxk_state *state) switch_antenna_to_dvbt() argument
5997 if (!state->antenna_gpio) switch_antenna_to_dvbt()
6000 gpio_state = state->m_gpio & state->antenna_gpio; switch_antenna_to_dvbt()
6002 if (!(state->antenna_dvbt ^ gpio_state)) { switch_antenna_to_dvbt()
6004 if (state->antenna_dvbt) switch_antenna_to_dvbt()
6005 state->m_gpio |= state->antenna_gpio; switch_antenna_to_dvbt()
6007 state->m_gpio &= ~state->antenna_gpio; switch_antenna_to_dvbt()
6008 status = write_gpio(state); switch_antenna_to_dvbt()
6016 static int power_down_device(struct drxk_state *state) power_down_device() argument
6027 if (state->m_b_p_down_open_bridge) { power_down_device()
6029 status = ConfigureI2CBridge(state, true); power_down_device()
6034 status = dvbt_enable_ofdm_token_ring(state, false); power_down_device()
6038 status = write16(state, SIO_CC_PWD_MODE__A, power_down_device()
6042 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); power_down_device()
6045 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; power_down_device()
6046 status = hi_cfg_command(state); power_down_device()
6054 static int init_drxk(struct drxk_state *state) init_drxk() argument
6061 if ((state->m_drxk_state == DRXK_UNINITIALIZED)) { init_drxk()
6062 drxk_i2c_lock(state); init_drxk()
6063 status = power_up_device(state); init_drxk()
6066 status = drxx_open(state); init_drxk()
6070 status = write16(state, SIO_CC_SOFT_RST__A, init_drxk()
6076 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); init_drxk()
6084 state->m_drxk_a3_patch_code = true; init_drxk()
6085 status = get_device_capabilities(state); init_drxk()
6092 state->m_hi_cfg_bridge_delay = init_drxk()
6093 (u16) ((state->m_osc_clock_freq / 1000) * init_drxk()
6096 if (state->m_hi_cfg_bridge_delay > init_drxk()
6098 state->m_hi_cfg_bridge_delay = init_drxk()
6102 state->m_hi_cfg_bridge_delay += init_drxk()
6103 state->m_hi_cfg_bridge_delay << init_drxk()
6106 status = init_hi(state); init_drxk()
6111 if (!(state->m_DRXK_A1_ROM_CODE) init_drxk()
6112 && !(state->m_DRXK_A2_ROM_CODE)) init_drxk()
6115 status = write16(state, SCU_RAM_GPIO__A, init_drxk()
6122 status = mpegts_disable(state); init_drxk()
6127 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); init_drxk()
6130 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); init_drxk()
6135 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, init_drxk()
6141 status = write16(state, SIO_BL_COMM_EXEC__A, init_drxk()
6145 status = bl_chain_cmd(state, 0, 6, 100); init_drxk()
6149 if (state->fw) { init_drxk()
6150 status = download_microcode(state, state->fw->data, init_drxk()
6151 state->fw->size); init_drxk()
6157 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, init_drxk()
6163 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); init_drxk()
6166 status = drxx_open(state); init_drxk()
6173 status = ctrl_power_mode(state, &power_mode); init_drxk()
6188 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, init_drxk()
6197 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, init_drxk()
6217 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); init_drxk()
6223 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); init_drxk()
6227 status = mpegts_dto_init(state); init_drxk()
6230 status = mpegts_stop(state); init_drxk()
6233 status = mpegts_configure_polarity(state); init_drxk()
6236 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); init_drxk()
6240 status = write_gpio(state); init_drxk()
6244 state->m_drxk_state = DRXK_STOPPED; init_drxk()
6246 if (state->m_b_power_down) { init_drxk()
6247 status = power_down_device(state); init_drxk()
6250 state->m_drxk_state = DRXK_POWERED_DOWN; init_drxk()
6252 state->m_drxk_state = DRXK_STOPPED; init_drxk()
6256 if (state->m_has_dvbc) { init_drxk()
6257 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; init_drxk()
6258 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; init_drxk()
6259 strlcat(state->frontend.ops.info.name, " DVB-C", init_drxk()
6260 sizeof(state->frontend.ops.info.name)); init_drxk()
6262 if (state->m_has_dvbt) { init_drxk()
6263 state->frontend.ops.delsys[n++] = SYS_DVBT; init_drxk()
6264 strlcat(state->frontend.ops.info.name, " DVB-T", init_drxk()
6265 sizeof(state->frontend.ops.info.name)); init_drxk()
6267 drxk_i2c_unlock(state); init_drxk()
6271 state->m_drxk_state = DRXK_NO_DEV; init_drxk()
6272 drxk_i2c_unlock(state); init_drxk()
6282 struct drxk_state *state = context; load_firmware_cb() local
6287 state->microcode_name); load_firmware_cb()
6289 state->microcode_name); load_firmware_cb()
6290 state->microcode_name = NULL; load_firmware_cb()
6303 state->fw = fw; load_firmware_cb()
6305 init_drxk(state); load_firmware_cb()
6310 struct drxk_state *state = fe->demodulator_priv; drxk_release() local
6313 release_firmware(state->fw); drxk_release()
6315 kfree(state); drxk_release()
6320 struct drxk_state *state = fe->demodulator_priv; drxk_sleep() local
6324 if (state->m_drxk_state == DRXK_NO_DEV) drxk_sleep()
6326 if (state->m_drxk_state == DRXK_UNINITIALIZED) drxk_sleep()
6329 shut_down(state); drxk_sleep()
6335 struct drxk_state *state = fe->demodulator_priv; drxk_gate_ctrl() local
6339 if (state->m_drxk_state == DRXK_NO_DEV) drxk_gate_ctrl()
6342 return ConfigureI2CBridge(state, enable ? true : false); drxk_gate_ctrl()
6349 struct drxk_state *state = fe->demodulator_priv; drxk_set_parameters() local
6354 if (state->m_drxk_state == DRXK_NO_DEV) drxk_set_parameters()
6357 if (state->m_drxk_state == DRXK_UNINITIALIZED) drxk_set_parameters()
6372 old_delsys = state->props.delivery_system; drxk_set_parameters()
6373 state->props = *p; drxk_set_parameters()
6376 shut_down(state); drxk_set_parameters()
6380 if (!state->m_has_dvbc) drxk_set_parameters()
6382 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? drxk_set_parameters()
6384 if (state->m_itut_annex_c) drxk_set_parameters()
6385 setoperation_mode(state, OM_QAM_ITU_C); drxk_set_parameters()
6387 setoperation_mode(state, OM_QAM_ITU_A); drxk_set_parameters()
6390 if (!state->m_has_dvbt) drxk_set_parameters()
6392 setoperation_mode(state, OM_DVBT); drxk_set_parameters()
6400 start(state, 0, IF); drxk_set_parameters()
6417 static int get_strength(struct drxk_state *state, u64 *strength) get_strength() argument
6432 if (is_dvbt(state)) { get_strength()
6433 rf_agc = state->m_dvbt_rf_agc_cfg; get_strength()
6434 if_agc = state->m_dvbt_if_agc_cfg; get_strength()
6435 } else if (is_qam(state)) { get_strength()
6436 rf_agc = state->m_qam_rf_agc_cfg; get_strength()
6437 if_agc = state->m_qam_if_agc_cfg; get_strength()
6439 rf_agc = state->m_atv_rf_agc_cfg; get_strength()
6440 if_agc = state->m_atv_if_agc_cfg; get_strength()
6445 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); get_strength()
6450 read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); get_strength()
6478 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, get_strength()
6483 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, get_strength()
6521 struct drxk_state *state = fe->demodulator_priv; drxk_get_stats() local
6534 if (state->m_drxk_state == DRXK_NO_DEV) drxk_get_stats()
6536 if (state->m_drxk_state == DRXK_UNINITIALIZED) drxk_get_stats()
6540 state->fe_status = 0; drxk_get_stats()
6541 get_lock_status(state, &stat); drxk_get_stats()
6543 state->fe_status |= 0x1f; drxk_get_stats()
6545 state->fe_status |= 0x0f; drxk_get_stats()
6547 state->fe_status |= 0x07; drxk_get_stats()
6552 get_strength(state, &c->strength.stat[0].uvalue); drxk_get_stats()
6557 get_signal_to_noise(state, &cnr); drxk_get_stats()
6585 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16); drxk_get_stats()
6590 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16); drxk_get_stats()
6596 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16); drxk_get_stats()
6601 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16); drxk_get_stats()
6606 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16); drxk_get_stats()
6611 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16); drxk_get_stats()
6615 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); drxk_get_stats()
6644 struct drxk_state *state = fe->demodulator_priv; drxk_read_status() local
6653 *status = state->fe_status; drxk_read_status()
6661 struct drxk_state *state = fe->demodulator_priv; drxk_read_signal_strength() local
6666 if (state->m_drxk_state == DRXK_NO_DEV) drxk_read_signal_strength()
6668 if (state->m_drxk_state == DRXK_UNINITIALIZED) drxk_read_signal_strength()
6677 struct drxk_state *state = fe->demodulator_priv; drxk_read_snr() local
6682 if (state->m_drxk_state == DRXK_NO_DEV) drxk_read_snr()
6684 if (state->m_drxk_state == DRXK_UNINITIALIZED) drxk_read_snr()
6687 get_signal_to_noise(state, &snr2); drxk_read_snr()
6698 struct drxk_state *state = fe->demodulator_priv; drxk_read_ucblocks() local
6703 if (state->m_drxk_state == DRXK_NO_DEV) drxk_read_ucblocks()
6705 if (state->m_drxk_state == DRXK_UNINITIALIZED) drxk_read_ucblocks()
6708 dvbtqam_get_acc_pkt_err(state, &err); drxk_read_ucblocks()
6716 struct drxk_state *state = fe->demodulator_priv; drxk_get_tune_settings() local
6721 if (state->m_drxk_state == DRXK_NO_DEV) drxk_get_tune_settings()
6723 if (state->m_drxk_state == DRXK_UNINITIALIZED) drxk_get_tune_settings()
6776 struct drxk_state *state = NULL; drxk_attach() local
6781 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); drxk_attach()
6782 if (!state) drxk_attach()
6785 state->i2c = i2c; drxk_attach()
6786 state->demod_address = adr; drxk_attach()
6787 state->single_master = config->single_master; drxk_attach()
6788 state->microcode_name = config->microcode_name; drxk_attach()
6789 state->qam_demod_parameter_count = config->qam_demod_parameter_count; drxk_attach()
6790 state->no_i2c_bridge = config->no_i2c_bridge; drxk_attach()
6791 state->antenna_gpio = config->antenna_gpio; drxk_attach()
6792 state->antenna_dvbt = config->antenna_dvbt; drxk_attach()
6793 state->m_chunk_size = config->chunk_size; drxk_attach()
6794 state->enable_merr_cfg = config->enable_merr_cfg; drxk_attach()
6797 state->m_dvbt_static_clk = false; drxk_attach()
6798 state->m_dvbc_static_clk = false; drxk_attach()
6800 state->m_dvbt_static_clk = true; drxk_attach()
6801 state->m_dvbc_static_clk = true; drxk_attach()
6806 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; drxk_attach()
6808 state->m_ts_clockk_strength = 0x06; drxk_attach()
6811 state->m_enable_parallel = true; drxk_attach()
6813 state->m_enable_parallel = false; drxk_attach()
6816 state->uio_mask = config->antenna_gpio; drxk_attach()
6819 if (!state->antenna_dvbt && state->antenna_gpio) drxk_attach()
6820 state->m_gpio |= state->antenna_gpio; drxk_attach()
6822 state->m_gpio &= ~state->antenna_gpio; drxk_attach()
6824 mutex_init(&state->mutex); drxk_attach()
6826 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); drxk_attach()
6827 state->frontend.demodulator_priv = state; drxk_attach()
6829 init_state(state); drxk_attach()
6832 if (state->microcode_name) { drxk_attach()
6835 status = request_firmware(&fw, state->microcode_name, drxk_attach()
6836 state->i2c->dev.parent); drxk_attach()
6839 load_firmware_cb(fw, state); drxk_attach()
6840 } else if (init_drxk(state) < 0) drxk_attach()
6845 p = &state->frontend.dtv_property_cache; drxk_attach()
6865 return &state->frontend; drxk_attach()
6869 kfree(state); drxk_attach()
H A Ddib0070.c85 static u16 dib0070_read_reg(struct dib0070_state *state, u8 reg) dib0070_read_reg() argument
89 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib0070_read_reg()
94 state->i2c_write_buffer[0] = reg; dib0070_read_reg()
96 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); dib0070_read_reg()
97 state->msg[0].addr = state->cfg->i2c_address; dib0070_read_reg()
98 state->msg[0].flags = 0; dib0070_read_reg()
99 state->msg[0].buf = state->i2c_write_buffer; dib0070_read_reg()
100 state->msg[0].len = 1; dib0070_read_reg()
101 state->msg[1].addr = state->cfg->i2c_address; dib0070_read_reg()
102 state->msg[1].flags = I2C_M_RD; dib0070_read_reg()
103 state->msg[1].buf = state->i2c_read_buffer; dib0070_read_reg()
104 state->msg[1].len = 2; dib0070_read_reg()
106 if (i2c_transfer(state->i2c, state->msg, 2) != 2) { dib0070_read_reg()
110 ret = (state->i2c_read_buffer[0] << 8) dib0070_read_reg()
111 | state->i2c_read_buffer[1]; dib0070_read_reg()
113 mutex_unlock(&state->i2c_buffer_lock); dib0070_read_reg()
117 static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) dib0070_write_reg() argument
121 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib0070_write_reg()
125 state->i2c_write_buffer[0] = reg; dib0070_write_reg()
126 state->i2c_write_buffer[1] = val >> 8; dib0070_write_reg()
127 state->i2c_write_buffer[2] = val & 0xff; dib0070_write_reg()
129 memset(state->msg, 0, sizeof(struct i2c_msg)); dib0070_write_reg()
130 state->msg[0].addr = state->cfg->i2c_address; dib0070_write_reg()
131 state->msg[0].flags = 0; dib0070_write_reg()
132 state->msg[0].buf = state->i2c_write_buffer; dib0070_write_reg()
133 state->msg[0].len = 3; dib0070_write_reg()
135 if (i2c_transfer(state->i2c, state->msg, 1) != 1) { dib0070_write_reg()
141 mutex_unlock(&state->i2c_buffer_lock); dib0070_write_reg()
145 #define HARD_RESET(state) do { \
146 state->cfg->sleep(state->fe, 0); \
147 if (state->cfg->reset) { \
148 state->cfg->reset(state->fe,1); msleep(10); \
149 state->cfg->reset(state->fe,0); msleep(10); \
155 struct dib0070_state *state = fe->tuner_priv; dib0070_set_bandwidth() local
156 u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff; dib0070_set_bandwidth()
158 if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000) dib0070_set_bandwidth()
160 else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000) dib0070_set_bandwidth()
162 else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000) dib0070_set_bandwidth()
167 dib0070_write_reg(state, 0x02, tmp); dib0070_set_bandwidth()
170 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) { dib0070_set_bandwidth()
171 u16 value = dib0070_read_reg(state, 0x17); dib0070_set_bandwidth()
173 dib0070_write_reg(state, 0x17, value & 0xfffc); dib0070_set_bandwidth()
174 tmp = dib0070_read_reg(state, 0x01) & 0x01ff; dib0070_set_bandwidth()
175 dib0070_write_reg(state, 0x01, tmp | (60 << 9)); dib0070_set_bandwidth()
177 dib0070_write_reg(state, 0x17, value); dib0070_set_bandwidth()
182 static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state) dib0070_captrim() argument
190 dib0070_write_reg(state, 0x0f, 0xed10); dib0070_captrim()
191 dib0070_write_reg(state, 0x17, 0x0034); dib0070_captrim()
193 dib0070_write_reg(state, 0x18, 0x0032); dib0070_captrim()
194 state->step = state->captrim = state->fcaptrim = 64; dib0070_captrim()
195 state->adc_diff = 3000; dib0070_captrim()
200 state->step /= 2; dib0070_captrim()
201 dib0070_write_reg(state, 0x14, state->lo4 | state->captrim); dib0070_captrim()
207 adc = dib0070_read_reg(state, 0x19); dib0070_captrim()
209 dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024); dib0070_captrim()
219 if (adc < state->adc_diff) { dib0070_captrim()
220 dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff); dib0070_captrim()
221 state->adc_diff = adc; dib0070_captrim()
222 state->fcaptrim = state->captrim; dib0070_captrim()
227 state->captrim += (step_sign * state->step); dib0070_captrim()
229 if (state->step >= 1) dib0070_captrim()
235 dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim); dib0070_captrim()
236 dib0070_write_reg(state, 0x18, 0x07ff); dib0070_captrim()
245 struct dib0070_state *state = fe->tuner_priv; dib0070_set_ctrl_lo5() local
248 return dib0070_write_reg(state, 0x15, lo5); dib0070_set_ctrl_lo5()
253 struct dib0070_state *state = fe->tuner_priv; dib0070_ctrl_agc_filter() local
256 dib0070_write_reg(state, 0x1b, 0xff00); dib0070_ctrl_agc_filter()
257 dib0070_write_reg(state, 0x1a, 0x0000); dib0070_ctrl_agc_filter()
259 dib0070_write_reg(state, 0x1b, 0x4112); dib0070_ctrl_agc_filter()
260 if (state->cfg->vga_filter != 0) { dib0070_ctrl_agc_filter()
261 dib0070_write_reg(state, 0x1a, state->cfg->vga_filter); dib0070_ctrl_agc_filter()
262 dprintk("vga filter register is set to %x", state->cfg->vga_filter); dib0070_ctrl_agc_filter()
264 dib0070_write_reg(state, 0x1a, 0x0009); dib0070_ctrl_agc_filter()
340 struct dib0070_state *state = fe->tuner_priv; dib0070_tune_digital() local
345 enum frontend_tune_state *tune_state = &state->tune_state; dib0070_tune_digital()
349 u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf); dib0070_tune_digital()
352 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1) dib0070_tune_digital()
353 if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) dib0070_tune_digital()
354 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) dib0070_tune_digital()
355 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) dib0070_tune_digital()
356 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2))) dib0070_tune_digital()
357 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) dib0070_tune_digital()
358 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))) dib0070_tune_digital()
361 if (state->current_rf != freq) { dib0070_tune_digital()
363 switch (state->revision) { dib0070_tune_digital()
370 if (state->cfg->flip_chip) dib0070_tune_digital()
381 state->current_tune_table_index = tune; dib0070_tune_digital()
382 state->lna_match = lna_match; dib0070_tune_digital()
387 if (state->current_rf != freq) { dib0070_tune_digital()
392 state->current_rf = freq; dib0070_tune_digital()
393 state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7); dib0070_tune_digital()
396 dib0070_write_reg(state, 0x17, 0x30); dib0070_tune_digital()
399 VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2; dib0070_tune_digital()
403 REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000); dib0070_tune_digital()
406 REFDIV = (u8) ((state->cfg->clock_khz) / 1000); dib0070_tune_digital()
409 REFDIV = (u8) (state->cfg->clock_khz / 10000); dib0070_tune_digital()
412 FREF = state->cfg->clock_khz / REFDIV; dib0070_tune_digital()
416 switch (state->revision) { dib0070_tune_digital()
418 FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF); dib0070_tune_digital()
419 Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF; dib0070_tune_digital()
443 state->lo4 |= (1 << 14) | (1 << 12); dib0070_tune_digital()
448 dib0070_write_reg(state, 0x11, (u16)FBDiv); dib0070_tune_digital()
449 dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV); dib0070_tune_digital()
450 dib0070_write_reg(state, 0x13, (u16) Rest); dib0070_tune_digital()
452 if (state->revision == DIB0070S_P1A) { dib0070_tune_digital()
456 dib0070_write_reg(state, 0x1d, 0xFFFF); dib0070_tune_digital()
461 dib0070_write_reg(state, 0x20, dib0070_tune_digital()
462 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable); dib0070_tune_digital()
466 dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1); dib0070_tune_digital()
467 dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv); dib0070_tune_digital()
468 dprintk("VCO = %hd", state->current_tune_table_index->vco_band); dib0070_tune_digital()
469 dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq); dib0070_tune_digital()
478 ret = dib0070_captrim(state, tune_state); dib0070_tune_digital()
481 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; dib0070_tune_digital()
485 dib0070_write_reg(state, 0x0f, dib0070_tune_digital()
488 | (state->current_tune_table_index->wbdmux << 0)); dib0070_tune_digital()
489 state->wbd_gain_current = tmp->wbd_gain_val; dib0070_tune_digital()
491 dib0070_write_reg(state, 0x0f, dib0070_tune_digital()
492 (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index-> dib0070_tune_digital()
494 state->wbd_gain_current = 6; dib0070_tune_digital()
497 dib0070_write_reg(state, 0x06, 0x3fff); dib0070_tune_digital()
498 dib0070_write_reg(state, 0x07, dib0070_tune_digital()
499 (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0)); dib0070_tune_digital()
500 dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127)); dib0070_tune_digital()
501 dib0070_write_reg(state, 0x0d, 0x0d80); dib0070_tune_digital()
504 dib0070_write_reg(state, 0x18, 0x07ff); dib0070_tune_digital()
505 dib0070_write_reg(state, 0x17, 0x0033); dib0070_tune_digital()
521 struct dib0070_state *state = fe->tuner_priv; dib0070_tune() local
524 state->tune_state = CT_TUNER_START; dib0070_tune()
532 } while (state->tune_state != CT_TUNER_STOP); dib0070_tune()
539 struct dib0070_state *state = fe->tuner_priv; dib0070_wakeup() local
540 if (state->cfg->sleep) dib0070_wakeup()
541 state->cfg->sleep(fe, 0); dib0070_wakeup()
547 struct dib0070_state *state = fe->tuner_priv; dib0070_sleep() local
548 if (state->cfg->sleep) dib0070_sleep()
549 state->cfg->sleep(fe, 1); dib0070_sleep()
555 struct dib0070_state *state = fe->tuner_priv; dib0070_get_rf_output() local
556 return (dib0070_read_reg(state, 0x07) >> 11) & 0x3; dib0070_get_rf_output()
562 struct dib0070_state *state = fe->tuner_priv; dib0070_set_rf_output() local
563 u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff; dib0070_set_rf_output()
568 return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11)); dib0070_set_rf_output()
611 static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain) dib0070_read_wbd_offset() argument
613 u16 tuner_en = dib0070_read_reg(state, 0x20); dib0070_read_wbd_offset()
616 dib0070_write_reg(state, 0x18, 0x07ff); dib0070_read_wbd_offset()
617 dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001); dib0070_read_wbd_offset()
618 dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0)); dib0070_read_wbd_offset()
620 offset = dib0070_read_reg(state, 0x19); dib0070_read_wbd_offset()
621 dib0070_write_reg(state, 0x20, tuner_en); dib0070_read_wbd_offset()
625 static void dib0070_wbd_offset_calibration(struct dib0070_state *state) dib0070_wbd_offset_calibration() argument
629 state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2); dib0070_wbd_offset_calibration()
630 dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]); dib0070_wbd_offset_calibration()
636 struct dib0070_state *state = fe->tuner_priv; dib0070_wbd_offset() local
637 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; dib0070_wbd_offset()
643 state->wbd_gain_current = tmp->wbd_gain_val; dib0070_wbd_offset()
645 state->wbd_gain_current = 6; dib0070_wbd_offset()
647 return state->wbd_offset_3_3[state->wbd_gain_current - 6]; dib0070_wbd_offset()
654 struct dib0070_state *state = fe->tuner_priv; dib0070_reset() local
657 HARD_RESET(state); dib0070_reset()
661 if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1) dib0070_reset()
662 state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff; dib0070_reset()
667 state->revision = DIB0070S_P1A; dib0070_reset()
670 dprintk("Revision: %x", state->revision); dib0070_reset()
672 if (state->revision == DIB0070_P1D) { dib0070_reset()
682 dib0070_write_reg(state, (u8)r, pgm_read_word(n++)); dib0070_reset()
688 if (state->cfg->force_crystal_mode != 0) dib0070_reset()
689 r = state->cfg->force_crystal_mode; dib0070_reset()
690 else if (state->cfg->clock_khz >= 24000) dib0070_reset()
696 r |= state->cfg->osc_buffer_state << 3; dib0070_reset()
698 dib0070_write_reg(state, 0x10, r); dib0070_reset()
699 dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5)); dib0070_reset()
701 if (state->cfg->invert_iq) { dib0070_reset()
702 r = dib0070_read_reg(state, 0x02) & 0xffdf; dib0070_reset()
703 dib0070_write_reg(state, 0x02, r | (1 << 5)); dib0070_reset()
706 if (state->revision == DIB0070S_P1A) dib0070_reset()
709 dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump, state->cfg->enable_third_order_filter); dib0070_reset()
711 dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8); dib0070_reset()
713 dib0070_wbd_offset_calibration(state); dib0070_reset()
720 struct dib0070_state *state = fe->tuner_priv; dib0070_get_frequency() local
722 *frequency = 1000 * state->current_rf; dib0070_get_frequency()
752 struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL); dib0070_attach() local
753 if (state == NULL) dib0070_attach()
756 state->cfg = cfg; dib0070_attach()
757 state->i2c = i2c; dib0070_attach()
758 state->fe = fe; dib0070_attach()
759 mutex_init(&state->i2c_buffer_lock); dib0070_attach()
760 fe->tuner_priv = state; dib0070_attach()
768 fe->tuner_priv = state; dib0070_attach()
772 kfree(state); dib0070_attach()
H A Dtda18271c2dd.c119 static int PowerScan(struct tda_state *state,
142 static int WriteRegs(struct tda_state *state, WriteRegs() argument
156 return i2c_write(state->i2c, state->adr, data, nRegs + 1); WriteRegs()
159 static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) WriteReg() argument
163 return i2c_write(state->i2c, state->adr, msg, 2); WriteReg()
166 static int Read(struct tda_state *state, u8 * Regs) Read() argument
168 return i2c_readn(state->i2c, state->adr, Regs, 16); Read()
171 static int ReadExtented(struct tda_state *state, u8 * Regs) ReadExtented() argument
173 return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS); ReadExtented()
176 static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo) UpdateRegs() argument
178 return WriteRegs(state, RegFrom, UpdateRegs()
179 &state->m_Regs[RegFrom], RegTo-RegFrom+1); UpdateRegs()
181 static int UpdateReg(struct tda_state *state, u8 Reg) UpdateReg() argument
183 return WriteReg(state, Reg, state->m_Regs[Reg]); UpdateReg()
188 static void reset(struct tda_state *state) reset() argument
200 state->m_Frequency = 0; reset()
201 state->m_SettlingTime = 100; reset()
202 state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2; reset()
203 state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2; reset()
204 state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2; reset()
205 state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2; reset()
207 state->m_EP4 = 0x20; reset()
209 state->m_EP4 |= 0x40; reset()
211 state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F; reset()
212 state->m_bMaster = (ulSlave == 0); reset()
214 state->m_SettlingTime = ulSettlingTime; reset()
216 state->m_bFMInput = (ulFMInput == 2); reset()
274 static int ThermometerRead(struct tda_state *state, u8 *pTM_Value) ThermometerRead() argument
280 state->m_Regs[TM] |= 0x10; ThermometerRead()
281 status = UpdateReg(state, TM); ThermometerRead()
284 status = Read(state, Regs); ThermometerRead()
289 state->m_Regs[TM] ^= 0x20; ThermometerRead()
290 status = UpdateReg(state, TM); ThermometerRead()
294 status = Read(state, Regs); ThermometerRead()
301 state->m_Regs[TM] &= ~0x10; /* Thermometer off */ ThermometerRead()
302 status = UpdateReg(state, TM); ThermometerRead()
305 state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */ ThermometerRead()
306 status = UpdateReg(state, EP4); ThermometerRead()
314 static int StandBy(struct tda_state *state) StandBy() argument
318 state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */ StandBy()
319 status = UpdateReg(state, EB12); StandBy()
322 state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */ StandBy()
323 status = UpdateReg(state, EB18); StandBy()
326 state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */ StandBy()
327 state->m_Regs[EP3] = state->m_EP3_Standby; StandBy()
328 status = UpdateReg(state, EP3); StandBy()
331 state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */ StandBy()
332 status = UpdateRegs(state, EB21, EB23); StandBy()
339 static int CalcMainPLL(struct tda_state *state, u32 freq) CalcMainPLL() argument
355 state->m_Regs[MPD] = PostDiv & 0x77; CalcMainPLL()
356 state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F); CalcMainPLL()
357 state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF); CalcMainPLL()
358 state->m_Regs[MD3] = (MainDiv & 0xFF); CalcMainPLL()
360 return UpdateRegs(state, MPD, MD3); CalcMainPLL()
363 static int CalcCalPLL(struct tda_state *state, u32 freq) CalcCalPLL() argument
379 state->m_Regs[CPD] = PostDiv; CalcCalPLL()
380 state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF); CalcCalPLL()
381 state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF); CalcCalPLL()
382 state->m_Regs[CD3] = (CalDiv & 0xFF); CalcCalPLL()
384 return UpdateRegs(state, CPD, CD3); CalcCalPLL()
387 static int CalibrateRF(struct tda_state *state, CalibrateRF() argument
398 state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */ CalibrateRF()
399 status = UpdateReg(state, EP4); CalibrateRF()
402 state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */ CalibrateRF()
403 status = UpdateReg(state, EB18); CalibrateRF()
409 if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */ CalibrateRF()
410 state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */ CalibrateRF()
417 state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter; CalibrateRF()
418 state->m_Regs[EP2] = (RFBand << 5) | GainTaper; CalibrateRF()
420 state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2); CalibrateRF()
422 status = UpdateRegs(state, EP1, EP3); CalibrateRF()
425 status = UpdateReg(state, EB13); CalibrateRF()
429 state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */ CalibrateRF()
430 status = UpdateReg(state, EB4); CalibrateRF()
434 state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */ CalibrateRF()
435 status = UpdateReg(state, EB7); CalibrateRF()
439 state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */ CalibrateRF()
440 status = UpdateReg(state, EB14); CalibrateRF()
444 state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */ CalibrateRF()
445 status = UpdateReg(state, EB20); CalibrateRF()
449 state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */ CalibrateRF()
450 status = UpdateRegs(state, EP4, EP5); CalibrateRF()
454 status = CalcCalPLL(state, freq); CalibrateRF()
457 status = CalcMainPLL(state, freq + 1000000); CalibrateRF()
462 status = UpdateReg(state, EP2); CalibrateRF()
465 status = UpdateReg(state, EP1); CalibrateRF()
468 status = UpdateReg(state, EP2); CalibrateRF()
471 status = UpdateReg(state, EP1); CalibrateRF()
475 state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */ CalibrateRF()
476 status = UpdateReg(state, EB4); CalibrateRF()
480 state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */ CalibrateRF()
481 status = UpdateReg(state, EB7); CalibrateRF()
486 state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */ CalibrateRF()
487 status = UpdateReg(state, EB20); CalibrateRF()
492 state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */ CalibrateRF()
493 state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */ CalibrateRF()
494 state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */ CalibrateRF()
495 status = UpdateReg(state, EB18); CalibrateRF()
498 status = UpdateRegs(state, EP3, EP4); CalibrateRF()
501 status = UpdateReg(state, EP1); CalibrateRF()
505 status = ReadExtented(state, Regs); CalibrateRF()
515 static int RFTrackingFiltersInit(struct tda_state *state, RFTrackingFiltersInit() argument
532 state->m_RF_A1[RFBand] = 0; RFTrackingFiltersInit()
533 state->m_RF_B1[RFBand] = 0; RFTrackingFiltersInit()
534 state->m_RF_A2[RFBand] = 0; RFTrackingFiltersInit()
535 state->m_RF_B2[RFBand] = 0; RFTrackingFiltersInit()
538 status = PowerScan(state, RFBand, RF1, &RF1, &bcal); RFTrackingFiltersInit()
542 status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1); RFTrackingFiltersInit()
549 state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1; RFTrackingFiltersInit()
550 /* state->m_RF_A1[RF_Band] = ???? */ RFTrackingFiltersInit()
555 status = PowerScan(state, RFBand, RF2, &RF2, &bcal); RFTrackingFiltersInit()
559 status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2); RFTrackingFiltersInit()
567 state->m_RF_A1[RFBand] = RFTrackingFiltersInit()
574 status = PowerScan(state, RFBand, RF3, &RF3, &bcal); RFTrackingFiltersInit()
578 status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3); RFTrackingFiltersInit()
585 state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2)); RFTrackingFiltersInit()
586 state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2; RFTrackingFiltersInit()
590 state->m_RF1[RFBand] = RF1; RFTrackingFiltersInit()
591 state->m_RF2[RFBand] = RF2; RFTrackingFiltersInit()
592 state->m_RF3[RFBand] = RF3; RFTrackingFiltersInit()
596 RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2, RFTrackingFiltersInit()
597 state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3); RFTrackingFiltersInit()
603 static int PowerScan(struct tda_state *state, PowerScan() argument
627 state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper; PowerScan()
628 state->m_Regs[EB14] = (RFC_Cprog); PowerScan()
629 status = UpdateReg(state, EP2); PowerScan()
632 status = UpdateReg(state, EB14); PowerScan()
637 status = CalcMainPLL(state, freq_MainPLL); PowerScan()
641 state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */ PowerScan()
642 status = UpdateReg(state, EP4); PowerScan()
645 status = UpdateReg(state, EP2); /* Launch power measurement */ PowerScan()
648 status = ReadExtented(state, Regs); PowerScan()
652 state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */ PowerScan()
658 status = CalcMainPLL(state, freq_MainPLL); PowerScan()
663 status = UpdateReg(state, EP2); /* Launch power measurement */ PowerScan()
666 status = ReadExtented(state, Regs); PowerScan()
694 static int PowerScanInit(struct tda_state *state) PowerScanInit() argument
698 state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12; PowerScanInit()
699 state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */ PowerScanInit()
700 status = UpdateRegs(state, EP3, EP4); PowerScanInit()
703 state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */ PowerScanInit()
704 status = UpdateReg(state, EB18); PowerScanInit()
707 state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */ PowerScanInit()
708 state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ PowerScanInit()
709 status = UpdateRegs(state, EB21, EB23); PowerScanInit()
716 static int CalcRFFilterCurve(struct tda_state *state) CalcRFFilterCurve() argument
721 status = PowerScanInit(state); CalcRFFilterCurve()
724 status = RFTrackingFiltersInit(state, 0); CalcRFFilterCurve()
727 status = RFTrackingFiltersInit(state, 1); CalcRFFilterCurve()
730 status = RFTrackingFiltersInit(state, 2); CalcRFFilterCurve()
733 status = RFTrackingFiltersInit(state, 3); CalcRFFilterCurve()
736 status = RFTrackingFiltersInit(state, 4); CalcRFFilterCurve()
739 status = RFTrackingFiltersInit(state, 5); CalcRFFilterCurve()
742 status = RFTrackingFiltersInit(state, 6); CalcRFFilterCurve()
745 status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */ CalcRFFilterCurve()
753 static int FixedContentsI2CUpdate(struct tda_state *state) FixedContentsI2CUpdate() argument
768 memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1); FixedContentsI2CUpdate()
770 status = UpdateRegs(state, TM, EB23); FixedContentsI2CUpdate()
775 state->m_Regs[EB17] = 0x00; FixedContentsI2CUpdate()
776 status = UpdateReg(state, EB17); FixedContentsI2CUpdate()
779 state->m_Regs[EB17] = 0x03; FixedContentsI2CUpdate()
780 status = UpdateReg(state, EB17); FixedContentsI2CUpdate()
783 state->m_Regs[EB17] = 0x43; FixedContentsI2CUpdate()
784 status = UpdateReg(state, EB17); FixedContentsI2CUpdate()
787 state->m_Regs[EB17] = 0x4C; FixedContentsI2CUpdate()
788 status = UpdateReg(state, EB17); FixedContentsI2CUpdate()
793 state->m_Regs[EP3] = 0x1F; FixedContentsI2CUpdate()
794 state->m_Regs[EP4] = 0x66; FixedContentsI2CUpdate()
795 state->m_Regs[EP5] = 0x81; FixedContentsI2CUpdate()
796 state->m_Regs[CPD] = 0xCC; FixedContentsI2CUpdate()
797 state->m_Regs[CD1] = 0x6C; FixedContentsI2CUpdate()
798 state->m_Regs[CD2] = 0x00; FixedContentsI2CUpdate()
799 state->m_Regs[CD3] = 0x00; FixedContentsI2CUpdate()
800 state->m_Regs[MPD] = 0xC5; FixedContentsI2CUpdate()
801 state->m_Regs[MD1] = 0x77; FixedContentsI2CUpdate()
802 state->m_Regs[MD2] = 0x08; FixedContentsI2CUpdate()
803 state->m_Regs[MD3] = 0x00; FixedContentsI2CUpdate()
804 status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */ FixedContentsI2CUpdate()
809 state->m_Regs[EB4] = 0x61; /* missing in sw */ FixedContentsI2CUpdate()
810 status = UpdateReg(state, EB4); FixedContentsI2CUpdate()
814 state->m_Regs[EB4] = 0x41; FixedContentsI2CUpdate()
815 status = UpdateReg(state, EB4); FixedContentsI2CUpdate()
821 status = UpdateReg(state, EP1); FixedContentsI2CUpdate()
826 state->m_Regs[EP5] = 0x85; FixedContentsI2CUpdate()
827 state->m_Regs[CPD] = 0xCB; FixedContentsI2CUpdate()
828 state->m_Regs[CD1] = 0x66; FixedContentsI2CUpdate()
829 state->m_Regs[CD2] = 0x70; FixedContentsI2CUpdate()
830 status = UpdateRegs(state, EP3, CD3); FixedContentsI2CUpdate()
834 status = UpdateReg(state, EP2); FixedContentsI2CUpdate()
840 state->m_Regs[EP5] = 0x82; FixedContentsI2CUpdate()
841 state->m_Regs[CPD] = 0xA8; FixedContentsI2CUpdate()
842 state->m_Regs[CD2] = 0x00; FixedContentsI2CUpdate()
843 state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */ FixedContentsI2CUpdate()
844 state->m_Regs[MD1] = 0x73; FixedContentsI2CUpdate()
845 state->m_Regs[MD2] = 0x1A; FixedContentsI2CUpdate()
846 status = UpdateRegs(state, EP3, MD3); FixedContentsI2CUpdate()
851 status = UpdateReg(state, EP1); FixedContentsI2CUpdate()
856 state->m_Regs[EP5] = 0x86; FixedContentsI2CUpdate()
857 state->m_Regs[CPD] = 0xA8; FixedContentsI2CUpdate()
858 state->m_Regs[CD1] = 0x66; FixedContentsI2CUpdate()
859 state->m_Regs[CD2] = 0xA0; FixedContentsI2CUpdate()
860 status = UpdateRegs(state, EP3, CD3); FixedContentsI2CUpdate()
864 status = UpdateReg(state, EP2); FixedContentsI2CUpdate()
870 state->m_Regs[EP5] = 0x83; FixedContentsI2CUpdate()
871 state->m_Regs[CPD] = 0x98; FixedContentsI2CUpdate()
872 state->m_Regs[CD1] = 0x65; FixedContentsI2CUpdate()
873 state->m_Regs[CD2] = 0x00; FixedContentsI2CUpdate()
874 state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */ FixedContentsI2CUpdate()
875 state->m_Regs[MD1] = 0x71; FixedContentsI2CUpdate()
876 state->m_Regs[MD2] = 0xCD; FixedContentsI2CUpdate()
877 status = UpdateRegs(state, EP3, MD3); FixedContentsI2CUpdate()
881 status = UpdateReg(state, EP1); FixedContentsI2CUpdate()
885 state->m_Regs[EP5] = 0x87; FixedContentsI2CUpdate()
886 state->m_Regs[CD1] = 0x65; FixedContentsI2CUpdate()
887 state->m_Regs[CD2] = 0x50; FixedContentsI2CUpdate()
888 status = UpdateRegs(state, EP3, CD3); FixedContentsI2CUpdate()
892 status = UpdateReg(state, EP2); FixedContentsI2CUpdate()
898 state->m_Regs[EP4] = 0x64; FixedContentsI2CUpdate()
899 status = UpdateReg(state, EP4); FixedContentsI2CUpdate()
902 status = UpdateReg(state, EP1); FixedContentsI2CUpdate()
910 static int InitCal(struct tda_state *state) InitCal() argument
915 status = FixedContentsI2CUpdate(state); InitCal()
918 status = CalcRFFilterCurve(state); InitCal()
921 status = StandBy(state); InitCal()
929 static int RFTrackingFiltersCorrection(struct tda_state *state, RFTrackingFiltersCorrection() argument
945 u32 RF1 = state->m_RF1[RFBand]; RFTrackingFiltersCorrection()
946 u32 RF2 = state->m_RF1[RFBand]; RFTrackingFiltersCorrection()
947 u32 RF3 = state->m_RF1[RFBand]; RFTrackingFiltersCorrection()
948 s32 RF_A1 = state->m_RF_A1[RFBand]; RFTrackingFiltersCorrection()
949 s32 RF_B1 = state->m_RF_B1[RFBand]; RFTrackingFiltersCorrection()
950 s32 RF_A2 = state->m_RF_A2[RFBand]; RFTrackingFiltersCorrection()
951 s32 RF_B2 = state->m_RF_B2[RFBand]; RFTrackingFiltersCorrection()
955 state->m_Regs[EP3] &= ~0xE0; /* Power up */ RFTrackingFiltersCorrection()
956 status = UpdateReg(state, EP3); RFTrackingFiltersCorrection()
960 status = ThermometerRead(state, &TMValue_Current); RFTrackingFiltersCorrection()
969 TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000; RFTrackingFiltersCorrection()
981 state->m_Regs[EB14] = Capprox; RFTrackingFiltersCorrection()
983 status = UpdateReg(state, EB14); RFTrackingFiltersCorrection()
991 static int ChannelConfiguration(struct tda_state *state, ChannelConfiguration() argument
1003 state->IF = IntermediateFrequency; ChannelConfiguration()
1017 state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0; ChannelConfiguration()
1018 state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */ ChannelConfiguration()
1021 state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog); ChannelConfiguration()
1022 /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */ ChannelConfiguration()
1024 state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog; ChannelConfiguration()
1026 state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT; ChannelConfiguration()
1028 state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC; ChannelConfiguration()
1030 state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; ChannelConfiguration()
1032 if ((Standard == HF_FM_Radio) && state->m_bFMInput) ChannelConfiguration()
1033 state->m_Regs[EP4] |= 0x80; ChannelConfiguration()
1035 state->m_Regs[MPD] &= ~0x80; ChannelConfiguration()
1037 state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */ ChannelConfiguration()
1039 state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22; ChannelConfiguration()
1043 state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ ChannelConfiguration()
1045 state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */ ChannelConfiguration()
1047 status = UpdateRegs(state, EB22, EB23); ChannelConfiguration()
1051 state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */ ChannelConfiguration()
1052 state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas; ChannelConfiguration()
1053 state->m_Regs[EP2] = (RF_Band << 5) | GainTaper; ChannelConfiguration()
1055 state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) | ChannelConfiguration()
1056 (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */ ChannelConfiguration()
1059 status = UpdateReg(state, EB1); ChannelConfiguration()
1063 if (state->m_bMaster) { ChannelConfiguration()
1064 status = CalcMainPLL(state, Frequency + IntermediateFrequency); ChannelConfiguration()
1067 status = UpdateRegs(state, TM, EP5); ChannelConfiguration()
1070 state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */ ChannelConfiguration()
1071 status = UpdateReg(state, EB4); ChannelConfiguration()
1075 state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ ChannelConfiguration()
1076 status = UpdateReg(state, EB4); ChannelConfiguration()
1082 status = CalcCalPLL(state, Frequency + IntermediateFrequency); ChannelConfiguration()
1087 state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77); ChannelConfiguration()
1088 status = UpdateReg(state, MPD); ChannelConfiguration()
1091 status = UpdateRegs(state, TM, EP5); ChannelConfiguration()
1095 state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */ ChannelConfiguration()
1096 status = UpdateReg(state, EB7); ChannelConfiguration()
1100 state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */ ChannelConfiguration()
1101 status = UpdateReg(state, EB7); ChannelConfiguration()
1107 state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */ ChannelConfiguration()
1108 status = UpdateReg(state, EP3); ChannelConfiguration()
1118 struct tda_state *state = fe->tuner_priv; sleep() local
1120 StandBy(state); sleep()
1139 struct tda_state *state = fe->tuner_priv; set_params() local
1145 state->m_Frequency = fe->dtv_property_cache.frequency; set_params()
1176 status = RFTrackingFiltersCorrection(state, state->m_Frequency); set_params()
1179 status = ChannelConfiguration(state, state->m_Frequency, set_params()
1184 msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ set_params()
1206 struct tda_state *state = fe->tuner_priv; get_if_frequency() local
1208 *frequency = state->IF; get_if_frequency()
1214 /* struct tda_state *state = fe->tuner_priv; */ get_bandwidth()
1238 struct tda_state *state; tda18271c2dd_attach() local
1240 state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); tda18271c2dd_attach()
1241 if (!state) tda18271c2dd_attach()
1244 fe->tuner_priv = state; tda18271c2dd_attach()
1245 state->adr = adr; tda18271c2dd_attach()
1246 state->i2c = i2c; tda18271c2dd_attach()
1248 reset(state); tda18271c2dd_attach()
1249 InitCal(state); tda18271c2dd_attach()
H A Ddib3000mc.c50 static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg) dib3000mc_read_word() argument
55 { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 }, dib3000mc_read_word()
56 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 }, dib3000mc_read_word()
59 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) dib3000mc_read_word()
65 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) dib3000mc_write_word() argument
72 .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4 dib3000mc_write_word()
74 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; dib3000mc_write_word()
77 static int dib3000mc_identify(struct dib3000mc_state *state) dib3000mc_identify() argument
80 if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) { dib3000mc_identify()
85 value = dib3000mc_read_word(state, 1026); dib3000mc_identify()
90 state->dev_id = value; dib3000mc_identify()
92 dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id); dib3000mc_identify()
97 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset) dib3000mc_set_timing() argument
101 if (state->timf == 0) { dib3000mc_set_timing()
106 timf = state->timf; dib3000mc_set_timing()
111 s16 tim_offs = dib3000mc_read_word(state, 416); dib3000mc_set_timing()
120 state->timf = timf / (bw / 1000); dib3000mc_set_timing()
125 dib3000mc_write_word(state, 23, (u16) (timf >> 16)); dib3000mc_set_timing()
126 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff); dib3000mc_set_timing()
131 static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state) dib3000mc_setup_pwm_state() argument
133 u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb; dib3000mc_setup_pwm_state()
134 if (state->cfg->pwm3_inversion) { dib3000mc_setup_pwm_state()
141 dib3000mc_write_word(state, 51, reg_51); dib3000mc_setup_pwm_state()
142 dib3000mc_write_word(state, 52, reg_52); dib3000mc_setup_pwm_state()
144 if (state->cfg->use_pwm3) dib3000mc_setup_pwm_state()
145 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0)); dib3000mc_setup_pwm_state()
147 dib3000mc_write_word(state, 245, 0); dib3000mc_setup_pwm_state()
149 dib3000mc_write_word(state, 1040, 0x3); dib3000mc_setup_pwm_state()
153 static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode) dib3000mc_set_output_mode() argument
160 u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */ dib3000mc_set_output_mode()
163 &state->demod, mode); dib3000mc_set_output_mode()
197 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod); dib3000mc_set_output_mode()
202 if ((state->cfg->output_mpeg2_in_188_bytes)) dib3000mc_set_output_mode()
205 outreg = dib3000mc_read_word(state, 244) & 0x07FF; dib3000mc_set_output_mode()
207 ret |= dib3000mc_write_word(state, 244, outreg); dib3000mc_set_output_mode()
208 ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/ dib3000mc_set_output_mode()
209 ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */ dib3000mc_set_output_mode()
210 ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */ dib3000mc_set_output_mode()
214 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw) dib3000mc_set_bandwidth() argument
246 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]); dib3000mc_set_bandwidth()
247 dib3000mc_write_word(state, 12, 0x0000); dib3000mc_set_bandwidth()
248 dib3000mc_write_word(state, 13, 0x03e8); dib3000mc_set_bandwidth()
249 dib3000mc_write_word(state, 14, 0x0000); dib3000mc_set_bandwidth()
250 dib3000mc_write_word(state, 15, 0x03f2); dib3000mc_set_bandwidth()
251 dib3000mc_write_word(state, 16, 0x0001); dib3000mc_set_bandwidth()
252 dib3000mc_write_word(state, 17, 0xb0d0); dib3000mc_set_bandwidth()
254 dib3000mc_write_word(state, 18, 0x0393); dib3000mc_set_bandwidth()
255 dib3000mc_write_word(state, 19, 0x8700); dib3000mc_set_bandwidth()
258 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]); dib3000mc_set_bandwidth()
261 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0); dib3000mc_set_bandwidth()
274 static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft) dib3000mc_set_impulse_noise() argument
278 dib3000mc_write_word(state, i, impulse_noise_val[i-58]); dib3000mc_set_impulse_noise()
281 dib3000mc_write_word(state, 58, 0x3b); dib3000mc_set_impulse_noise()
282 dib3000mc_write_word(state, 84, 0x00); dib3000mc_set_impulse_noise()
283 dib3000mc_write_word(state, 85, 0x8200); dib3000mc_set_impulse_noise()
286 dib3000mc_write_word(state, 34, 0x1294); dib3000mc_set_impulse_noise()
287 dib3000mc_write_word(state, 35, 0x1ff8); dib3000mc_set_impulse_noise()
289 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10)); dib3000mc_set_impulse_noise()
294 struct dib3000mc_state *state = demod->demodulator_priv; dib3000mc_init() local
295 struct dibx000_agc_config *agc = state->cfg->agc; dib3000mc_init()
298 dib3000mc_write_word(state, 1027, 0x8000); dib3000mc_init()
299 dib3000mc_write_word(state, 1027, 0x0000); dib3000mc_init()
302 dib3000mc_write_word(state, 140, 0x0000); dib3000mc_init()
303 dib3000mc_write_word(state, 1031, 0); dib3000mc_init()
305 if (state->cfg->mobile_mode) { dib3000mc_init()
306 dib3000mc_write_word(state, 139, 0x0000); dib3000mc_init()
307 dib3000mc_write_word(state, 141, 0x0000); dib3000mc_init()
308 dib3000mc_write_word(state, 175, 0x0002); dib3000mc_init()
309 dib3000mc_write_word(state, 1032, 0x0000); dib3000mc_init()
311 dib3000mc_write_word(state, 139, 0x0001); dib3000mc_init()
312 dib3000mc_write_word(state, 141, 0x0000); dib3000mc_init()
313 dib3000mc_write_word(state, 175, 0x0000); dib3000mc_init()
314 dib3000mc_write_word(state, 1032, 0x012C); dib3000mc_init()
316 dib3000mc_write_word(state, 1033, 0x0000); dib3000mc_init()
319 dib3000mc_write_word(state, 1037, 0x3130); dib3000mc_init()
324 dib3000mc_write_word(state, 33, (5 << 0)); dib3000mc_init()
325 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0)); dib3000mc_init()
329 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0)); dib3000mc_init()
331 if (state->cfg->phase_noise_mode == 0) dib3000mc_init()
332 dib3000mc_write_word(state, 111, 0x00); dib3000mc_init()
334 dib3000mc_write_word(state, 111, 0x02); dib3000mc_init()
337 dib3000mc_write_word(state, 50, 0x8000); dib3000mc_init()
340 dib3000mc_setup_pwm_state(state); dib3000mc_init()
343 dib3000mc_write_word(state, 53, 0x87); dib3000mc_init()
345 dib3000mc_write_word(state, 54, 0x87); dib3000mc_init()
348 dib3000mc_write_word(state, 36, state->cfg->max_time); dib3000mc_init()
349 dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0)); dib3000mc_init()
350 dib3000mc_write_word(state, 38, state->cfg->pwm3_value); dib3000mc_init()
351 dib3000mc_write_word(state, 39, state->cfg->ln_adc_level); dib3000mc_init()
354 dib3000mc_write_word(state, 40, 0x0179); dib3000mc_init()
355 dib3000mc_write_word(state, 41, 0x03f0); dib3000mc_init()
357 dib3000mc_write_word(state, 42, agc->agc1_max); dib3000mc_init()
358 dib3000mc_write_word(state, 43, agc->agc1_min); dib3000mc_init()
359 dib3000mc_write_word(state, 44, agc->agc2_max); dib3000mc_init()
360 dib3000mc_write_word(state, 45, agc->agc2_min); dib3000mc_init()
361 dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2); dib3000mc_init()
362 dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2); dib3000mc_init()
363 dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2); dib3000mc_init()
364 dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2); dib3000mc_init()
368 dib3000mc_write_word(state, 110, 3277); dib3000mc_init()
370 dib3000mc_write_word(state, 26, 0x6680); dib3000mc_init()
372 dib3000mc_write_word(state, 1, 4); dib3000mc_init()
374 dib3000mc_write_word(state, 2, 4); dib3000mc_init()
376 dib3000mc_write_word(state, 3, 0x1000); dib3000mc_init()
378 dib3000mc_write_word(state, 5, 1); dib3000mc_init()
380 dib3000mc_set_bandwidth(state, 8000); dib3000mc_init()
383 dib3000mc_write_word(state, 4, 0x814); dib3000mc_init()
385 dib3000mc_write_word(state, 21, (1 << 9) | 0x164); dib3000mc_init()
386 dib3000mc_write_word(state, 22, 0x463d); dib3000mc_init()
390 dib3000mc_write_word(state, 120, 0x200f); dib3000mc_init()
392 dib3000mc_write_word(state, 134, 0); dib3000mc_init()
395 dib3000mc_write_word(state, 195, 0x10); dib3000mc_init()
398 dib3000mc_write_word(state, 180, 0x2FF0); dib3000mc_init()
401 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K); dib3000mc_init()
404 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); dib3000mc_init()
407 dib3000mc_write_word(state, 769, (1 << 7) ); dib3000mc_init()
414 struct dib3000mc_state *state = demod->demodulator_priv; dib3000mc_sleep() local
416 dib3000mc_write_word(state, 1031, 0xFFFF); dib3000mc_sleep()
417 dib3000mc_write_word(state, 1032, 0xFFFF); dib3000mc_sleep()
418 dib3000mc_write_word(state, 1033, 0xFFF0); dib3000mc_sleep()
423 static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam) dib3000mc_set_adp_cfg() argument
438 dib3000mc_write_word(state, reg, cfg[reg - 129]); dib3000mc_set_adp_cfg()
441 static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, dib3000mc_set_channel_cfg() argument
447 dib3000mc_set_bandwidth(state, bw); dib3000mc_set_channel_cfg()
448 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0); dib3000mc_set_channel_cfg()
451 // dib3000mc_write_word(state, 100, (11 << 6) + 6); dib3000mc_set_channel_cfg()
453 dib3000mc_write_word(state, 100, (16 << 6) + 9); dib3000mc_set_channel_cfg()
455 dib3000mc_write_word(state, 1027, 0x0800); dib3000mc_set_channel_cfg()
456 dib3000mc_write_word(state, 1027, 0x0000); dib3000mc_set_channel_cfg()
459 dib3000mc_write_word(state, 26, 0x6680); dib3000mc_set_channel_cfg()
460 dib3000mc_write_word(state, 29, 0x1273); dib3000mc_set_channel_cfg()
461 dib3000mc_write_word(state, 33, 5); dib3000mc_set_channel_cfg()
462 dib3000mc_set_adp_cfg(state, QAM_16); dib3000mc_set_channel_cfg()
463 dib3000mc_write_word(state, 133, 15564); dib3000mc_set_channel_cfg()
465 dib3000mc_write_word(state, 12 , 0x0); dib3000mc_set_channel_cfg()
466 dib3000mc_write_word(state, 13 , 0x3e8); dib3000mc_set_channel_cfg()
467 dib3000mc_write_word(state, 14 , 0x0); dib3000mc_set_channel_cfg()
468 dib3000mc_write_word(state, 15 , 0x3f2); dib3000mc_set_channel_cfg()
470 dib3000mc_write_word(state, 93,0); dib3000mc_set_channel_cfg()
471 dib3000mc_write_word(state, 94,0); dib3000mc_set_channel_cfg()
472 dib3000mc_write_word(state, 95,0); dib3000mc_set_channel_cfg()
473 dib3000mc_write_word(state, 96,0); dib3000mc_set_channel_cfg()
474 dib3000mc_write_word(state, 97,0); dib3000mc_set_channel_cfg()
475 dib3000mc_write_word(state, 98,0); dib3000mc_set_channel_cfg()
477 dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode); dib3000mc_set_channel_cfg()
504 dib3000mc_write_word(state, 0, value); dib3000mc_set_channel_cfg()
505 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); dib3000mc_set_channel_cfg()
520 dib3000mc_write_word(state, 181, value); dib3000mc_set_channel_cfg()
536 value |= dib3000mc_read_word(state, 180) & 0x000f; dib3000mc_set_channel_cfg()
537 dib3000mc_write_word(state, 180, value); dib3000mc_set_channel_cfg()
540 value = dib3000mc_read_word(state, 0); dib3000mc_set_channel_cfg()
541 dib3000mc_write_word(state, 0, value | (1 << 9)); dib3000mc_set_channel_cfg()
542 dib3000mc_write_word(state, 0, value); dib3000mc_set_channel_cfg()
546 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode); dib3000mc_set_channel_cfg()
552 struct dib3000mc_state *state = demod->demodulator_priv; dib3000mc_autosearch_start() local
569 dib3000mc_set_channel_cfg(state, &schan, 11); dib3000mc_autosearch_start()
571 reg = dib3000mc_read_word(state, 0); dib3000mc_autosearch_start()
572 dib3000mc_write_word(state, 0, reg | (1 << 8)); dib3000mc_autosearch_start()
573 dib3000mc_read_word(state, 511); dib3000mc_autosearch_start()
574 dib3000mc_write_word(state, 0, reg); dib3000mc_autosearch_start()
581 struct dib3000mc_state *state = demod->demodulator_priv; dib3000mc_autosearch_is_irq() local
582 u16 irq_pending = dib3000mc_read_word(state, 511); dib3000mc_autosearch_is_irq()
596 struct dib3000mc_state *state = demod->demodulator_priv; dib3000mc_tune() local
599 dib3000mc_set_channel_cfg(state, ch, 0); dib3000mc_tune()
602 if (state->sfn_workaround_active) { dib3000mc_tune()
604 dib3000mc_write_word(state, 29, 0x1273); dib3000mc_tune()
605 dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift dib3000mc_tune()
607 dib3000mc_write_word(state, 29, 0x1073); dib3000mc_tune()
608 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift dib3000mc_tune()
611 dib3000mc_set_adp_cfg(state, (u8)ch->modulation); dib3000mc_tune()
613 dib3000mc_write_word(state, 26, 38528); dib3000mc_tune()
614 dib3000mc_write_word(state, 33, 8); dib3000mc_tune()
616 dib3000mc_write_word(state, 26, 30336); dib3000mc_tune()
617 dib3000mc_write_word(state, 33, 6); dib3000mc_tune()
620 if (dib3000mc_read_word(state, 509) & 0x80) dib3000mc_tune()
621 dib3000mc_set_timing(state, ch->transmission_mode, dib3000mc_tune()
638 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_get_frontend() local
639 u16 tps = dib3000mc_read_word(state,458); dib3000mc_get_frontend()
643 fep->bandwidth_hz = state->current_bandwidth; dib3000mc_get_frontend()
693 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_set_frontend() local
696 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); dib3000mc_set_frontend()
698 state->current_bandwidth = fep->bandwidth_hz; dib3000mc_set_frontend()
699 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz)); dib3000mc_set_frontend()
702 state->sfn_workaround_active = buggy_sfn_workaround; dib3000mc_set_frontend()
731 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO); dib3000mc_set_frontend()
737 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_read_status() local
738 u16 lock = dib3000mc_read_word(state, 509); dib3000mc_read_status()
758 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_read_ber() local
759 *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501); dib3000mc_read_ber()
765 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_read_unc_blocks() local
766 *unc = dib3000mc_read_word(state, 508); dib3000mc_read_unc_blocks()
772 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_read_signal_strength() local
773 u16 val = dib3000mc_read_word(state, 392); dib3000mc_read_signal_strength()
792 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_release() local
793 dibx000_exit_i2c_master(&state->i2c_master); dib3000mc_release()
794 kfree(state); dib3000mc_release()
799 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_pid_control() local
800 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0); dib3000mc_pid_control()
807 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_pid_parse() local
808 u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4); dib3000mc_pid_parse()
810 return dib3000mc_write_word(state, 206, tmp); dib3000mc_pid_parse()
816 struct dib3000mc_state *state = fe->demodulator_priv; dib3000mc_set_config() local
817 state->cfg = cfg; dib3000mc_set_config()
H A Dstb0899_drv.c225 static int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg) _stb0899_read_reg() argument
234 .addr = state->config->demod_address, _stb0899_read_reg()
239 .addr = state->config->demod_address, _stb0899_read_reg()
246 ret = i2c_transfer(state->i2c, msg, 2); _stb0899_read_reg()
249 dprintk(state->verbose, FE_ERROR, 1, _stb0899_read_reg()
255 if (unlikely(*state->verbose >= FE_DEBUGREG)) _stb0899_read_reg()
256 dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%02x], data=%02x", _stb0899_read_reg()
262 int stb0899_read_reg(struct stb0899_state *state, unsigned int reg) stb0899_read_reg() argument
266 result = _stb0899_read_reg(state, reg); stb0899_read_reg()
274 _stb0899_read_reg(state, (reg | 0x00ff)); stb0899_read_reg()
279 u32 _stb0899_read_s2reg(struct stb0899_state *state, _stb0899_read_s2reg() argument
303 .addr = state->config->demod_address, _stb0899_read_s2reg()
310 .addr = state->config->demod_address, _stb0899_read_s2reg()
317 .addr = state->config->demod_address, _stb0899_read_s2reg()
330 status = i2c_transfer(state->i2c, &msg_0, 1); _stb0899_read_s2reg()
340 status = i2c_transfer(state->i2c, &msg_1, 1); _stb0899_read_s2reg()
344 status = i2c_transfer(state->i2c, &msg_r, 1); _stb0899_read_s2reg()
352 status = i2c_transfer(state->i2c, &msg_1, 1); _stb0899_read_s2reg()
360 status = i2c_transfer(state->i2c, &msg_r, 1); _stb0899_read_s2reg()
369 if (unlikely(*state->verbose >= FE_DEBUGREG)) _stb0899_read_s2reg()
379 int stb0899_write_s2reg(struct stb0899_state *state, stb0899_write_s2reg() argument
406 .addr = state->config->demod_address, stb0899_write_s2reg()
413 .addr = state->config->demod_address, stb0899_write_s2reg()
426 if (unlikely(*state->verbose >= FE_DEBUGREG)) stb0899_write_s2reg()
430 status = i2c_transfer(state->i2c, &msg_0, 1); stb0899_write_s2reg()
437 status = i2c_transfer(state->i2c, &msg_1, 1); stb0899_write_s2reg()
452 int stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, u32 count) stb0899_read_regs() argument
460 .addr = state->config->demod_address, stb0899_read_regs()
465 .addr = state->config->demod_address, stb0899_read_regs()
472 status = i2c_transfer(state->i2c, msg, 2); stb0899_read_regs()
486 _stb0899_read_reg(state, (reg | 0x00ff)); stb0899_read_regs()
488 if (unlikely(*state->verbose >= FE_DEBUGREG)) { stb0899_read_regs()
503 int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, u32 count) stb0899_write_regs() argument
508 .addr = state->config->demod_address, stb0899_write_regs()
525 if (unlikely(*state->verbose >= FE_DEBUGREG)) { stb0899_write_regs()
533 ret = i2c_transfer(state->i2c, &i2c_msg, 1); stb0899_write_regs()
541 stb0899_read_reg(state, (reg | 0x00ff)); stb0899_write_regs()
545 dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", stb0899_write_regs()
553 int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data) stb0899_write_reg() argument
555 return stb0899_write_regs(state, reg, &data, 1); stb0899_write_reg()
563 static u32 stb0899_get_mclk(struct stb0899_state *state) stb0899_get_mclk() argument
567 div = stb0899_read_reg(state, STB0899_NCOARSE); stb0899_get_mclk()
568 mclk = (div + 1) * state->config->xtal_freq / 6; stb0899_get_mclk()
569 dprintk(state->verbose, FE_DEBUG, 1, "div=%d, mclk=%d", div, mclk); stb0899_get_mclk()
580 static void stb0899_set_mclk(struct stb0899_state *state, u32 Mclk) stb0899_set_mclk() argument
582 struct stb0899_internal *internal = &state->internal; stb0899_set_mclk()
585 dprintk(state->verbose, FE_DEBUG, 1, "state->config=%p", state->config); stb0899_set_mclk()
586 mdiv = ((6 * Mclk) / state->config->xtal_freq) - 1; stb0899_set_mclk()
587 dprintk(state->verbose, FE_DEBUG, 1, "mdiv=%d", mdiv); stb0899_set_mclk()
589 stb0899_write_reg(state, STB0899_NCOARSE, mdiv); stb0899_set_mclk()
590 internal->master_clk = stb0899_get_mclk(state); stb0899_set_mclk()
592 dprintk(state->verbose, FE_DEBUG, 1, "MasterCLOCK=%d", internal->master_clk); stb0899_set_mclk()
595 static int stb0899_postproc(struct stb0899_state *state, u8 ctl, int enable) stb0899_postproc() argument
597 struct stb0899_config *config = state->config; stb0899_postproc()
604 stb0899_write_reg(state, postproc[ctl].gpio, 0x02); stb0899_postproc()
606 stb0899_write_reg(state, postproc[ctl].gpio, 0x82); stb0899_postproc()
609 stb0899_write_reg(state, postproc[ctl].gpio, 0x82); stb0899_postproc()
611 stb0899_write_reg(state, postproc[ctl].gpio, 0x02); stb0899_postproc()
619 struct stb0899_state *state = fe->demodulator_priv; stb0899_release() local
621 dprintk(state->verbose, FE_DEBUG, 1, "Release Frontend"); stb0899_release()
623 stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0); stb0899_release()
624 kfree(state); stb0899_release()
631 static int stb0899_get_alpha(struct stb0899_state *state) stb0899_get_alpha() argument
635 mode_coeff = stb0899_read_reg(state, STB0899_DEMOD); stb0899_get_alpha()
646 static void stb0899_init_calc(struct stb0899_state *state) stb0899_init_calc() argument
648 struct stb0899_internal *internal = &state->internal; stb0899_init_calc()
654 stb0899_read_regs(state, STB0899_AGC1REF, agc, 2); /* AGC1R and AGC2O */ stb0899_init_calc()
657 master_clk = stb0899_get_mclk(state); stb0899_init_calc()
662 internal->rolloff = stb0899_get_alpha(state); stb0899_init_calc()
669 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); stb0899_init_calc()
686 static int stb0899_wait_diseqc_fifo_empty(struct stb0899_state *state, int timeout) stb0899_wait_diseqc_fifo_empty() argument
692 reg = stb0899_read_reg(state, STB0899_DISSTATUS); stb0899_wait_diseqc_fifo_empty()
696 dprintk(state->verbose, FE_ERROR, 1, "timed out !!"); stb0899_wait_diseqc_fifo_empty()
706 struct stb0899_state *state = fe->demodulator_priv; stb0899_send_diseqc_msg() local
713 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_msg()
715 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_msg()
718 if (stb0899_wait_diseqc_fifo_empty(state, 100) < 0) stb0899_send_diseqc_msg()
721 stb0899_write_reg(state, STB0899_DISFIFO, cmd->msg[i]); stb0899_send_diseqc_msg()
723 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_msg()
725 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_msg()
730 static int stb0899_wait_diseqc_rxidle(struct stb0899_state *state, int timeout) stb0899_wait_diseqc_rxidle() argument
736 reg = stb0899_read_reg(state, STB0899_DISRX_ST0); stb0899_wait_diseqc_rxidle()
738 dprintk(state->verbose, FE_ERROR, 1, "timed out!!"); stb0899_wait_diseqc_rxidle()
749 struct stb0899_state *state = fe->demodulator_priv; stb0899_recv_slave_reply() local
753 if (stb0899_wait_diseqc_rxidle(state, 100) < 0) stb0899_recv_slave_reply()
756 reg = stb0899_read_reg(state, STB0899_DISRX_ST0); stb0899_recv_slave_reply()
759 reg = stb0899_read_reg(state, STB0899_DISRX_ST1); stb0899_recv_slave_reply()
770 reply->msg[i] = stb0899_read_reg(state, STB0899_DISFIFO); stb0899_recv_slave_reply()
779 static int stb0899_wait_diseqc_txidle(struct stb0899_state *state, int timeout) stb0899_wait_diseqc_txidle() argument
785 reg = stb0899_read_reg(state, STB0899_DISSTATUS); stb0899_wait_diseqc_txidle()
787 dprintk(state->verbose, FE_ERROR, 1, "timed out!!"); stb0899_wait_diseqc_txidle()
797 struct stb0899_state *state = fe->demodulator_priv; stb0899_send_diseqc_burst() local
801 if (stb0899_wait_diseqc_txidle(state, 100) < 0) stb0899_send_diseqc_burst()
804 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_burst()
809 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_burst()
813 stb0899_write_reg(state, STB0899_DISFIFO, 0x00); stb0899_send_diseqc_burst()
817 stb0899_write_reg(state, STB0899_DISFIFO, 0xff); stb0899_send_diseqc_burst()
820 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_burst()
822 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_burst()
824 if (stb0899_wait_diseqc_txidle(state, 100) < 0) stb0899_send_diseqc_burst()
827 /* restore state */ stb0899_send_diseqc_burst()
828 stb0899_write_reg(state, STB0899_DISCNTRL1, old_state); stb0899_send_diseqc_burst()
833 static int stb0899_diseqc_init(struct stb0899_state *state) stb0899_diseqc_init() argument
841 reg = stb0899_read_reg(state, STB0899_DISCNTRL2); stb0899_diseqc_init()
843 stb0899_write_reg(state, STB0899_DISCNTRL2, reg); stb0899_diseqc_init()
846 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_diseqc_init()
848 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_diseqc_init()
850 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_diseqc_init()
852 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_diseqc_init()
854 mclk = stb0899_get_mclk(state); stb0899_diseqc_init()
856 stb0899_write_reg(state, STB0899_DISF22, f22_tx); /* DiSEqC Tx freq */ stb0899_diseqc_init()
857 state->rx_freq = 20000; stb0899_diseqc_init()
864 struct stb0899_state *state = fe->demodulator_priv; stb0899_sleep() local
868 dprintk(state->verbose, FE_DEBUG, 1, "Going to Sleep .. (Really tired .. :-))"); stb0899_sleep()
870 stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0); stb0899_sleep()
878 struct stb0899_state *state = fe->demodulator_priv; stb0899_wakeup() local
880 if ((rc = stb0899_write_reg(state, STB0899_SYNTCTRL, STB0899_SELOSCI))) stb0899_wakeup()
883 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK1, 0x00))) stb0899_wakeup()
885 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK2, 0x00))) stb0899_wakeup()
889 stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 1); stb0899_wakeup()
897 struct stb0899_state *state = fe->demodulator_priv; stb0899_init() local
898 struct stb0899_config *config = state->config; stb0899_init()
900 dprintk(state->verbose, FE_DEBUG, 1, "Initializing STB0899 ... "); stb0899_init()
903 dprintk(state->verbose, FE_DEBUG, 1, "init device"); stb0899_init()
905 stb0899_write_reg(state, config->init_dev[i].address, config->init_dev[i].data); stb0899_init()
907 dprintk(state->verbose, FE_DEBUG, 1, "init S2 demod"); stb0899_init()
910 stb0899_write_s2reg(state, STB0899_S2DEMOD, stb0899_init()
915 dprintk(state->verbose, FE_DEBUG, 1, "init S1 demod"); stb0899_init()
918 stb0899_write_reg(state, config->init_s1_demod[i].address, config->init_s1_demod[i].data); stb0899_init()
920 dprintk(state->verbose, FE_DEBUG, 1, "init S2 FEC"); stb0899_init()
923 stb0899_write_s2reg(state, STB0899_S2FEC, stb0899_init()
928 dprintk(state->verbose, FE_DEBUG, 1, "init TST"); stb0899_init()
931 stb0899_write_reg(state, config->init_tst[i].address, config->init_tst[i].data); stb0899_init()
933 stb0899_init_calc(state); stb0899_init()
934 stb0899_diseqc_init(state); stb0899_init()
967 struct stb0899_state *state = fe->demodulator_priv; stb0899_read_signal_strength() local
968 struct stb0899_internal *internal = &state->internal; stb0899_read_signal_strength()
973 switch (state->delsys) { stb0899_read_signal_strength()
977 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_read_signal_strength()
980 reg = stb0899_read_reg(state, STB0899_AGCIQIN); stb0899_read_signal_strength()
985 dprintk(state->verbose, FE_DEBUG, 1, "AGCIQVALUE = 0x%02x, C = %d * 0.1 dBm", stb0899_read_signal_strength()
997 dprintk(state->verbose, FE_DEBUG, 1, "IF_AGC_GAIN = 0x%04x, C = %d * 0.1 dBm", stb0899_read_signal_strength()
1002 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system"); stb0899_read_signal_strength()
1011 struct stb0899_state *state = fe->demodulator_priv; stb0899_read_snr() local
1012 struct stb0899_internal *internal = &state->internal; stb0899_read_snr()
1019 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_read_snr()
1020 switch (state->delsys) { stb0899_read_snr()
1026 stb0899_read_regs(state, STB0899_NIRM, buf, 2); stb0899_read_snr()
1030 dprintk(state->verbose, FE_DEBUG, 1, "NIR = 0x%02x%02x = %u, C/N = %d * 0.1 dBm\n", stb0899_read_snr()
1054 dprintk(state->verbose, FE_DEBUG, 1, "Es/N0 quant = %d (%d) estimate = %u (%d), C/N = %d * 0.1 dBm", stb0899_read_snr()
1059 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system"); stb0899_read_snr()
1068 struct stb0899_state *state = fe->demodulator_priv; stb0899_read_status() local
1069 struct stb0899_internal *internal = &state->internal; stb0899_read_status()
1073 switch (state->delsys) { stb0899_read_status()
1076 dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S/DSS"); stb0899_read_status()
1078 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_read_status()
1080 dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_CARRIER | FE_HAS_LOCK"); stb0899_read_status()
1083 reg = stb0899_read_reg(state, STB0899_PLPARM); stb0899_read_status()
1085 dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_VITERBI | FE_HAS_SYNC"); stb0899_read_status()
1088 stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1); stb0899_read_status()
1094 dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S2"); stb0899_read_status()
1099 dprintk(state->verbose, FE_DEBUG, 1, stb0899_read_status()
1102 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); stb0899_read_status()
1105 dprintk(state->verbose, FE_DEBUG, 1, stb0899_read_status()
1111 dprintk(state->verbose, FE_DEBUG, 1, stb0899_read_status()
1116 dprintk(state->verbose, FE_DEBUG, 1, stb0899_read_status()
1119 stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1); stb0899_read_status()
1125 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system"); stb0899_read_status()
1139 struct stb0899_state *state = fe->demodulator_priv; stb0899_read_ber() local
1140 struct stb0899_internal *internal = &state->internal; stb0899_read_ber()
1146 switch (state->delsys) { stb0899_read_ber()
1150 lsb = stb0899_read_reg(state, STB0899_ECNT1L); stb0899_read_ber()
1151 msb = stb0899_read_reg(state, STB0899_ECNT1M); stb0899_read_ber()
1165 lsb = stb0899_read_reg(state, STB0899_ECNT1L); stb0899_read_ber()
1166 msb = stb0899_read_reg(state, STB0899_ECNT1M); stb0899_read_ber()
1174 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system"); stb0899_read_ber()
1183 struct stb0899_state *state = fe->demodulator_priv; stb0899_set_voltage() local
1187 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82); stb0899_set_voltage()
1188 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02); stb0899_set_voltage()
1189 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x00); stb0899_set_voltage()
1192 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x02); stb0899_set_voltage()
1193 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02); stb0899_set_voltage()
1194 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82); stb0899_set_voltage()
1197 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82); stb0899_set_voltage()
1198 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x82); stb0899_set_voltage()
1199 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82); stb0899_set_voltage()
1210 struct stb0899_state *state = fe->demodulator_priv; stb0899_set_tone() local
1211 struct stb0899_internal *internal = &state->internal; stb0899_set_tone()
1216 if (stb0899_wait_diseqc_txidle(state, 100) < 0) stb0899_set_tone()
1223 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x66); stb0899_set_tone()
1224 reg = stb0899_read_reg(state, STB0899_ACRPRESC); stb0899_set_tone()
1226 stb0899_write_reg(state, STB0899_ACRPRESC, reg); stb0899_set_tone()
1227 stb0899_write_reg(state, STB0899_ACRDIV1, div); stb0899_set_tone()
1230 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x20); stb0899_set_tone()
1241 struct stb0899_state *state = fe->demodulator_priv; stb0899_i2c_gate_ctrl() local
1243 i2c_stat = stb0899_read_reg(state, STB0899_I2CRPT); stb0899_i2c_gate_ctrl()
1248 dprintk(state->verbose, FE_DEBUG, 1, "Enabling I2C Repeater ..."); stb0899_i2c_gate_ctrl()
1250 if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0) stb0899_i2c_gate_ctrl()
1253 dprintk(state->verbose, FE_DEBUG, 1, "Disabling I2C Repeater ..."); stb0899_i2c_gate_ctrl()
1255 if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0) stb0899_i2c_gate_ctrl()
1260 dprintk(state->verbose, FE_ERROR, 1, "I2C Repeater control failed"); stb0899_i2c_gate_ctrl()
1274 static int stb0899_get_dev_id(struct stb0899_state *state) stb0899_get_dev_id() argument
1282 id = stb0899_read_reg(state, STB0899_DEV_ID); stb0899_get_dev_id()
1283 dprintk(state->verbose, FE_DEBUG, 1, "ID reg=[0x%02x]", id); stb0899_get_dev_id()
1287 dprintk(state->verbose, FE_ERROR, 1, "Device ID=[%d], Release=[%d]", stb0899_get_dev_id()
1293 dprintk(state->verbose, FE_ERROR, 1, "Demodulator Core ID=[%s], Version=[%d]", (char *) &demod_str, demod_ver); stb0899_get_dev_id()
1297 dprintk(state->verbose, FE_ERROR, 1, "couldn't find a STB 0899"); stb0899_get_dev_id()
1301 dprintk(state->verbose, FE_ERROR, 1, "FEC Core ID=[%s], Version=[%d]", (char*) &fec_str, fec_ver); stb0899_get_dev_id()
1306 static void stb0899_set_delivery(struct stb0899_state *state) stb0899_set_delivery() argument
1311 stop_clk[0] = stb0899_read_reg(state, STB0899_STOPCLK1); stb0899_set_delivery()
1312 stop_clk[1] = stb0899_read_reg(state, STB0899_STOPCLK2); stb0899_set_delivery()
1314 switch (state->delsys) { stb0899_set_delivery()
1316 dprintk(state->verbose, FE_DEBUG, 1, "Delivery System -- DVB-S"); stb0899_set_delivery()
1318 reg = stb0899_read_reg(state, STB0899_FECM); stb0899_set_delivery()
1321 stb0899_write_reg(state, STB0899_FECM, reg); stb0899_set_delivery()
1323 stb0899_write_reg(state, STB0899_RSULC, 0xb1); stb0899_set_delivery()
1324 stb0899_write_reg(state, STB0899_TSULC, 0x40); stb0899_set_delivery()
1325 stb0899_write_reg(state, STB0899_RSLLC, 0x42); stb0899_set_delivery()
1326 stb0899_write_reg(state, STB0899_TSLPL, 0x12); stb0899_set_delivery()
1328 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_set_delivery()
1330 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_set_delivery()
1346 reg = stb0899_read_reg(state, STB0899_FECM); stb0899_set_delivery()
1349 stb0899_write_reg(state, STB0899_FECM, reg); stb0899_set_delivery()
1351 stb0899_write_reg(state, STB0899_RSULC, 0xb1); stb0899_set_delivery()
1352 stb0899_write_reg(state, STB0899_TSULC, 0x42); stb0899_set_delivery()
1353 stb0899_write_reg(state, STB0899_RSLLC, 0x40); stb0899_set_delivery()
1354 stb0899_write_reg(state, STB0899_TSLPL, 0x02); stb0899_set_delivery()
1356 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_set_delivery()
1358 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_set_delivery()
1374 reg = stb0899_read_reg(state, STB0899_FECM); stb0899_set_delivery()
1377 stb0899_write_reg(state, STB0899_FECM, reg); stb0899_set_delivery()
1379 stb0899_write_reg(state, STB0899_RSULC, 0xa1); stb0899_set_delivery()
1380 stb0899_write_reg(state, STB0899_TSULC, 0x61); stb0899_set_delivery()
1381 stb0899_write_reg(state, STB0899_RSLLC, 0x42); stb0899_set_delivery()
1383 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_set_delivery()
1385 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_set_delivery()
1399 dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system"); stb0899_set_delivery()
1403 stb0899_write_regs(state, STB0899_STOPCLK1, stop_clk, 2); stb0899_set_delivery()
1410 static void stb0899_set_iterations(struct stb0899_state *state) stb0899_set_iterations() argument
1412 struct stb0899_internal *internal = &state->internal; stb0899_set_iterations()
1413 struct stb0899_config *config = state->config; stb0899_set_iterations()
1428 stb0899_write_s2reg(state, STB0899_S2FEC, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg); stb0899_set_iterations()
1433 struct stb0899_state *state = fe->demodulator_priv; stb0899_search() local
1434 struct stb0899_params *i_params = &state->params; stb0899_search()
1435 struct stb0899_internal *internal = &state->internal; stb0899_search()
1436 struct stb0899_config *config = state->config; stb0899_search()
1443 state->delsys = props->delivery_system; stb0899_search()
1444 dprintk(state->verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys); stb0899_search()
1447 dprintk(state->verbose, FE_DEBUG, 1, "Frequency=%d, Srate=%d", i_params->freq, i_params->srate); stb0899_search()
1450 dprintk(state->verbose, FE_DEBUG, 1, "Parameters IN RANGE"); stb0899_search()
1451 stb0899_set_delivery(state); stb0899_search()
1453 if (state->config->tuner_set_rfsiggain) { stb0899_search()
1460 state->config->tuner_set_rfsiggain(fe, gain); stb0899_search()
1464 stb0899_set_mclk(state, config->lo_clk); stb0899_search()
1466 stb0899_set_mclk(state, config->hi_clk); stb0899_search()
1468 switch (state->delsys) { stb0899_search()
1471 dprintk(state->verbose, FE_DEBUG, 1, "DVB-S delivery system"); stb0899_search()
1485 stb0899_i2c_gate_ctrl(&state->frontend, 1); stb0899_search()
1487 if (state->config->tuner_set_bandwidth) stb0899_search()
1488 state->config->tuner_set_bandwidth(fe, (13 * (stb0899_carr_width(state) + SearchRange)) / 10); stb0899_search()
1489 if (state->config->tuner_get_bandwidth) stb0899_search()
1490 state->config->tuner_get_bandwidth(fe, &internal->tuner_bw); stb0899_search()
1493 stb0899_i2c_gate_ctrl(&state->frontend, 0); stb0899_search()
1496 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x11); stb0899_search()
1499 dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S search algo .."); stb0899_search()
1500 if (stb0899_dvbs_algo(state) == RANGEOK) { stb0899_search()
1502 dprintk(state->verbose, FE_DEBUG, 1, stb0899_search()
1505 // stb0899_write_reg(state, STB0899_ERRCTRL1, 0x3d); /* Viterbi Errors */ stb0899_search()
1506 // internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_search()
1507 // internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1); stb0899_search()
1508 // dprintk(state->verbose, FE_DEBUG, 1, "VSTATUS=0x%02x", internal->v_status); stb0899_search()
1509 // dprintk(state->verbose, FE_DEBUG, 1, "ERR_CTRL=0x%02x", internal->err_ctrl); stb0899_search()
1524 stb0899_i2c_gate_ctrl(&state->frontend, 1); stb0899_search()
1526 if (state->config->tuner_set_bandwidth) stb0899_search()
1527 state->config->tuner_set_bandwidth(fe, (stb0899_carr_width(state) + SearchRange)); stb0899_search()
1528 if (state->config->tuner_get_bandwidth) stb0899_search()
1529 state->config->tuner_get_bandwidth(fe, &internal->tuner_bw); stb0899_search()
1532 stb0899_i2c_gate_ctrl(&state->frontend, 0); stb0899_search()
1537 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x1c); stb0899_search()
1540 stb0899_set_iterations(state); stb0899_search()
1543 dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S2 search algo .."); stb0899_search()
1544 if (stb0899_dvbs2_algo(state) == DVBS2_FEC_LOCK) { stb0899_search()
1546 dprintk(state->verbose, FE_DEBUG, 1, stb0899_search()
1549 // stb0899_write_reg(state, STB0899_ERRCTRL1, 0xb6); /* Packet Errors */ stb0899_search()
1550 // internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_search()
1551 // internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1); stb0899_search()
1561 dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system"); stb0899_search()
1572 struct stb0899_state *state = fe->demodulator_priv; stb0899_get_frontend() local
1573 struct stb0899_internal *internal = &state->internal; stb0899_get_frontend()
1575 dprintk(state->verbose, FE_DEBUG, 1, "Get params"); stb0899_get_frontend()
1631 struct stb0899_state *state = NULL; stb0899_attach() local
1633 state = kzalloc(sizeof (struct stb0899_state), GFP_KERNEL); stb0899_attach()
1634 if (state == NULL) stb0899_attach()
1637 state->verbose = &verbose; stb0899_attach()
1638 state->config = config; stb0899_attach()
1639 state->i2c = i2c; stb0899_attach()
1640 state->frontend.ops = stb0899_ops; stb0899_attach()
1641 state->frontend.demodulator_priv = state; stb0899_attach()
1643 state->internal.inversion = config->inversion; stb0899_attach()
1645 stb0899_wakeup(&state->frontend); stb0899_attach()
1646 if (stb0899_get_dev_id(state) == -ENODEV) { stb0899_attach()
1652 return &state->frontend; stb0899_attach()
1655 kfree(state); stb0899_attach()
H A Dtda10023.c64 static u8 tda10023_readreg (struct tda10023_state* state, u8 reg) tda10023_readreg() argument
68 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, tda10023_readreg()
69 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; tda10023_readreg()
72 ret = i2c_transfer (state->i2c, msg, 2); tda10023_readreg()
74 int num = state->frontend.dvb ? state->frontend.dvb->num : -1; tda10023_readreg()
82 static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data) tda10023_writereg() argument
85 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; tda10023_writereg()
88 ret = i2c_transfer (state->i2c, &msg, 1); tda10023_writereg()
90 int num = state->frontend.dvb ? state->frontend.dvb->num : -1; tda10023_writereg()
99 static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data) tda10023_writebit() argument
102 return tda10023_writereg(state, reg, data); tda10023_writebit()
105 val=tda10023_readreg(state,reg); tda10023_writebit()
108 return tda10023_writereg(state, reg, val); tda10023_writebit()
112 static void tda10023_writetab(struct tda10023_state* state, u8* tab) tda10023_writetab() argument
126 tda10023_writebit(state,r,m,v); tda10023_writetab()
131 static int lock_tuner(struct tda10023_state* state) lock_tuner() argument
134 struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2}; lock_tuner()
136 if(i2c_transfer(state->i2c, &msg, 1) != 1) lock_tuner()
145 static int unlock_tuner(struct tda10023_state* state) unlock_tuner() argument
148 struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2}; unlock_tuner()
150 if(i2c_transfer(state->i2c, &msg_post, 1) != 1) unlock_tuner()
158 static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0) tda10023_setup_reg0() argument
160 reg0 |= state->reg0 & 0x63; tda10023_setup_reg0()
162 tda10023_writereg (state, 0x00, reg0 & 0xfe); tda10023_setup_reg0()
163 tda10023_writereg (state, 0x00, reg0 | 0x01); tda10023_setup_reg0()
165 state->reg0 = reg0; tda10023_setup_reg0()
169 static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr) tda10023_set_symbolrate() argument
178 u32 sysclk_x_10 = state->sysclk * 10; tda10023_set_symbolrate()
203 BDRI = (state->sysclk)*16; tda10023_set_symbolrate()
216 do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */ tda10023_set_symbolrate()
222 tda10023_writebit (state, 0x03, 0xc0, NDEC<<6); tda10023_set_symbolrate()
223 tda10023_writereg (state, 0x0a, BDR&255); tda10023_set_symbolrate()
224 tda10023_writereg (state, 0x0b, (BDR>>8)&255); tda10023_set_symbolrate()
225 tda10023_writereg (state, 0x0c, (BDR>>16)&31); tda10023_set_symbolrate()
226 tda10023_writereg (state, 0x0d, BDRI); tda10023_set_symbolrate()
227 tda10023_writereg (state, 0x3d, (SFIL<<7)); tda10023_set_symbolrate()
233 struct tda10023_state* state = fe->demodulator_priv; tda10023_init() local
241 /* 012 */ 0x28, 0xff, (state->pll_m-1), tda10023_init()
243 /* 015 */ 0x29, 0xff, ((state->pll_p-1)<<6)|(state->pll_n-1), tda10023_init()
288 if (state->config->deltaf) { tda10023_init()
289 tda10023_inittab[80] = (state->config->deltaf & 0xff); tda10023_init()
290 tda10023_inittab[83] = (state->config->deltaf >> 8); tda10023_init()
293 if (state->config->output_mode) tda10023_init()
294 tda10023_inittab[95] = state->config->output_mode; tda10023_init()
296 tda10023_writetab(state, tda10023_inittab); tda10023_init()
311 struct tda10023_state* state = fe->demodulator_priv; tda10023_set_parameters() local
357 tda10023_set_symbolrate(state, c->symbol_rate); tda10023_set_parameters()
358 tda10023_writereg(state, 0x05, qam_params[qam].lockthr); tda10023_set_parameters()
359 tda10023_writereg(state, 0x08, qam_params[qam].mseth); tda10023_set_parameters()
360 tda10023_writereg(state, 0x09, qam_params[qam].aref); tda10023_set_parameters()
361 tda10023_writereg(state, 0xb4, qam_params[qam].agcrefnyq); tda10023_set_parameters()
362 tda10023_writereg(state, 0xb6, qam_params[qam].eragnyq_thd); tda10023_set_parameters()
364 tda10023_writereg(state, 0x04, (c->inversion ? 0x12 : 0x32)); tda10023_set_parameters()
365 tda10023_writebit(state, 0x04, 0x60, (c->inversion ? 0 : 0x20)); tda10023_set_parameters()
367 tda10023_writebit(state, 0x04, 0x40, 0x40); tda10023_set_parameters()
370 tda10023_writebit(state, 0x3d, 0xfc, 0x03); tda10023_set_parameters()
372 tda10023_writebit(state, 0x3d, 0xfc, 0x02); tda10023_set_parameters()
374 tda10023_setup_reg0(state, qam_params[qam].qam); tda10023_set_parameters()
381 struct tda10023_state* state = fe->demodulator_priv; tda10023_read_status() local
390 sync = tda10023_readreg (state, 0x11); tda10023_read_status()
406 struct tda10023_state* state = fe->demodulator_priv; tda10023_read_ber() local
408 a=tda10023_readreg(state, 0x14); tda10023_read_ber()
409 b=tda10023_readreg(state, 0x15); tda10023_read_ber()
410 c=tda10023_readreg(state, 0x16)&0xf; tda10023_read_ber()
411 tda10023_writebit (state, 0x10, 0xc0, 0x00); tda10023_read_ber()
419 struct tda10023_state* state = fe->demodulator_priv; tda10023_read_signal_strength() local
420 u8 ifgain=tda10023_readreg(state, 0x2f); tda10023_read_signal_strength()
422 u16 gain = ((255-tda10023_readreg(state, 0x17))) + (255-ifgain)/16; tda10023_read_signal_strength()
435 struct tda10023_state* state = fe->demodulator_priv; tda10023_read_snr() local
437 u8 quality = ~tda10023_readreg(state, 0x18); tda10023_read_snr()
444 struct tda10023_state* state = fe->demodulator_priv; tda10023_read_ucblocks() local
446 a= tda10023_readreg (state, 0x74); tda10023_read_ucblocks()
447 b= tda10023_readreg (state, 0x75); tda10023_read_ucblocks()
448 c= tda10023_readreg (state, 0x76); tda10023_read_ucblocks()
449 d= tda10023_readreg (state, 0x77); tda10023_read_ucblocks()
452 tda10023_writebit (state, 0x10, 0x20,0x00); tda10023_read_ucblocks()
453 tda10023_writebit (state, 0x10, 0x20,0x20); tda10023_read_ucblocks()
454 tda10023_writebit (state, 0x13, 0x01, 0x00); tda10023_read_ucblocks()
462 struct tda10023_state* state = fe->demodulator_priv; tda10023_get_frontend() local
466 sync = tda10023_readreg(state, 0x11); tda10023_get_frontend()
467 afc = tda10023_readreg(state, 0x19); tda10023_get_frontend()
468 inv = tda10023_readreg(state, 0x04); tda10023_get_frontend()
474 state->frontend.dvb->num, afc, tda10023_get_frontend()
479 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16; tda10023_get_frontend()
492 struct tda10023_state* state = fe->demodulator_priv; tda10023_sleep() local
494 tda10023_writereg (state, 0x1b, 0x02); /* pdown ADC */ tda10023_sleep()
495 tda10023_writereg (state, 0x00, 0x80); /* standby */ tda10023_sleep()
502 struct tda10023_state* state = fe->demodulator_priv; tda10023_i2c_gate_ctrl() local
505 lock_tuner(state); tda10023_i2c_gate_ctrl()
507 unlock_tuner(state); tda10023_i2c_gate_ctrl()
514 struct tda10023_state* state = fe->demodulator_priv; tda10023_release() local
515 kfree(state); tda10023_release()
524 struct tda10023_state* state = NULL; tda10023_attach() local
526 /* allocate memory for the internal state */ tda10023_attach()
527 state = kzalloc(sizeof(struct tda10023_state), GFP_KERNEL); tda10023_attach()
528 if (state == NULL) goto error; tda10023_attach()
530 /* setup the state */ tda10023_attach()
531 state->config = config; tda10023_attach()
532 state->i2c = i2c; tda10023_attach()
535 tda10023_writereg (state, 0x00, 0x33); tda10023_attach()
537 if ((tda10023_readreg(state, 0x1a) & 0xf0) != 0x70) goto error; tda10023_attach()
540 memcpy(&state->frontend.ops, &tda10023_ops, sizeof(struct dvb_frontend_ops)); tda10023_attach()
541 state->pwm = pwm; tda10023_attach()
542 state->reg0 = REG0_INIT_VAL; tda10023_attach()
543 if (state->config->xtal) { tda10023_attach()
544 state->xtal = state->config->xtal; tda10023_attach()
545 state->pll_m = state->config->pll_m; tda10023_attach()
546 state->pll_p = state->config->pll_p; tda10023_attach()
547 state->pll_n = state->config->pll_n; tda10023_attach()
550 state->xtal = 28920000; tda10023_attach()
551 state->pll_m = 8; tda10023_attach()
552 state->pll_p = 4; tda10023_attach()
553 state->pll_n = 1; tda10023_attach()
557 state->sysclk = (state->xtal * state->pll_m / \ tda10023_attach()
558 (state->pll_n * state->pll_p)); tda10023_attach()
560 state->frontend.ops.info.symbol_rate_min = (state->sysclk/2)/64; tda10023_attach()
561 state->frontend.ops.info.symbol_rate_max = (state->sysclk/2)/4; tda10023_attach()
564 __func__, state->xtal, state->pll_m, state->pll_p, tda10023_attach()
565 state->pll_n); tda10023_attach()
567 state->frontend.demodulator_priv = state; tda10023_attach()
568 return &state->frontend; tda10023_attach()
571 kfree(state); tda10023_attach()
H A Dstv090x.c695 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) stv090x_read_reg() argument
697 const struct stv090x_config *config = state->config; stv090x_read_reg()
708 ret = i2c_transfer(state->i2c, msg, 2); stv090x_read_reg()
717 if (unlikely(*state->verbose >= FE_DEBUGREG)) stv090x_read_reg()
724 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) stv090x_write_regs() argument
726 const struct stv090x_config *config = state->config; stv090x_write_regs()
742 if (unlikely(*state->verbose >= FE_DEBUGREG)) { stv090x_write_regs()
751 ret = i2c_transfer(state->i2c, &i2c_msg, 1); stv090x_write_regs()
762 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) stv090x_write_reg() argument
764 return stv090x_write_regs(state, reg, &data, 1); stv090x_write_reg()
767 static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) stv090x_i2c_gate_ctrl() argument
772 * NOTE! A lock is used as a FSM to control the state in which stv090x_i2c_gate_ctrl()
781 if (state->config->tuner_i2c_lock) stv090x_i2c_gate_ctrl()
782 state->config->tuner_i2c_lock(&state->frontend, 1); stv090x_i2c_gate_ctrl()
784 mutex_lock(&state->internal->tuner_lock); stv090x_i2c_gate_ctrl()
787 reg = STV090x_READ_DEMOD(state, I2CRPT); stv090x_i2c_gate_ctrl()
791 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) stv090x_i2c_gate_ctrl()
797 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) stv090x_i2c_gate_ctrl()
802 if (state->config->tuner_i2c_lock) stv090x_i2c_gate_ctrl()
803 state->config->tuner_i2c_lock(&state->frontend, 0); stv090x_i2c_gate_ctrl()
805 mutex_unlock(&state->internal->tuner_lock); stv090x_i2c_gate_ctrl()
811 if (state->config->tuner_i2c_lock) stv090x_i2c_gate_ctrl()
812 state->config->tuner_i2c_lock(&state->frontend, 0); stv090x_i2c_gate_ctrl()
814 mutex_unlock(&state->internal->tuner_lock); stv090x_i2c_gate_ctrl()
818 static void stv090x_get_lock_tmg(struct stv090x_state *state) stv090x_get_lock_tmg() argument
820 switch (state->algo) { stv090x_get_lock_tmg()
823 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ stv090x_get_lock_tmg()
824 state->DemodTimeout = 1500; stv090x_get_lock_tmg()
825 state->FecTimeout = 400; stv090x_get_lock_tmg()
826 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ stv090x_get_lock_tmg()
827 state->DemodTimeout = 1000; stv090x_get_lock_tmg()
828 state->FecTimeout = 300; stv090x_get_lock_tmg()
830 state->DemodTimeout = 700; stv090x_get_lock_tmg()
831 state->FecTimeout = 100; stv090x_get_lock_tmg()
839 if (state->srate <= 1000000) { /*SR <=1Msps*/ stv090x_get_lock_tmg()
840 state->DemodTimeout = 4500; stv090x_get_lock_tmg()
841 state->FecTimeout = 1700; stv090x_get_lock_tmg()
842 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ stv090x_get_lock_tmg()
843 state->DemodTimeout = 2500; stv090x_get_lock_tmg()
844 state->FecTimeout = 1100; stv090x_get_lock_tmg()
845 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ stv090x_get_lock_tmg()
846 state->DemodTimeout = 1000; stv090x_get_lock_tmg()
847 state->FecTimeout = 550; stv090x_get_lock_tmg()
848 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ stv090x_get_lock_tmg()
849 state->DemodTimeout = 700; stv090x_get_lock_tmg()
850 state->FecTimeout = 250; stv090x_get_lock_tmg()
851 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ stv090x_get_lock_tmg()
852 state->DemodTimeout = 400; stv090x_get_lock_tmg()
853 state->FecTimeout = 130; stv090x_get_lock_tmg()
855 state->DemodTimeout = 300; stv090x_get_lock_tmg()
856 state->FecTimeout = 100; stv090x_get_lock_tmg()
861 if (state->algo == STV090x_WARM_SEARCH) stv090x_get_lock_tmg()
862 state->DemodTimeout /= 2; stv090x_get_lock_tmg()
865 static int stv090x_set_srate(struct stv090x_state *state, u32 srate) stv090x_set_srate() argument
871 sym /= (state->internal->mclk >> 12); stv090x_set_srate()
874 sym /= (state->internal->mclk >> 10); stv090x_set_srate()
877 sym /= (state->internal->mclk >> 7); stv090x_set_srate()
880 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ stv090x_set_srate()
882 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ stv090x_set_srate()
891 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) stv090x_set_max_srate() argument
898 sym /= (state->internal->mclk >> 12); stv090x_set_max_srate()
901 sym /= (state->internal->mclk >> 10); stv090x_set_max_srate()
904 sym /= (state->internal->mclk >> 7); stv090x_set_max_srate()
908 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ stv090x_set_max_srate()
910 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ stv090x_set_max_srate()
913 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ stv090x_set_max_srate()
915 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ stv090x_set_max_srate()
925 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) stv090x_set_min_srate() argument
932 sym /= (state->internal->mclk >> 12); stv090x_set_min_srate()
935 sym /= (state->internal->mclk >> 10); stv090x_set_min_srate()
938 sym /= (state->internal->mclk >> 7); stv090x_set_min_srate()
941 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ stv090x_set_min_srate()
943 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ stv090x_set_min_srate()
971 static int stv090x_set_vit_thacq(struct stv090x_state *state) stv090x_set_vit_thacq() argument
973 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) stv090x_set_vit_thacq()
975 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) stv090x_set_vit_thacq()
977 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) stv090x_set_vit_thacq()
979 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) stv090x_set_vit_thacq()
981 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) stv090x_set_vit_thacq()
983 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) stv090x_set_vit_thacq()
991 static int stv090x_set_vit_thtracq(struct stv090x_state *state) stv090x_set_vit_thtracq() argument
993 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) stv090x_set_vit_thtracq()
995 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) stv090x_set_vit_thtracq()
997 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) stv090x_set_vit_thtracq()
999 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) stv090x_set_vit_thtracq()
1001 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) stv090x_set_vit_thtracq()
1003 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) stv090x_set_vit_thtracq()
1011 static int stv090x_set_viterbi(struct stv090x_state *state) stv090x_set_viterbi() argument
1013 switch (state->search_mode) { stv090x_set_viterbi()
1015 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ stv090x_set_viterbi()
1017 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ stv090x_set_viterbi()
1021 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ stv090x_set_viterbi()
1023 switch (state->fec) { stv090x_set_viterbi()
1025 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) stv090x_set_viterbi()
1030 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) stv090x_set_viterbi()
1035 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) stv090x_set_viterbi()
1040 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) stv090x_set_viterbi()
1045 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) stv090x_set_viterbi()
1050 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ stv090x_set_viterbi()
1056 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) stv090x_set_viterbi()
1058 switch (state->fec) { stv090x_set_viterbi()
1060 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) stv090x_set_viterbi()
1065 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) stv090x_set_viterbi()
1070 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) stv090x_set_viterbi()
1075 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ stv090x_set_viterbi()
1089 static int stv090x_stop_modcod(struct stv090x_state *state) stv090x_stop_modcod() argument
1091 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) stv090x_stop_modcod()
1093 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) stv090x_stop_modcod()
1095 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) stv090x_stop_modcod()
1097 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) stv090x_stop_modcod()
1099 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) stv090x_stop_modcod()
1101 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) stv090x_stop_modcod()
1103 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) stv090x_stop_modcod()
1105 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) stv090x_stop_modcod()
1107 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) stv090x_stop_modcod()
1109 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) stv090x_stop_modcod()
1111 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) stv090x_stop_modcod()
1113 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) stv090x_stop_modcod()
1115 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) stv090x_stop_modcod()
1117 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) stv090x_stop_modcod()
1119 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) stv090x_stop_modcod()
1121 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) stv090x_stop_modcod()
1129 static int stv090x_activate_modcod(struct stv090x_state *state) stv090x_activate_modcod() argument
1131 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) stv090x_activate_modcod()
1133 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) stv090x_activate_modcod()
1135 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) stv090x_activate_modcod()
1137 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) stv090x_activate_modcod()
1139 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) stv090x_activate_modcod()
1141 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) stv090x_activate_modcod()
1143 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) stv090x_activate_modcod()
1145 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) stv090x_activate_modcod()
1147 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) stv090x_activate_modcod()
1149 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) stv090x_activate_modcod()
1151 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) stv090x_activate_modcod()
1153 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) stv090x_activate_modcod()
1155 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) stv090x_activate_modcod()
1157 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) stv090x_activate_modcod()
1159 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) stv090x_activate_modcod()
1161 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) stv090x_activate_modcod()
1170 static int stv090x_activate_modcod_single(struct stv090x_state *state) stv090x_activate_modcod_single() argument
1173 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) stv090x_activate_modcod_single()
1175 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) stv090x_activate_modcod_single()
1177 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) stv090x_activate_modcod_single()
1179 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) stv090x_activate_modcod_single()
1181 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) stv090x_activate_modcod_single()
1183 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) stv090x_activate_modcod_single()
1185 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) stv090x_activate_modcod_single()
1187 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) stv090x_activate_modcod_single()
1189 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) stv090x_activate_modcod_single()
1191 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) stv090x_activate_modcod_single()
1193 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) stv090x_activate_modcod_single()
1195 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) stv090x_activate_modcod_single()
1197 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) stv090x_activate_modcod_single()
1199 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) stv090x_activate_modcod_single()
1201 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) stv090x_activate_modcod_single()
1203 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) stv090x_activate_modcod_single()
1213 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) stv090x_vitclk_ctl() argument
1217 switch (state->demod) { stv090x_vitclk_ctl()
1219 mutex_lock(&state->internal->demod_lock); stv090x_vitclk_ctl()
1220 reg = stv090x_read_reg(state, STV090x_STOPCLK2); stv090x_vitclk_ctl()
1222 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) stv090x_vitclk_ctl()
1224 mutex_unlock(&state->internal->demod_lock); stv090x_vitclk_ctl()
1228 mutex_lock(&state->internal->demod_lock); stv090x_vitclk_ctl()
1229 reg = stv090x_read_reg(state, STV090x_STOPCLK2); stv090x_vitclk_ctl()
1231 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) stv090x_vitclk_ctl()
1233 mutex_unlock(&state->internal->demod_lock); stv090x_vitclk_ctl()
1242 mutex_unlock(&state->internal->demod_lock); stv090x_vitclk_ctl()
1247 static int stv090x_dvbs_track_crl(struct stv090x_state *state) stv090x_dvbs_track_crl() argument
1249 if (state->internal->dev_ver >= 0x30) { stv090x_dvbs_track_crl()
1251 if (state->srate >= 15000000) { stv090x_dvbs_track_crl()
1252 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) stv090x_dvbs_track_crl()
1254 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) stv090x_dvbs_track_crl()
1256 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { stv090x_dvbs_track_crl()
1257 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) stv090x_dvbs_track_crl()
1259 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) stv090x_dvbs_track_crl()
1261 } else if (state->srate < 7000000) { stv090x_dvbs_track_crl()
1262 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) stv090x_dvbs_track_crl()
1264 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) stv090x_dvbs_track_crl()
1270 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) stv090x_dvbs_track_crl()
1272 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) stv090x_dvbs_track_crl()
1281 static int stv090x_delivery_search(struct stv090x_state *state) stv090x_delivery_search() argument
1285 switch (state->search_mode) { stv090x_delivery_search()
1288 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_delivery_search()
1291 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_delivery_search()
1297 if (stv090x_vitclk_ctl(state, 0) < 0) stv090x_delivery_search()
1300 if (stv090x_dvbs_track_crl(state) < 0) stv090x_delivery_search()
1303 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ stv090x_delivery_search()
1306 if (stv090x_set_vit_thacq(state) < 0) stv090x_delivery_search()
1308 if (stv090x_set_viterbi(state) < 0) stv090x_delivery_search()
1313 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_delivery_search()
1316 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_delivery_search()
1320 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_delivery_search()
1323 if (stv090x_vitclk_ctl(state, 1) < 0) stv090x_delivery_search()
1326 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ stv090x_delivery_search()
1328 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) stv090x_delivery_search()
1331 if (state->internal->dev_ver <= 0x20) { stv090x_delivery_search()
1333 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) stv090x_delivery_search()
1337 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) stv090x_delivery_search()
1341 if (state->demod_mode != STV090x_SINGLE) { stv090x_delivery_search()
1343 if (stv090x_activate_modcod(state) < 0) stv090x_delivery_search()
1350 if (stv090x_activate_modcod_single(state) < 0) stv090x_delivery_search()
1354 if (stv090x_set_vit_thtracq(state) < 0) stv090x_delivery_search()
1361 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_delivery_search()
1364 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_delivery_search()
1368 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_delivery_search()
1371 if (stv090x_vitclk_ctl(state, 0) < 0) stv090x_delivery_search()
1374 if (stv090x_dvbs_track_crl(state) < 0) stv090x_delivery_search()
1377 if (state->internal->dev_ver <= 0x20) { stv090x_delivery_search()
1379 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) stv090x_delivery_search()
1383 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) stv090x_delivery_search()
1387 if (state->demod_mode != STV090x_SINGLE) { stv090x_delivery_search()
1389 if (stv090x_activate_modcod(state) < 0) stv090x_delivery_search()
1396 if (stv090x_activate_modcod_single(state) < 0) stv090x_delivery_search()
1400 if (stv090x_set_vit_thacq(state) < 0) stv090x_delivery_search()
1403 if (stv090x_set_viterbi(state) < 0) stv090x_delivery_search()
1413 static int stv090x_start_search(struct stv090x_state *state) stv090x_start_search() argument
1419 reg = STV090x_READ_DEMOD(state, DMDISTATE); stv090x_start_search()
1421 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) stv090x_start_search()
1424 if (state->internal->dev_ver <= 0x20) { stv090x_start_search()
1425 if (state->srate <= 5000000) { stv090x_start_search()
1426 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) stv090x_start_search()
1428 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) stv090x_start_search()
1430 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) stv090x_start_search()
1432 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) stv090x_start_search()
1434 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) stv090x_start_search()
1438 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) stv090x_start_search()
1443 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) stv090x_start_search()
1446 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) stv090x_start_search()
1451 if (state->srate <= 5000000) { stv090x_start_search()
1453 STV090x_WRITE_DEMOD(state, RTCS2, 0x68); stv090x_start_search()
1456 STV090x_WRITE_DEMOD(state, RTCS2, 0x44); stv090x_start_search()
1460 STV090x_WRITE_DEMOD(state, CARCFG, 0x46); stv090x_start_search()
1462 if (state->algo == STV090x_WARM_SEARCH) { stv090x_start_search()
1468 freq_abs /= (state->internal->mclk / 1000); stv090x_start_search()
1476 freq_abs = (state->search_range / 2000) + 600; stv090x_start_search()
1478 freq_abs /= (state->internal->mclk / 1000); stv090x_start_search()
1482 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) stv090x_start_search()
1484 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) stv090x_start_search()
1489 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) stv090x_start_search()
1491 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) stv090x_start_search()
1496 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) stv090x_start_search()
1498 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) stv090x_start_search()
1501 if (state->internal->dev_ver >= 0x20) { stv090x_start_search()
1502 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) stv090x_start_search()
1504 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) stv090x_start_search()
1507 if ((state->search_mode == STV090x_SEARCH_DVBS1) || stv090x_start_search()
1508 (state->search_mode == STV090x_SEARCH_DSS) || stv090x_start_search()
1509 (state->search_mode == STV090x_SEARCH_AUTO)) { stv090x_start_search()
1511 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) stv090x_start_search()
1513 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) stv090x_start_search()
1518 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) stv090x_start_search()
1520 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) stv090x_start_search()
1522 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) stv090x_start_search()
1525 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_start_search()
1528 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_start_search()
1530 reg = STV090x_READ_DEMOD(state, DMDCFG2); stv090x_start_search()
1532 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) stv090x_start_search()
1535 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) stv090x_start_search()
1538 if (state->internal->dev_ver >= 0x20) { stv090x_start_search()
1540 if (state->srate < 2000000) { stv090x_start_search()
1541 if (state->internal->dev_ver <= 0x20) { stv090x_start_search()
1543 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) stv090x_start_search()
1547 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) stv090x_start_search()
1550 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) stv090x_start_search()
1552 } else if (state->srate < 10000000) { stv090x_start_search()
1553 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) stv090x_start_search()
1555 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) stv090x_start_search()
1558 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) stv090x_start_search()
1560 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) stv090x_start_search()
1564 if (state->srate < 10000000) { stv090x_start_search()
1565 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) stv090x_start_search()
1568 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) stv090x_start_search()
1573 switch (state->algo) { stv090x_start_search()
1578 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) stv090x_start_search()
1580 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) stv090x_start_search()
1586 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) stv090x_start_search()
1588 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) stv090x_start_search()
1601 static int stv090x_get_agc2_min_level(struct stv090x_state *state) stv090x_get_agc2_min_level() argument
1606 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) stv090x_get_agc2_min_level()
1608 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_get_agc2_min_level()
1611 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_get_agc2_min_level()
1614 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ stv090x_get_agc2_min_level()
1616 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) stv090x_get_agc2_min_level()
1618 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ stv090x_get_agc2_min_level()
1620 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) stv090x_get_agc2_min_level()
1622 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ stv090x_get_agc2_min_level()
1624 if (stv090x_set_srate(state, 1000000) < 0) stv090x_get_agc2_min_level()
1627 steps = state->search_range / 1000000; stv090x_get_agc2_min_level()
1632 freq_step = (1000000 * 256) / (state->internal->mclk / 256); stv090x_get_agc2_min_level()
1643 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ stv090x_get_agc2_min_level()
1645 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) stv090x_get_agc2_min_level()
1647 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) stv090x_get_agc2_min_level()
1649 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ stv090x_get_agc2_min_level()
1655 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | stv090x_get_agc2_min_level()
1656 STV090x_READ_DEMOD(state, AGC2I0); stv090x_get_agc2_min_level()
1669 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) stv090x_get_srate() argument
1674 r3 = STV090x_READ_DEMOD(state, SFR3); stv090x_get_srate()
1675 r2 = STV090x_READ_DEMOD(state, SFR2); stv090x_get_srate()
1676 r1 = STV090x_READ_DEMOD(state, SFR1); stv090x_get_srate()
1677 r0 = STV090x_READ_DEMOD(state, SFR0); stv090x_get_srate()
1694 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) stv090x_srate_srch_coarse() argument
1696 struct dvb_frontend *fe = &state->frontend; stv090x_srate_srch_coarse()
1703 if (state->internal->dev_ver >= 0x30) stv090x_srate_srch_coarse()
1708 reg = STV090x_READ_DEMOD(state, DMDISTATE); stv090x_srate_srch_coarse()
1710 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) stv090x_srate_srch_coarse()
1712 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) stv090x_srate_srch_coarse()
1714 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) stv090x_srate_srch_coarse()
1716 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) stv090x_srate_srch_coarse()
1718 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) stv090x_srate_srch_coarse()
1720 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_srate_srch_coarse()
1723 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_srate_srch_coarse()
1726 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) stv090x_srate_srch_coarse()
1728 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) stv090x_srate_srch_coarse()
1730 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) stv090x_srate_srch_coarse()
1732 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) stv090x_srate_srch_coarse()
1734 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) stv090x_srate_srch_coarse()
1736 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) stv090x_srate_srch_coarse()
1739 if (state->internal->dev_ver >= 0x30) { stv090x_srate_srch_coarse()
1740 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) stv090x_srate_srch_coarse()
1742 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) stv090x_srate_srch_coarse()
1745 } else if (state->internal->dev_ver >= 0x20) { stv090x_srate_srch_coarse()
1746 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) stv090x_srate_srch_coarse()
1748 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) stv090x_srate_srch_coarse()
1752 if (state->srate <= 2000000) stv090x_srate_srch_coarse()
1754 else if (state->srate <= 5000000) stv090x_srate_srch_coarse()
1756 else if (state->srate <= 12000000) stv090x_srate_srch_coarse()
1761 steps = -1 + ((state->search_range / 1000) / car_step); stv090x_srate_srch_coarse()
1768 car_step = (state->search_range / 1000) / 10; stv090x_srate_srch_coarse()
1772 freq = state->frequency; stv090x_srate_srch_coarse()
1775 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ stv090x_srate_srch_coarse()
1777 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) stv090x_srate_srch_coarse()
1779 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) stv090x_srate_srch_coarse()
1781 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) stv090x_srate_srch_coarse()
1783 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) stv090x_srate_srch_coarse()
1786 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) stv090x_srate_srch_coarse()
1790 reg = STV090x_READ_DEMOD(state, DSTATUS); stv090x_srate_srch_coarse()
1793 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | stv090x_srate_srch_coarse()
1794 STV090x_READ_DEMOD(state, AGC2I0); stv090x_srate_srch_coarse()
1797 srate_coarse = stv090x_get_srate(state, state->internal->mclk); stv090x_srate_srch_coarse()
1810 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_srate_srch_coarse()
1813 if (state->config->tuner_set_frequency) { stv090x_srate_srch_coarse()
1814 if (state->config->tuner_set_frequency(fe, freq) < 0) stv090x_srate_srch_coarse()
1818 if (state->config->tuner_set_bandwidth) { stv090x_srate_srch_coarse()
1819 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) stv090x_srate_srch_coarse()
1823 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_srate_srch_coarse()
1828 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_srate_srch_coarse()
1831 if (state->config->tuner_get_status) { stv090x_srate_srch_coarse()
1832 if (state->config->tuner_get_status(fe, &reg) < 0) stv090x_srate_srch_coarse()
1841 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_srate_srch_coarse()
1849 srate_coarse = stv090x_get_srate(state, state->internal->mclk); stv090x_srate_srch_coarse()
1854 stv090x_i2c_gate_ctrl(state, 0); stv090x_srate_srch_coarse()
1860 static u32 stv090x_srate_srch_fine(struct stv090x_state *state) stv090x_srate_srch_fine() argument
1864 srate_coarse = stv090x_get_srate(state, state->internal->mclk); stv090x_srate_srch_fine()
1865 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; stv090x_srate_srch_fine()
1866 freq_coarse |= STV090x_READ_DEMOD(state, CFR1); stv090x_srate_srch_fine()
1869 if (sym < state->srate) stv090x_srate_srch_fine()
1872 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ stv090x_srate_srch_fine()
1874 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) stv090x_srate_srch_fine()
1876 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) stv090x_srate_srch_fine()
1878 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) stv090x_srate_srch_fine()
1880 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) stv090x_srate_srch_fine()
1882 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_srate_srch_fine()
1884 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_srate_srch_fine()
1887 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) stv090x_srate_srch_fine()
1890 if (state->internal->dev_ver >= 0x30) { stv090x_srate_srch_fine()
1891 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) stv090x_srate_srch_fine()
1893 } else if (state->internal->dev_ver >= 0x20) { stv090x_srate_srch_fine()
1894 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) stv090x_srate_srch_fine()
1901 sym /= (state->internal->mclk / 1000); stv090x_srate_srch_fine()
1902 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) stv090x_srate_srch_fine()
1904 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) stv090x_srate_srch_fine()
1908 sym /= (state->internal->mclk / 1000); stv090x_srate_srch_fine()
1909 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) stv090x_srate_srch_fine()
1911 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) stv090x_srate_srch_fine()
1914 sym /= (state->internal->mclk / 1000); stv090x_srate_srch_fine()
1915 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) stv090x_srate_srch_fine()
1917 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) stv090x_srate_srch_fine()
1922 sym /= (state->internal->mclk / 100); stv090x_srate_srch_fine()
1923 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) stv090x_srate_srch_fine()
1925 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) stv090x_srate_srch_fine()
1929 sym /= (state->internal->mclk / 100); stv090x_srate_srch_fine()
1930 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) stv090x_srate_srch_fine()
1932 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) stv090x_srate_srch_fine()
1935 sym /= (state->internal->mclk / 100); stv090x_srate_srch_fine()
1936 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) stv090x_srate_srch_fine()
1938 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) stv090x_srate_srch_fine()
1941 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) stv090x_srate_srch_fine()
1943 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) stv090x_srate_srch_fine()
1945 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) stv090x_srate_srch_fine()
1947 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ stv090x_srate_srch_fine()
1958 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) stv090x_get_dmdlock() argument
1965 reg = STV090x_READ_DEMOD(state, DMDSTATE); stv090x_get_dmdlock()
1977 reg = STV090x_READ_DEMOD(state, DSTATUS); stv090x_get_dmdlock()
1992 static int stv090x_blind_search(struct stv090x_state *state) stv090x_blind_search() argument
2003 agc2 = stv090x_get_agc2_min_level(state); stv090x_blind_search()
2005 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { stv090x_blind_search()
2009 if (state->internal->dev_ver <= 0x20) { stv090x_blind_search()
2010 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) stv090x_blind_search()
2014 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) stv090x_blind_search()
2018 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) stv090x_blind_search()
2021 if (state->internal->dev_ver >= 0x20) { stv090x_blind_search()
2022 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) stv090x_blind_search()
2024 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) stv090x_blind_search()
2026 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) stv090x_blind_search()
2028 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ stv090x_blind_search()
2034 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) stv090x_blind_search()
2036 if (stv090x_srate_srch_coarse(state) != 0) { stv090x_blind_search()
2037 srate_coarse = stv090x_srate_srch_fine(state); stv090x_blind_search()
2039 stv090x_get_lock_tmg(state); stv090x_blind_search()
2040 lock = stv090x_get_dmdlock(state, stv090x_blind_search()
2041 state->DemodTimeout); stv090x_blind_search()
2049 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | stv090x_blind_search()
2050 STV090x_READ_DEMOD(state, AGC2I0); stv090x_blind_search()
2053 reg = STV090x_READ_DEMOD(state, DSTATUS2); stv090x_blind_search()
2075 static int stv090x_chk_tmg(struct stv090x_state *state) stv090x_chk_tmg() argument
2082 freq = STV090x_READ_DEMOD(state, CARFREQ); stv090x_chk_tmg()
2083 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); stv090x_chk_tmg()
2084 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); stv090x_chk_tmg()
2085 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) stv090x_chk_tmg()
2087 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) stv090x_chk_tmg()
2090 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_chk_tmg()
2092 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_chk_tmg()
2094 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) stv090x_chk_tmg()
2097 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) stv090x_chk_tmg()
2099 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) stv090x_chk_tmg()
2102 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ stv090x_chk_tmg()
2104 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) stv090x_chk_tmg()
2106 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) stv090x_chk_tmg()
2109 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ stv090x_chk_tmg()
2114 reg = STV090x_READ_DEMOD(state, DSTATUS); stv090x_chk_tmg()
2122 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) stv090x_chk_tmg()
2124 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ stv090x_chk_tmg()
2126 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ stv090x_chk_tmg()
2129 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) stv090x_chk_tmg()
2131 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) stv090x_chk_tmg()
2133 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) stv090x_chk_tmg()
2143 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) stv090x_get_coldlock() argument
2145 struct dvb_frontend *fe = &state->frontend; stv090x_get_coldlock()
2151 if (state->srate >= 10000000) stv090x_get_coldlock()
2156 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ stv090x_get_coldlock()
2160 if (state->srate >= 10000000) { stv090x_get_coldlock()
2161 if (stv090x_chk_tmg(state)) { stv090x_get_coldlock()
2162 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) stv090x_get_coldlock()
2164 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) stv090x_get_coldlock()
2166 return stv090x_get_dmdlock(state, timeout_dmd); stv090x_get_coldlock()
2171 if (state->srate <= 4000000) stv090x_get_coldlock()
2173 else if (state->srate <= 7000000) stv090x_get_coldlock()
2175 else if (state->srate <= 10000000) stv090x_get_coldlock()
2180 steps = (state->search_range / 1000) / car_step; stv090x_get_coldlock()
2191 freq = state->frequency; stv090x_get_coldlock()
2192 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; stv090x_get_coldlock()
2200 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_get_coldlock()
2203 if (state->config->tuner_set_frequency) { stv090x_get_coldlock()
2204 if (state->config->tuner_set_frequency(fe, freq) < 0) stv090x_get_coldlock()
2208 if (state->config->tuner_set_bandwidth) { stv090x_get_coldlock()
2209 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) stv090x_get_coldlock()
2213 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_get_coldlock()
2218 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_get_coldlock()
2221 if (state->config->tuner_get_status) { stv090x_get_coldlock()
2222 if (state->config->tuner_get_status(fe, &reg) < 0) stv090x_get_coldlock()
2231 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_get_coldlock()
2234 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); stv090x_get_coldlock()
2235 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) stv090x_get_coldlock()
2237 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) stv090x_get_coldlock()
2239 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) stv090x_get_coldlock()
2241 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) stv090x_get_coldlock()
2243 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); stv090x_get_coldlock()
2252 stv090x_i2c_gate_ctrl(state, 0); stv090x_get_coldlock()
2258 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) stv090x_get_loop_params() argument
2262 srate = state->srate; stv090x_get_loop_params()
2263 car_max = state->search_range / 1000; stv090x_get_loop_params()
2266 car_max /= (state->internal->mclk / 1000); stv090x_get_loop_params()
2272 inc /= state->internal->mclk / 1000; stv090x_get_loop_params()
2277 switch (state->search_mode) { stv090x_get_loop_params()
2318 static int stv090x_chk_signal(struct stv090x_state *state) stv090x_chk_signal() argument
2323 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; stv090x_chk_signal()
2324 offst_car |= STV090x_READ_DEMOD(state, CFR1); stv090x_chk_signal()
2327 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; stv090x_chk_signal()
2328 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); stv090x_chk_signal()
2329 car_max = state->search_range / 1000; stv090x_chk_signal()
2333 car_max /= state->internal->mclk / 1000; stv090x_chk_signal()
2349 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) stv090x_search_car_loop() argument
2355 car_max = state->search_range / 1000; stv090x_search_car_loop()
2358 car_max /= (state->internal->mclk / 1000); stv090x_search_car_loop()
2368 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) stv090x_search_car_loop()
2370 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) stv090x_search_car_loop()
2372 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) stv090x_search_car_loop()
2374 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) stv090x_search_car_loop()
2377 reg = STV090x_READ_DEMOD(state, PDELCTRL1); stv090x_search_car_loop()
2379 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) stv090x_search_car_loop()
2393 lock = stv090x_get_dmdlock(state, timeout); stv090x_search_car_loop()
2394 no_signal = stv090x_chk_signal(state); stv090x_search_car_loop()
2402 reg = STV090x_READ_DEMOD(state, PDELCTRL1); stv090x_search_car_loop()
2404 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) stv090x_search_car_loop()
2413 static int stv090x_sw_algo(struct stv090x_state *state) stv090x_sw_algo() argument
2422 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); stv090x_sw_algo()
2424 switch (state->search_mode) { stv090x_sw_algo()
2428 if (state->internal->dev_ver >= 0x20) { stv090x_sw_algo()
2429 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) stv090x_sw_algo()
2433 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) stv090x_sw_algo()
2439 if (state->internal->dev_ver >= 0x20) { stv090x_sw_algo()
2440 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) stv090x_sw_algo()
2444 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) stv090x_sw_algo()
2452 if (state->internal->dev_ver >= 0x20) { stv090x_sw_algo()
2453 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) stv090x_sw_algo()
2455 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) stv090x_sw_algo()
2459 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) stv090x_sw_algo()
2467 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); stv090x_sw_algo()
2468 no_signal = stv090x_chk_signal(state); stv090x_sw_algo()
2474 if (state->internal->dev_ver >= 0x20) { stv090x_sw_algo()
2475 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) stv090x_sw_algo()
2477 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) stv090x_sw_algo()
2481 reg = STV090x_READ_DEMOD(state, DMDSTATE); stv090x_sw_algo()
2485 reg = STV090x_READ_DEMOD(state, DMDFLYW); stv090x_sw_algo()
2489 reg = STV090x_READ_DEMOD(state, DMDFLYW); stv090x_sw_algo()
2496 if (state->internal->dev_ver >= 0x20) { stv090x_sw_algo()
2497 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) stv090x_sw_algo()
2501 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) stv090x_sw_algo()
2515 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) stv090x_get_std() argument
2520 reg = STV090x_READ_DEMOD(state, DMDSTATE); stv090x_get_std()
2524 reg = STV090x_READ_DEMOD(state, FECM); stv090x_get_std()
2537 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) stv090x_get_car_freq() argument
2541 derot = STV090x_READ_DEMOD(state, CFR2) << 16; stv090x_get_car_freq()
2542 derot |= STV090x_READ_DEMOD(state, CFR1) << 8; stv090x_get_car_freq()
2543 derot |= STV090x_READ_DEMOD(state, CFR0); stv090x_get_car_freq()
2560 static int stv090x_get_viterbi(struct stv090x_state *state) stv090x_get_viterbi() argument
2564 reg = STV090x_READ_DEMOD(state, VITCURPUN); stv090x_get_viterbi()
2569 state->fec = STV090x_PR12; stv090x_get_viterbi()
2573 state->fec = STV090x_PR23; stv090x_get_viterbi()
2577 state->fec = STV090x_PR34; stv090x_get_viterbi()
2581 state->fec = STV090x_PR56; stv090x_get_viterbi()
2585 state->fec = STV090x_PR67; stv090x_get_viterbi()
2589 state->fec = STV090x_PR78; stv090x_get_viterbi()
2593 state->fec = STV090x_PRERR; stv090x_get_viterbi()
2600 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) stv090x_get_sig_params() argument
2602 struct dvb_frontend *fe = &state->frontend; stv090x_get_sig_params()
2610 if (state->algo == STV090x_BLIND_SEARCH) { stv090x_get_sig_params()
2611 tmg = STV090x_READ_DEMOD(state, TMGREG2); stv090x_get_sig_params()
2612 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); stv090x_get_sig_params()
2614 tmg = STV090x_READ_DEMOD(state, TMGREG2); stv090x_get_sig_params()
2619 state->delsys = stv090x_get_std(state); stv090x_get_sig_params()
2621 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_get_sig_params()
2624 if (state->config->tuner_get_frequency) { stv090x_get_sig_params()
2625 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) stv090x_get_sig_params()
2629 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_get_sig_params()
2632 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; stv090x_get_sig_params()
2633 state->frequency += offst_freq; stv090x_get_sig_params()
2635 if (stv090x_get_viterbi(state) < 0) stv090x_get_sig_params()
2638 reg = STV090x_READ_DEMOD(state, DMDMODCOD); stv090x_get_sig_params()
2639 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); stv090x_get_sig_params()
2640 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; stv090x_get_sig_params()
2641 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; stv090x_get_sig_params()
2642 reg = STV090x_READ_DEMOD(state, TMGOBS); stv090x_get_sig_params()
2643 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); stv090x_get_sig_params()
2644 reg = STV090x_READ_DEMOD(state, FECM); stv090x_get_sig_params()
2645 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); stv090x_get_sig_params()
2647 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { stv090x_get_sig_params()
2649 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_get_sig_params()
2652 if (state->config->tuner_get_frequency) { stv090x_get_sig_params()
2653 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) stv090x_get_sig_params()
2657 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_get_sig_params()
2660 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) stv090x_get_sig_params()
2662 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) stv090x_get_sig_params()
2665 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) stv090x_get_sig_params()
2672 stv090x_i2c_gate_ctrl(state, 0); stv090x_get_sig_params()
2678 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) stv090x_get_tmgoffst() argument
2682 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; stv090x_get_tmgoffst()
2683 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; stv090x_get_tmgoffst()
2684 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); stv090x_get_tmgoffst()
2696 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) stv090x_optimize_carloop() argument
2702 if (state->internal->dev_ver == 0x20) { stv090x_optimize_carloop()
2738 if (state->srate <= 3000000) stv090x_optimize_carloop()
2740 else if (state->srate <= 7000000) stv090x_optimize_carloop()
2742 else if (state->srate <= 15000000) stv090x_optimize_carloop()
2744 else if (state->srate <= 25000000) stv090x_optimize_carloop()
2749 if (state->srate <= 3000000) stv090x_optimize_carloop()
2751 else if (state->srate <= 7000000) stv090x_optimize_carloop()
2753 else if (state->srate <= 15000000) stv090x_optimize_carloop()
2755 else if (state->srate <= 25000000) stv090x_optimize_carloop()
2763 if (state->srate <= 3000000) stv090x_optimize_carloop()
2765 else if (state->srate <= 7000000) stv090x_optimize_carloop()
2767 else if (state->srate <= 15000000) stv090x_optimize_carloop()
2769 else if (state->srate <= 25000000) stv090x_optimize_carloop()
2774 if (state->srate <= 3000000) stv090x_optimize_carloop()
2776 else if (state->srate <= 7000000) stv090x_optimize_carloop()
2778 else if (state->srate <= 15000000) stv090x_optimize_carloop()
2780 else if (state->srate <= 25000000) stv090x_optimize_carloop()
2792 if (state->srate <= 3000000) stv090x_optimize_carloop()
2794 else if (state->srate <= 7000000) stv090x_optimize_carloop()
2796 else if (state->srate <= 15000000) stv090x_optimize_carloop()
2798 else if (state->srate <= 25000000) stv090x_optimize_carloop()
2807 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) stv090x_optimize_carloop_short() argument
2813 switch (state->modulation) { stv090x_optimize_carloop_short()
2829 if (state->internal->dev_ver >= 0x30) { stv090x_optimize_carloop_short()
2837 if (state->srate <= 3000000) stv090x_optimize_carloop_short()
2839 else if (state->srate <= 7000000) stv090x_optimize_carloop_short()
2841 else if (state->srate <= 15000000) stv090x_optimize_carloop_short()
2843 else if (state->srate <= 25000000) stv090x_optimize_carloop_short()
2851 static int stv090x_optimize_track(struct stv090x_state *state) stv090x_optimize_track() argument
2853 struct dvb_frontend *fe = &state->frontend; stv090x_optimize_track()
2860 srate = stv090x_get_srate(state, state->internal->mclk); stv090x_optimize_track()
2861 srate += stv090x_get_tmgoffst(state, srate); stv090x_optimize_track()
2863 switch (state->delsys) { stv090x_optimize_track()
2866 if (state->search_mode == STV090x_SEARCH_AUTO) { stv090x_optimize_track()
2867 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_optimize_track()
2870 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_optimize_track()
2873 reg = STV090x_READ_DEMOD(state, DEMOD); stv090x_optimize_track()
2874 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); stv090x_optimize_track()
2876 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) stv090x_optimize_track()
2879 if (state->internal->dev_ver >= 0x30) { stv090x_optimize_track()
2880 if (stv090x_get_viterbi(state) < 0) stv090x_optimize_track()
2883 if (state->fec == STV090x_PR12) { stv090x_optimize_track()
2884 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) stv090x_optimize_track()
2886 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) stv090x_optimize_track()
2889 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) stv090x_optimize_track()
2891 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) stv090x_optimize_track()
2896 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) stv090x_optimize_track()
2901 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_optimize_track()
2904 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_optimize_track()
2906 if (state->internal->dev_ver >= 0x30) { stv090x_optimize_track()
2907 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) stv090x_optimize_track()
2909 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) stv090x_optimize_track()
2912 if (state->frame_len == STV090x_LONG_FRAME) { stv090x_optimize_track()
2913 reg = STV090x_READ_DEMOD(state, DMDMODCOD); stv090x_optimize_track()
2916 aclc = stv090x_optimize_carloop(state, modcod, pilots); stv090x_optimize_track()
2918 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); stv090x_optimize_track()
2920 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) stv090x_optimize_track()
2922 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) stv090x_optimize_track()
2925 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { stv090x_optimize_track()
2927 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) stv090x_optimize_track()
2929 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) stv090x_optimize_track()
2932 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) stv090x_optimize_track()
2934 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) stv090x_optimize_track()
2940 aclc = stv090x_optimize_carloop_short(state); stv090x_optimize_track()
2941 if (state->modulation == STV090x_QPSK) { stv090x_optimize_track()
2942 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) stv090x_optimize_track()
2944 } else if (state->modulation == STV090x_8PSK) { stv090x_optimize_track()
2945 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) stv090x_optimize_track()
2947 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) stv090x_optimize_track()
2949 } else if (state->modulation == STV090x_16APSK) { stv090x_optimize_track()
2950 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) stv090x_optimize_track()
2952 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) stv090x_optimize_track()
2954 } else if (state->modulation == STV090x_32APSK) { stv090x_optimize_track()
2955 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) stv090x_optimize_track()
2957 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) stv090x_optimize_track()
2962 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */ stv090x_optimize_track()
2967 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_optimize_track()
2970 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_optimize_track()
2975 f_1 = STV090x_READ_DEMOD(state, CFR2); stv090x_optimize_track()
2976 f_0 = STV090x_READ_DEMOD(state, CFR1); stv090x_optimize_track()
2977 reg = STV090x_READ_DEMOD(state, TMGOBS); stv090x_optimize_track()
2979 if (state->algo == STV090x_BLIND_SEARCH) { stv090x_optimize_track()
2980 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); stv090x_optimize_track()
2981 reg = STV090x_READ_DEMOD(state, DMDCFGMD); stv090x_optimize_track()
2984 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) stv090x_optimize_track()
2986 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) stv090x_optimize_track()
2989 if (stv090x_set_srate(state, srate) < 0) stv090x_optimize_track()
2993 if (stv090x_dvbs_track_crl(state) < 0) stv090x_optimize_track()
2997 if (state->internal->dev_ver >= 0x20) { stv090x_optimize_track()
2998 if ((state->search_mode == STV090x_SEARCH_DVBS1) || stv090x_optimize_track()
2999 (state->search_mode == STV090x_SEARCH_DSS) || stv090x_optimize_track()
3000 (state->search_mode == STV090x_SEARCH_AUTO)) { stv090x_optimize_track()
3002 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) stv090x_optimize_track()
3004 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) stv090x_optimize_track()
3009 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) stv090x_optimize_track()
3013 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) stv090x_optimize_track()
3016 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) stv090x_optimize_track()
3019 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || stv090x_optimize_track()
3020 (state->srate < 10000000)) { stv090x_optimize_track()
3022 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) stv090x_optimize_track()
3024 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) stv090x_optimize_track()
3026 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; stv090x_optimize_track()
3028 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { stv090x_optimize_track()
3030 if (state->algo != STV090x_WARM_SEARCH) { stv090x_optimize_track()
3032 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_optimize_track()
3035 if (state->config->tuner_set_bandwidth) { stv090x_optimize_track()
3036 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) stv090x_optimize_track()
3040 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_optimize_track()
3045 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) stv090x_optimize_track()
3050 stv090x_get_lock_tmg(state); stv090x_optimize_track()
3052 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { stv090x_optimize_track()
3053 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) stv090x_optimize_track()
3055 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) stv090x_optimize_track()
3057 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) stv090x_optimize_track()
3059 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) stv090x_optimize_track()
3064 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { stv090x_optimize_track()
3066 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) stv090x_optimize_track()
3068 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) stv090x_optimize_track()
3070 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) stv090x_optimize_track()
3072 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) stv090x_optimize_track()
3080 if (state->internal->dev_ver >= 0x20) { stv090x_optimize_track()
3081 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) stv090x_optimize_track()
3085 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) stv090x_optimize_track()
3086 stv090x_set_vit_thtracq(state); stv090x_optimize_track()
3091 stv090x_i2c_gate_ctrl(state, 0); stv090x_optimize_track()
3097 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) stv090x_get_feclock() argument
3103 reg = STV090x_READ_DEMOD(state, DMDSTATE); stv090x_get_feclock()
3114 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); stv090x_get_feclock()
3119 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); stv090x_get_feclock()
3131 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) stv090x_get_lock() argument
3137 lock = stv090x_get_dmdlock(state, timeout_dmd); stv090x_get_lock()
3139 lock = stv090x_get_feclock(state, timeout_fec); stv090x_get_lock()
3145 reg = STV090x_READ_DEMOD(state, TSSTATUS); stv090x_get_lock()
3155 static int stv090x_set_s2rolloff(struct stv090x_state *state) stv090x_set_s2rolloff() argument
3159 if (state->internal->dev_ver <= 0x20) { stv090x_set_s2rolloff()
3161 reg = STV090x_READ_DEMOD(state, DEMOD); stv090x_set_s2rolloff()
3163 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) stv090x_set_s2rolloff()
3167 reg = STV090x_READ_DEMOD(state, DEMOD); stv090x_set_s2rolloff()
3169 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) stv090x_set_s2rolloff()
3179 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) stv090x_algo() argument
3181 struct dvb_frontend *fe = &state->frontend; stv090x_algo()
3187 reg = STV090x_READ_DEMOD(state, TSCFGH); stv090x_algo()
3189 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) stv090x_algo()
3192 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ stv090x_algo()
3195 if (state->internal->dev_ver >= 0x20) { stv090x_algo()
3196 if (state->srate > 5000000) { stv090x_algo()
3197 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) stv090x_algo()
3200 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) stv090x_algo()
3205 stv090x_get_lock_tmg(state); stv090x_algo()
3207 if (state->algo == STV090x_BLIND_SEARCH) { stv090x_algo()
3208 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ stv090x_algo()
3209 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ stv090x_algo()
3211 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) stv090x_algo()
3213 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */ stv090x_algo()
3217 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) stv090x_algo()
3219 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) stv090x_algo()
3222 if (state->srate < 2000000) { stv090x_algo()
3224 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) stv090x_algo()
3228 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) stv090x_algo()
3232 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) stv090x_algo()
3235 if (state->internal->dev_ver >= 0x20) { stv090x_algo()
3236 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) stv090x_algo()
3238 if (state->algo == STV090x_COLD_SEARCH) stv090x_algo()
3239 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; stv090x_algo()
3240 else if (state->algo == STV090x_WARM_SEARCH) stv090x_algo()
3241 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; stv090x_algo()
3247 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ stv090x_algo()
3250 if (stv090x_set_srate(state, state->srate) < 0) stv090x_algo()
3253 if (stv090x_set_max_srate(state, state->internal->mclk, stv090x_algo()
3254 state->srate) < 0) stv090x_algo()
3256 if (stv090x_set_min_srate(state, state->internal->mclk, stv090x_algo()
3257 state->srate) < 0) stv090x_algo()
3260 if (state->srate >= 10000000) stv090x_algo()
3267 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_algo()
3270 if (state->config->tuner_set_bbgain) { stv090x_algo()
3271 reg = state->config->tuner_bbgain; stv090x_algo()
3274 if (state->config->tuner_set_bbgain(fe, reg) < 0) stv090x_algo()
3278 if (state->config->tuner_set_frequency) { stv090x_algo()
3279 if (state->config->tuner_set_frequency(fe, state->frequency) < 0) stv090x_algo()
3283 if (state->config->tuner_set_bandwidth) { stv090x_algo()
3284 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) stv090x_algo()
3288 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_algo()
3293 if (state->config->tuner_get_status) { stv090x_algo()
3294 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_algo()
3296 if (state->config->tuner_get_status(fe, &reg) < 0) stv090x_algo()
3298 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_algo()
3310 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), stv090x_algo()
3311 STV090x_READ_DEMOD(state, AGCIQIN0)); stv090x_algo()
3318 power_iq += (STV090x_READ_DEMOD(state, POWERI) + stv090x_algo()
3319 STV090x_READ_DEMOD(state, POWERQ)) >> 1; stv090x_algo()
3329 reg = STV090x_READ_DEMOD(state, DEMOD); stv090x_algo()
3330 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); stv090x_algo()
3332 if (state->internal->dev_ver <= 0x20) { stv090x_algo()
3339 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) stv090x_algo()
3342 if (stv090x_delivery_search(state) < 0) stv090x_algo()
3345 if (state->algo != STV090x_BLIND_SEARCH) { stv090x_algo()
3346 if (stv090x_start_search(state) < 0) stv090x_algo()
3354 if (state->algo == STV090x_BLIND_SEARCH) stv090x_algo()
3355 lock = stv090x_blind_search(state); stv090x_algo()
3357 else if (state->algo == STV090x_COLD_SEARCH) stv090x_algo()
3358 lock = stv090x_get_coldlock(state, state->DemodTimeout); stv090x_algo()
3360 else if (state->algo == STV090x_WARM_SEARCH) stv090x_algo()
3361 lock = stv090x_get_dmdlock(state, state->DemodTimeout); stv090x_algo()
3363 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { stv090x_algo()
3365 if (stv090x_chk_tmg(state)) stv090x_algo()
3366 lock = stv090x_sw_algo(state); stv090x_algo()
3371 signal_state = stv090x_get_sig_params(state); stv090x_algo()
3374 stv090x_optimize_track(state); stv090x_algo()
3376 if (state->internal->dev_ver >= 0x20) { stv090x_algo()
3380 reg = STV090x_READ_DEMOD(state, TSCFGH); stv090x_algo()
3382 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) stv090x_algo()
3388 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) stv090x_algo()
3392 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) stv090x_algo()
3396 lock = stv090x_get_lock(state, state->FecTimeout, stv090x_algo()
3397 state->FecTimeout); stv090x_algo()
3399 if (state->delsys == STV090x_DVBS2) { stv090x_algo()
3400 stv090x_set_s2rolloff(state); stv090x_algo()
3402 reg = STV090x_READ_DEMOD(state, PDELCTRL2); stv090x_algo()
3404 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) stv090x_algo()
3407 reg = STV090x_READ_DEMOD(state, PDELCTRL2); stv090x_algo()
3409 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) stv090x_algo()
3412 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */ stv090x_algo()
3415 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) stv090x_algo()
3419 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) stv090x_algo()
3422 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) stv090x_algo()
3426 stv090x_chk_signal(state); stv090x_algo()
3432 stv090x_i2c_gate_ctrl(state, 0); stv090x_algo()
3438 static int stv090x_set_mis(struct stv090x_state *state, int mis) stv090x_set_mis() argument
3444 reg = STV090x_READ_DEMOD(state, PDELCTRL1); stv090x_set_mis()
3446 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) stv090x_set_mis()
3450 reg = STV090x_READ_DEMOD(state, PDELCTRL1); stv090x_set_mis()
3452 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) stv090x_set_mis()
3454 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) stv090x_set_mis()
3456 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0) stv090x_set_mis()
3467 struct stv090x_state *state = fe->demodulator_priv; stv090x_search() local
3475 state->delsys = STV090x_DSS; stv090x_search()
3478 state->delsys = STV090x_DVBS1; stv090x_search()
3481 state->delsys = STV090x_DVBS2; stv090x_search()
3487 state->frequency = props->frequency; stv090x_search()
3488 state->srate = props->symbol_rate; stv090x_search()
3489 state->search_mode = STV090x_SEARCH_AUTO; stv090x_search()
3490 state->algo = STV090x_COLD_SEARCH; stv090x_search()
3491 state->fec = STV090x_PRERR; stv090x_search()
3492 if (state->srate > 10000000) { stv090x_search()
3494 state->search_range = 10000000; stv090x_search()
3497 state->search_range = 5000000; stv090x_search()
3500 stv090x_set_mis(state, props->stream_id); stv090x_search()
3502 if (stv090x_algo(state) == STV090x_RANGEOK) { stv090x_search()
3515 struct stv090x_state *state = fe->demodulator_priv; stv090x_read_status() local
3521 dstatus = STV090x_READ_DEMOD(state, DSTATUS); stv090x_read_status()
3525 reg = STV090x_READ_DEMOD(state, DMDSTATE); stv090x_read_status()
3538 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); stv090x_read_status()
3541 reg = STV090x_READ_DEMOD(state, TSSTATUS); stv090x_read_status()
3551 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); stv090x_read_status()
3554 reg = STV090x_READ_DEMOD(state, TSSTATUS); stv090x_read_status()
3567 struct stv090x_state *state = fe->demodulator_priv; stv090x_read_per() local
3578 reg = STV090x_READ_DEMOD(state, ERRCNT22); stv090x_read_per()
3581 reg = STV090x_READ_DEMOD(state, ERRCNT21); stv090x_read_per()
3584 reg = STV090x_READ_DEMOD(state, ERRCNT20); stv090x_read_per()
3589 count_4 = STV090x_READ_DEMOD(state, FBERCPT4); stv090x_read_per()
3590 count_3 = STV090x_READ_DEMOD(state, FBERCPT3); stv090x_read_per()
3591 count_2 = STV090x_READ_DEMOD(state, FBERCPT2); stv090x_read_per()
3592 count_1 = STV090x_READ_DEMOD(state, FBERCPT1); stv090x_read_per()
3593 count_0 = STV090x_READ_DEMOD(state, FBERCPT0); stv090x_read_per()
3605 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) stv090x_read_per()
3607 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) stv090x_read_per()
3654 struct stv090x_state *state = fe->demodulator_priv; stv090x_read_signal_strength() local
3659 reg = STV090x_READ_DEMOD(state, AGCIQIN1); stv090x_read_signal_strength()
3661 reg = STV090x_READ_DEMOD(state, AGCIQIN0); stv090x_read_signal_strength()
3678 struct stv090x_state *state = fe->demodulator_priv; stv090x_read_cnr() local
3685 switch (state->delsys) { stv090x_read_cnr()
3687 reg = STV090x_READ_DEMOD(state, DSTATUS); stv090x_read_cnr()
3692 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); stv090x_read_cnr()
3694 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); stv090x_read_cnr()
3709 reg = STV090x_READ_DEMOD(state, DSTATUS); stv090x_read_cnr()
3714 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); stv090x_read_cnr()
3716 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); stv090x_read_cnr()
3737 struct stv090x_state *state = fe->demodulator_priv; stv090x_set_tone() local
3740 reg = STV090x_READ_DEMOD(state, DISTXCTL); stv090x_set_tone()
3745 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_set_tone()
3748 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_set_tone()
3755 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_set_tone()
3776 struct stv090x_state *state = fe->demodulator_priv; stv090x_send_diseqc_msg() local
3780 reg = STV090x_READ_DEMOD(state, DISTXCTL); stv090x_send_diseqc_msg()
3783 (state->config->diseqc_envelope_mode) ? 4 : 2); stv090x_send_diseqc_msg()
3785 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_msg()
3788 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_msg()
3792 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_msg()
3798 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); stv090x_send_diseqc_msg()
3802 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) stv090x_send_diseqc_msg()
3805 reg = STV090x_READ_DEMOD(state, DISTXCTL); stv090x_send_diseqc_msg()
3807 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_msg()
3813 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); stv090x_send_diseqc_msg()
3827 struct stv090x_state *state = fe->demodulator_priv; stv090x_send_diseqc_burst() local
3832 reg = STV090x_READ_DEMOD(state, DISTXCTL); stv090x_send_diseqc_burst()
3835 mode = (state->config->diseqc_envelope_mode) ? 5 : 3; stv090x_send_diseqc_burst()
3838 mode = (state->config->diseqc_envelope_mode) ? 4 : 2; stv090x_send_diseqc_burst()
3844 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_burst()
3847 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_burst()
3851 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_burst()
3855 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); stv090x_send_diseqc_burst()
3859 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) stv090x_send_diseqc_burst()
3862 reg = STV090x_READ_DEMOD(state, DISTXCTL); stv090x_send_diseqc_burst()
3864 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) stv090x_send_diseqc_burst()
3870 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); stv090x_send_diseqc_burst()
3884 struct stv090x_state *state = fe->demodulator_priv; stv090x_recv_slave_reply() local
3890 reg = STV090x_READ_DEMOD(state, DISRX_ST0); stv090x_recv_slave_reply()
3897 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); stv090x_recv_slave_reply()
3905 struct stv090x_state *state = fe->demodulator_priv; stv090x_sleep() local
3909 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_sleep()
3912 if (state->config->tuner_sleep) { stv090x_sleep()
3913 if (state->config->tuner_sleep(fe) < 0) stv090x_sleep()
3917 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_sleep()
3921 state->device == STV0900 ? "STV0900" : "STV0903", stv090x_sleep()
3922 state->demod); stv090x_sleep()
3924 mutex_lock(&state->internal->demod_lock); stv090x_sleep()
3926 switch (state->demod) { stv090x_sleep()
3929 reg = stv090x_read_reg(state, STV090x_TSTTNR1); stv090x_sleep()
3931 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) stv090x_sleep()
3934 reg = stv090x_read_reg(state, STV090x_TSTTNR2); stv090x_sleep()
3936 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) stv090x_sleep()
3941 reg = stv090x_read_reg(state, STV090x_TSTTNR3); stv090x_sleep()
3946 reg = stv090x_read_reg(state, STV090x_STOPCLK1); stv090x_sleep()
3955 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) stv090x_sleep()
3957 reg = stv090x_read_reg(state, STV090x_STOPCLK2); stv090x_sleep()
3966 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) stv090x_sleep()
3972 reg = stv090x_read_reg(state, STV090x_TSTTNR3); stv090x_sleep()
3974 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) stv090x_sleep()
3977 reg = stv090x_read_reg(state, STV090x_TSTTNR4); stv090x_sleep()
3979 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) stv090x_sleep()
3984 reg = stv090x_read_reg(state, STV090x_TSTTNR1); stv090x_sleep()
3989 reg = stv090x_read_reg(state, STV090x_STOPCLK1); stv090x_sleep()
3998 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) stv090x_sleep()
4000 reg = stv090x_read_reg(state, STV090x_STOPCLK2); stv090x_sleep()
4009 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) stv090x_sleep()
4020 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); stv090x_sleep()
4022 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) stv090x_sleep()
4026 mutex_unlock(&state->internal->demod_lock); stv090x_sleep()
4030 stv090x_i2c_gate_ctrl(state, 0); stv090x_sleep()
4033 mutex_unlock(&state->internal->demod_lock); stv090x_sleep()
4041 struct stv090x_state *state = fe->demodulator_priv; stv090x_wakeup() local
4045 state->device == STV0900 ? "STV0900" : "STV0903", stv090x_wakeup()
4046 state->demod); stv090x_wakeup()
4048 mutex_lock(&state->internal->demod_lock); stv090x_wakeup()
4051 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); stv090x_wakeup()
4053 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) stv090x_wakeup()
4056 switch (state->demod) { stv090x_wakeup()
4059 reg = stv090x_read_reg(state, STV090x_TSTTNR1); stv090x_wakeup()
4061 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) stv090x_wakeup()
4064 reg = stv090x_read_reg(state, STV090x_TSTTNR2); stv090x_wakeup()
4066 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) stv090x_wakeup()
4070 reg = stv090x_read_reg(state, STV090x_STOPCLK1); stv090x_wakeup()
4077 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) stv090x_wakeup()
4079 reg = stv090x_read_reg(state, STV090x_STOPCLK2); stv090x_wakeup()
4086 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) stv090x_wakeup()
4092 reg = stv090x_read_reg(state, STV090x_TSTTNR3); stv090x_wakeup()
4094 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) stv090x_wakeup()
4097 reg = stv090x_read_reg(state, STV090x_TSTTNR4); stv090x_wakeup()
4099 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) stv090x_wakeup()
4103 reg = stv090x_read_reg(state, STV090x_STOPCLK1); stv090x_wakeup()
4110 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) stv090x_wakeup()
4112 reg = stv090x_read_reg(state, STV090x_STOPCLK2); stv090x_wakeup()
4119 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) stv090x_wakeup()
4128 mutex_unlock(&state->internal->demod_lock); stv090x_wakeup()
4131 mutex_unlock(&state->internal->demod_lock); stv090x_wakeup()
4138 struct stv090x_state *state = fe->demodulator_priv; stv090x_release() local
4140 state->internal->num_used--; stv090x_release()
4141 if (state->internal->num_used <= 0) { stv090x_release()
4145 remove_dev(state->internal); stv090x_release()
4146 kfree(state->internal); stv090x_release()
4149 kfree(state); stv090x_release()
4152 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) stv090x_ldpc_mode() argument
4156 reg = stv090x_read_reg(state, STV090x_GENCFG); stv090x_ldpc_mode()
4161 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { stv090x_ldpc_mode()
4163 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) stv090x_ldpc_mode()
4166 state->demod_mode = STV090x_DUAL; stv090x_ldpc_mode()
4168 reg = stv090x_read_reg(state, STV090x_TSTRES0); stv090x_ldpc_mode()
4170 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) stv090x_ldpc_mode()
4173 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) stv090x_ldpc_mode()
4176 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) stv090x_ldpc_mode()
4178 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) stv090x_ldpc_mode()
4180 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) stv090x_ldpc_mode()
4182 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) stv090x_ldpc_mode()
4184 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) stv090x_ldpc_mode()
4186 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) stv090x_ldpc_mode()
4188 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) stv090x_ldpc_mode()
4191 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) stv090x_ldpc_mode()
4193 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) stv090x_ldpc_mode()
4195 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) stv090x_ldpc_mode()
4197 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) stv090x_ldpc_mode()
4199 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) stv090x_ldpc_mode()
4201 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) stv090x_ldpc_mode()
4203 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) stv090x_ldpc_mode()
4206 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) stv090x_ldpc_mode()
4208 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) stv090x_ldpc_mode()
4214 if (stv090x_stop_modcod(state) < 0) stv090x_ldpc_mode()
4216 if (stv090x_activate_modcod_single(state) < 0) stv090x_ldpc_mode()
4219 if (state->demod == STV090x_DEMODULATOR_1) { stv090x_ldpc_mode()
4220 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ stv090x_ldpc_mode()
4223 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ stv090x_ldpc_mode()
4227 reg = stv090x_read_reg(state, STV090x_TSTRES0); stv090x_ldpc_mode()
4229 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) stv090x_ldpc_mode()
4232 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) stv090x_ldpc_mode()
4235 reg = STV090x_READ_DEMOD(state, PDELCTRL1); stv090x_ldpc_mode()
4237 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) stv090x_ldpc_mode()
4240 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) stv090x_ldpc_mode()
4252 static u32 stv090x_get_mclk(struct stv090x_state *state) stv090x_get_mclk() argument
4254 const struct stv090x_config *config = state->config; stv090x_get_mclk()
4258 div = stv090x_read_reg(state, STV090x_NCOARSE); stv090x_get_mclk()
4259 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); stv090x_get_mclk()
4265 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) stv090x_set_mclk() argument
4267 const struct stv090x_config *config = state->config; stv090x_set_mclk()
4270 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); stv090x_set_mclk()
4275 reg = stv090x_read_reg(state, STV090x_NCOARSE); stv090x_set_mclk()
4277 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) stv090x_set_mclk()
4280 state->internal->mclk = stv090x_get_mclk(state); stv090x_set_mclk()
4283 div = state->internal->mclk / 704000; stv090x_set_mclk()
4284 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) stv090x_set_mclk()
4286 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) stv090x_set_mclk()
4295 static int stv0900_set_tspath(struct stv090x_state *state) stv0900_set_tspath() argument
4299 if (state->internal->dev_ver >= 0x20) { stv0900_set_tspath()
4300 switch (state->config->ts1_mode) { stv0900_set_tspath()
4303 switch (state->config->ts2_mode) { stv0900_set_tspath()
4307 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); stv0900_set_tspath()
4312 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ stv0900_set_tspath()
4314 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); stv0900_set_tspath()
4316 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) stv0900_set_tspath()
4318 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); stv0900_set_tspath()
4320 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) stv0900_set_tspath()
4322 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) stv0900_set_tspath()
4324 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) stv0900_set_tspath()
4333 switch (state->config->ts2_mode) { stv0900_set_tspath()
4337 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) stv0900_set_tspath()
4343 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) stv0900_set_tspath()
4350 switch (state->config->ts1_mode) { stv0900_set_tspath()
4353 switch (state->config->ts2_mode) { stv0900_set_tspath()
4357 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); stv0900_set_tspath()
4362 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); stv0900_set_tspath()
4363 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); stv0900_set_tspath()
4365 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) stv0900_set_tspath()
4367 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); stv0900_set_tspath()
4369 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) stv0900_set_tspath()
4371 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) stv0900_set_tspath()
4373 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) stv0900_set_tspath()
4382 switch (state->config->ts2_mode) { stv0900_set_tspath()
4386 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); stv0900_set_tspath()
4391 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); stv0900_set_tspath()
4398 switch (state->config->ts1_mode) { stv0900_set_tspath()
4400 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0900_set_tspath()
4401 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); stv0900_set_tspath()
4404 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0900_set_tspath()
4409 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0900_set_tspath()
4410 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); stv0900_set_tspath()
4413 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0900_set_tspath()
4418 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0900_set_tspath()
4419 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); stv0900_set_tspath()
4422 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0900_set_tspath()
4427 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0900_set_tspath()
4428 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); stv0900_set_tspath()
4431 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0900_set_tspath()
4439 switch (state->config->ts2_mode) { stv0900_set_tspath()
4441 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); stv0900_set_tspath()
4442 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); stv0900_set_tspath()
4445 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) stv0900_set_tspath()
4450 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); stv0900_set_tspath()
4451 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); stv0900_set_tspath()
4454 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) stv0900_set_tspath()
4459 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); stv0900_set_tspath()
4460 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); stv0900_set_tspath()
4463 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) stv0900_set_tspath()
4468 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); stv0900_set_tspath()
4469 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); stv0900_set_tspath()
4472 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) stv0900_set_tspath()
4480 if (state->config->ts1_clk > 0) { stv0900_set_tspath()
4483 switch (state->config->ts1_mode) { stv0900_set_tspath()
4487 speed = state->internal->mclk / stv0900_set_tspath()
4488 (state->config->ts1_clk / 4); stv0900_set_tspath()
4496 speed = state->internal->mclk / stv0900_set_tspath()
4497 (state->config->ts1_clk / 32); stv0900_set_tspath()
4504 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); stv0900_set_tspath()
4506 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) stv0900_set_tspath()
4508 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) stv0900_set_tspath()
4512 if (state->config->ts2_clk > 0) { stv0900_set_tspath()
4515 switch (state->config->ts2_mode) { stv0900_set_tspath()
4519 speed = state->internal->mclk / stv0900_set_tspath()
4520 (state->config->ts2_clk / 4); stv0900_set_tspath()
4528 speed = state->internal->mclk / stv0900_set_tspath()
4529 (state->config->ts2_clk / 32); stv0900_set_tspath()
4536 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); stv0900_set_tspath()
4538 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) stv0900_set_tspath()
4540 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) stv0900_set_tspath()
4544 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); stv0900_set_tspath()
4546 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) stv0900_set_tspath()
4549 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) stv0900_set_tspath()
4552 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0900_set_tspath()
4554 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0900_set_tspath()
4557 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0900_set_tspath()
4566 static int stv0903_set_tspath(struct stv090x_state *state) stv0903_set_tspath() argument
4570 if (state->internal->dev_ver >= 0x20) { stv0903_set_tspath()
4571 switch (state->config->ts1_mode) { stv0903_set_tspath()
4574 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); stv0903_set_tspath()
4580 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c); stv0903_set_tspath()
4584 switch (state->config->ts1_mode) { stv0903_set_tspath()
4587 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); stv0903_set_tspath()
4593 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); stv0903_set_tspath()
4598 switch (state->config->ts1_mode) { stv0903_set_tspath()
4600 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0903_set_tspath()
4603 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0903_set_tspath()
4608 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0903_set_tspath()
4611 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0903_set_tspath()
4616 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0903_set_tspath()
4619 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0903_set_tspath()
4624 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0903_set_tspath()
4627 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0903_set_tspath()
4635 if (state->config->ts1_clk > 0) { stv0903_set_tspath()
4638 switch (state->config->ts1_mode) { stv0903_set_tspath()
4642 speed = state->internal->mclk / stv0903_set_tspath()
4643 (state->config->ts1_clk / 4); stv0903_set_tspath()
4651 speed = state->internal->mclk / stv0903_set_tspath()
4652 (state->config->ts1_clk / 32); stv0903_set_tspath()
4659 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); stv0903_set_tspath()
4661 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) stv0903_set_tspath()
4663 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) stv0903_set_tspath()
4667 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); stv0903_set_tspath()
4669 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0903_set_tspath()
4672 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) stv0903_set_tspath()
4683 struct stv090x_state *state = fe->demodulator_priv; stv090x_init() local
4684 const struct stv090x_config *config = state->config; stv090x_init()
4687 if (state->internal->mclk == 0) { stv090x_init()
4691 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_init()
4699 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_init()
4702 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ stv090x_init()
4704 if (stv090x_write_reg(state, STV090x_SYNTCTRL, stv090x_init()
4707 stv090x_get_mclk(state); stv090x_init()
4715 if (stv090x_ldpc_mode(state, state->demod_mode) < 0) stv090x_init()
4718 reg = STV090x_READ_DEMOD(state, TNRCFG2); stv090x_init()
4719 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); stv090x_init()
4720 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) stv090x_init()
4722 reg = STV090x_READ_DEMOD(state, DEMOD); stv090x_init()
4723 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); stv090x_init()
4724 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) stv090x_init()
4727 if (stv090x_i2c_gate_ctrl(state, 1) < 0) stv090x_init()
4740 if (stv090x_i2c_gate_ctrl(state, 0) < 0) stv090x_init()
4743 if (state->device == STV0900) { stv090x_init()
4744 if (stv0900_set_tspath(state) < 0) stv090x_init()
4747 if (stv0903_set_tspath(state) < 0) stv090x_init()
4754 stv090x_i2c_gate_ctrl(state, 0); stv090x_init()
4762 struct stv090x_state *state = fe->demodulator_priv; stv090x_setup() local
4763 const struct stv090x_config *config = state->config; stv090x_setup()
4771 if (state->device == STV0900) { stv090x_setup()
4777 } else if (state->device == STV0903) { stv090x_setup()
4788 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) stv090x_setup()
4790 if (state->device == STV0900) stv090x_setup()
4791 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) stv090x_setup()
4797 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) stv090x_setup()
4799 if (state->device == STV0900) stv090x_setup()
4800 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) stv090x_setup()
4805 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) stv090x_setup()
4807 if (state->device == STV0900) stv090x_setup()
4808 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) stv090x_setup()
4811 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ stv090x_setup()
4814 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ stv090x_setup()
4816 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ stv090x_setup()
4823 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) stv090x_setup()
4827 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); stv090x_setup()
4828 if (state->internal->dev_ver >= 0x20) { stv090x_setup()
4829 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) stv090x_setup()
4835 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) stv090x_setup()
4839 } else if (state->internal->dev_ver < 0x20) { stv090x_setup()
4841 state->internal->dev_ver); stv090x_setup()
4844 } else if (state->internal->dev_ver > 0x30) { stv090x_setup()
4847 state->internal->dev_ver); stv090x_setup()
4851 reg = stv090x_read_reg(state, STV090x_TSTTNR1); stv090x_setup()
4854 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) stv090x_setup()
4858 reg = stv090x_read_reg(state, STV090x_TSTTNR3); stv090x_setup()
4861 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) stv090x_setup()
4864 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) stv090x_setup()
4866 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) stv090x_setup()
4878 struct stv090x_state *state = fe->demodulator_priv; stv090x_set_gpio() local
4885 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); stv090x_set_gpio()
4927 struct stv090x_state *state = NULL; stv090x_attach() local
4930 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL); stv090x_attach()
4931 if (state == NULL) stv090x_attach()
4934 state->verbose = &verbose; stv090x_attach()
4935 state->config = config; stv090x_attach()
4936 state->i2c = i2c; stv090x_attach()
4937 state->frontend.ops = stv090x_ops; stv090x_attach()
4938 state->frontend.demodulator_priv = state; stv090x_attach()
4939 state->demod = demod; stv090x_attach()
4940 state->demod_mode = config->demod_mode; /* Single or Dual mode */ stv090x_attach()
4941 state->device = config->device; stv090x_attach()
4942 state->rolloff = STV090x_RO_35; /* default */ stv090x_attach()
4944 temp_int = find_dev(state->i2c, stv090x_attach()
4945 state->config->address); stv090x_attach()
4947 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) { stv090x_attach()
4948 state->internal = temp_int->internal; stv090x_attach()
4949 state->internal->num_used++; stv090x_attach()
4952 state->internal = kmalloc(sizeof(struct stv090x_internal), stv090x_attach()
4954 if (!state->internal) stv090x_attach()
4956 temp_int = append_internal(state->internal); stv090x_attach()
4958 kfree(state->internal); stv090x_attach()
4961 state->internal->num_used = 1; stv090x_attach()
4962 state->internal->mclk = 0; stv090x_attach()
4963 state->internal->dev_ver = 0; stv090x_attach()
4964 state->internal->i2c_adap = state->i2c; stv090x_attach()
4965 state->internal->i2c_addr = state->config->address; stv090x_attach()
4968 mutex_init(&state->internal->demod_lock); stv090x_attach()
4969 mutex_init(&state->internal->tuner_lock); stv090x_attach()
4971 if (stv090x_setup(&state->frontend) < 0) { stv090x_attach()
4977 if (state->internal->dev_ver >= 0x30) stv090x_attach()
4978 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM; stv090x_attach()
4982 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); stv090x_attach()
4987 state->device == STV0900 ? "STV0900" : "STV0903", stv090x_attach()
4989 state->internal->dev_ver); stv090x_attach()
4991 return &state->frontend; stv090x_attach()
4994 remove_dev(state->internal); stv090x_attach()
4995 kfree(state->internal); stv090x_attach()
4997 kfree(state); stv090x_attach()
H A Ddib9000.c203 static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
204 static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
228 static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute) dib9000_read16_attr() argument
234 if (state->platform.risc.fw_is_running && (reg < 1024)) dib9000_read16_attr()
235 return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len); dib9000_read16_attr()
237 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); dib9000_read16_attr()
238 state->msg[0].addr = state->i2c.i2c_addr >> 1; dib9000_read16_attr()
239 state->msg[0].flags = 0; dib9000_read16_attr()
240 state->msg[0].buf = state->i2c_write_buffer; dib9000_read16_attr()
241 state->msg[0].len = 2; dib9000_read16_attr()
242 state->msg[1].addr = state->i2c.i2c_addr >> 1; dib9000_read16_attr()
243 state->msg[1].flags = I2C_M_RD; dib9000_read16_attr()
244 state->msg[1].buf = b; dib9000_read16_attr()
245 state->msg[1].len = len; dib9000_read16_attr()
247 state->i2c_write_buffer[0] = reg >> 8; dib9000_read16_attr()
248 state->i2c_write_buffer[1] = reg & 0xff; dib9000_read16_attr()
251 state->i2c_write_buffer[0] |= (1 << 5); dib9000_read16_attr()
253 state->i2c_write_buffer[0] |= (1 << 4); dib9000_read16_attr()
257 state->msg[1].len = l; dib9000_read16_attr()
258 state->msg[1].buf = b; dib9000_read16_attr()
259 ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 2) != 2 ? -EREMOTEIO : 0; dib9000_read16_attr()
295 static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg) dib9000_read_word() argument
297 if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0) dib9000_read_word()
299 return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; dib9000_read_word()
302 static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute) dib9000_read_word_attr() argument
304 if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, dib9000_read_word_attr()
307 return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; dib9000_read_word_attr()
310 #define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
312 static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute) dib9000_write16_attr() argument
318 if (state->platform.risc.fw_is_running && (reg < 1024)) { dib9000_write16_attr()
320 (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0) dib9000_write16_attr()
325 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); dib9000_write16_attr()
326 state->msg[0].addr = state->i2c.i2c_addr >> 1; dib9000_write16_attr()
327 state->msg[0].flags = 0; dib9000_write16_attr()
328 state->msg[0].buf = state->i2c_write_buffer; dib9000_write16_attr()
329 state->msg[0].len = len + 2; dib9000_write16_attr()
331 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; dib9000_write16_attr()
332 state->i2c_write_buffer[1] = (reg) & 0xff; dib9000_write16_attr()
335 state->i2c_write_buffer[0] |= (1 << 5); dib9000_write16_attr()
337 state->i2c_write_buffer[0] |= (1 << 4); dib9000_write16_attr()
341 state->msg[0].len = l + 2; dib9000_write16_attr()
342 memcpy(&state->i2c_write_buffer[2], buf, l); dib9000_write16_attr()
344 ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0; dib9000_write16_attr()
371 static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val) dib9000_write_word() argument
374 return dib9000_write16_attr(state, reg, b, 2, 0); dib9000_write_word()
377 static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute) dib9000_write_word_attr() argument
380 return dib9000_write16_attr(state, reg, b, 2, attribute); dib9000_write_word_attr()
383 #define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
384 #define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
385 #define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
387 #define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
388 #define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
393 #define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
394 #define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
396 static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading) dib9000_risc_mem_setup_cmd() argument
400 /* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */ dib9000_risc_mem_setup_cmd()
420 dib9000_write(state, 1056, b, 14); dib9000_risc_mem_setup_cmd()
422 dib9000_write_word(state, 1056, (1 << 15) | 1); dib9000_risc_mem_setup_cmd()
423 state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */ dib9000_risc_mem_setup_cmd()
426 static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd) dib9000_risc_mem_setup() argument
428 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f]; dib9000_risc_mem_setup()
430 if (state->platform.risc.memcmd == cmd && /* same command */ dib9000_risc_mem_setup()
433 dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80); dib9000_risc_mem_setup()
434 state->platform.risc.memcmd = cmd; dib9000_risc_mem_setup()
437 static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len) dib9000_risc_mem_read() argument
439 if (!state->platform.risc.fw_is_running) dib9000_risc_mem_read()
442 if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) { dib9000_risc_mem_read()
446 dib9000_risc_mem_setup(state, cmd | 0x80); dib9000_risc_mem_read()
447 dib9000_risc_mem_read_chunks(state, b, len); dib9000_risc_mem_read()
448 mutex_unlock(&state->platform.risc.mem_lock); dib9000_risc_mem_read()
452 static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b) dib9000_risc_mem_write() argument
454 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd]; dib9000_risc_mem_write()
455 if (!state->platform.risc.fw_is_running) dib9000_risc_mem_write()
458 if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) { dib9000_risc_mem_write()
462 dib9000_risc_mem_setup(state, cmd); dib9000_risc_mem_write()
463 dib9000_risc_mem_write_chunks(state, b, m->size); dib9000_risc_mem_write()
464 mutex_unlock(&state->platform.risc.mem_lock); dib9000_risc_mem_write()
468 static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len) dib9000_firmware_download() argument
478 dib9000_write_word(state, 1024 + offs, 0x000f); dib9000_firmware_download()
479 dib9000_write_word(state, 1025 + offs, 0); dib9000_firmware_download()
480 dib9000_write_word(state, 1031 + offs, key); dib9000_firmware_download()
483 if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) { dib9000_firmware_download()
493 static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id) dib9000_mbx_host_init() argument
505 dib9000_write_word(state, 1027 + mbox_offs, 0x8000); dib9000_mbx_host_init()
509 reset_reg = dib9000_read_word(state, 1027 + mbox_offs); dib9000_mbx_host_init()
522 static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr) dib9000_mbx_send_attr() argument
530 if (!state->platform.risc.fw_is_running) dib9000_mbx_send_attr()
533 if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) { dib9000_mbx_send_attr()
539 size = dib9000_read_word_attr(state, 1043, attr) & 0xff; dib9000_mbx_send_attr()
571 if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) { dib9000_mbx_send_attr()
577 ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr); dib9000_mbx_send_attr()
580 mutex_unlock(&state->platform.risc.mbx_if_lock); dib9000_mbx_send_attr()
585 static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr) dib9000_mbx_read() argument
595 if (!state->platform.risc.fw_is_running) dib9000_mbx_read()
598 if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) { dib9000_mbx_read()
608 *data = dib9000_read_word_attr(state, 1029 + mc_base, attr); dib9000_mbx_read()
615 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr); dib9000_mbx_read()
634 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr); dib9000_mbx_read()
637 dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr); dib9000_mbx_read()
639 mutex_unlock(&state->platform.risc.mbx_if_lock); dib9000_mbx_read()
644 static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size) dib9000_risc_debug_buf() argument
654 dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<empty>"); dib9000_risc_debug_buf()
658 static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr) dib9000_mbx_fetch_to_cache() argument
665 block = state->platform.risc.message_cache[i]; dib9000_mbx_fetch_to_cache()
667 size = dib9000_mbx_read(state, block, 1, attr); dib9000_mbx_fetch_to_cache()
673 dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */ dib9000_mbx_fetch_to_cache()
678 dib9000_risc_data_process(state, block + 1, size); dib9000_mbx_fetch_to_cache()
693 static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr) dib9000_mbx_count() argument
696 return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */ dib9000_mbx_count()
698 return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */ dib9000_mbx_count()
701 static int dib9000_mbx_process(struct dib9000_state *state, u16 attr) dib9000_mbx_process() argument
705 if (!state->platform.risc.fw_is_running) dib9000_mbx_process()
708 if (mutex_lock_interruptible(&state->platform.risc.mbx_lock) < 0) { dib9000_mbx_process()
713 if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */ dib9000_mbx_process()
714 ret = dib9000_mbx_fetch_to_cache(state, attr); dib9000_mbx_process()
716 dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */ dib9000_mbx_process()
719 mutex_unlock(&state->platform.risc.mbx_lock); dib9000_mbx_process()
724 static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr) dib9000_mbx_get_message_attr() argument
734 block = state->platform.risc.message_cache[i]; dib9000_mbx_get_message_attr()
747 if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */ dib9000_mbx_get_message_attr()
760 static int dib9000_risc_check_version(struct dib9000_state *state) dib9000_risc_check_version() argument
766 if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0) dib9000_risc_check_version()
769 if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0) dib9000_risc_check_version()
795 static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB) dib9000_fw_boot() argument
798 dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */ dib9000_fw_boot()
799 dib9000_write_word(state, 1226, 0x05); dib9000_fw_boot()
802 dib9000_write_word(state, 1542, 1); dib9000_fw_boot()
805 dib9000_write_word(state, 1074, 0); dib9000_fw_boot()
806 dib9000_write_word(state, 1075, 0); dib9000_fw_boot()
809 dib9000_write_word(state, 1237, 0); dib9000_fw_boot()
813 dib9000_write_word(state, 1024, 2); dib9000_fw_boot()
815 dib9000_write_word(state, 1024, 15); dib9000_fw_boot()
817 dib9000_write_word(state, 1040, 2); dib9000_fw_boot()
820 dib9000_firmware_download(state, 0, 0x1234, codeA, lenA); dib9000_fw_boot()
822 dib9000_firmware_download(state, 1, 0x1234, codeB, lenB); dib9000_fw_boot()
826 dib9000_write_word(state, 1024, 0); dib9000_fw_boot()
828 dib9000_write_word(state, 1040, 0); dib9000_fw_boot()
831 if (dib9000_mbx_host_init(state, 0) != 0) dib9000_fw_boot()
834 if (dib9000_mbx_host_init(state, 1) != 0) dib9000_fw_boot()
838 state->platform.risc.fw_is_running = 1; dib9000_fw_boot()
840 if (dib9000_risc_check_version(state) != 0) dib9000_fw_boot()
843 state->platform.risc.memcmd = 0xff; dib9000_fw_boot()
893 static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode) dib9000_set_power_mode() argument
899 if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005) dib9000_set_power_mode()
904 reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */ dib9000_set_power_mode()
946 if (!state->platform.host.mobile_mode) dib9000_set_power_mode()
950 if (state->revision != 0x4000) dib9000_set_power_mode()
953 dib9000_write_word(state, 903 + offset, reg_903); dib9000_set_power_mode()
954 dib9000_write_word(state, 904 + offset, reg_904); dib9000_set_power_mode()
955 dib9000_write_word(state, 905 + offset, reg_905); dib9000_set_power_mode()
956 dib9000_write_word(state, 906 + offset, reg_906); dib9000_set_power_mode()
961 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_reset() local
963 dib9000_write_word(state, 1817, 0x0003); dib9000_fw_reset()
965 dib9000_write_word(state, 1227, 1); dib9000_fw_reset()
966 dib9000_write_word(state, 1227, 0); dib9000_fw_reset()
968 switch ((state->revision = dib9000_identify(&state->i2c))) { dib9000_fw_reset()
972 state->reg_offs = 1; dib9000_fw_reset()
979 dibx000_reset_i2c_master(&state->i2c_master); dib9000_fw_reset()
981 dib9000_set_power_mode(state, DIB9000_POWER_ALL); dib9000_fw_reset()
984 dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1)); dib9000_fw_reset()
985 dib9000_write_word(state, 1796, 0); dib9000_fw_reset()
986 dib9000_write_word(state, 1805, 0x805); dib9000_fw_reset()
989 dib9000_write_word(state, 898, 0xffff); dib9000_fw_reset()
990 dib9000_write_word(state, 899, 0xffff); dib9000_fw_reset()
991 dib9000_write_word(state, 900, 0x0001); dib9000_fw_reset()
992 dib9000_write_word(state, 901, 0xff19); dib9000_fw_reset()
993 dib9000_write_word(state, 902, 0x003c); dib9000_fw_reset()
995 dib9000_write_word(state, 898, 0); dib9000_fw_reset()
996 dib9000_write_word(state, 899, 0); dib9000_fw_reset()
997 dib9000_write_word(state, 900, 0); dib9000_fw_reset()
998 dib9000_write_word(state, 901, 0); dib9000_fw_reset()
999 dib9000_write_word(state, 902, 0); dib9000_fw_reset()
1001 dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives); dib9000_fw_reset()
1003 dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY); dib9000_fw_reset()
1008 static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len) dib9000_risc_apb_access_read() argument
1013 if (address >= 1024 || !state->platform.risc.fw_is_running) dib9000_risc_apb_access_read()
1020 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute); dib9000_risc_apb_access_read()
1021 switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) { dib9000_risc_apb_access_read()
1035 static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len) dib9000_risc_apb_access_write() argument
1040 if (address >= 1024 || !state->platform.risc.fw_is_running) dib9000_risc_apb_access_write()
1054 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, (3 + len) / 2, attribute); dib9000_risc_apb_access_write()
1055 return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL; dib9000_risc_apb_access_write()
1058 static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i) dib9000_fw_memmbx_sync() argument
1062 if (!state->platform.risc.fw_is_running) dib9000_fw_memmbx_sync()
1064 dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i); dib9000_fw_memmbx_sync()
1066 dib9000_risc_mem_read(state, FE_MM_RW_SYNC, state->i2c_read_buffer, 1); dib9000_fw_memmbx_sync()
1067 } while (state->i2c_read_buffer[0] && index_loop--); dib9000_fw_memmbx_sync()
1074 static int dib9000_fw_init(struct dib9000_state *state) dib9000_fw_init() argument
1081 if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0) dib9000_fw_init()
1085 for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) { dib9000_fw_init()
1086 f = &state->chip.d9.cfg.gpio_function[i]; dib9000_fw_init()
1102 if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0) dib9000_fw_init()
1106 b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */ dib9000_fw_init()
1107 for (i = 0; i < state->chip.d9.cfg.subband.size; i++) { dib9000_fw_init()
1108 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz; dib9000_fw_init()
1109 b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask; dib9000_fw_init()
1110 b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction; dib9000_fw_init()
1111 b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value; dib9000_fw_init()
1114 if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0) dib9000_fw_init()
1121 b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff); dib9000_fw_init()
1122 b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff); dib9000_fw_init()
1123 b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff); dib9000_fw_init()
1124 b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff); dib9000_fw_init()
1125 b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff); dib9000_fw_init()
1126 b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff); dib9000_fw_init()
1127 b[29] = state->chip.d9.cfg.if_drives; dib9000_fw_init()
1128 if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0) dib9000_fw_init()
1131 if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0) dib9000_fw_init()
1134 if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0) dib9000_fw_init()
1144 state->platform.risc.fe_mm[i / 2].addr = b[i + 0]; dib9000_fw_init()
1145 state->platform.risc.fe_mm[i / 2].size = b[i + 1]; dib9000_fw_init()
1151 static void dib9000_fw_set_channel_head(struct dib9000_state *state) dib9000_fw_set_channel_head() argument
1154 u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000; dib9000_fw_set_channel_head()
1155 if (state->fe_id % 2) dib9000_fw_set_channel_head()
1162 b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff); dib9000_fw_set_channel_head()
1163 b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff); dib9000_fw_set_channel_head()
1164 b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff); dib9000_fw_set_channel_head()
1165 b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff); dib9000_fw_set_channel_head()
1167 if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT) dib9000_fw_set_channel_head()
1169 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b); dib9000_fw_set_channel_head()
1174 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_get_channel() local
1193 if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) { dib9000_fw_get_channel()
1197 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) { dib9000_fw_get_channel()
1202 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, dib9000_fw_get_channel()
1203 state->i2c_read_buffer, sizeof(struct dibDVBTChannel)); dib9000_fw_get_channel()
1204 ch = (struct dibDVBTChannel *)state->i2c_read_buffer; dib9000_fw_get_channel()
1209 state->fe[0]->dtv_property_cache.inversion = INVERSION_ON; dib9000_fw_get_channel()
1212 state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF; dib9000_fw_get_channel()
1216 state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO; dib9000_fw_get_channel()
1221 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K; dib9000_fw_get_channel()
1224 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K; dib9000_fw_get_channel()
1227 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; dib9000_fw_get_channel()
1231 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO; dib9000_fw_get_channel()
1236 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32; dib9000_fw_get_channel()
1239 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16; dib9000_fw_get_channel()
1242 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; dib9000_fw_get_channel()
1245 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4; dib9000_fw_get_channel()
1249 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO; dib9000_fw_get_channel()
1254 state->fe[0]->dtv_property_cache.modulation = QAM_64; dib9000_fw_get_channel()
1257 state->fe[0]->dtv_property_cache.modulation = QAM_16; dib9000_fw_get_channel()
1260 state->fe[0]->dtv_property_cache.modulation = QPSK; dib9000_fw_get_channel()
1264 state->fe[0]->dtv_property_cache.modulation = QAM_AUTO; dib9000_fw_get_channel()
1269 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE; dib9000_fw_get_channel()
1272 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1; dib9000_fw_get_channel()
1276 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO; dib9000_fw_get_channel()
1281 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2; dib9000_fw_get_channel()
1284 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3; dib9000_fw_get_channel()
1287 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4; dib9000_fw_get_channel()
1290 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6; dib9000_fw_get_channel()
1293 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8; dib9000_fw_get_channel()
1297 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO; dib9000_fw_get_channel()
1302 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2; dib9000_fw_get_channel()
1305 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3; dib9000_fw_get_channel()
1308 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4; dib9000_fw_get_channel()
1311 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6; dib9000_fw_get_channel()
1314 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8; dib9000_fw_get_channel()
1318 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO; dib9000_fw_get_channel()
1323 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_fw_get_channel()
1329 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_set_channel_union() local
1347 switch (state->fe[0]->dtv_property_cache.inversion) { dib9000_fw_set_channel_union()
1359 switch (state->fe[0]->dtv_property_cache.transmission_mode) { dib9000_fw_set_channel_union()
1374 switch (state->fe[0]->dtv_property_cache.guard_interval) { dib9000_fw_set_channel_union()
1392 switch (state->fe[0]->dtv_property_cache.modulation) { dib9000_fw_set_channel_union()
1407 switch (state->fe[0]->dtv_property_cache.hierarchy) { dib9000_fw_set_channel_union()
1422 switch (state->fe[0]->dtv_property_cache.code_rate_HP) { dib9000_fw_set_channel_union()
1443 switch (state->fe[0]->dtv_property_cache.code_rate_LP) { dib9000_fw_set_channel_union()
1467 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch); dib9000_fw_set_channel_union()
1474 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_tune() local
1475 int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN; dib9000_fw_tune()
1478 switch (state->tune_state) { dib9000_fw_tune()
1480 dib9000_fw_set_channel_head(state); dib9000_fw_tune()
1483 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info); dib9000_fw_tune()
1484 dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info); dib9000_fw_tune()
1487 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0); dib9000_fw_tune()
1490 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0); dib9000_fw_tune()
1492 state->tune_state = CT_DEMOD_STEP_1; dib9000_fw_tune()
1496 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, state->i2c_read_buffer, 1); dib9000_fw_tune()
1498 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, state->i2c_read_buffer, 1); dib9000_fw_tune()
1499 i = (s8)state->i2c_read_buffer[0]; dib9000_fw_tune()
1505 state->status = FE_STATUS_DEMOD_SUCCESS; dib9000_fw_tune()
1507 state->tune_state = CT_DEMOD_STOP; dib9000_fw_tune()
1508 state->status = FE_STATUS_LOCKED; dib9000_fw_tune()
1512 state->status = FE_STATUS_TUNE_FAILED; dib9000_fw_tune()
1513 state->tune_state = CT_DEMOD_STOP; dib9000_fw_tune()
1527 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_set_diversity_in() local
1529 return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1); dib9000_fw_set_diversity_in()
1534 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_set_output_mode() local
1559 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]); dib9000_fw_set_output_mode()
1563 dib9000_write_word(state, 1795, outreg); dib9000_fw_set_output_mode()
1570 smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1); dib9000_fw_set_output_mode()
1571 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes) dib9000_fw_set_output_mode()
1573 dib9000_write_word(state, 295, smo_mode); dib9000_fw_set_output_mode()
1578 return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1); dib9000_fw_set_output_mode()
1583 struct dib9000_state *state = i2c_get_adapdata(i2c_adap); dib9000_tuner_xfer() local
1592 if (dib9000_read_word(state, 790) != 0) dib9000_tuner_xfer()
1595 dib9000_write_word(state, 784, (u16) (msg[index_msg].addr)); dib9000_tuner_xfer()
1596 dib9000_write_word(state, 787, (len / 2) - 1); dib9000_tuner_xfer()
1597 dib9000_write_word(state, 786, 1); /* start read */ dib9000_tuner_xfer()
1600 while (dib9000_read_word(state, 790) != (len / 2) && i) dib9000_tuner_xfer()
1607 t = dib9000_read_word(state, 785); dib9000_tuner_xfer()
1611 if (dib9000_read_word(state, 790) != 0) dib9000_tuner_xfer()
1615 while (dib9000_read_word(state, 789) && i) dib9000_tuner_xfer()
1625 dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]); dib9000_tuner_xfer()
1626 dib9000_write_word(state, 784, (u16) msg[index_msg].addr); dib9000_tuner_xfer()
1627 dib9000_write_word(state, 787, (len / 2) - 1); dib9000_tuner_xfer()
1628 dib9000_write_word(state, 786, 0); /* start write */ dib9000_tuner_xfer()
1631 while (dib9000_read_word(state, 791) > 0 && i) dib9000_tuner_xfer()
1642 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_set_component_bus_speed() local
1644 state->component_bus_speed = speed; dib9000_fw_set_component_bus_speed()
1651 struct dib9000_state *state = i2c_get_adapdata(i2c_adap); dib9000_fw_component_bus_xfer() local
1654 u16 scl = state->component_bus_speed; /* SCL frequency */ dib9000_fw_component_bus_xfer()
1655 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER]; dib9000_fw_component_bus_xfer()
1678 if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) { dib9000_fw_component_bus_xfer()
1683 dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p); dib9000_fw_component_bus_xfer()
1686 dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0); dib9000_fw_component_bus_xfer()
1687 dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len); dib9000_fw_component_bus_xfer()
1691 if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) { dib9000_fw_component_bus_xfer()
1692 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_fw_component_bus_xfer()
1698 dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len); dib9000_fw_component_bus_xfer()
1700 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_fw_component_bus_xfer()
1769 struct dib9000_state *state = fe->demodulator_priv; dib9000_set_gpio() local
1770 return dib9000_cfg_gpio(state, num, dir, val); dib9000_set_gpio()
1776 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_pid_filter_ctrl() local
1780 if ((state->pid_ctrl_index != -2) && (state->pid_ctrl_index < 9)) { dib9000_fw_pid_filter_ctrl()
1783 state->pid_ctrl_index++; dib9000_fw_pid_filter_ctrl()
1784 state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER_CTRL; dib9000_fw_pid_filter_ctrl()
1785 state->pid_ctrl[state->pid_ctrl_index].onoff = onoff; dib9000_fw_pid_filter_ctrl()
1789 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_fw_pid_filter_ctrl()
1794 val = dib9000_read_word(state, 294 + 1) & 0xffef; dib9000_fw_pid_filter_ctrl()
1798 ret = dib9000_write_word(state, 294 + 1, val); dib9000_fw_pid_filter_ctrl()
1799 mutex_unlock(&state->demod_lock); dib9000_fw_pid_filter_ctrl()
1807 struct dib9000_state *state = fe->demodulator_priv; dib9000_fw_pid_filter() local
1810 if (state->pid_ctrl_index != -2) { dib9000_fw_pid_filter()
1813 if (state->pid_ctrl_index < 9) { dib9000_fw_pid_filter()
1814 state->pid_ctrl_index++; dib9000_fw_pid_filter()
1815 state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER; dib9000_fw_pid_filter()
1816 state->pid_ctrl[state->pid_ctrl_index].id = id; dib9000_fw_pid_filter()
1817 state->pid_ctrl[state->pid_ctrl_index].pid = pid; dib9000_fw_pid_filter()
1818 state->pid_ctrl[state->pid_ctrl_index].onoff = onoff; dib9000_fw_pid_filter()
1824 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_fw_pid_filter()
1829 ret = dib9000_write_word(state, 300 + 1 + id, dib9000_fw_pid_filter()
1831 mutex_unlock(&state->demod_lock); dib9000_fw_pid_filter()
1838 struct dib9000_state *state = fe->demodulator_priv; dib9000_firmware_post_pll_init() local
1839 return dib9000_fw_init(state); dib9000_firmware_post_pll_init()
1866 struct dib9000_state *state = fe->demodulator_priv; dib9000_sleep() local
1870 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_sleep()
1874 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_sleep()
1875 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); dib9000_sleep()
1879 ret = dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0); dib9000_sleep()
1882 mutex_unlock(&state->demod_lock); dib9000_sleep()
1894 struct dib9000_state *state = fe->demodulator_priv; dib9000_get_frontend() local
1899 if (state->get_frontend_internal == 0) { dib9000_get_frontend()
1900 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_get_frontend()
1906 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_get_frontend()
1907 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); dib9000_get_frontend()
1912 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]); dib9000_get_frontend()
1913 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); dib9000_get_frontend()
1916 state->fe[sub_index_frontend]->dtv_property_cache.modulation = dib9000_get_frontend()
1917 state->fe[index_frontend]->dtv_property_cache.modulation; dib9000_get_frontend()
1918 state->fe[sub_index_frontend]->dtv_property_cache.inversion = dib9000_get_frontend()
1919 state->fe[index_frontend]->dtv_property_cache.inversion; dib9000_get_frontend()
1920 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = dib9000_get_frontend()
1921 state->fe[index_frontend]->dtv_property_cache.transmission_mode; dib9000_get_frontend()
1922 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = dib9000_get_frontend()
1923 state->fe[index_frontend]->dtv_property_cache.guard_interval; dib9000_get_frontend()
1924 state->fe[sub_index_frontend]->dtv_property_cache.hierarchy = dib9000_get_frontend()
1925 state->fe[index_frontend]->dtv_property_cache.hierarchy; dib9000_get_frontend()
1926 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP = dib9000_get_frontend()
1927 state->fe[index_frontend]->dtv_property_cache.code_rate_HP; dib9000_get_frontend()
1928 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP = dib9000_get_frontend()
1929 state->fe[index_frontend]->dtv_property_cache.code_rate_LP; dib9000_get_frontend()
1930 state->fe[sub_index_frontend]->dtv_property_cache.rolloff = dib9000_get_frontend()
1931 state->fe[index_frontend]->dtv_property_cache.rolloff; dib9000_get_frontend()
1945 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_get_frontend()
1946 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion; dib9000_get_frontend()
1947 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode; dib9000_get_frontend()
1948 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval; dib9000_get_frontend()
1949 state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation; dib9000_get_frontend()
1950 state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy; dib9000_get_frontend()
1951 state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP; dib9000_get_frontend()
1952 state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP; dib9000_get_frontend()
1953 state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff; dib9000_get_frontend()
1958 if (state->get_frontend_internal == 0) dib9000_get_frontend()
1959 mutex_unlock(&state->demod_lock); dib9000_get_frontend()
1965 struct dib9000_state *state = fe->demodulator_priv; dib9000_set_tune_state() local
1966 state->tune_state = tune_state; dib9000_set_tune_state()
1968 state->status = FE_STATUS_TUNE_PENDING; dib9000_set_tune_state()
1975 struct dib9000_state *state = fe->demodulator_priv; dib9000_get_status() local
1976 return state->status; dib9000_get_status()
1981 struct dib9000_state *state = fe->demodulator_priv; dib9000_set_channel_status() local
1983 memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext)); dib9000_set_channel_status()
1989 struct dib9000_state *state = fe->demodulator_priv; dib9000_set_frontend() local
1996 if (state->fe[0]->dtv_property_cache.frequency == 0) { dib9000_set_frontend()
2001 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) { dib9000_set_frontend()
2006 state->pid_ctrl_index = -1; /* postpone the pid filtering cmd */ dib9000_set_frontend()
2007 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_set_frontend()
2015 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO || dib9000_set_frontend()
2016 state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO || dib9000_set_frontend()
2017 state->fe[0]->dtv_property_cache.modulation == QAM_AUTO || dib9000_set_frontend()
2018 state->fe[0]->dtv_property_cache.code_rate_HP == FEC_AUTO) { dib9000_set_frontend()
2020 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN; dib9000_set_frontend()
2022 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET; dib9000_set_frontend()
2025 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_set_frontend()
2026 dib9000_fw_set_diversity_in(state->fe[index_frontend], 1); dib9000_set_frontend()
2029 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties)); dib9000_set_frontend()
2031 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT; dib9000_set_frontend()
2032 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z); dib9000_set_frontend()
2034 dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status); dib9000_set_frontend()
2035 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); dib9000_set_frontend()
2042 sleep_time = dib9000_fw_tune(state->fe[0]); dib9000_set_frontend()
2043 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_set_frontend()
2044 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]); dib9000_set_frontend()
2058 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_set_frontend()
2059 frontend_status = -dib9000_get_status(state->fe[index_frontend]); dib9000_set_frontend()
2076 mutex_unlock(&state->demod_lock); dib9000_set_frontend()
2078 state->pid_ctrl_index = -1; dib9000_set_frontend()
2085 state->get_frontend_internal = 1; dib9000_set_frontend()
2086 dib9000_get_frontend(state->fe[0]); dib9000_set_frontend()
2087 state->get_frontend_internal = 0; dib9000_set_frontend()
2091 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_set_frontend()
2094 dib9000_set_channel_status(state->fe[index_frontend], &channel_status); dib9000_set_frontend()
2095 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); dib9000_set_frontend()
2100 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_set_frontend()
2102 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]); dib9000_set_frontend()
2115 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_set_frontend()
2117 frontend_status = -dib9000_get_status(state->fe[index_frontend]); dib9000_set_frontend()
2125 dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode); dib9000_set_frontend()
2126 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) dib9000_set_frontend()
2127 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY); dib9000_set_frontend()
2130 dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0); dib9000_set_frontend()
2132 mutex_unlock(&state->demod_lock); dib9000_set_frontend()
2133 if (state->pid_ctrl_index >= 0) { dib9000_set_frontend()
2135 u8 pid_ctrl_index = state->pid_ctrl_index; dib9000_set_frontend()
2137 state->pid_ctrl_index = -2; dib9000_set_frontend()
2141 if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER_CTRL) dib9000_set_frontend()
2142 dib9000_fw_pid_filter_ctrl(state->fe[0], dib9000_set_frontend()
2143 state->pid_ctrl[index_pid_filter_cmd].onoff); dib9000_set_frontend()
2144 else if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER) dib9000_set_frontend()
2145 dib9000_fw_pid_filter(state->fe[0], dib9000_set_frontend()
2146 state->pid_ctrl[index_pid_filter_cmd].id, dib9000_set_frontend()
2147 state->pid_ctrl[index_pid_filter_cmd].pid, dib9000_set_frontend()
2148 state->pid_ctrl[index_pid_filter_cmd].onoff); dib9000_set_frontend()
2152 state->pid_ctrl_index = -2; dib9000_set_frontend()
2159 struct dib9000_state *state = fe->demodulator_priv; dib9000_read_lock() local
2161 return dib9000_read_word(state, 535); dib9000_read_lock()
2166 struct dib9000_state *state = fe->demodulator_priv; dib9000_read_status() local
2170 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_read_status()
2174 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) dib9000_read_status()
2175 lock_slave |= dib9000_read_lock(state->fe[index_frontend]); dib9000_read_status()
2177 lock = dib9000_read_word(state, 535); dib9000_read_status()
2192 mutex_unlock(&state->demod_lock); dib9000_read_status()
2199 struct dib9000_state *state = fe->demodulator_priv; dib9000_read_ber() local
2203 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_read_ber()
2207 if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) { dib9000_read_ber()
2212 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) { dib9000_read_ber()
2213 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_read_ber()
2217 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, dib9000_read_ber()
2218 state->i2c_read_buffer, 16 * 2); dib9000_read_ber()
2219 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_read_ber()
2221 c = (u16 *)state->i2c_read_buffer; dib9000_read_ber()
2226 mutex_unlock(&state->demod_lock); dib9000_read_ber()
2232 struct dib9000_state *state = fe->demodulator_priv; dib9000_read_signal_strength() local
2234 u16 *c = (u16 *)state->i2c_read_buffer; dib9000_read_signal_strength()
2238 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_read_signal_strength()
2243 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib9000_read_signal_strength()
2244 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); dib9000_read_signal_strength()
2251 if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) { dib9000_read_signal_strength()
2256 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) { dib9000_read_signal_strength()
2257 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_read_signal_strength()
2261 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2); dib9000_read_signal_strength()
2262 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_read_signal_strength()
2271 mutex_unlock(&state->demod_lock); dib9000_read_signal_strength()
2277 struct dib9000_state *state = fe->demodulator_priv; dib9000_get_snr() local
2278 u16 *c = (u16 *)state->i2c_read_buffer; dib9000_get_snr()
2282 if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) { dib9000_get_snr()
2286 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) { dib9000_get_snr()
2287 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_get_snr()
2290 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2); dib9000_get_snr()
2291 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_get_snr()
2317 struct dib9000_state *state = fe->demodulator_priv; dib9000_read_snr() local
2321 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_read_snr()
2326 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) dib9000_read_snr()
2327 snr_master += dib9000_get_snr(state->fe[index_frontend]); dib9000_read_snr()
2335 mutex_unlock(&state->demod_lock); dib9000_read_snr()
2342 struct dib9000_state *state = fe->demodulator_priv; dib9000_read_unc_blocks() local
2343 u16 *c = (u16 *)state->i2c_read_buffer; dib9000_read_unc_blocks()
2346 if (mutex_lock_interruptible(&state->demod_lock) < 0) { dib9000_read_unc_blocks()
2350 if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) { dib9000_read_unc_blocks()
2355 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) { dib9000_read_unc_blocks()
2356 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_read_unc_blocks()
2360 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2); dib9000_read_unc_blocks()
2361 mutex_unlock(&state->platform.risc.mem_mbx_lock); dib9000_read_unc_blocks()
2366 mutex_unlock(&state->demod_lock); dib9000_read_unc_blocks()
2441 struct dib9000_state *state = fe->demodulator_priv; dib9000_set_slave_frontend() local
2444 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) dib9000_set_slave_frontend()
2448 state->fe[index_frontend] = fe_slave; dib9000_set_slave_frontend()
2459 struct dib9000_state *state = fe->demodulator_priv; dib9000_remove_slave_frontend() local
2462 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) dib9000_remove_slave_frontend()
2465 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1); dib9000_remove_slave_frontend()
2466 state->fe[index_frontend] = NULL; dib9000_remove_slave_frontend()
2477 struct dib9000_state *state = fe->demodulator_priv; dib9000_get_slave_frontend() local
2481 return state->fe[slave_index]; dib9000_get_slave_frontend()
H A Dlgs8gl5.c72 lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data) lgs8gl5_write_reg() argument
77 .addr = state->config->demod_address, lgs8gl5_write_reg()
83 ret = i2c_transfer(state->i2c, &msg, 1); lgs8gl5_write_reg()
93 lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg) lgs8gl5_read_reg() argument
100 .addr = state->config->demod_address, lgs8gl5_read_reg()
106 .addr = state->config->demod_address, lgs8gl5_read_reg()
113 ret = i2c_transfer(state->i2c, msg, 2); lgs8gl5_read_reg()
122 lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data) lgs8gl5_update_reg() argument
124 lgs8gl5_read_reg(state, reg); lgs8gl5_update_reg()
125 lgs8gl5_write_reg(state, reg, data); lgs8gl5_update_reg()
133 lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data) lgs8gl5_update_alt_reg() argument
141 .addr = state->config->demod_address + 2, lgs8gl5_update_alt_reg()
147 .addr = state->config->demod_address + 2, lgs8gl5_update_alt_reg()
153 .addr = state->config->demod_address + 2, lgs8gl5_update_alt_reg()
160 ret = i2c_transfer(state->i2c, msg, 3); lgs8gl5_update_alt_reg()
166 lgs8gl5_soft_reset(struct lgs8gl5_state *state) lgs8gl5_soft_reset() argument
172 val = lgs8gl5_read_reg(state, REG_RESET); lgs8gl5_soft_reset()
173 lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF); lgs8gl5_soft_reset()
174 lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF); lgs8gl5_soft_reset()
181 lgs8gl5_start_demod(struct lgs8gl5_state *state) lgs8gl5_start_demod() argument
188 lgs8gl5_update_alt_reg(state, 0xc2, 0x28); lgs8gl5_start_demod()
189 lgs8gl5_soft_reset(state); lgs8gl5_start_demod()
190 lgs8gl5_update_reg(state, REG_07, 0x10); lgs8gl5_start_demod()
191 lgs8gl5_update_reg(state, REG_07, 0x10); lgs8gl5_start_demod()
192 lgs8gl5_write_reg(state, REG_09, 0x0e); lgs8gl5_start_demod()
193 lgs8gl5_write_reg(state, REG_0A, 0xe5); lgs8gl5_start_demod()
194 lgs8gl5_write_reg(state, REG_0B, 0x35); lgs8gl5_start_demod()
195 lgs8gl5_write_reg(state, REG_0C, 0x30); lgs8gl5_start_demod()
197 lgs8gl5_update_reg(state, REG_03, 0x00); lgs8gl5_start_demod()
198 lgs8gl5_update_reg(state, REG_7E, 0x01); lgs8gl5_start_demod()
199 lgs8gl5_update_alt_reg(state, 0xc5, 0x00); lgs8gl5_start_demod()
200 lgs8gl5_update_reg(state, REG_04, 0x02); lgs8gl5_start_demod()
201 lgs8gl5_update_reg(state, REG_37, 0x01); lgs8gl5_start_demod()
202 lgs8gl5_soft_reset(state); lgs8gl5_start_demod()
206 val = lgs8gl5_read_reg(state, REG_STRENGTH); lgs8gl5_start_demod()
217 val = lgs8gl5_read_reg(state, REG_STATUS); lgs8gl5_start_demod()
226 lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2)); lgs8gl5_start_demod()
227 lgs8gl5_soft_reset(state); lgs8gl5_start_demod()
234 struct lgs8gl5_state *state = fe->demodulator_priv; lgs8gl5_init() local
238 lgs8gl5_update_alt_reg(state, 0xc2, 0x28); lgs8gl5_init()
239 lgs8gl5_soft_reset(state); lgs8gl5_init()
240 lgs8gl5_update_reg(state, REG_07, 0x10); lgs8gl5_init()
241 lgs8gl5_update_reg(state, REG_07, 0x10); lgs8gl5_init()
242 lgs8gl5_write_reg(state, REG_09, 0x0e); lgs8gl5_init()
243 lgs8gl5_write_reg(state, REG_0A, 0xe5); lgs8gl5_init()
244 lgs8gl5_write_reg(state, REG_0B, 0x35); lgs8gl5_init()
245 lgs8gl5_write_reg(state, REG_0C, 0x30); lgs8gl5_init()
254 struct lgs8gl5_state *state = fe->demodulator_priv; lgs8gl5_read_status() local
255 u8 level = lgs8gl5_read_reg(state, REG_STRENGTH); lgs8gl5_read_status()
256 u8 flags = lgs8gl5_read_reg(state, REG_STATUS); lgs8gl5_read_status()
285 struct lgs8gl5_state *state = fe->demodulator_priv; lgs8gl5_read_signal_strength() local
286 u8 level = lgs8gl5_read_reg(state, REG_STRENGTH); lgs8gl5_read_signal_strength()
296 struct lgs8gl5_state *state = fe->demodulator_priv; lgs8gl5_read_snr() local
297 u8 level = lgs8gl5_read_reg(state, REG_STRENGTH); lgs8gl5_read_snr()
317 struct lgs8gl5_state *state = fe->demodulator_priv; lgs8gl5_set_frontend() local
330 /* lgs8gl5_set_inversion(state, p->inversion); */ lgs8gl5_set_frontend()
332 lgs8gl5_start_demod(state); lgs8gl5_set_frontend()
342 struct lgs8gl5_state *state = fe->demodulator_priv; lgs8gl5_get_frontend() local
343 u8 inv = lgs8gl5_read_reg(state, REG_INVERSION); lgs8gl5_get_frontend()
373 struct lgs8gl5_state *state = fe->demodulator_priv; lgs8gl5_release() local
374 kfree(state); lgs8gl5_release()
384 struct lgs8gl5_state *state = NULL; lgs8gl5_attach() local
388 /* Allocate memory for the internal state */ lgs8gl5_attach()
389 state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL); lgs8gl5_attach()
390 if (state == NULL) lgs8gl5_attach()
393 /* Setup the state */ lgs8gl5_attach()
394 state->config = config; lgs8gl5_attach()
395 state->i2c = i2c; lgs8gl5_attach()
398 if (lgs8gl5_read_reg(state, REG_RESET) < 0) lgs8gl5_attach()
402 memcpy(&state->frontend.ops, &lgs8gl5_ops, lgs8gl5_attach()
404 state->frontend.demodulator_priv = state; lgs8gl5_attach()
405 return &state->frontend; lgs8gl5_attach()
408 kfree(state); lgs8gl5_attach()
H A Dmb86a16.c76 static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) mb86a16_write() argument
82 .addr = state->config->demod_address, mb86a16_write()
90 state->config->demod_address, buf[0], buf[1]); mb86a16_write()
92 ret = i2c_transfer(state->i2c_adap, &msg, 1); mb86a16_write()
97 static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) mb86a16_read() argument
105 .addr = state->config->demod_address, mb86a16_read()
110 .addr = state->config->demod_address, mb86a16_read()
116 ret = i2c_transfer(state->i2c_adap, msg, 2); mb86a16_read()
130 static int CNTM_set(struct mb86a16_state *state, CNTM_set() argument
138 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0) CNTM_set()
148 static int smrt_set(struct mb86a16_state *state, int rate) smrt_set() argument
154 m = 1 << state->deci; smrt_set()
155 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk; smrt_set()
160 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) | smrt_set()
161 (state->csel << 1) | smrt_set()
162 state->rsel) < 0) smrt_set()
164 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0) smrt_set()
166 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0) smrt_set()
175 static int srst(struct mb86a16_state *state) srst() argument
177 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0) srst()
187 static int afcex_data_set(struct mb86a16_state *state, afcex_data_set() argument
191 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0) afcex_data_set()
193 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0) afcex_data_set()
203 static int afcofs_data_set(struct mb86a16_state *state, afcofs_data_set() argument
207 if (mb86a16_write(state, 0x58, AFCEX_L) < 0) afcofs_data_set()
209 if (mb86a16_write(state, 0x59, AFCEX_H) < 0) afcofs_data_set()
218 static int stlp_set(struct mb86a16_state *state, stlp_set() argument
222 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0) stlp_set()
231 static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA) Vi_set() argument
233 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0) Vi_set()
235 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0) Vi_set()
244 static int initial_set(struct mb86a16_state *state) initial_set() argument
246 if (stlp_set(state, 5, 7)) initial_set()
250 if (afcex_data_set(state, 0, 0)) initial_set()
254 if (afcofs_data_set(state, 0, 0)) initial_set()
258 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0) initial_set()
260 if (mb86a16_write(state, 0x2f, 0x21) < 0) initial_set()
262 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0) initial_set()
264 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0) initial_set()
266 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0) initial_set()
268 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0) initial_set()
270 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0) initial_set()
272 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0) initial_set()
274 if (mb86a16_write(state, 0x54, 0xff) < 0) initial_set()
276 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0) initial_set()
286 static int S01T_set(struct mb86a16_state *state, S01T_set() argument
290 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0) S01T_set()
300 static int EN_set(struct mb86a16_state *state, EN_set() argument
307 if (mb86a16_write(state, 0x49, val) < 0) EN_set()
316 static int AFCEXEN_set(struct mb86a16_state *state, AFCEXEN_set() argument
331 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0) AFCEXEN_set()
341 static int DAGC_data_set(struct mb86a16_state *state, DAGC_data_set() argument
345 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0) DAGC_data_set()
355 static void smrt_info_get(struct mb86a16_state *state, int rate) smrt_info_get() argument
358 state->deci = 0; state->csel = 0; state->rsel = 0; smrt_info_get()
360 state->deci = 0; state->csel = 0; state->rsel = 1; smrt_info_get()
362 state->deci = 0; state->csel = 1; state->rsel = 0; smrt_info_get()
364 state->deci = 0; state->csel = 1; state->rsel = 1; smrt_info_get()
366 state->deci = 1; state->csel = 0; state->rsel = 0; smrt_info_get()
368 state->deci = 1; state->csel = 0; state->rsel = 1; smrt_info_get()
370 state->deci = 1; state->csel = 1; state->rsel = 0; smrt_info_get()
372 state->deci = 1; state->csel = 1; state->rsel = 1; smrt_info_get()
374 state->deci = 2; state->csel = 0; state->rsel = 0; smrt_info_get()
376 state->deci = 2; state->csel = 0; state->rsel = 1; smrt_info_get()
378 state->deci = 2; state->csel = 1; state->rsel = 0; smrt_info_get()
380 state->deci = 2; state->csel = 1; state->rsel = 1; smrt_info_get()
382 state->deci = 3; state->csel = 0; state->rsel = 0; smrt_info_get()
384 state->deci = 3; state->csel = 0; state->rsel = 1; smrt_info_get()
386 state->deci = 3; state->csel = 1; state->rsel = 0; smrt_info_get()
388 state->deci = 3; state->csel = 1; state->rsel = 1; smrt_info_get()
390 state->deci = 4; state->csel = 0; state->rsel = 0; smrt_info_get()
392 state->deci = 4; state->csel = 0; state->rsel = 1; smrt_info_get()
394 state->deci = 4; state->csel = 1; state->rsel = 0; smrt_info_get()
396 state->deci = 4; state->csel = 1; state->rsel = 1; smrt_info_get()
398 state->deci = 5; state->csel = 0; state->rsel = 0; smrt_info_get()
400 state->deci = 5; state->csel = 0; state->rsel = 1; smrt_info_get()
402 state->deci = 5; state->csel = 1; state->rsel = 0; smrt_info_get()
404 state->deci = 5; state->csel = 1; state->rsel = 1; smrt_info_get()
407 if (state->csel == 0) smrt_info_get()
408 state->master_clk = 92000; smrt_info_get()
410 state->master_clk = 61333; smrt_info_get()
414 static int signal_det(struct mb86a16_state *state, signal_det() argument
428 if (CNTM_set(state, 2, 1, 2) < 0) { signal_det()
434 if (CNTM_set(state, 3, 1, 2) < 0) { signal_det()
447 smrt_info_get(state, smrtd); signal_det()
448 smrt_set(state, smrtd); signal_det()
449 srst(state); signal_det()
454 if (mb86a16_read(state, 0x37, &(S[i])) != 2) { signal_det()
468 if (CNTM_set(state, 0, 1, 2) < 0) { signal_det()
476 static int rf_val_set(struct mb86a16_state *state, rf_val_set() argument
533 if (mb86a16_write(state, 0x21, rf_val[0]) < 0) rf_val_set()
535 if (mb86a16_write(state, 0x22, rf_val[1]) < 0) rf_val_set()
537 if (mb86a16_write(state, 0x23, rf_val[2]) < 0) rf_val_set()
539 if (mb86a16_write(state, 0x24, rf_val[3]) < 0) rf_val_set()
541 if (mb86a16_write(state, 0x25, 0x01) < 0) rf_val_set()
551 static int afcerr_chk(struct mb86a16_state *state) afcerr_chk() argument
557 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2) afcerr_chk()
559 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2) afcerr_chk()
568 afcerr = afcm * state->master_clk / 8192; afcerr_chk()
577 static int dagcm_val_get(struct mb86a16_state *state) dagcm_val_get() argument
582 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2) dagcm_val_get()
584 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2) dagcm_val_get()
599 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_read_status() local
603 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2) mb86a16_read_status()
605 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2) mb86a16_read_status()
612 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2) mb86a16_read_status()
620 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2) mb86a16_read_status()
633 static int sync_chk(struct mb86a16_state *state, sync_chk() argument
639 if (mb86a16_read(state, 0x0d, &val) != 2) sync_chk()
653 static int freqerr_chk(struct mb86a16_state *state, freqerr_chk() argument
666 if (mb86a16_read(state, 0x43, &CRM) != 2) freqerr_chk()
675 if (mb86a16_read(state, 0x49, &temp1) != 2) freqerr_chk()
680 if (mb86a16_read(state, 0x2a, &temp1) != 2) freqerr_chk()
686 if (mb86a16_read(state, 0x0e, &AFCML) != 2) freqerr_chk()
688 if (mb86a16_read(state, 0x0f, &AFCMH) != 2) freqerr_chk()
691 if (mb86a16_read(state, 0x2b, &AFCML) != 2) freqerr_chk()
693 if (mb86a16_read(state, 0x2c, &AFCMH) != 2) freqerr_chk()
697 smrt_info_get(state, smrt); freqerr_chk()
704 afcerr = afcm * state->master_clk / 8192; freqerr_chk()
708 if (mb86a16_read(state, 0x22, &temp1) != 2) freqerr_chk()
710 if (mb86a16_read(state, 0x23, &temp2) != 2) freqerr_chk()
712 if (mb86a16_read(state, 0x24, &temp3) != 2) freqerr_chk()
739 static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt) vco_dev_get() argument
751 static void swp_info_get(struct mb86a16_state *state, swp_info_get() argument
776 AFCEX = *afcex_freq * 8192 / state->master_clk; swp_info_get()
782 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin, swp_freq_calcuation() argument
930 static void swp_info_get2(struct mb86a16_state *state, swp_info_get2() argument
951 AFCEX = *afcex_freq * 8192 / state->master_clk; swp_info_get2()
956 static void afcex_info_get(struct mb86a16_state *state, afcex_info_get() argument
963 AFCEX = afcex_freq * 8192 / state->master_clk; afcex_info_get()
968 static int SEQ_set(struct mb86a16_state *state, unsigned char loop) SEQ_set() argument
971 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) { SEQ_set()
979 static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV) iq_vt_set() argument
982 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) { iq_vt_set()
990 static int FEC_srst(struct mb86a16_state *state) FEC_srst() argument
992 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) { FEC_srst()
1000 static int S2T_set(struct mb86a16_state *state, unsigned char S2T) S2T_set() argument
1002 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) { S2T_set()
1010 static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T) S45T_set() argument
1012 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) { S45T_set()
1021 static int mb86a16_set_fe(struct mb86a16_state *state) mb86a16_set_fe() argument
1065 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate); mb86a16_set_fe()
1068 swp_ofs = state->srate / 4; mb86a16_set_fe()
1079 SEQ_set(state, 0); mb86a16_set_fe()
1080 iq_vt_set(state, 0); mb86a16_set_fe()
1091 if (initial_set(state) < 0) { mb86a16_set_fe()
1095 if (DAGC_data_set(state, 3, 2) < 0) { mb86a16_set_fe()
1099 if (EN_set(state, CREN, AFCEN) < 0) { mb86a16_set_fe()
1103 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { mb86a16_set_fe()
1107 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) { mb86a16_set_fe()
1111 if (S01T_set(state, S1T, S0T) < 0) { mb86a16_set_fe()
1115 smrt_info_get(state, state->srate); mb86a16_set_fe()
1116 if (smrt_set(state, state->srate) < 0) { mb86a16_set_fe()
1121 R = vco_dev_get(state, state->srate); mb86a16_set_fe()
1123 fOSC_start = state->frequency; mb86a16_set_fe()
1126 if (state->frequency % 2 == 0) { mb86a16_set_fe()
1127 fOSC_start = state->frequency; mb86a16_set_fe()
1129 fOSC_start = state->frequency + 1; mb86a16_set_fe()
1131 fOSC_start = state->frequency - 1; mb86a16_set_fe()
1147 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4)) mb86a16_set_fe()
1165 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4)) mb86a16_set_fe()
1170 wait_t = (8000 + state->srate / 2) / state->srate; mb86a16_set_fe()
1184 swp_info_get(state, fOSC_start, state->srate, mb86a16_set_fe()
1189 if (rf_val_set(state, fOSC, state->srate, R) < 0) { mb86a16_set_fe()
1194 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { mb86a16_set_fe()
1198 if (srst(state) < 0) { mb86a16_set_fe()
1204 if (mb86a16_read(state, 0x37, &SIG1) != 2) { mb86a16_set_fe()
1209 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin, mb86a16_set_fe()
1220 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) { mb86a16_set_fe()
1221 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate); mb86a16_set_fe()
1224 swp_info_get2(state, state->srate, R, swp_freq, mb86a16_set_fe()
1228 if (rf_val_set(state, fOSC, state->srate, R) < 0) { mb86a16_set_fe()
1232 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { mb86a16_set_fe()
1236 signal = signal_det(state, state->srate, &SIG1); mb86a16_set_fe()
1242 smrt_info_get(state, state->srate); mb86a16_set_fe()
1243 if (smrt_set(state, state->srate) < 0) { mb86a16_set_fe()
1277 if (S01T_set(state, S1T, S0T) < 0) { mb86a16_set_fe()
1281 smrt_info_get(state, state->srate); mb86a16_set_fe()
1282 if (smrt_set(state, state->srate) < 0) { mb86a16_set_fe()
1286 if (EN_set(state, CREN, AFCEN) < 0) { mb86a16_set_fe()
1290 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { mb86a16_set_fe()
1294 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H); mb86a16_set_fe()
1295 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) { mb86a16_set_fe()
1299 if (srst(state) < 0) { mb86a16_set_fe()
1304 wait_t = 200000 / state->master_clk + 200000 / state->srate; mb86a16_set_fe()
1306 afcerr = afcerr_chk(state); mb86a16_set_fe()
1312 if (state->srate >= 1500) mb86a16_set_fe()
1313 smrt_d = state->srate / 3; mb86a16_set_fe()
1315 smrt_d = state->srate / 2; mb86a16_set_fe()
1316 smrt_info_get(state, smrt_d); mb86a16_set_fe()
1317 if (smrt_set(state, smrt_d) < 0) { mb86a16_set_fe()
1321 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) { mb86a16_set_fe()
1325 R = vco_dev_get(state, smrt_d); mb86a16_set_fe()
1326 if (DAGC_data_set(state, 2, 0) < 0) { mb86a16_set_fe()
1331 temp_freq = swp_freq + (i - 1) * state->srate / 8; mb86a16_set_fe()
1332 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); mb86a16_set_fe()
1333 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { mb86a16_set_fe()
1337 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { mb86a16_set_fe()
1341 wait_t = 200000 / state->master_clk + 40000 / smrt_d; mb86a16_set_fe()
1343 dagcm[i] = dagcm_val_get(state); mb86a16_set_fe()
1349 temp_freq = swp_freq - 2 * state->srate / 8; mb86a16_set_fe()
1350 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); mb86a16_set_fe()
1351 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { mb86a16_set_fe()
1355 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { mb86a16_set_fe()
1359 wait_t = 200000 / state->master_clk + 40000 / smrt_d; mb86a16_set_fe()
1361 dagcm[3] = dagcm_val_get(state); mb86a16_set_fe()
1363 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300; mb86a16_set_fe()
1370 temp_freq = swp_freq + 2 * state->srate / 8; mb86a16_set_fe()
1371 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); mb86a16_set_fe()
1372 if (rf_val_set(state, fOSC, smrt_d, R) < 0) { mb86a16_set_fe()
1376 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { mb86a16_set_fe()
1380 wait_t = 200000 / state->master_clk + 40000 / smrt_d; mb86a16_set_fe()
1382 dagcm[3] = dagcm_val_get(state); mb86a16_set_fe()
1384 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300; mb86a16_set_fe()
1394 if (ABS(state->frequency * 1000 - swp_freq) > 3800) { mb86a16_set_fe()
1404 if (S01T_set(state, S1T, S0T) < 0) { mb86a16_set_fe()
1408 if (DAGC_data_set(state, 0, 0) < 0) { mb86a16_set_fe()
1412 R = vco_dev_get(state, state->srate); mb86a16_set_fe()
1413 smrt_info_get(state, state->srate); mb86a16_set_fe()
1414 if (smrt_set(state, state->srate) < 0) { mb86a16_set_fe()
1418 if (EN_set(state, CREN, AFCEN) < 0) { mb86a16_set_fe()
1422 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) { mb86a16_set_fe()
1426 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H); mb86a16_set_fe()
1427 if (rf_val_set(state, fOSC, state->srate, R) < 0) { mb86a16_set_fe()
1431 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) { mb86a16_set_fe()
1435 if (srst(state) < 0) { mb86a16_set_fe()
1439 wait_t = 7 + (10000 + state->srate / 2) / state->srate; mb86a16_set_fe()
1443 if (mb86a16_read(state, 0x37, &SIG1) != 2) { mb86a16_set_fe()
1450 wait_t = 7 + (917504 + state->srate / 2) / state->srate; mb86a16_set_fe()
1453 wait_t = 7 + (1048576 + state->srate / 2) / state->srate; mb86a16_set_fe()
1456 wait_t = 7 + (1310720 + state->srate / 2) / state->srate; mb86a16_set_fe()
1459 wait_t = 7 + (1572864 + state->srate / 2) / state->srate; mb86a16_set_fe()
1462 wait_t = 7 + (2097152 + state->srate / 2) / state->srate; mb86a16_set_fe()
1465 S2T_set(state, S2T); mb86a16_set_fe()
1466 S45T_set(state, S4T, S5T); mb86a16_set_fe()
1467 Vi_set(state, ETH, VIA); mb86a16_set_fe()
1468 srst(state); mb86a16_set_fe()
1470 sync = sync_chk(state, &VIRM); mb86a16_set_fe()
1476 wait_t = (786432 + state->srate / 2) / state->srate; mb86a16_set_fe()
1478 wait_t = (1572864 + state->srate / 2) / state->srate; mb86a16_set_fe()
1479 if (state->srate < 5000) mb86a16_set_fe()
1485 if (sync_chk(state, &junk) == 0) { mb86a16_set_fe()
1486 iq_vt_set(state, 1); mb86a16_set_fe()
1487 FEC_srst(state); mb86a16_set_fe()
1492 wait_t = (786432 + state->srate / 2) / state->srate; mb86a16_set_fe()
1494 wait_t = (1572864 + state->srate / 2) / state->srate; mb86a16_set_fe()
1496 SEQ_set(state, 1); mb86a16_set_fe()
1499 SEQ_set(state, 1); mb86a16_set_fe()
1508 sync = sync_chk(state, &junk); mb86a16_set_fe()
1511 freqerr_chk(state, state->frequency, state->srate, 1); mb86a16_set_fe()
1517 mb86a16_read(state, 0x15, &agcval); mb86a16_set_fe()
1518 mb86a16_read(state, 0x26, &cnmval); mb86a16_set_fe()
1527 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_send_diseqc_msg() local
1531 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) mb86a16_send_diseqc_msg()
1533 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) mb86a16_send_diseqc_msg()
1535 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) mb86a16_send_diseqc_msg()
1544 if (mb86a16_write(state, regs, cmd->msg[i]) < 0) mb86a16_send_diseqc_msg()
1553 if (mb86a16_write(state, MB86A16_DCC1, i) < 0) mb86a16_send_diseqc_msg()
1555 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) mb86a16_send_diseqc_msg()
1567 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_send_diseqc_burst() local
1571 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | mb86a16_send_diseqc_burst()
1575 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) mb86a16_send_diseqc_burst()
1579 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | mb86a16_send_diseqc_burst()
1582 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) mb86a16_send_diseqc_burst()
1595 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_set_tone() local
1599 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0) mb86a16_set_tone()
1601 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA | mb86a16_set_tone()
1605 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0) mb86a16_set_tone()
1609 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0) mb86a16_set_tone()
1611 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0) mb86a16_set_tone()
1613 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0) mb86a16_set_tone()
1629 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_search() local
1631 state->frequency = p->frequency / 1000; mb86a16_search()
1632 state->srate = p->symbol_rate / 1000; mb86a16_search()
1634 if (!mb86a16_set_fe(state)) { mb86a16_search()
1645 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_release() local
1646 kfree(state); mb86a16_release()
1664 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_read_ber() local
1667 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2) mb86a16_read_ber()
1669 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2) mb86a16_read_ber()
1671 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2) mb86a16_read_ber()
1673 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2) mb86a16_read_ber()
1675 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2) mb86a16_read_ber()
1729 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_read_signal_strength() local
1732 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) { mb86a16_read_signal_strength()
1775 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_read_snr() local
1781 if (mb86a16_read(state, 0x26, &cn) != 2) { mb86a16_read_snr()
1802 struct mb86a16_state *state = fe->demodulator_priv; mb86a16_read_ucblocks() local
1804 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) { mb86a16_read_ucblocks()
1856 struct mb86a16_state *state = NULL; mb86a16_attach() local
1858 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL); mb86a16_attach()
1859 if (state == NULL) mb86a16_attach()
1862 state->config = config; mb86a16_attach()
1863 state->i2c_adap = i2c_adap; mb86a16_attach()
1865 mb86a16_read(state, 0x7f, &dev_id); mb86a16_attach()
1869 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops)); mb86a16_attach()
1870 state->frontend.demodulator_priv = state; mb86a16_attach()
1871 state->frontend.ops.set_voltage = state->config->set_voltage; mb86a16_attach()
1873 return &state->frontend; mb86a16_attach()
1875 kfree(state); mb86a16_attach()
H A Ddib7000p.c93 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
94 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
96 static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) dib7000p_read_word() argument
100 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib7000p_read_word()
105 state->i2c_write_buffer[0] = reg >> 8; dib7000p_read_word()
106 state->i2c_write_buffer[1] = reg & 0xff; dib7000p_read_word()
108 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); dib7000p_read_word()
109 state->msg[0].addr = state->i2c_addr >> 1; dib7000p_read_word()
110 state->msg[0].flags = 0; dib7000p_read_word()
111 state->msg[0].buf = state->i2c_write_buffer; dib7000p_read_word()
112 state->msg[0].len = 2; dib7000p_read_word()
113 state->msg[1].addr = state->i2c_addr >> 1; dib7000p_read_word()
114 state->msg[1].flags = I2C_M_RD; dib7000p_read_word()
115 state->msg[1].buf = state->i2c_read_buffer; dib7000p_read_word()
116 state->msg[1].len = 2; dib7000p_read_word()
118 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2) dib7000p_read_word()
121 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; dib7000p_read_word()
122 mutex_unlock(&state->i2c_buffer_lock); dib7000p_read_word()
126 static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val) dib7000p_write_word() argument
130 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib7000p_write_word()
135 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; dib7000p_write_word()
136 state->i2c_write_buffer[1] = reg & 0xff; dib7000p_write_word()
137 state->i2c_write_buffer[2] = (val >> 8) & 0xff; dib7000p_write_word()
138 state->i2c_write_buffer[3] = val & 0xff; dib7000p_write_word()
140 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); dib7000p_write_word()
141 state->msg[0].addr = state->i2c_addr >> 1; dib7000p_write_word()
142 state->msg[0].flags = 0; dib7000p_write_word()
143 state->msg[0].buf = state->i2c_write_buffer; dib7000p_write_word()
144 state->msg[0].len = 4; dib7000p_write_word()
146 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? dib7000p_write_word()
148 mutex_unlock(&state->i2c_buffer_lock); dib7000p_write_word()
152 static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf) dib7000p_write_tab() argument
161 dib7000p_write_word(state, r, *n++); dib7000p_write_tab()
168 static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode) dib7000p_set_output_mode() argument
175 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); dib7000p_set_output_mode()
177 dprintk("setting output mode for demod %p to %d", &state->demod, mode); dib7000p_set_output_mode()
190 if (state->cfg.hostbus_diversity) dib7000p_set_output_mode()
207 dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod); dib7000p_set_output_mode()
211 if (state->cfg.output_mpeg2_in_188_bytes) dib7000p_set_output_mode()
214 ret |= dib7000p_write_word(state, 235, smo_mode); dib7000p_set_output_mode()
215 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ dib7000p_set_output_mode()
216 if (state->version != SOC7090) dib7000p_set_output_mode()
217 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */ dib7000p_set_output_mode()
224 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_set_diversity_in() local
226 if (state->div_force_off) { dib7000p_set_diversity_in()
229 dib7000p_write_word(state, 207, 0); dib7000p_set_diversity_in()
231 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0)); dib7000p_set_diversity_in()
233 state->div_state = (u8) onoff; dib7000p_set_diversity_in()
236 dib7000p_write_word(state, 204, 6); dib7000p_set_diversity_in()
237 dib7000p_write_word(state, 205, 16); dib7000p_set_diversity_in()
240 dib7000p_write_word(state, 204, 1); dib7000p_set_diversity_in()
241 dib7000p_write_word(state, 205, 0); dib7000p_set_diversity_in()
247 static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode) dib7000p_set_power_mode() argument
250 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff); dib7000p_set_power_mode()
260 if (state->version == SOC7090) dib7000p_set_power_mode()
272 if (state->version != SOC7090) dib7000p_set_power_mode()
279 if (state->version == SOC7090) dib7000p_set_power_mode()
288 dib7000p_write_word(state, 774, reg_774); dib7000p_set_power_mode()
289 dib7000p_write_word(state, 775, reg_775); dib7000p_set_power_mode()
290 dib7000p_write_word(state, 776, reg_776); dib7000p_set_power_mode()
291 dib7000p_write_word(state, 1280, reg_1280); dib7000p_set_power_mode()
292 if (state->version != SOC7090) dib7000p_set_power_mode()
293 dib7000p_write_word(state, 899, reg_899); dib7000p_set_power_mode()
298 static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no) dib7000p_set_adc_state() argument
303 if (state->version != SOC7090) { dib7000p_set_adc_state()
304 reg_908 = dib7000p_read_word(state, 908); dib7000p_set_adc_state()
305 reg_909 = dib7000p_read_word(state, 909); dib7000p_set_adc_state()
310 if (state->version == SOC7090) { dib7000p_set_adc_state()
311 reg = dib7000p_read_word(state, 1925); dib7000p_set_adc_state()
313 dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */ dib7000p_set_adc_state()
315 reg = dib7000p_read_word(state, 1925); /* read acces to make it works... strange ... */ dib7000p_set_adc_state()
317 dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */ dib7000p_set_adc_state()
319 reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12)); dib7000p_set_adc_state()
320 dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */ dib7000p_set_adc_state()
323 dib7000p_write_word(state, 909, reg_909); dib7000p_set_adc_state()
329 if (state->version == SOC7090) { dib7000p_set_adc_state()
330 reg = dib7000p_read_word(state, 1925); dib7000p_set_adc_state()
331 dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */ dib7000p_set_adc_state()
360 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4; dib7000p_set_adc_state()
361 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7; dib7000p_set_adc_state()
363 if (state->version != SOC7090) { dib7000p_set_adc_state()
364 dib7000p_write_word(state, 908, reg_908); dib7000p_set_adc_state()
365 dib7000p_write_word(state, 909, reg_909); dib7000p_set_adc_state()
369 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw) dib7000p_set_bandwidth() argument
374 state->current_bandwidth = bw; dib7000p_set_bandwidth()
376 if (state->timf == 0) { dib7000p_set_bandwidth()
378 timf = state->cfg.bw->timf; dib7000p_set_bandwidth()
381 timf = state->timf; dib7000p_set_bandwidth()
386 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); dib7000p_set_bandwidth()
387 dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff)); dib7000p_set_bandwidth()
392 static int dib7000p_sad_calib(struct dib7000p_state *state) dib7000p_sad_calib() argument
395 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0)); dib7000p_sad_calib()
397 if (state->version == SOC7090) dib7000p_sad_calib()
398 dib7000p_write_word(state, 74, 2048); dib7000p_sad_calib()
400 dib7000p_write_word(state, 74, 776); dib7000p_sad_calib()
403 dib7000p_write_word(state, 73, (1 << 0)); dib7000p_sad_calib()
404 dib7000p_write_word(state, 73, (0 << 0)); dib7000p_sad_calib()
413 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_set_wbd_ref() local
416 state->wbd_ref = value; dib7000p_set_wbd_ref()
417 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value); dib7000p_set_wbd_ref()
423 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_get_agc_values() local
426 *agc_global = dib7000p_read_word(state, 394); dib7000p_get_agc_values()
428 *agc1 = dib7000p_read_word(state, 392); dib7000p_get_agc_values()
430 *agc2 = dib7000p_read_word(state, 393); dib7000p_get_agc_values()
432 *wbd = dib7000p_read_word(state, 397); dib7000p_get_agc_values()
439 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_set_agc1_min() local
440 return dib7000p_write_word(state, 108, v); dib7000p_set_agc1_min()
443 static void dib7000p_reset_pll(struct dib7000p_state *state) dib7000p_reset_pll() argument
445 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; dib7000p_reset_pll()
448 if (state->version == SOC7090) { dib7000p_reset_pll()
449 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv)); dib7000p_reset_pll()
451 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) dib7000p_reset_pll()
454 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15)); dib7000p_reset_pll()
460 dib7000p_write_word(state, 900, clk_cfg0); dib7000p_reset_pll()
463 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset); dib7000p_reset_pll()
465 dib7000p_write_word(state, 900, clk_cfg0); dib7000p_reset_pll()
468 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff)); dib7000p_reset_pll()
469 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff)); dib7000p_reset_pll()
470 dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff)); dib7000p_reset_pll()
471 dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff)); dib7000p_reset_pll()
473 dib7000p_write_word(state, 72, bw->sad_cfg); dib7000p_reset_pll()
476 static u32 dib7000p_get_internal_freq(struct dib7000p_state *state) dib7000p_get_internal_freq() argument
478 u32 internal = (u32) dib7000p_read_word(state, 18) << 16; dib7000p_get_internal_freq()
479 internal |= (u32) dib7000p_read_word(state, 19); dib7000p_get_internal_freq()
487 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_update_pll() local
488 u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856); dib7000p_update_pll()
499 reg_1857 = dib7000p_read_word(state, 1857); dib7000p_update_pll()
500 dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15)); dib7000p_update_pll()
502 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f)); dib7000p_update_pll()
505 internal = dib7000p_get_internal_freq(state); dib7000p_update_pll()
508 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff)); dib7000p_update_pll()
509 dib7000p_write_word(state, 19, (u16) (internal & 0xffff)); dib7000p_update_pll()
511 dib7000p_write_word(state, 1857, reg_1857 | (1 << 15)); dib7000p_update_pll()
513 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) dib7000p_update_pll()
554 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_set_gpio() local
555 return dib7000p_cfg_gpio(state, num, dir, val); dib7000p_set_gpio()
643 static int dib7000p_demod_reset(struct dib7000p_state *state) dib7000p_demod_reset() argument
645 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); dib7000p_demod_reset()
647 if (state->version == SOC7090) dib7000p_demod_reset()
648 dibx000_reset_i2c_master(&state->i2c_master); dib7000p_demod_reset()
650 dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE); dib7000p_demod_reset()
653 dib7000p_write_word(state, 770, 0xffff); dib7000p_demod_reset()
654 dib7000p_write_word(state, 771, 0xffff); dib7000p_demod_reset()
655 dib7000p_write_word(state, 772, 0x001f); dib7000p_demod_reset()
656 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3))); dib7000p_demod_reset()
658 dib7000p_write_word(state, 770, 0); dib7000p_demod_reset()
659 dib7000p_write_word(state, 771, 0); dib7000p_demod_reset()
660 dib7000p_write_word(state, 772, 0); dib7000p_demod_reset()
661 dib7000p_write_word(state, 1280, 0); dib7000p_demod_reset()
663 if (state->version != SOC7090) { dib7000p_demod_reset()
664 dib7000p_write_word(state, 898, 0x0003); dib7000p_demod_reset()
665 dib7000p_write_word(state, 898, 0); dib7000p_demod_reset()
669 dib7000p_reset_pll(state); dib7000p_demod_reset()
671 if (dib7000p_reset_gpio(state) != 0) dib7000p_demod_reset()
674 if (state->version == SOC7090) { dib7000p_demod_reset()
675 dib7000p_write_word(state, 899, 0); dib7000p_demod_reset()
678 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */ dib7000p_demod_reset()
679 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */ dib7000p_demod_reset()
680 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */ dib7000p_demod_reset()
681 dib7000p_write_word(state, 273, (0<<6) | 30); dib7000p_demod_reset()
683 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0) dib7000p_demod_reset()
686 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); dib7000p_demod_reset()
687 dib7000p_sad_calib(state); dib7000p_demod_reset()
688 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF); dib7000p_demod_reset()
691 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1)); dib7000p_demod_reset()
693 dib7000p_set_bandwidth(state, 8000); dib7000p_demod_reset()
695 if (state->version == SOC7090) { dib7000p_demod_reset()
696 dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */ dib7000p_demod_reset()
698 if (state->cfg.tuner_is_baseband) dib7000p_demod_reset()
699 dib7000p_write_word(state, 36, 0x0755); dib7000p_demod_reset()
701 dib7000p_write_word(state, 36, 0x1f55); dib7000p_demod_reset()
704 dib7000p_write_tab(state, dib7000p_defaults); dib7000p_demod_reset()
705 if (state->version != SOC7090) { dib7000p_demod_reset()
706 dib7000p_write_word(state, 901, 0x0006); dib7000p_demod_reset()
707 dib7000p_write_word(state, 902, (3 << 10) | (1 << 6)); dib7000p_demod_reset()
708 dib7000p_write_word(state, 905, 0x2c8e); dib7000p_demod_reset()
711 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); dib7000p_demod_reset()
716 static void dib7000p_pll_clk_cfg(struct dib7000p_state *state) dib7000p_pll_clk_cfg() argument
719 tmp = dib7000p_read_word(state, 903); dib7000p_pll_clk_cfg()
720 dib7000p_write_word(state, 903, (tmp | 0x1)); dib7000p_pll_clk_cfg()
721 tmp = dib7000p_read_word(state, 900); dib7000p_pll_clk_cfg()
722 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); dib7000p_pll_clk_cfg()
725 static void dib7000p_restart_agc(struct dib7000p_state *state) dib7000p_restart_agc() argument
728 dib7000p_write_word(state, 770, (1 << 11) | (1 << 9)); dib7000p_restart_agc()
729 dib7000p_write_word(state, 770, 0x0000); dib7000p_restart_agc()
732 static int dib7000p_update_lna(struct dib7000p_state *state) dib7000p_update_lna() argument
736 if (state->cfg.update_lna) { dib7000p_update_lna()
737 dyn_gain = dib7000p_read_word(state, 394); dib7000p_update_lna()
738 if (state->cfg.update_lna(&state->demod, dyn_gain)) { dib7000p_update_lna()
739 dib7000p_restart_agc(state); dib7000p_update_lna()
747 static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band) dib7000p_set_agc_config() argument
751 if (state->current_band == band && state->current_agc != NULL) dib7000p_set_agc_config()
753 state->current_band = band; dib7000p_set_agc_config()
755 for (i = 0; i < state->cfg.agc_config_count; i++) dib7000p_set_agc_config()
756 if (state->cfg.agc[i].band_caps & band) { dib7000p_set_agc_config()
757 agc = &state->cfg.agc[i]; dib7000p_set_agc_config()
766 state->current_agc = agc; dib7000p_set_agc_config()
769 dib7000p_write_word(state, 75, agc->setup); dib7000p_set_agc_config()
770 dib7000p_write_word(state, 76, agc->inv_gain); dib7000p_set_agc_config()
771 dib7000p_write_word(state, 77, agc->time_stabiliz); dib7000p_set_agc_config()
772 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock); dib7000p_set_agc_config()
775 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp); dib7000p_set_agc_config()
776 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp); dib7000p_set_agc_config()
780 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); dib7000p_set_agc_config()
782 if (state->wbd_ref != 0) dib7000p_set_agc_config()
783 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref); dib7000p_set_agc_config()
785 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref); dib7000p_set_agc_config()
787 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); dib7000p_set_agc_config()
789 dib7000p_write_word(state, 107, agc->agc1_max); dib7000p_set_agc_config()
790 dib7000p_write_word(state, 108, agc->agc1_min); dib7000p_set_agc_config()
791 dib7000p_write_word(state, 109, agc->agc2_max); dib7000p_set_agc_config()
792 dib7000p_write_word(state, 110, agc->agc2_min); dib7000p_set_agc_config()
793 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2); dib7000p_set_agc_config()
794 dib7000p_write_word(state, 112, agc->agc1_pt3); dib7000p_set_agc_config()
795 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); dib7000p_set_agc_config()
796 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); dib7000p_set_agc_config()
797 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); dib7000p_set_agc_config()
801 static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz) dib7000p_set_dds() argument
803 u32 internal = dib7000p_get_internal_freq(state); dib7000p_set_dds()
806 u32 dds = state->cfg.bw->ifreq & 0x1ffffff; dib7000p_set_dds()
807 u8 invert = !!(state->cfg.bw->ifreq & (1 << 25)); dib7000p_set_dds()
821 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9))); dib7000p_set_dds()
822 dib7000p_write_word(state, 22, (u16) (dds & 0xffff)); dib7000p_set_dds()
829 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_agc_startup() local
831 u8 *agc_state = &state->agc_state; dib7000p_agc_startup()
837 switch (state->agc_state) { dib7000p_agc_startup()
839 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); dib7000p_agc_startup()
840 if (state->version == SOC7090) { dib7000p_agc_startup()
841 reg = dib7000p_read_word(state, 0x79b) & 0xff00; dib7000p_agc_startup()
842 dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */ dib7000p_agc_startup()
843 dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF)); dib7000p_agc_startup()
846 reg = dib7000p_read_word(state, 0x780); dib7000p_agc_startup()
847 dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7))); dib7000p_agc_startup()
849 dib7000p_set_adc_state(state, DIBX000_ADC_ON); dib7000p_agc_startup()
850 dib7000p_pll_clk_cfg(state); dib7000p_agc_startup()
853 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0) dib7000p_agc_startup()
863 dib7000p_set_dds(state, frequency_offset); dib7000p_agc_startup()
869 if (state->cfg.agc_control) dib7000p_agc_startup()
870 state->cfg.agc_control(&state->demod, 1); dib7000p_agc_startup()
872 dib7000p_write_word(state, 78, 32768); dib7000p_agc_startup()
873 if (!state->current_agc->perform_agc_softsplit) { dib7000p_agc_startup()
876 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8)); dib7000p_agc_startup()
886 dib7000p_restart_agc(state); dib7000p_agc_startup()
890 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */ dib7000p_agc_startup()
891 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */ dib7000p_agc_startup()
897 agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */ dib7000p_agc_startup()
898 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */ dib7000p_agc_startup()
900 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */ dib7000p_agc_startup()
901 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */ dib7000p_agc_startup()
903 dib7000p_restart_agc(state); dib7000p_agc_startup()
914 if (dib7000p_update_lna(state)) dib7000p_agc_startup()
921 if (state->cfg.agc_control) dib7000p_agc_startup()
922 state->cfg.agc_control(&state->demod, 0); dib7000p_agc_startup()
931 static void dib7000p_update_timf(struct dib7000p_state *state) dib7000p_update_timf() argument
933 u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428); dib7000p_update_timf()
934 state->timf = timf * 160 / (state->current_bandwidth / 50); dib7000p_update_timf()
935 dib7000p_write_word(state, 23, (u16) (timf >> 16)); dib7000p_update_timf()
936 dib7000p_write_word(state, 24, (u16) (timf & 0xffff)); dib7000p_update_timf()
937 dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf); dib7000p_update_timf()
943 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_ctrl_timf() local
946 state->timf = timf; dib7000p_ctrl_timf()
949 dib7000p_update_timf(state); dib7000p_ctrl_timf()
954 dib7000p_set_bandwidth(state, state->current_bandwidth); dib7000p_ctrl_timf()
955 return state->timf; dib7000p_ctrl_timf()
958 static void dib7000p_set_channel(struct dib7000p_state *state, dib7000p_set_channel() argument
963 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); dib7000p_set_channel()
1018 dib7000p_write_word(state, 0, value); dib7000p_set_channel()
1019 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */ dib7000p_set_channel()
1047 dib7000p_write_word(state, 208, value); dib7000p_set_channel()
1050 dib7000p_write_word(state, 26, 0x6680); dib7000p_set_channel()
1051 dib7000p_write_word(state, 32, 0x0003); dib7000p_set_channel()
1052 dib7000p_write_word(state, 29, 0x1273); dib7000p_set_channel()
1053 dib7000p_write_word(state, 33, 0x0005); dib7000p_set_channel()
1083 if (state->cfg.diversity_delay == 0) dib7000p_set_channel()
1084 state->div_sync_wait = (value * 3) / 2 + 48; dib7000p_set_channel()
1086 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay; dib7000p_set_channel()
1089 state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K; dib7000p_set_channel()
1090 dib7000p_set_diversity_in(&state->demod, state->div_state); dib7000p_set_channel()
1114 dib7000p_write_word(state, 187 + value, est[value]); dib7000p_set_channel()
1120 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_autosearch_start() local
1123 u32 internal = dib7000p_get_internal_freq(state); dib7000p_autosearch_start()
1133 dib7000p_set_channel(state, &schan, 7); dib7000p_autosearch_start()
1137 if (state->version == SOC7090) dib7000p_autosearch_start()
1145 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); dib7000p_autosearch_start()
1146 dib7000p_write_word(state, 7, (u16) (value & 0xffff)); dib7000p_autosearch_start()
1148 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); dib7000p_autosearch_start()
1149 dib7000p_write_word(state, 9, (u16) (value & 0xffff)); dib7000p_autosearch_start()
1151 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); dib7000p_autosearch_start()
1152 dib7000p_write_word(state, 11, (u16) (value & 0xffff)); dib7000p_autosearch_start()
1154 value = dib7000p_read_word(state, 0); dib7000p_autosearch_start()
1155 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value)); dib7000p_autosearch_start()
1156 dib7000p_read_word(state, 1284); dib7000p_autosearch_start()
1157 dib7000p_write_word(state, 0, (u16) value); dib7000p_autosearch_start()
1164 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_autosearch_is_irq() local
1165 u16 irq_pending = dib7000p_read_word(state, 1284); dib7000p_autosearch_is_irq()
1176 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw) dib7000p_spur_protect() argument
1198 u32 xtal = state->cfg.bw->xtal_hz / 1000; dib7000p_spur_protect()
1212 dib7000p_write_word(state, 142, 0x0610); dib7000p_spur_protect()
1257 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); dib7000p_spur_protect()
1258 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff); dib7000p_spur_protect()
1259 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); dib7000p_spur_protect()
1261 dib7000p_write_word(state, 143, 0); dib7000p_spur_protect()
1267 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_tune() local
1271 dib7000p_set_channel(state, ch, 0); dib7000p_tune()
1276 dib7000p_write_word(state, 770, 0x4000); dib7000p_tune()
1277 dib7000p_write_word(state, 770, 0x0000); dib7000p_tune()
1282 if (state->sfn_workaround_active) { dib7000p_tune()
1285 dib7000p_write_word(state, 166, 0x4000); dib7000p_tune()
1287 dib7000p_write_word(state, 166, 0x0000); dib7000p_tune()
1289 dib7000p_write_word(state, 29, tmp); dib7000p_tune()
1292 if (state->timf == 0) dib7000p_tune()
1311 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */ dib7000p_tune()
1327 dib7000p_write_word(state, 32, tmp); dib7000p_tune()
1343 dib7000p_write_word(state, 33, tmp); dib7000p_tune()
1345 tmp = dib7000p_read_word(state, 509); dib7000p_tune()
1348 tmp = dib7000p_read_word(state, 771); dib7000p_tune()
1349 dib7000p_write_word(state, 771, tmp | (1 << 1)); dib7000p_tune()
1350 dib7000p_write_word(state, 771, tmp); dib7000p_tune()
1352 tmp = dib7000p_read_word(state, 509); dib7000p_tune()
1356 dib7000p_update_timf(state); dib7000p_tune()
1358 tmp = dib7000p_read_word(state, 26); dib7000p_tune()
1359 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12)); dib7000p_tune()
1362 if (state->cfg.spur_protect) dib7000p_tune()
1363 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); dib7000p_tune()
1365 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); dib7000p_tune()
1374 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_wakeup() local
1375 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); dib7000p_wakeup()
1376 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); dib7000p_wakeup()
1377 if (state->version == SOC7090) dib7000p_wakeup()
1378 dib7000p_sad_calib(state); dib7000p_wakeup()
1384 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_sleep() local
1385 if (state->version == SOC7090) dib7000p_sleep()
1386 return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); dib7000p_sleep()
1387 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); dib7000p_sleep()
1411 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_get_frontend() local
1412 u16 tps = dib7000p_read_word(state, 463); dib7000p_get_frontend()
1416 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth); dib7000p_get_frontend()
1499 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */ dib7000p_get_frontend()
1507 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_set_frontend() local
1510 if (state->version == SOC7090) dib7000p_set_frontend()
1513 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z); dib7000p_set_frontend()
1516 state->sfn_workaround_active = buggy_sfn_workaround; dib7000p_set_frontend()
1522 state->agc_state = 0; dib7000p_set_frontend()
1549 if (state->version == SOC7090) { dib7000p_set_frontend()
1550 dib7090_set_output_mode(fe, state->cfg.output_mode); dib7000p_set_frontend()
1551 if (state->cfg.enMpegOutput == 0) { dib7000p_set_frontend()
1552 dib7090_setDibTxMux(state, MPEG_ON_DIBTX); dib7000p_set_frontend()
1553 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS); dib7000p_set_frontend()
1556 dib7000p_set_output_mode(state, state->cfg.output_mode); dib7000p_set_frontend()
1565 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_read_status() local
1566 u16 lock = dib7000p_read_word(state, 509); dib7000p_read_status()
1588 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_read_ber() local
1589 *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501); dib7000p_read_ber()
1595 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_read_unc_blocks() local
1596 *unc = dib7000p_read_word(state, 506); dib7000p_read_unc_blocks()
1602 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_read_signal_strength() local
1603 u16 val = dib7000p_read_word(state, 394); dib7000p_read_signal_strength()
1610 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_get_snr() local
1615 val = dib7000p_read_word(state, 479); dib7000p_get_snr()
1618 val = dib7000p_read_word(state, 480); dib7000p_get_snr()
1653 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_reset_stats() local
1681 state->old_ucb = ucb; dib7000p_reset_stats()
1682 state->ber_jiffies_stats = 0; dib7000p_reset_stats()
1683 state->per_jiffies_stats = 0; dib7000p_reset_stats()
1882 struct dib7000p_state *state = demod->demodulator_priv; dib7000p_get_stats() local
1914 if (time_after(jiffies, state->per_jiffies_stats)) { dib7000p_get_stats()
1915 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000); dib7000p_get_stats()
1928 ucb = val - state->old_ucb; dib7000p_get_stats()
1929 if (val < state->old_ucb) dib7000p_get_stats()
1950 if (time_after(jiffies, state->ber_jiffies_stats)) { dib7000p_get_stats()
1952 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000); dib7000p_get_stats()
2050 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_pid_filter_ctrl() local
2051 u16 val = dib7000p_read_word(state, 235) & 0xffef; dib7000p_pid_filter_ctrl()
2054 return dib7000p_write_word(state, 235, val); dib7000p_pid_filter_ctrl()
2059 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_pid_filter() local
2061 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0); dib7000p_pid_filter()
2130 struct dib7000p_state *state = fe->demodulator_priv; dib7000p_get_adc_power() local
2136 buf[0] = dib7000p_read_word(state, 0x184); dib7000p_get_adc_power()
2137 buf[1] = dib7000p_read_word(state, 0x185); dib7000p_get_adc_power()
2179 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); w7090p_tuner_write_serpar() local
2185 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1; w7090p_tuner_write_serpar()
2190 dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); w7090p_tuner_write_serpar()
2191 dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); w7090p_tuner_write_serpar()
2198 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); w7090p_tuner_read_serpar() local
2205 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1; w7090p_tuner_read_serpar()
2210 dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f)); w7090p_tuner_read_serpar()
2214 n_empty = dib7000p_read_word(state, 1984) & 0x1; w7090p_tuner_read_serpar()
2219 read_word = dib7000p_read_word(state, 1987); w7090p_tuner_read_serpar()
2241 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); dib7090p_rw_on_apb() local
2245 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2]))); dib7090p_rw_on_apb()
2247 word = dib7000p_read_word(state, apb_address); dib7090p_rw_on_apb()
2257 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap); dib7090_tuner_xfer() local
2347 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3); dib7090_tuner_xfer()
2348 word = dib7000p_read_word(state, 384 + i); dib7090_tuner_xfer()
2356 word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12); dib7090_tuner_xfer()
2357 dib7000p_write_word(state, 72, word); /* Set the proper input */ dib7090_tuner_xfer()
2386 static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive) dib7090_host_bus_drive() argument
2391 reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); dib7090_host_bus_drive()
2393 dib7000p_write_word(state, 1798, reg); dib7090_host_bus_drive()
2396 reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); dib7090_host_bus_drive()
2398 dib7000p_write_word(state, 1799, reg); dib7090_host_bus_drive()
2401 reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); dib7090_host_bus_drive()
2403 dib7000p_write_word(state, 1800, reg); dib7090_host_bus_drive()
2406 reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); dib7090_host_bus_drive()
2408 dib7000p_write_word(state, 1801, reg); dib7090_host_bus_drive()
2411 reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); dib7090_host_bus_drive()
2413 dib7000p_write_word(state, 1802, reg); dib7090_host_bus_drive()
2436 static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize) dib7090_cfg_DibTx() argument
2440 dib7000p_write_word(state, 1615, 1); dib7090_cfg_DibTx()
2441 dib7000p_write_word(state, 1603, P_Kin); dib7090_cfg_DibTx()
2442 dib7000p_write_word(state, 1605, P_Kout); dib7090_cfg_DibTx()
2443 dib7000p_write_word(state, 1606, insertExtSynchro); dib7090_cfg_DibTx()
2444 dib7000p_write_word(state, 1608, synchroMode); dib7090_cfg_DibTx()
2445 dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff); dib7090_cfg_DibTx()
2446 dib7000p_write_word(state, 1610, syncWord & 0xffff); dib7090_cfg_DibTx()
2447 dib7000p_write_word(state, 1612, syncSize); dib7090_cfg_DibTx()
2448 dib7000p_write_word(state, 1615, 0); dib7090_cfg_DibTx()
2453 static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize, dib7090_cfg_DibRx() argument
2461 dib7000p_write_word(state, 1542, syncFreq); dib7090_cfg_DibRx()
2463 dib7000p_write_word(state, 1554, 1); dib7090_cfg_DibRx()
2464 dib7000p_write_word(state, 1536, P_Kin); dib7090_cfg_DibRx()
2465 dib7000p_write_word(state, 1537, P_Kout); dib7090_cfg_DibRx()
2466 dib7000p_write_word(state, 1539, synchroMode); dib7090_cfg_DibRx()
2467 dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff); dib7090_cfg_DibRx()
2468 dib7000p_write_word(state, 1541, syncWord & 0xffff); dib7090_cfg_DibRx()
2469 dib7000p_write_word(state, 1543, syncSize); dib7090_cfg_DibRx()
2470 dib7000p_write_word(state, 1544, dataOutRate); dib7090_cfg_DibRx()
2471 dib7000p_write_word(state, 1554, 0); dib7090_cfg_DibRx()
2476 static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff) dib7090_enMpegMux() argument
2478 u16 reg_1287 = dib7000p_read_word(state, 1287); dib7090_enMpegMux()
2489 dib7000p_write_word(state, 1287, reg_1287); dib7090_enMpegMux()
2492 static void dib7090_configMpegMux(struct dib7000p_state *state, dib7090_configMpegMux() argument
2497 dib7090_enMpegMux(state, 0); dib7090_configMpegMux()
2500 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1)) dib7090_configMpegMux()
2503 dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2) dib7090_configMpegMux()
2507 dib7090_enMpegMux(state, 1); dib7090_configMpegMux()
2510 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode) dib7090_setDibTxMux() argument
2512 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7); dib7090_setDibTxMux()
2517 dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); dib7090_setDibTxMux()
2522 dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); dib7090_setDibTxMux()
2527 dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); dib7090_setDibTxMux()
2533 dib7000p_write_word(state, 1288, reg_1288); dib7090_setDibTxMux()
2536 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode) dib7090_setHostBusMux() argument
2538 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4); dib7090_setHostBusMux()
2543 dib7090_enMpegMux(state, 0); dib7090_setHostBusMux()
2548 dib7090_enMpegMux(state, 0); dib7090_setHostBusMux()
2558 dib7000p_write_word(state, 1288, reg_1288); dib7090_setHostBusMux()
2563 struct dib7000p_state *state = fe->demodulator_priv; dib7090_set_diversity_in() local
2569 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); dib7090_set_diversity_in()
2573 reg_1287 = dib7000p_read_word(state, 1287); dib7090_set_diversity_in()
2578 dib7000p_write_word(state, 1287, reg_1287); dib7090_set_diversity_in()
2580 state->input_mode_mpeg = 1; dib7090_set_diversity_in()
2585 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); dib7090_set_diversity_in()
2586 state->input_mode_mpeg = 0; dib7090_set_diversity_in()
2590 dib7000p_set_diversity_in(&state->demod, onoff); dib7090_set_diversity_in()
2596 struct dib7000p_state *state = fe->demodulator_priv; dib7090_set_output_mode() local
2602 dib7090_host_bus_drive(state, 1); dib7090_set_output_mode()
2605 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); dib7090_set_output_mode()
2606 outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1)); dib7090_set_output_mode()
2616 dib7090_configMpegMux(state, 3, 1, 1); dib7090_set_output_mode()
2617 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS); dib7090_set_output_mode()
2620 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); dib7090_set_output_mode()
2628 dib7090_configMpegMux(state, 2, 0, 0); dib7090_set_output_mode()
2629 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS); dib7090_set_output_mode()
2632 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); dib7090_set_output_mode()
2639 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); dib7090_set_output_mode()
2645 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS); dib7090_set_output_mode()
2653 dib7090_setDibTxMux(state, DIV_ON_DIBTX); dib7090_set_output_mode()
2654 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS); dib7090_set_output_mode()
2659 dib7090_setDibTxMux(state, ADC_ON_DIBTX); dib7090_set_output_mode()
2660 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS); dib7090_set_output_mode()
2666 if (state->cfg.output_mpeg2_in_188_bytes) dib7090_set_output_mode()
2669 ret |= dib7000p_write_word(state, 235, smo_mode); dib7090_set_output_mode()
2670 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ dib7090_set_output_mode()
2671 ret |= dib7000p_write_word(state, 1286, outreg); dib7090_set_output_mode()
2678 struct dib7000p_state *state = fe->demodulator_priv; dib7090_tuner_sleep() local
2683 en_cur_state = dib7000p_read_word(state, 1922); dib7090_tuner_sleep()
2686 state->tuner_enable = en_cur_state; dib7090_tuner_sleep()
2691 if (state->tuner_enable != 0) dib7090_tuner_sleep()
2692 en_cur_state = state->tuner_enable; dib7090_tuner_sleep()
2695 dib7000p_write_word(state, 1922, en_cur_state); dib7090_tuner_sleep()
2707 struct dib7000p_state *state = fe->demodulator_priv; dib7090_slave_reset() local
2710 reg = dib7000p_read_word(state, 1794); dib7090_slave_reset()
2711 dib7000p_write_word(state, 1794, reg | (4 << 12)); dib7090_slave_reset()
2713 dib7000p_write_word(state, 1032, 0xffff); dib7090_slave_reset()
H A Dau8522_decoder.c187 static void setup_vbi(struct au8522_state *state, int aud_input) setup_vbi() argument
192 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00); setup_vbi()
193 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00); setup_vbi()
194 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00); setup_vbi()
195 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00); setup_vbi()
196 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00); setup_vbi()
197 au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00); setup_vbi()
198 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00); setup_vbi()
199 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00); setup_vbi()
200 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00); setup_vbi()
201 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H, setup_vbi()
203 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H, setup_vbi()
205 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H, setup_vbi()
210 au8522_writereg(state, i, 0x40); setup_vbi()
214 au8522_writereg(state, 0x44, 0x60); setup_vbi()
218 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, setup_vbi()
223 static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo) setup_decoder_defaults() argument
229 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07); setup_decoder_defaults()
230 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed); setup_decoder_defaults()
231 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79); setup_decoder_defaults()
232 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80); setup_decoder_defaults()
233 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80); setup_decoder_defaults()
234 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00); setup_decoder_defaults()
235 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00); setup_decoder_defaults()
238 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00); setup_decoder_defaults()
241 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04); setup_decoder_defaults()
243 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00); setup_decoder_defaults()
245 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H, setup_decoder_defaults()
247 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H, setup_decoder_defaults()
249 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H, setup_decoder_defaults()
252 if (state->std == V4L2_STD_PAL_M) { setup_decoder_defaults()
253 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H, setup_decoder_defaults()
257 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H, setup_decoder_defaults()
261 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H, setup_decoder_defaults()
265 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H, setup_decoder_defaults()
268 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H, setup_decoder_defaults()
270 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H, setup_decoder_defaults()
272 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H, setup_decoder_defaults()
274 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H, setup_decoder_defaults()
276 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H, setup_decoder_defaults()
278 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H, setup_decoder_defaults()
280 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H, setup_decoder_defaults()
282 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH, setup_decoder_defaults()
284 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH, setup_decoder_defaults()
287 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, setup_decoder_defaults()
289 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, setup_decoder_defaults()
292 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, setup_decoder_defaults()
294 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, setup_decoder_defaults()
297 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH, setup_decoder_defaults()
299 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH, setup_decoder_defaults()
301 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H, setup_decoder_defaults()
303 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS); setup_decoder_defaults()
304 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS); setup_decoder_defaults()
305 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H, setup_decoder_defaults()
307 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS); setup_decoder_defaults()
308 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS); setup_decoder_defaults()
309 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H, setup_decoder_defaults()
311 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H, setup_decoder_defaults()
313 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H, setup_decoder_defaults()
315 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH, setup_decoder_defaults()
317 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH, setup_decoder_defaults()
319 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H, setup_decoder_defaults()
321 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H, setup_decoder_defaults()
323 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS); setup_decoder_defaults()
325 setup_vbi(state, 0); setup_decoder_defaults()
338 au8522_writereg(state, filter_coef[i].reg_name, setup_decoder_defaults()
344 au8522_writereg(state, AU8522_REG42EH, 0x87); setup_decoder_defaults()
345 au8522_writereg(state, AU8522_REG42FH, 0xa2); setup_decoder_defaults()
346 au8522_writereg(state, AU8522_REG430H, 0xbf); setup_decoder_defaults()
347 au8522_writereg(state, AU8522_REG431H, 0xcb); setup_decoder_defaults()
348 au8522_writereg(state, AU8522_REG432H, 0xa1); setup_decoder_defaults()
349 au8522_writereg(state, AU8522_REG433H, 0x41); setup_decoder_defaults()
350 au8522_writereg(state, AU8522_REG434H, 0x88); setup_decoder_defaults()
351 au8522_writereg(state, AU8522_REG435H, 0xc2); setup_decoder_defaults()
352 au8522_writereg(state, AU8522_REG436H, 0x3c); setup_decoder_defaults()
355 static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode) au8522_setup_cvbs_mode() argument
358 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, au8522_setup_cvbs_mode()
362 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); au8522_setup_cvbs_mode()
365 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00); au8522_setup_cvbs_mode()
367 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode); au8522_setup_cvbs_mode()
369 setup_decoder_defaults(state, false); au8522_setup_cvbs_mode()
371 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, au8522_setup_cvbs_mode()
375 static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state, au8522_setup_cvbs_tuner_mode() argument
379 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, au8522_setup_cvbs_tuner_mode()
384 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); au8522_setup_cvbs_tuner_mode()
387 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e); au8522_setup_cvbs_tuner_mode()
390 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10); au8522_setup_cvbs_tuner_mode()
393 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode); au8522_setup_cvbs_tuner_mode()
395 setup_decoder_defaults(state, false); au8522_setup_cvbs_tuner_mode()
397 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, au8522_setup_cvbs_tuner_mode()
401 static void au8522_setup_svideo_mode(struct au8522_state *state, au8522_setup_svideo_mode() argument
404 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, au8522_setup_svideo_mode()
408 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode); au8522_setup_svideo_mode()
411 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); au8522_setup_svideo_mode()
414 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00); au8522_setup_svideo_mode()
416 setup_decoder_defaults(state, true); au8522_setup_svideo_mode()
418 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, au8522_setup_svideo_mode()
424 static void disable_audio_input(struct au8522_state *state) disable_audio_input() argument
426 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00); disable_audio_input()
427 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00); disable_audio_input()
428 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00); disable_audio_input()
430 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04); disable_audio_input()
431 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02); disable_audio_input()
433 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, disable_audio_input()
438 static void set_audio_input(struct au8522_state *state) set_audio_input() argument
440 int aud_input = state->aud_input; set_audio_input()
447 disable_audio_input(state); set_audio_input()
460 au8522_writereg(state, lpfilter_coef[i].reg_name, set_audio_input()
465 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00); set_audio_input()
466 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00); set_audio_input()
467 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00); set_audio_input()
468 au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80); set_audio_input()
469 au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84); set_audio_input()
471 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00); set_audio_input()
473 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, set_audio_input()
476 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F); set_audio_input()
477 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F); set_audio_input()
478 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff); set_audio_input()
480 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F); set_audio_input()
481 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F); set_audio_input()
482 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO); set_audio_input()
483 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82); set_audio_input()
485 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09); set_audio_input()
486 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03); set_audio_input()
487 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2); set_audio_input()
494 struct au8522_state *state = au8522_s_ctrl() local
499 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, au8522_s_ctrl()
503 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, au8522_s_ctrl()
507 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, au8522_s_ctrl()
509 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, au8522_s_ctrl()
513 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, au8522_s_ctrl()
515 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, au8522_s_ctrl()
531 struct au8522_state *state = to_state(sd); au8522_g_register() local
533 reg->val = au8522_readreg(state, reg->reg & 0xffff); au8522_g_register()
540 struct au8522_state *state = to_state(sd); au8522_s_register() local
542 au8522_writereg(state, reg->reg, reg->val & 0xff); au8522_s_register()
547 static void au8522_video_set(struct au8522_state *state) au8522_video_set() argument
551 au8522_writereg(state, 0xa4, 1 << 5); au8522_video_set()
553 switch (state->vid_input) { au8522_video_set()
556 au8522_setup_cvbs_mode(state, input_mode); au8522_video_set()
560 au8522_setup_cvbs_mode(state, input_mode); au8522_video_set()
564 au8522_setup_cvbs_mode(state, input_mode); au8522_video_set()
568 au8522_setup_cvbs_mode(state, input_mode); au8522_video_set()
572 au8522_setup_svideo_mode(state, input_mode); au8522_video_set()
576 au8522_setup_svideo_mode(state, input_mode); au8522_video_set()
581 au8522_setup_cvbs_tuner_mode(state, input_mode); au8522_video_set()
588 struct au8522_state *state = to_state(sd); au8522_s_stream() local
592 * Clear out any state associated with the digital side of the au8522_s_stream()
596 state->current_frequency = 0; au8522_s_stream()
598 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, au8522_s_stream()
602 au8522_video_set(state); au8522_s_stream()
603 set_audio_input(state); au8522_s_stream()
605 state->operational_mode = AU8522_ANALOG_MODE; au8522_s_stream()
609 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, au8522_s_stream()
611 state->operational_mode = AU8522_SUSPEND_MODE; au8522_s_stream()
619 struct au8522_state *state = to_state(sd); au8522_s_video_routing() local
625 state->vid_input = input; au8522_s_video_routing()
632 if (state->operational_mode == AU8522_ANALOG_MODE) au8522_s_video_routing()
633 au8522_video_set(state); au8522_s_video_routing()
640 struct au8522_state *state = to_state(sd); au8522_s_std() local
645 state->std = std; au8522_s_std()
647 if (state->operational_mode == AU8522_ANALOG_MODE) au8522_s_std()
648 au8522_video_set(state); au8522_s_std()
656 struct au8522_state *state = to_state(sd); au8522_s_audio_routing() local
658 state->aud_input = input; au8522_s_audio_routing()
660 if (state->operational_mode == AU8522_ANALOG_MODE) au8522_s_audio_routing()
661 set_audio_input(state); au8522_s_audio_routing()
669 struct au8522_state *state = to_state(sd); au8522_g_tuner() local
673 lock_status = au8522_readreg(state, 0x00); au8522_g_tuner()
729 struct au8522_state *state; au8522_probe() local
741 /* allocate memory for the internal state */ au8522_probe()
742 instance = au8522_get_state(&state, client->adapter, client->addr); au8522_probe()
760 kfree(state); au8522_probe()
765 state->config = demod_config; au8522_probe()
766 state->i2c = client->adapter; au8522_probe()
768 sd = &state->sd; au8522_probe()
771 hdl = &state->hdl; au8522_probe()
788 kfree(state); au8522_probe()
792 state->c = client; au8522_probe()
793 state->std = V4L2_STD_NTSC_M; au8522_probe()
794 state->vid_input = AU8522_COMPOSITE_CH1; au8522_probe()
795 state->aud_input = AU8522_AUDIO_NONE; au8522_probe()
796 state->id = 8522; au8522_probe()
797 state->rev = 0; au8522_probe()
800 au8522_writereg(state, 0x106, 1); au8522_probe()
H A Dtda8083.c61 static int tda8083_writereg (struct tda8083_state* state, u8 reg, u8 data) tda8083_writereg() argument
65 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; tda8083_writereg()
67 ret = i2c_transfer(state->i2c, &msg, 1); tda8083_writereg()
76 static int tda8083_readregs (struct tda8083_state* state, u8 reg1, u8 *b, u8 len) tda8083_readregs() argument
79 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = &reg1, .len = 1 }, tda8083_readregs()
80 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = len } }; tda8083_readregs()
82 ret = i2c_transfer(state->i2c, msg, 2); tda8083_readregs()
91 static inline u8 tda8083_readreg (struct tda8083_state* state, u8 reg) tda8083_readreg() argument
95 tda8083_readregs (state, reg, &val, 1); tda8083_readreg()
100 static int tda8083_set_inversion (struct tda8083_state* state, fe_spectral_inversion_t inversion) tda8083_set_inversion() argument
109 static int tda8083_set_fec (struct tda8083_state* state, fe_code_rate_t fec) tda8083_set_fec() argument
112 return tda8083_writereg (state, 0x07, 0xff); tda8083_set_fec()
115 return tda8083_writereg (state, 0x07, 1 << (FEC_8_9 - fec)); tda8083_set_fec()
120 static fe_code_rate_t tda8083_get_fec (struct tda8083_state* state) tda8083_get_fec() argument
126 index = tda8083_readreg(state, 0x0e) & 0x07; tda8083_get_fec()
131 static int tda8083_set_symbolrate (struct tda8083_state* state, u32 srate) tda8083_set_symbolrate() argument
159 tda8083_writereg (state, 0x05, filter); tda8083_set_symbolrate()
160 tda8083_writereg (state, 0x02, (ratio >> 16) & 0xff); tda8083_set_symbolrate()
161 tda8083_writereg (state, 0x03, (ratio >> 8) & 0xff); tda8083_set_symbolrate()
162 tda8083_writereg (state, 0x04, (ratio ) & 0xff); tda8083_set_symbolrate()
164 tda8083_writereg (state, 0x00, 0x3c); tda8083_set_symbolrate()
165 tda8083_writereg (state, 0x00, 0x04); tda8083_set_symbolrate()
170 static void tda8083_wait_diseqc_fifo (struct tda8083_state* state, int timeout) tda8083_wait_diseqc_fifo() argument
175 !(tda8083_readreg(state, 0x02) & 0x80)) tda8083_wait_diseqc_fifo()
181 static int tda8083_set_tone (struct tda8083_state* state, fe_sec_tone_mode_t tone) tda8083_set_tone() argument
183 tda8083_writereg (state, 0x26, 0xf1); tda8083_set_tone()
187 return tda8083_writereg (state, 0x29, 0x00); tda8083_set_tone()
189 return tda8083_writereg (state, 0x29, 0x80); tda8083_set_tone()
195 static int tda8083_set_voltage (struct tda8083_state* state, fe_sec_voltage_t voltage) tda8083_set_voltage() argument
199 return tda8083_writereg (state, 0x20, 0x00); tda8083_set_voltage()
201 return tda8083_writereg (state, 0x20, 0x11); tda8083_set_voltage()
207 static int tda8083_send_diseqc_burst (struct tda8083_state* state, fe_sec_mini_cmd_t burst) tda8083_send_diseqc_burst() argument
211 tda8083_writereg (state, 0x29, (5 << 2)); /* send burst A */ tda8083_send_diseqc_burst()
214 tda8083_writereg (state, 0x29, (7 << 2)); /* send B */ tda8083_send_diseqc_burst()
220 tda8083_wait_diseqc_fifo (state, 100); tda8083_send_diseqc_burst()
228 struct tda8083_state* state = fe->demodulator_priv; tda8083_send_diseqc_msg() local
231 tda8083_writereg (state, 0x29, (m->msg_len - 3) | (1 << 2)); /* enable */ tda8083_send_diseqc_msg()
234 tda8083_writereg (state, 0x23 + i, m->msg[i]); tda8083_send_diseqc_msg()
236 tda8083_writereg (state, 0x29, (m->msg_len - 3) | (3 << 2)); /* send!! */ tda8083_send_diseqc_msg()
238 tda8083_wait_diseqc_fifo (state, 100); tda8083_send_diseqc_msg()
245 struct tda8083_state* state = fe->demodulator_priv; tda8083_read_status() local
247 u8 signal = ~tda8083_readreg (state, 0x01); tda8083_read_status()
248 u8 sync = tda8083_readreg (state, 0x02); tda8083_read_status()
275 struct tda8083_state* state = fe->demodulator_priv; tda8083_read_ber() local
279 if ((ret = tda8083_readregs(state, 0x0b, buf, sizeof(buf)))) tda8083_read_ber()
289 struct tda8083_state* state = fe->demodulator_priv; tda8083_read_signal_strength() local
291 u8 signal = ~tda8083_readreg (state, 0x01); tda8083_read_signal_strength()
299 struct tda8083_state* state = fe->demodulator_priv; tda8083_read_snr() local
301 u8 _snr = tda8083_readreg (state, 0x08); tda8083_read_snr()
309 struct tda8083_state* state = fe->demodulator_priv; tda8083_read_ucblocks() local
311 *ucblocks = tda8083_readreg(state, 0x0f); tda8083_read_ucblocks()
321 struct tda8083_state* state = fe->demodulator_priv; tda8083_set_frontend() local
328 tda8083_set_inversion (state, p->inversion); tda8083_set_frontend()
329 tda8083_set_fec(state, p->fec_inner); tda8083_set_frontend()
330 tda8083_set_symbolrate(state, p->symbol_rate); tda8083_set_frontend()
332 tda8083_writereg (state, 0x00, 0x3c); tda8083_set_frontend()
333 tda8083_writereg (state, 0x00, 0x04); tda8083_set_frontend()
341 struct tda8083_state* state = fe->demodulator_priv; tda8083_get_frontend() local
345 p->inversion = (tda8083_readreg (state, 0x0e) & 0x80) ? tda8083_get_frontend()
347 p->fec_inner = tda8083_get_fec(state); tda8083_get_frontend()
348 /*p->symbol_rate = tda8083_get_symbolrate (state);*/ tda8083_get_frontend()
355 struct tda8083_state* state = fe->demodulator_priv; tda8083_sleep() local
357 tda8083_writereg (state, 0x00, 0x02); tda8083_sleep()
363 struct tda8083_state* state = fe->demodulator_priv; tda8083_init() local
367 tda8083_writereg (state, i, tda8083_init_tab[i]); tda8083_init()
369 tda8083_writereg (state, 0x00, 0x3c); tda8083_init()
370 tda8083_writereg (state, 0x00, 0x04); tda8083_init()
377 struct tda8083_state* state = fe->demodulator_priv; tda8083_diseqc_send_burst() local
379 tda8083_send_diseqc_burst (state, burst); tda8083_diseqc_send_burst()
380 tda8083_writereg (state, 0x00, 0x3c); tda8083_diseqc_send_burst()
381 tda8083_writereg (state, 0x00, 0x04); tda8083_diseqc_send_burst()
388 struct tda8083_state* state = fe->demodulator_priv; tda8083_diseqc_set_tone() local
390 tda8083_set_tone (state, tone); tda8083_diseqc_set_tone()
391 tda8083_writereg (state, 0x00, 0x3c); tda8083_diseqc_set_tone()
392 tda8083_writereg (state, 0x00, 0x04); tda8083_diseqc_set_tone()
399 struct tda8083_state* state = fe->demodulator_priv; tda8083_diseqc_set_voltage() local
401 tda8083_set_voltage (state, voltage); tda8083_diseqc_set_voltage()
402 tda8083_writereg (state, 0x00, 0x3c); tda8083_diseqc_set_voltage()
403 tda8083_writereg (state, 0x00, 0x04); tda8083_diseqc_set_voltage()
410 struct tda8083_state* state = fe->demodulator_priv; tda8083_release() local
411 kfree(state); tda8083_release()
419 struct tda8083_state* state = NULL; tda8083_attach() local
421 /* allocate memory for the internal state */ tda8083_attach()
422 state = kzalloc(sizeof(struct tda8083_state), GFP_KERNEL); tda8083_attach()
423 if (state == NULL) goto error; tda8083_attach()
425 /* setup the state */ tda8083_attach()
426 state->config = config; tda8083_attach()
427 state->i2c = i2c; tda8083_attach()
430 if ((tda8083_readreg(state, 0x00)) != 0x05) goto error; tda8083_attach()
433 memcpy(&state->frontend.ops, &tda8083_ops, sizeof(struct dvb_frontend_ops)); tda8083_attach()
434 state->frontend.demodulator_priv = state; tda8083_attach()
435 return &state->frontend; tda8083_attach()
438 kfree(state); tda8083_attach()
H A Dves1820.c59 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data) ves1820_writereg() argument
62 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 }; ves1820_writereg()
65 ret = i2c_transfer(state->i2c, &msg, 1); ves1820_writereg()
74 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg) ves1820_readreg() argument
79 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2}, ves1820_readreg()
80 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1} ves1820_readreg()
84 ret = i2c_transfer(state->i2c, msg, 2); ves1820_readreg()
93 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion) ves1820_setup_reg0() argument
95 reg0 |= state->reg0 & 0x62; ves1820_setup_reg0()
98 if (!state->config->invert) reg0 |= 0x20; ves1820_setup_reg0()
101 if (!state->config->invert) reg0 &= ~0x20; ves1820_setup_reg0()
105 ves1820_writereg(state, 0x00, reg0 & 0xfe); ves1820_setup_reg0()
106 ves1820_writereg(state, 0x00, reg0 | 0x01); ves1820_setup_reg0()
108 state->reg0 = reg0; ves1820_setup_reg0()
113 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate) ves1820_set_symbolrate() argument
125 if (symbolrate > state->config->xin / 2) ves1820_set_symbolrate()
126 symbolrate = state->config->xin / 2; ves1820_set_symbolrate()
131 if (symbolrate < state->config->xin / 16) ves1820_set_symbolrate()
133 if (symbolrate < state->config->xin / 32) ves1820_set_symbolrate()
135 if (symbolrate < state->config->xin / 64) ves1820_set_symbolrate()
139 fpxin = state->config->xin * 10; ves1820_set_symbolrate()
162 fin = state->config->xin >> 4; ves1820_set_symbolrate()
171 BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2; ves1820_set_symbolrate()
180 ves1820_writereg(state, 0x03, NDEC); ves1820_set_symbolrate()
181 ves1820_writereg(state, 0x0a, BDR & 0xff); ves1820_set_symbolrate()
182 ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff); ves1820_set_symbolrate()
183 ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f); ves1820_set_symbolrate()
185 ves1820_writereg(state, 0x0d, BDRI); ves1820_set_symbolrate()
186 ves1820_writereg(state, 0x0e, SFIL); ves1820_set_symbolrate()
193 struct ves1820_state* state = fe->demodulator_priv; ves1820_init() local
196 ves1820_writereg(state, 0, 0); ves1820_init()
199 ves1820_writereg(state, i, ves1820_inittab[i]); ves1820_init()
200 if (state->config->selagc) ves1820_init()
201 ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08); ves1820_init()
203 ves1820_writereg(state, 0x34, state->pwm); ves1820_init()
211 struct ves1820_state* state = fe->demodulator_priv; ves1820_set_parameters() local
227 ves1820_set_symbolrate(state, p->symbol_rate); ves1820_set_parameters()
228 ves1820_writereg(state, 0x34, state->pwm); ves1820_set_parameters()
230 ves1820_writereg(state, 0x01, reg0x01[real_qam]); ves1820_set_parameters()
231 ves1820_writereg(state, 0x05, reg0x05[real_qam]); ves1820_set_parameters()
232 ves1820_writereg(state, 0x08, reg0x08[real_qam]); ves1820_set_parameters()
233 ves1820_writereg(state, 0x09, reg0x09[real_qam]); ves1820_set_parameters()
235 ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion); ves1820_set_parameters()
236 ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0)); ves1820_set_parameters()
242 struct ves1820_state* state = fe->demodulator_priv; ves1820_read_status() local
246 sync = ves1820_readreg(state, 0x11); ves1820_read_status()
268 struct ves1820_state* state = fe->demodulator_priv; ves1820_read_ber() local
270 u32 _ber = ves1820_readreg(state, 0x14) | ves1820_read_ber()
271 (ves1820_readreg(state, 0x15) << 8) | ves1820_read_ber()
272 ((ves1820_readreg(state, 0x16) & 0x0f) << 16); ves1820_read_ber()
280 struct ves1820_state* state = fe->demodulator_priv; ves1820_read_signal_strength() local
282 u8 gain = ves1820_readreg(state, 0x17); ves1820_read_signal_strength()
290 struct ves1820_state* state = fe->demodulator_priv; ves1820_read_snr() local
292 u8 quality = ~ves1820_readreg(state, 0x18); ves1820_read_snr()
300 struct ves1820_state* state = fe->demodulator_priv; ves1820_read_ucblocks() local
302 *ucblocks = ves1820_readreg(state, 0x13) & 0x7f; ves1820_read_ucblocks()
307 ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf); ves1820_read_ucblocks()
308 ves1820_writereg(state, 0x10, ves1820_inittab[0x10]); ves1820_read_ucblocks()
316 struct ves1820_state* state = fe->demodulator_priv; ves1820_get_frontend() local
320 sync = ves1820_readreg(state, 0x11); ves1820_get_frontend()
321 afc = ves1820_readreg(state, 0x19); ves1820_get_frontend()
328 if (!state->config->invert) { ves1820_get_frontend()
329 p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF; ves1820_get_frontend()
331 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF; ves1820_get_frontend()
334 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16; ves1820_get_frontend()
347 struct ves1820_state* state = fe->demodulator_priv; ves1820_sleep() local
349 ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */ ves1820_sleep()
350 ves1820_writereg(state, 0x00, 0x80); /* standby */ ves1820_sleep()
366 struct ves1820_state* state = fe->demodulator_priv; ves1820_release() local
367 kfree(state); ves1820_release()
376 struct ves1820_state* state = NULL; ves1820_attach() local
378 /* allocate memory for the internal state */ ves1820_attach()
379 state = kzalloc(sizeof(struct ves1820_state), GFP_KERNEL); ves1820_attach()
380 if (state == NULL) ves1820_attach()
383 /* setup the state */ ves1820_attach()
384 state->reg0 = ves1820_inittab[0]; ves1820_attach()
385 state->config = config; ves1820_attach()
386 state->i2c = i2c; ves1820_attach()
387 state->pwm = pwm; ves1820_attach()
390 if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70) ves1820_attach()
394 printk("ves1820: pwm=0x%02x\n", state->pwm); ves1820_attach()
397 memcpy(&state->frontend.ops, &ves1820_ops, sizeof(struct dvb_frontend_ops)); ves1820_attach()
398 state->frontend.ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */ ves1820_attach()
399 state->frontend.ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */ ves1820_attach()
400 state->frontend.demodulator_priv = state; ves1820_attach()
402 return &state->frontend; ves1820_attach()
405 kfree(state); ves1820_attach()
H A Dtda1004x.c128 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) tda1004x_write_byteI() argument
136 msg.addr = state->config->demod_address; tda1004x_write_byteI()
137 ret = i2c_transfer(state->i2c, &msg, 1); tda1004x_write_byteI()
148 static int tda1004x_read_byte(struct tda1004x_state *state, int reg) tda1004x_read_byte() argument
158 msg[0].addr = state->config->demod_address; tda1004x_read_byte()
159 msg[1].addr = state->config->demod_address; tda1004x_read_byte()
160 ret = i2c_transfer(state->i2c, msg, 2); tda1004x_read_byte()
173 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) tda1004x_write_mask() argument
180 val = tda1004x_read_byte(state, reg); tda1004x_write_mask()
189 return tda1004x_write_byteI(state, reg, val); tda1004x_write_mask()
192 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) tda1004x_write_buf() argument
201 result = tda1004x_write_byteI(state, reg + i, buf[i]); tda1004x_write_buf()
209 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) tda1004x_enable_tuner_i2c() argument
214 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); tda1004x_enable_tuner_i2c()
219 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) tda1004x_disable_tuner_i2c() argument
223 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); tda1004x_disable_tuner_i2c()
226 static int tda10045h_set_bandwidth(struct tda1004x_state *state, tda10045h_set_bandwidth() argument
235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); tda10045h_set_bandwidth()
239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); tda10045h_set_bandwidth()
243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); tda10045h_set_bandwidth()
250 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); tda10045h_set_bandwidth()
255 static int tda10046h_set_bandwidth(struct tda1004x_state *state, tda10046h_set_bandwidth() argument
267 if ((state->config->if_freq == TDA10046_FREQ_045) || tda10046h_set_bandwidth()
268 (state->config->if_freq == TDA10046_FREQ_052)) tda10046h_set_bandwidth()
275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, tda10046h_set_bandwidth()
278 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M, tda10046h_set_bandwidth()
280 if (state->config->if_freq == TDA10046_FREQ_045) { tda10046h_set_bandwidth()
281 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); tda10046h_set_bandwidth()
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab); tda10046h_set_bandwidth()
288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, tda10046h_set_bandwidth()
291 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M, tda10046h_set_bandwidth()
293 if (state->config->if_freq == TDA10046_FREQ_045) { tda10046h_set_bandwidth()
294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); tda10046h_set_bandwidth()
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); tda10046h_set_bandwidth()
301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, tda10046h_set_bandwidth()
304 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M, tda10046h_set_bandwidth()
306 if (state->config->if_freq == TDA10046_FREQ_045) { tda10046h_set_bandwidth()
307 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); tda10046h_set_bandwidth()
308 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55); tda10046h_set_bandwidth()
319 static int tda1004x_do_upload(struct tda1004x_state *state, tda1004x_do_upload() argument
329 tda1004x_write_byteI(state, dspCodeCounterReg, 0); tda1004x_do_upload()
330 fw_msg.addr = state->config->demod_address; tda1004x_do_upload()
332 i2c_lock_adapter(state->i2c); tda1004x_do_upload()
343 if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) { tda1004x_do_upload()
345 i2c_unlock_adapter(state->i2c); tda1004x_do_upload()
352 i2c_unlock_adapter(state->i2c); tda1004x_do_upload()
360 static int tda1004x_check_upload_ok(struct tda1004x_state *state) tda1004x_check_upload_ok() argument
365 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { tda1004x_check_upload_ok()
367 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { tda1004x_check_upload_ok()
378 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP tda1004x_check_upload_ok()
379 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); tda1004x_check_upload_ok()
381 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); tda1004x_check_upload_ok()
382 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); tda1004x_check_upload_ok()
393 struct tda1004x_state* state = fe->demodulator_priv; tda10045_fwupload() local
398 if (tda1004x_check_upload_ok(state) == 0) tda10045_fwupload()
403 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); tda10045_fwupload()
410 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); tda10045_fwupload()
411 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); tda10045_fwupload()
412 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); tda10045_fwupload()
416 tda10045h_set_bandwidth(state, 8000000); tda10045_fwupload()
418 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); tda10045_fwupload()
428 return tda1004x_check_upload_ok(state); tda10045_fwupload()
433 struct tda1004x_state* state = fe->demodulator_priv; tda10046_init_plls() local
436 if ((state->config->if_freq == TDA10046_FREQ_045) || tda10046_init_plls()
437 (state->config->if_freq == TDA10046_FREQ_052)) tda10046_init_plls()
442 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); tda10046_init_plls()
445 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8 tda10046_init_plls()
448 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3 tda10046_init_plls()
450 if (state->config->xtal_freq == TDA10046_XTAL_4M ) { tda10046_init_plls()
452 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 tda10046_init_plls()
455 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 tda10046_init_plls()
458 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67); tda10046_init_plls()
460 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72); tda10046_init_plls()
462 switch (state->config->if_freq) { tda10046_init_plls()
464 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); tda10046_init_plls()
465 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); tda10046_init_plls()
468 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); tda10046_init_plls()
469 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7); tda10046_init_plls()
472 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); tda10046_init_plls()
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59); tda10046_init_plls()
476 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); tda10046_init_plls()
477 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); tda10046_init_plls()
480 tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */ tda10046_init_plls()
487 struct tda1004x_state* state = fe->demodulator_priv; tda10046_fwupload() local
492 if (state->config->xtal_freq == TDA10046_XTAL_4M) { tda10046_fwupload()
498 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); tda10046_fwupload()
500 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); tda10046_fwupload()
502 if (state->config->gpio_config != TDA10046_GPTRI) { tda10046_fwupload()
503 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33); tda10046_fwupload()
504 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f); tda10046_fwupload()
511 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0); tda10046_fwupload()
514 if (tda1004x_check_upload_ok(state) == 0) tda10046_fwupload()
526 goes into an instable state. So, proper locking are needed tda10046_fwupload()
530 tda1004x_write_byteI(state, TDA1004X_CONFC4, 4); tda10046_fwupload()
532 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); tda10046_fwupload()
535 if (tda1004x_check_upload_ok(state) == 0) tda10046_fwupload()
540 if (state->config->request_firmware != NULL) { tda10046_fwupload()
543 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); tda10046_fwupload()
546 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); tda10046_fwupload()
559 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST tda10046_fwupload()
560 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); tda10046_fwupload()
562 return tda1004x_check_upload_ok(state); tda10046_fwupload()
607 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_write() local
612 return tda1004x_write_byteI(state, buf[0], buf[1]); tda1004x_write()
617 struct tda1004x_state* state = fe->demodulator_priv; tda10045_init() local
626 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC tda10045_init()
629 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer tda10045_init()
630 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream tda10045_init()
631 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal tda10045_init()
632 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer tda10045_init()
633 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset tda10045_init()
634 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset tda10045_init()
635 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface tda10045_init()
636 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface tda10045_init()
637 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits tda10045_init()
638 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity tda10045_init()
639 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); tda10045_init()
641 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); tda10045_init()
648 struct tda1004x_state* state = fe->demodulator_priv; tda10046_init() local
657 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer tda10046_init()
658 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream tda10046_init()
659 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer tda10046_init()
661 switch (state->config->agc_config) { tda10046_init()
663 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup tda10046_init()
664 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities tda10046_init()
667 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup tda10046_init()
668 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities tda10046_init()
671 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup tda10046_init()
672 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities tda10046_init()
675 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup tda10046_init()
676 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold tda10046_init()
677 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize tda10046_init()
678 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities tda10046_init()
681 if (state->config->ts_mode == 0) { tda10046_init()
682 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40); tda10046_init()
683 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); tda10046_init()
685 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80); tda10046_init()
686 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10, tda10046_init()
687 state->config->invert_oclk << 4); tda10046_init()
689 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38); tda10046_init()
690 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on tda10046_init()
691 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } tda10046_init()
692 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values tda10046_init()
693 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } tda10046_init()
694 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } tda10046_init()
695 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1 tda10046_init()
696 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits tda10046_init()
697 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config tda10046_init()
698 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config tda10046_init()
699 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes tda10046_init()
707 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_set_fe() local
713 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { tda1004x_set_fe()
715 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); tda1004x_set_fe()
716 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); tda1004x_set_fe()
717 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); tda1004x_set_fe()
720 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); tda1004x_set_fe()
732 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { tda1004x_set_fe()
743 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto tda1004x_set_fe()
744 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */ tda1004x_set_fe()
745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits tda1004x_set_fe()
746 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits tda1004x_set_fe()
748 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto tda1004x_set_fe()
754 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); tda1004x_set_fe()
760 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); tda1004x_set_fe()
765 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); tda1004x_set_fe()
769 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); tda1004x_set_fe()
773 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); tda1004x_set_fe()
783 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); tda1004x_set_fe()
787 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); tda1004x_set_fe()
791 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); tda1004x_set_fe()
795 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); tda1004x_set_fe()
804 switch (state->demod_type) { tda1004x_set_fe()
806 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz); tda1004x_set_fe()
810 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz); tda1004x_set_fe()
816 if (state->config->invert) tda1004x_set_fe()
820 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); tda1004x_set_fe()
824 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); tda1004x_set_fe()
834 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); tda1004x_set_fe()
835 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); tda1004x_set_fe()
839 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); tda1004x_set_fe()
840 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); tda1004x_set_fe()
844 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); tda1004x_set_fe()
845 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); tda1004x_set_fe()
849 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); tda1004x_set_fe()
850 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); tda1004x_set_fe()
854 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); tda1004x_set_fe()
855 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); tda1004x_set_fe()
865 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); tda1004x_set_fe()
866 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); tda1004x_set_fe()
870 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); tda1004x_set_fe()
871 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); tda1004x_set_fe()
875 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); tda1004x_set_fe()
876 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); tda1004x_set_fe()
884 switch (state->demod_type) { tda1004x_set_fe()
886 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); tda1004x_set_fe()
887 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); tda1004x_set_fe()
891 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); tda1004x_set_fe()
893 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1); tda1004x_set_fe()
905 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_get_fe() local
910 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); tda1004x_get_fe()
920 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) tda1004x_get_fe()
922 if (state->config->invert) tda1004x_get_fe()
926 switch (state->demod_type) { tda1004x_get_fe()
928 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { tda1004x_get_fe()
941 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { tda1004x_get_fe()
960 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); tda1004x_get_fe()
962 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); tda1004x_get_fe()
965 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { tda1004x_get_fe()
979 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) tda1004x_get_fe()
983 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { tda1004x_get_fe()
999 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { tda1004x_get_fe()
1019 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_read_status() local
1027 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); tda1004x_read_status()
1044 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); tda1004x_read_status()
1047 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); tda1004x_read_status()
1052 tda1004x_read_byte(state, TDA1004X_CBER_RESET); tda1004x_read_status()
1062 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); tda1004x_read_status()
1065 status = tda1004x_read_byte(state, TDA1004X_VBER_MID); tda1004x_read_status()
1069 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); tda1004x_read_status()
1074 tda1004x_read_byte(state, TDA1004X_CVBER_LUT); tda1004x_read_status()
1089 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_read_signal_strength() local
1096 switch (state->demod_type) { tda1004x_read_signal_strength()
1107 tmp = tda1004x_read_byte(state, reg); tda1004x_read_signal_strength()
1118 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_read_snr() local
1124 tmp = tda1004x_read_byte(state, TDA1004X_SNR); tda1004x_read_snr()
1136 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_read_ucblocks() local
1145 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); tda1004x_read_ucblocks()
1150 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); tda1004x_read_ucblocks()
1151 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); tda1004x_read_ucblocks()
1152 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); tda1004x_read_ucblocks()
1154 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); tda1004x_read_ucblocks()
1173 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_read_ber() local
1179 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); tda1004x_read_ber()
1183 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); tda1004x_read_ber()
1188 tda1004x_read_byte(state, TDA1004X_CBER_RESET); tda1004x_read_ber()
1196 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_sleep() local
1199 switch (state->demod_type) { tda1004x_sleep()
1201 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); tda1004x_sleep()
1206 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff); tda1004x_sleep()
1208 gpio_conf = state->config->gpio_config; tda1004x_sleep()
1210 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, tda1004x_sleep()
1213 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0); tda1004x_sleep()
1214 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); tda1004x_sleep()
1223 struct tda1004x_state* state = fe->demodulator_priv; tda1004x_i2c_gate_ctrl() local
1226 return tda1004x_enable_tuner_i2c(state); tda1004x_i2c_gate_ctrl()
1228 return tda1004x_disable_tuner_i2c(state); tda1004x_i2c_gate_ctrl()
1243 struct tda1004x_state *state = fe->demodulator_priv; tda1004x_release() local
1244 kfree(state); tda1004x_release()
1282 struct tda1004x_state *state; tda10045_attach() local
1285 /* allocate memory for the internal state */ tda10045_attach()
1286 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); tda10045_attach()
1287 if (!state) { tda10045_attach()
1288 printk(KERN_ERR "Can't allocate memory for tda10045 state\n"); tda10045_attach()
1292 /* setup the state */ tda10045_attach()
1293 state->config = config; tda10045_attach()
1294 state->i2c = i2c; tda10045_attach()
1295 state->demod_type = TDA1004X_DEMOD_TDA10045; tda10045_attach()
1298 id = tda1004x_read_byte(state, TDA1004X_CHIPID); tda10045_attach()
1301 kfree(state); tda10045_attach()
1307 kfree(state); tda10045_attach()
1312 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); tda10045_attach()
1313 state->frontend.demodulator_priv = state; tda10045_attach()
1314 return &state->frontend; tda10045_attach()
1352 struct tda1004x_state *state; tda10046_attach() local
1355 /* allocate memory for the internal state */ tda10046_attach()
1356 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); tda10046_attach()
1357 if (!state) { tda10046_attach()
1358 printk(KERN_ERR "Can't allocate memory for tda10046 state\n"); tda10046_attach()
1362 /* setup the state */ tda10046_attach()
1363 state->config = config; tda10046_attach()
1364 state->i2c = i2c; tda10046_attach()
1365 state->demod_type = TDA1004X_DEMOD_TDA10046; tda10046_attach()
1368 id = tda1004x_read_byte(state, TDA1004X_CHIPID); tda10046_attach()
1371 kfree(state); tda10046_attach()
1376 kfree(state); tda10046_attach()
1381 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); tda10046_attach()
1382 state->frontend.demodulator_priv = state; tda10046_attach()
1383 return &state->frontend; tda10046_attach()
H A Ddib8000.c167 static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg) __dib8000_read_word() argument
171 state->i2c_write_buffer[0] = reg >> 8; __dib8000_read_word()
172 state->i2c_write_buffer[1] = reg & 0xff; __dib8000_read_word()
174 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); __dib8000_read_word()
175 state->msg[0].addr = state->i2c.addr >> 1; __dib8000_read_word()
176 state->msg[0].flags = 0; __dib8000_read_word()
177 state->msg[0].buf = state->i2c_write_buffer; __dib8000_read_word()
178 state->msg[0].len = 2; __dib8000_read_word()
179 state->msg[1].addr = state->i2c.addr >> 1; __dib8000_read_word()
180 state->msg[1].flags = I2C_M_RD; __dib8000_read_word()
181 state->msg[1].buf = state->i2c_read_buffer; __dib8000_read_word()
182 state->msg[1].len = 2; __dib8000_read_word()
184 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2) __dib8000_read_word()
187 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; __dib8000_read_word()
192 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) dib8000_read_word() argument
196 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib8000_read_word()
201 ret = __dib8000_read_word(state, reg); dib8000_read_word()
203 mutex_unlock(&state->i2c_buffer_lock); dib8000_read_word()
208 static u32 dib8000_read32(struct dib8000_state *state, u16 reg) dib8000_read32() argument
212 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib8000_read32()
217 rw[0] = __dib8000_read_word(state, reg + 0); dib8000_read32()
218 rw[1] = __dib8000_read_word(state, reg + 1); dib8000_read32()
220 mutex_unlock(&state->i2c_buffer_lock); dib8000_read32()
247 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) dib8000_write_word() argument
251 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib8000_write_word()
256 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; dib8000_write_word()
257 state->i2c_write_buffer[1] = reg & 0xff; dib8000_write_word()
258 state->i2c_write_buffer[2] = (val >> 8) & 0xff; dib8000_write_word()
259 state->i2c_write_buffer[3] = val & 0xff; dib8000_write_word()
261 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); dib8000_write_word()
262 state->msg[0].addr = state->i2c.addr >> 1; dib8000_write_word()
263 state->msg[0].flags = 0; dib8000_write_word()
264 state->msg[0].buf = state->i2c_write_buffer; dib8000_write_word()
265 state->msg[0].len = 4; dib8000_write_word()
267 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ? dib8000_write_word()
269 mutex_unlock(&state->i2c_buffer_lock); dib8000_write_word()
375 static u16 fft_to_mode(struct dib8000_state *state) fft_to_mode() argument
378 switch (state->fe[0]->dtv_property_cache.transmission_mode) { fft_to_mode()
394 static void dib8000_set_acquisition_mode(struct dib8000_state *state) dib8000_set_acquisition_mode() argument
396 u16 nud = dib8000_read_word(state, 298); dib8000_set_acquisition_mode()
399 dib8000_write_word(state, 298, nud); dib8000_set_acquisition_mode()
403 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_output_mode() local
406 state->output_mode = mode; dib8000_set_output_mode()
409 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); dib8000_set_output_mode()
412 &state->fe[0], mode); dib8000_set_output_mode()
425 if (state->cfg.hostbus_diversity) { dib8000_set_output_mode()
442 dib8000_set_acquisition_mode(state); dib8000_set_output_mode()
447 &state->fe[0]); dib8000_set_output_mode()
451 if (state->cfg.output_mpeg2_in_188_bytes) dib8000_set_output_mode()
454 dib8000_write_word(state, 299, smo_mode); dib8000_set_output_mode()
455 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */ dib8000_set_output_mode()
456 dib8000_write_word(state, 1286, outreg); dib8000_set_output_mode()
457 dib8000_write_word(state, 1291, sram); dib8000_set_output_mode()
464 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_diversity_in() local
465 u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0; dib8000_set_diversity_in()
468 if (!state->differential_constellation) { dib8000_set_diversity_in()
469 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1 dib8000_set_diversity_in()
470 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2 dib8000_set_diversity_in()
472 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 dib8000_set_diversity_in()
473 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 dib8000_set_diversity_in()
475 state->diversity_onoff = onoff; dib8000_set_diversity_in()
479 dib8000_write_word(state, 270, 1); dib8000_set_diversity_in()
480 dib8000_write_word(state, 271, 0); dib8000_set_diversity_in()
483 dib8000_write_word(state, 270, 6); dib8000_set_diversity_in()
484 dib8000_write_word(state, 271, 6); dib8000_set_diversity_in()
487 dib8000_write_word(state, 270, 0); dib8000_set_diversity_in()
488 dib8000_write_word(state, 271, 1); dib8000_set_diversity_in()
492 if (state->revision == 0x8002) { dib8000_set_diversity_in()
493 tmp = dib8000_read_word(state, 903); dib8000_set_diversity_in()
494 dib8000_write_word(state, 903, tmp & ~(1 << 3)); dib8000_set_diversity_in()
496 dib8000_write_word(state, 903, tmp | (1 << 3)); dib8000_set_diversity_in()
501 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode) dib8000_set_power_mode() argument
505 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, dib8000_set_power_mode()
508 if (state->revision != 0x8090) dib8000_set_power_mode()
509 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; dib8000_set_power_mode()
511 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80; dib8000_set_power_mode()
521 if (state->revision != 0x8090) dib8000_set_power_mode()
527 if (state->revision != 0x8090) dib8000_set_power_mode()
535 dib8000_write_word(state, 774, reg_774); dib8000_set_power_mode()
536 dib8000_write_word(state, 775, reg_775); dib8000_set_power_mode()
537 dib8000_write_word(state, 776, reg_776); dib8000_set_power_mode()
538 dib8000_write_word(state, 900, reg_900); dib8000_set_power_mode()
539 dib8000_write_word(state, 1280, reg_1280); dib8000_set_power_mode()
542 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no) dib8000_set_adc_state() argument
545 u16 reg, reg_907 = dib8000_read_word(state, 907); dib8000_set_adc_state()
546 u16 reg_908 = dib8000_read_word(state, 908); dib8000_set_adc_state()
550 if (state->revision != 0x8090) { dib8000_set_adc_state()
552 ret |= dib8000_write_word(state, 908, reg_908); dib8000_set_adc_state()
555 reg = dib8000_read_word(state, 1925); dib8000_set_adc_state()
557 dib8000_write_word(state, 1925, reg | dib8000_set_adc_state()
561 reg = dib8000_read_word(state, 1925); dib8000_set_adc_state()
564 dib8000_write_word(state, 1925, reg & ~(1<<4)); dib8000_set_adc_state()
566 reg = dib8000_read_word(state, 921) & ~((0x3 << 14) dib8000_set_adc_state()
570 dib8000_write_word(state, 921, reg | (1 << 14) dib8000_set_adc_state()
576 if (state->revision == 0x8090) { dib8000_set_adc_state()
577 reg = dib8000_read_word(state, 1925); dib8000_set_adc_state()
579 dib8000_write_word(state, 1925, dib8000_set_adc_state()
607 ret |= dib8000_write_word(state, 907, reg_907); dib8000_set_adc_state()
608 ret |= dib8000_write_word(state, 908, reg_908); dib8000_set_adc_state()
615 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_bandwidth() local
621 if (state->timf == 0) { dib8000_set_bandwidth()
623 timf = state->timf_default; dib8000_set_bandwidth()
626 timf = state->timf; dib8000_set_bandwidth()
629 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); dib8000_set_bandwidth()
630 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); dib8000_set_bandwidth()
635 static int dib8000_sad_calib(struct dib8000_state *state) dib8000_sad_calib() argument
639 if (state->revision == 0x8090) { dib8000_sad_calib()
640 dib8000_write_word(state, 922, (sad_sel << 2)); dib8000_sad_calib()
641 dib8000_write_word(state, 923, 2048); dib8000_sad_calib()
643 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1); dib8000_sad_calib()
644 dib8000_write_word(state, 922, (sad_sel << 2)); dib8000_sad_calib()
647 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); dib8000_sad_calib()
648 dib8000_write_word(state, 924, 776); dib8000_sad_calib()
651 dib8000_write_word(state, 923, (1 << 0)); dib8000_sad_calib()
652 dib8000_write_word(state, 923, (0 << 0)); dib8000_sad_calib()
661 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_wbd_ref() local
664 state->wbd_ref = value; dib8000_set_wbd_ref()
665 return dib8000_write_word(state, 106, value); dib8000_set_wbd_ref()
668 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw) dib8000_reset_pll_common() argument
671 if (state->revision != 0x8090) { dib8000_reset_pll_common()
672 dib8000_write_word(state, 23, dib8000_reset_pll_common()
674 dib8000_write_word(state, 24, dib8000_reset_pll_common()
677 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); dib8000_reset_pll_common()
678 dib8000_write_word(state, 24, dib8000_reset_pll_common()
681 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); dib8000_reset_pll_common()
682 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); dib8000_reset_pll_common()
683 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); dib8000_reset_pll_common()
685 if (state->revision != 0x8090) dib8000_reset_pll_common()
686 dib8000_write_word(state, 922, bw->sad_cfg); dib8000_reset_pll_common()
689 static void dib8000_reset_pll(struct dib8000_state *state) dib8000_reset_pll() argument
691 const struct dibx000_bandwidth_config *pll = state->cfg.pll; dib8000_reset_pll()
694 if (state->revision != 0x8090) { dib8000_reset_pll()
695 dib8000_write_word(state, 901, dib8000_reset_pll()
703 dib8000_write_word(state, 902, clk_cfg1); dib8000_reset_pll()
705 dib8000_write_word(state, 902, clk_cfg1); dib8000_reset_pll()
710 if (state->cfg.pll->ADClkSrc == 0) dib8000_reset_pll()
711 dib8000_write_word(state, 904, dib8000_reset_pll()
715 else if (state->cfg.refclksel != 0) dib8000_reset_pll()
716 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | dib8000_reset_pll()
717 ((state->cfg.refclksel & 0x3) << 10) | dib8000_reset_pll()
721 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | dib8000_reset_pll()
725 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | dib8000_reset_pll()
729 reg = dib8000_read_word(state, 1857); dib8000_reset_pll()
730 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); dib8000_reset_pll()
732 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */ dib8000_reset_pll()
733 dib8000_write_word(state, 1858, reg | 1); dib8000_reset_pll()
735 dib8000_write_word(state, 904, (pll->modulo << 8)); dib8000_reset_pll()
738 dib8000_reset_pll_common(state, pll); dib8000_reset_pll()
744 struct dib8000_state *state = fe->demodulator_priv; dib8000_update_pll() local
745 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856); dib8000_update_pll()
746 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; dib8000_update_pll()
758 if (state->revision == 0x8090) { dib8000_update_pll()
760 reg_1857 = dib8000_read_word(state, 1857); dib8000_update_pll()
762 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15)); dib8000_update_pll()
764 dib8000_write_word(state, 1856, reg_1856 | dib8000_update_pll()
769 internal = dib8000_read32(state, 23) / 1000; dib8000_update_pll()
776 dib8000_write_word(state, 23, dib8000_update_pll()
778 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff)); dib8000_update_pll()
780 dib8000_write_word(state, 1857, reg_1857 | (1 << 15)); dib8000_update_pll()
782 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1) dib8000_update_pll()
786 reg_1856 = dib8000_read_word(state, 1856); dib8000_update_pll()
790 if (bw != state->current_demod_bw) { dib8000_update_pll()
792 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv); dib8000_update_pll()
794 if (state->cfg.pll->pll_prediv != oldprediv) { dib8000_update_pll()
798 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio); dib8000_update_pll()
799 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */ dib8000_update_pll()
800 dib8000_reset_pll(state); dib8000_update_pll()
801 dib8000_write_word(state, 898, 0x0004); /* sad */ dib8000_update_pll()
803 ratio = state->cfg.pll->pll_ratio; dib8000_update_pll()
805 state->current_demod_bw = bw; dib8000_update_pll()
810 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)", state->cfg.pll->pll_prediv, ratio); dib8000_update_pll()
811 dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */ dib8000_update_pll()
851 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_gpio() local
852 return dib8000_cfg_gpio(state, num, dir, val); dib8000_set_gpio()
993 struct dib8000_state *state = fe->demodulator_priv; dib8000_reset_stats() local
994 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_reset_stats()
1021 state->init_ucb = -ucb; dib8000_reset_stats()
1022 state->ber_jiffies_stats = 0; dib8000_reset_stats()
1023 state->per_jiffies_stats = 0; dib8000_reset_stats()
1024 memset(&state->ber_jiffies_stats_layer, 0, dib8000_reset_stats()
1025 sizeof(state->ber_jiffies_stats_layer)); dib8000_reset_stats()
1030 struct dib8000_state *state = fe->demodulator_priv; dib8000_reset() local
1032 if ((state->revision = dib8000_identify(&state->i2c)) == 0) dib8000_reset()
1036 if (state->revision != 0x8090) dib8000_reset()
1037 dib8000_write_word(state, 1287, 0x0003); dib8000_reset()
1039 if (state->revision == 0x8000) dib8000_reset()
1042 dibx000_reset_i2c_master(&state->i2c_master); dib8000_reset()
1044 dib8000_set_power_mode(state, DIB8000_POWER_ALL); dib8000_reset()
1047 dib8000_set_adc_state(state, DIBX000_ADC_OFF); dib8000_reset()
1050 dib8000_write_word(state, 770, 0xffff); dib8000_reset()
1051 dib8000_write_word(state, 771, 0xffff); dib8000_reset()
1052 dib8000_write_word(state, 772, 0xfffc); dib8000_reset()
1053 dib8000_write_word(state, 898, 0x000c); /* restart sad */ dib8000_reset()
1054 if (state->revision == 0x8090) dib8000_reset()
1055 dib8000_write_word(state, 1280, 0x0045); dib8000_reset()
1057 dib8000_write_word(state, 1280, 0x004d); dib8000_reset()
1058 dib8000_write_word(state, 1281, 0x000c); dib8000_reset()
1060 dib8000_write_word(state, 770, 0x0000); dib8000_reset()
1061 dib8000_write_word(state, 771, 0x0000); dib8000_reset()
1062 dib8000_write_word(state, 772, 0x0000); dib8000_reset()
1063 dib8000_write_word(state, 898, 0x0004); // sad dib8000_reset()
1064 dib8000_write_word(state, 1280, 0x0000); dib8000_reset()
1065 dib8000_write_word(state, 1281, 0x0000); dib8000_reset()
1068 if (state->revision != 0x8090) { dib8000_reset()
1069 if (state->cfg.drives) dib8000_reset()
1070 dib8000_write_word(state, 906, state->cfg.drives); dib8000_reset()
1074 dib8000_write_word(state, 906, 0x2d98); dib8000_reset()
1078 dib8000_reset_pll(state); dib8000_reset()
1079 if (state->revision != 0x8090) dib8000_reset()
1080 dib8000_write_word(state, 898, 0x0004); dib8000_reset()
1082 if (dib8000_reset_gpio(state) != 0) dib8000_reset()
1085 if ((state->revision != 0x8090) && dib8000_reset()
1089 state->current_agc = NULL; dib8000_reset()
1093 if (state->cfg.pll->ifreq == 0) dib8000_reset()
1094 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ dib8000_reset()
1096 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ dib8000_reset()
1106 dib8000_write_word(state, r, *n++); dib8000_reset()
1113 state->isdbt_cfg_loaded = 0; dib8000_reset()
1116 if ((state->revision != 8090) && (state->cfg.div_cfg != 0)) dib8000_reset()
1117 dib8000_write_word(state, 903, state->cfg.div_cfg); dib8000_reset()
1120 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); dib8000_reset()
1124 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON); dib8000_reset()
1125 dib8000_sad_calib(state); dib8000_reset()
1126 if (state->revision != 0x8090) dib8000_reset()
1127 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF); dib8000_reset()
1130 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); dib8000_reset()
1132 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); dib8000_reset()
1139 static void dib8000_restart_agc(struct dib8000_state *state) dib8000_restart_agc() argument
1142 dib8000_write_word(state, 770, 0x0a00); dib8000_restart_agc()
1143 dib8000_write_word(state, 770, 0x0000); dib8000_restart_agc()
1146 static int dib8000_update_lna(struct dib8000_state *state) dib8000_update_lna() argument
1150 if (state->cfg.update_lna) { dib8000_update_lna()
1152 dyn_gain = dib8000_read_word(state, 390); dib8000_update_lna()
1154 if (state->cfg.update_lna(state->fe[0], dyn_gain)) { dib8000_update_lna()
1155 dib8000_restart_agc(state); dib8000_update_lna()
1162 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band) dib8000_set_agc_config() argument
1168 if (state->current_band == band && state->current_agc != NULL) dib8000_set_agc_config()
1170 state->current_band = band; dib8000_set_agc_config()
1172 for (i = 0; i < state->cfg.agc_config_count; i++) dib8000_set_agc_config()
1173 if (state->cfg.agc[i].band_caps & band) { dib8000_set_agc_config()
1174 agc = &state->cfg.agc[i]; dib8000_set_agc_config()
1183 state->current_agc = agc; dib8000_set_agc_config()
1186 dib8000_write_word(state, 76, agc->setup); dib8000_set_agc_config()
1187 dib8000_write_word(state, 77, agc->inv_gain); dib8000_set_agc_config()
1188 dib8000_write_word(state, 78, agc->time_stabiliz); dib8000_set_agc_config()
1189 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); dib8000_set_agc_config()
1192 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); dib8000_set_agc_config()
1193 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); dib8000_set_agc_config()
1196 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); dib8000_set_agc_config()
1199 if (state->wbd_ref != 0) dib8000_set_agc_config()
1200 dib8000_write_word(state, 106, state->wbd_ref); dib8000_set_agc_config()
1202 dib8000_write_word(state, 106, agc->wbd_ref); dib8000_set_agc_config()
1204 if (state->revision == 0x8090) { dib8000_set_agc_config()
1205 reg = dib8000_read_word(state, 922) & (0x3 << 2); dib8000_set_agc_config()
1206 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); dib8000_set_agc_config()
1209 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); dib8000_set_agc_config()
1210 dib8000_write_word(state, 108, agc->agc1_max); dib8000_set_agc_config()
1211 dib8000_write_word(state, 109, agc->agc1_min); dib8000_set_agc_config()
1212 dib8000_write_word(state, 110, agc->agc2_max); dib8000_set_agc_config()
1213 dib8000_write_word(state, 111, agc->agc2_min); dib8000_set_agc_config()
1214 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); dib8000_set_agc_config()
1215 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); dib8000_set_agc_config()
1216 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); dib8000_set_agc_config()
1217 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); dib8000_set_agc_config()
1219 dib8000_write_word(state, 75, agc->agc1_pt3); dib8000_set_agc_config()
1220 if (state->revision != 0x8090) dib8000_set_agc_config()
1221 dib8000_write_word(state, 923, dib8000_set_agc_config()
1222 (dib8000_read_word(state, 923) & 0xffe3) | dib8000_set_agc_config()
1230 struct dib8000_state *state = fe->demodulator_priv; dib8000_pwm_agc_reset() local
1231 dib8000_set_adc_state(state, DIBX000_ADC_ON); dib8000_pwm_agc_reset()
1232 dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))); dib8000_pwm_agc_reset()
1235 static int dib8000_agc_soft_split(struct dib8000_state *state) dib8000_agc_soft_split() argument
1239 if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0) dib8000_agc_soft_split()
1243 agc = dib8000_read_word(state, 390); dib8000_agc_soft_split()
1245 if (agc > state->current_agc->split.min_thres) dib8000_agc_soft_split()
1246 split_offset = state->current_agc->split.min; dib8000_agc_soft_split()
1247 else if (agc < state->current_agc->split.max_thres) dib8000_agc_soft_split()
1248 split_offset = state->current_agc->split.max; dib8000_agc_soft_split()
1250 split_offset = state->current_agc->split.max * dib8000_agc_soft_split()
1251 (agc - state->current_agc->split.min_thres) / dib8000_agc_soft_split()
1252 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); dib8000_agc_soft_split()
1257 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); dib8000_agc_soft_split()
1263 struct dib8000_state *state = fe->demodulator_priv; dib8000_agc_startup() local
1264 enum frontend_tune_state *tune_state = &state->tune_state; dib8000_agc_startup()
1273 if (state->revision != 0x8090) dib8000_agc_startup()
1274 dib8000_set_adc_state(state, DIBX000_ADC_ON); dib8000_agc_startup()
1276 dib8000_set_power_mode(state, DIB8000_POWER_ALL); dib8000_agc_startup()
1278 reg = dib8000_read_word(state, 1947)&0xff00; dib8000_agc_startup()
1279 dib8000_write_word(state, 1946, dib8000_agc_startup()
1282 dib8000_write_word(state, 1947, reg | (1<<14) | dib8000_agc_startup()
1286 reg = dib8000_read_word(state, 1920); dib8000_agc_startup()
1287 dib8000_write_word(state, 1920, (reg | 0x3) & dib8000_agc_startup()
1291 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) { dib8000_agc_startup()
1293 state->status = FE_STATUS_TUNE_FAILED; dib8000_agc_startup()
1303 if (state->cfg.agc_control) dib8000_agc_startup()
1304 state->cfg.agc_control(fe, 1); dib8000_agc_startup()
1306 dib8000_restart_agc(state); dib8000_agc_startup()
1317 if (dib8000_update_lna(state)) dib8000_agc_startup()
1325 dib8000_agc_soft_split(state); dib8000_agc_startup()
1327 if (state->cfg.agc_control) dib8000_agc_startup()
1328 state->cfg.agc_control(fe, 0); dib8000_agc_startup()
1333 ret = dib8000_agc_soft_split(state); dib8000_agc_startup()
1340 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive) dib8096p_host_bus_drive() argument
1347 reg = dib8000_read_word(state, 1798) & dib8096p_host_bus_drive()
1350 dib8000_write_word(state, 1798, reg); dib8096p_host_bus_drive()
1353 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); dib8096p_host_bus_drive()
1355 dib8000_write_word(state, 1799, reg); dib8096p_host_bus_drive()
1358 reg = dib8000_read_word(state, 1800) & dib8096p_host_bus_drive()
1361 dib8000_write_word(state, 1800, reg); dib8096p_host_bus_drive()
1364 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); dib8096p_host_bus_drive()
1366 dib8000_write_word(state, 1801, reg); dib8096p_host_bus_drive()
1369 reg = dib8000_read_word(state, 1802) & dib8096p_host_bus_drive()
1372 dib8000_write_word(state, 1802, reg); dib8096p_host_bus_drive()
1394 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin, dib8096p_cfg_DibTx() argument
1400 dib8000_write_word(state, 1615, 1); dib8096p_cfg_DibTx()
1401 dib8000_write_word(state, 1603, P_Kin); dib8096p_cfg_DibTx()
1402 dib8000_write_word(state, 1605, P_Kout); dib8096p_cfg_DibTx()
1403 dib8000_write_word(state, 1606, insertExtSynchro); dib8096p_cfg_DibTx()
1404 dib8000_write_word(state, 1608, synchroMode); dib8096p_cfg_DibTx()
1405 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff); dib8096p_cfg_DibTx()
1406 dib8000_write_word(state, 1610, syncWord & 0xffff); dib8096p_cfg_DibTx()
1407 dib8000_write_word(state, 1612, syncSize); dib8096p_cfg_DibTx()
1408 dib8000_write_word(state, 1615, 0); dib8096p_cfg_DibTx()
1411 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin, dib8096p_cfg_DibRx() argument
1422 dib8000_write_word(state, 1542, syncFreq); dib8096p_cfg_DibRx()
1425 dib8000_write_word(state, 1554, 1); dib8096p_cfg_DibRx()
1426 dib8000_write_word(state, 1536, P_Kin); dib8096p_cfg_DibRx()
1427 dib8000_write_word(state, 1537, P_Kout); dib8096p_cfg_DibRx()
1428 dib8000_write_word(state, 1539, synchroMode); dib8096p_cfg_DibRx()
1429 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff); dib8096p_cfg_DibRx()
1430 dib8000_write_word(state, 1541, syncWord & 0xffff); dib8096p_cfg_DibRx()
1431 dib8000_write_word(state, 1543, syncSize); dib8096p_cfg_DibRx()
1432 dib8000_write_word(state, 1544, dataOutRate); dib8096p_cfg_DibRx()
1433 dib8000_write_word(state, 1554, 0); dib8096p_cfg_DibRx()
1436 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff) dib8096p_enMpegMux() argument
1440 reg_1287 = dib8000_read_word(state, 1287); dib8096p_enMpegMux()
1451 dib8000_write_word(state, 1287, reg_1287); dib8096p_enMpegMux()
1454 static void dib8096p_configMpegMux(struct dib8000_state *state, dib8096p_configMpegMux() argument
1461 dib8096p_enMpegMux(state, 0); dib8096p_configMpegMux()
1464 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1)) dib8096p_configMpegMux()
1469 dib8000_write_word(state, 1287, reg_1287); dib8096p_configMpegMux()
1471 dib8096p_enMpegMux(state, 1); dib8096p_configMpegMux()
1474 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode) dib8096p_setDibTxMux() argument
1476 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7); dib8096p_setDibTxMux()
1481 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); dib8096p_setDibTxMux()
1485 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); dib8096p_setDibTxMux()
1489 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); dib8096p_setDibTxMux()
1494 dib8000_write_word(state, 1288, reg_1288); dib8096p_setDibTxMux()
1497 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode) dib8096p_setHostBusMux() argument
1499 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4); dib8096p_setHostBusMux()
1504 dib8096p_enMpegMux(state, 0); dib8096p_setHostBusMux()
1509 dib8096p_enMpegMux(state, 0); dib8096p_setHostBusMux()
1519 dib8000_write_word(state, 1288, reg_1288); dib8096p_setHostBusMux()
1524 struct dib8000_state *state = fe->demodulator_priv; dib8096p_set_diversity_in() local
1532 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); dib8096p_set_diversity_in()
1536 reg_1287 = dib8000_read_word(state, 1287); dib8096p_set_diversity_in()
1541 dib8000_write_word(state, 1287, reg_1287); dib8096p_set_diversity_in()
1543 state->input_mode_mpeg = 1; dib8096p_set_diversity_in()
1548 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); dib8096p_set_diversity_in()
1549 state->input_mode_mpeg = 0; dib8096p_set_diversity_in()
1553 dib8000_set_diversity_in(state->fe[0], onoff); dib8096p_set_diversity_in()
1559 struct dib8000_state *state = fe->demodulator_priv; dib8096p_set_output_mode() local
1564 state->output_mode = mode; dib8096p_set_output_mode()
1565 dib8096p_host_bus_drive(state, 1); dib8096p_set_output_mode()
1568 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); dib8096p_set_output_mode()
1569 outreg = dib8000_read_word(state, 1286) & dib8096p_set_output_mode()
1580 dib8096p_configMpegMux(state, 3, 1, 1); dib8096p_set_output_mode()
1581 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); dib8096p_set_output_mode()
1584 dib8096p_setHostBusMux(state, dib8096p_set_output_mode()
1593 dib8096p_configMpegMux(state, 2, 0, 0); dib8096p_set_output_mode()
1594 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); dib8096p_set_output_mode()
1597 dib8096p_setHostBusMux(state, dib8096p_set_output_mode()
1605 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); dib8096p_set_output_mode()
1613 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); dib8096p_set_output_mode()
1621 dib8096p_setDibTxMux(state, DIV_ON_DIBTX); dib8096p_set_output_mode()
1622 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); dib8096p_set_output_mode()
1627 dib8096p_setDibTxMux(state, ADC_ON_DIBTX); dib8096p_set_output_mode()
1628 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); dib8096p_set_output_mode()
1636 state->cfg.output_mpeg2_in_188_bytes); dib8096p_set_output_mode()
1637 if (state->cfg.output_mpeg2_in_188_bytes) dib8096p_set_output_mode()
1640 ret |= dib8000_write_word(state, 299, smo_mode); dib8096p_set_output_mode()
1642 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold); dib8096p_set_output_mode()
1643 ret |= dib8000_write_word(state, 1286, outreg); dib8096p_set_output_mode()
1672 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); dib8096p_tuner_write_serpar() local
1678 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; dib8096p_tuner_write_serpar()
1683 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); dib8096p_tuner_write_serpar()
1684 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); dib8096p_tuner_write_serpar()
1692 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); dib8096p_tuner_read_serpar() local
1699 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; dib8096p_tuner_read_serpar()
1704 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f)); dib8096p_tuner_read_serpar()
1708 n_empty = dib8000_read_word(state, 1984)&0x1; dib8096p_tuner_read_serpar()
1714 read_word = dib8000_read_word(state, 1987); dib8096p_tuner_read_serpar()
1736 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); dib8096p_rw_on_apb() local
1740 dib8000_write_word(state, apb_address, dib8096p_rw_on_apb()
1743 word = dib8000_read_word(state, apb_address); dib8096p_rw_on_apb()
1753 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); dib8096p_tuner_xfer() local
1844 i = ((dib8000_read_word(state, 921) >> 12)&0x3); dib8096p_tuner_xfer()
1845 word = dib8000_read_word(state, 924+i); dib8096p_tuner_xfer()
1855 word = (dib8000_read_word(state, 921) & dib8096p_tuner_xfer()
1858 dib8000_write_word(state, 921, word); dib8096p_tuner_xfer()
1889 struct dib8000_state *state = fe->demodulator_priv; dib8096p_tuner_sleep() local
1894 en_cur_state = dib8000_read_word(state, 1922); dib8096p_tuner_sleep()
1898 state->tuner_enable = en_cur_state ; dib8096p_tuner_sleep()
1903 if (state->tuner_enable != 0) dib8096p_tuner_sleep()
1904 en_cur_state = state->tuner_enable; dib8096p_tuner_sleep()
1907 dib8000_write_word(state, 1922, en_cur_state); dib8096p_tuner_sleep()
1919 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_adc_power() local
1923 val = dib8000_read32(state, 384); dib8000_get_adc_power()
1938 struct dib8000_state *state = fe->demodulator_priv; dib8090p_get_dc_power() local
1943 val = dib8000_read_word(state, 403); dib8090p_get_dc_power()
1946 val = dib8000_read_word(state, 404); dib8090p_get_dc_power()
1955 static void dib8000_update_timf(struct dib8000_state *state) dib8000_update_timf() argument
1957 u32 timf = state->timf = dib8000_read32(state, 435); dib8000_update_timf()
1959 dib8000_write_word(state, 29, (u16) (timf >> 16)); dib8000_update_timf()
1960 dib8000_write_word(state, 30, (u16) (timf & 0xffff)); dib8000_update_timf()
1961 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default); dib8000_update_timf()
1966 struct dib8000_state *state = fe->demodulator_priv; dib8000_ctrl_timf() local
1970 state->timf = timf; dib8000_ctrl_timf()
1973 dib8000_update_timf(state); dib8000_ctrl_timf()
1978 dib8000_set_bandwidth(state->fe[0], 6000); dib8000_ctrl_timf()
1980 return state->timf; dib8000_ctrl_timf()
1989 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation) dib8000_set_layer() argument
1992 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_set_layer()
2033 dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv); dib8000_set_layer()
2054 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation) dib8000_adp_fine_tune() argument
2076 dib8000_write_word(state, 215 + i, adp[i]); dib8000_adp_fine_tune()
2081 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain) dib8000_update_ana_gain() argument
2085 dib8000_write_word(state, 116, ana_gain); dib8000_update_ana_gain()
2090 dib8000_write_word(state, 80 + i, adc_target_16dB[i]); dib8000_update_ana_gain()
2093 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); dib8000_update_ana_gain()
2097 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe) dib8000_load_ana_fe_coefs() argument
2101 if (state->isdbt_cfg_loaded == 0) dib8000_load_ana_fe_coefs()
2103 dib8000_write_word(state, 117 + mode, ana_fe[mode]); dib8000_load_ana_fe_coefs()
2116 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel) dib8000_get_init_prbs() argument
2123 switch (state->fe[0]->dtv_property_cache.transmission_mode) { dib8000_get_init_prbs()
2134 static void dib8000_set_13seg_channel(struct dib8000_state *state) dib8000_set_13seg_channel() argument
2139 state->seg_mask = 0x1fff; /* All 13 segments enabled */ dib8000_set_13seg_channel()
2142 if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13 segments */ dib8000_set_13seg_channel()
2143 dib8000_write_word(state, 180, (16 << 6) | 9); dib8000_set_13seg_channel()
2144 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); dib8000_set_13seg_channel()
2147 dib8000_write_word(state, 181+i, coff_pow); dib8000_set_13seg_channel()
2151 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); dib8000_set_13seg_channel()
2154 dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); dib8000_set_13seg_channel()
2156 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); dib8000_set_13seg_channel()
2158 dib8000_write_word(state, 228, 0); /* default value */ dib8000_set_13seg_channel()
2159 dib8000_write_word(state, 265, 31); /* default value */ dib8000_set_13seg_channel()
2160 dib8000_write_word(state, 205, 0x200f); /* init value */ dib8000_set_13seg_channel()
2168 if (state->cfg.pll->ifreq == 0) dib8000_set_13seg_channel()
2169 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */ dib8000_set_13seg_channel()
2171 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg); dib8000_set_13seg_channel()
2174 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs) dib8000_set_subchannel_prbs() argument
2178 reg_1 = dib8000_read_word(state, 1); dib8000_set_subchannel_prbs()
2179 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */ dib8000_set_subchannel_prbs()
2182 static void dib8000_small_fine_tune(struct dib8000_state *state) dib8000_small_fine_tune() argument
2186 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_small_fine_tune()
2188 dib8000_write_word(state, 352, state->seg_diff_mask); dib8000_small_fine_tune()
2189 dib8000_write_word(state, 353, state->seg_mask); dib8000_small_fine_tune()
2192 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5); dib8000_small_fine_tune()
2262 dib8000_write_word(state, 343 + i, ncoeff[i]); dib8000_small_fine_tune()
2268 static void dib8000_set_sb_channel(struct dib8000_state *state) dib8000_set_sb_channel() argument
2270 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_set_sb_channel()
2275 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */ dib8000_set_sb_channel()
2276 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */ dib8000_set_sb_channel()
2278 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */ dib8000_set_sb_channel()
2279 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */ dib8000_set_sb_channel()
2283 state->seg_mask = 0x00E0; dib8000_set_sb_channel()
2285 state->seg_mask = 0x0040; dib8000_set_sb_channel()
2287 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); dib8000_set_sb_channel()
2291 dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3); dib8000_set_sb_channel()
2293 dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */ dib8000_set_sb_channel()
2294 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */ dib8000_set_sb_channel()
2299 if (state->mode == 3) dib8000_set_sb_channel()
2300 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14)); dib8000_set_sb_channel()
2302 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14)); dib8000_set_sb_channel()
2305 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); dib8000_set_sb_channel()
2308 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); dib8000_set_sb_channel()
2310 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); dib8000_set_sb_channel()
2314 dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */ dib8000_set_sb_channel()
2315 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */ dib8000_set_sb_channel()
2318 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */ dib8000_set_sb_channel()
2322 dib8000_write_word(state, 181+i, coff[i]); dib8000_set_sb_channel()
2323 dib8000_write_word(state, 184+i, coff[i]); dib8000_set_sb_channel()
2331 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */ dib8000_set_sb_channel()
2334 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */ dib8000_set_sb_channel()
2336 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ dib8000_set_sb_channel()
2339 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching) dib8000_set_isdbt_common_channel() argument
2345 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_set_isdbt_common_channel()
2351 dib8000_write_word(state, 10, (seq << 4)); dib8000_set_isdbt_common_channel()
2354 state->mode = fft_to_mode(state); dib8000_set_isdbt_common_channel()
2357 tmp = dib8000_read_word(state, 1); dib8000_set_isdbt_common_channel()
2358 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3)); dib8000_set_isdbt_common_channel()
2360 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4)); dib8000_set_isdbt_common_channel()
2364 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0]; dib8000_set_isdbt_common_channel()
2368 state->seg_diff_mask |= 1 << permu_seg[i+1]; dib8000_set_isdbt_common_channel()
2373 state->seg_diff_mask |= 1 << permu_seg[i]; dib8000_set_isdbt_common_channel()
2376 if (state->seg_diff_mask) dib8000_set_isdbt_common_channel()
2377 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); dib8000_set_isdbt_common_channel()
2379 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */ dib8000_set_isdbt_common_channel()
2382 max_constellation = dib8000_set_layer(state, i, max_constellation); dib8000_set_isdbt_common_channel()
2384 state->layer_b_nb_seg = c->layer[1].segment_count; dib8000_set_isdbt_common_channel()
2385 state->layer_c_nb_seg = c->layer[2].segment_count; dib8000_set_isdbt_common_channel()
2389 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask); dib8000_set_isdbt_common_channel()
2391 state->differential_constellation = (state->seg_diff_mask != 0); dib8000_set_isdbt_common_channel()
2394 ana_gain = dib8000_adp_fine_tune(state, max_constellation); dib8000_set_isdbt_common_channel()
2397 dib8000_update_ana_gain(state, ana_gain); dib8000_set_isdbt_common_channel()
2401 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg); dib8000_set_isdbt_common_channel()
2403 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */ dib8000_set_isdbt_common_channel()
2407 dib8000_set_sb_channel(state); dib8000_set_isdbt_common_channel()
2409 init_prbs = dib8000_get_init_prbs(state, c->isdbt_sb_subchannel); dib8000_set_isdbt_common_channel()
2413 dib8000_set_13seg_channel(state); dib8000_set_isdbt_common_channel()
2418 dib8000_small_fine_tune(state); dib8000_set_isdbt_common_channel()
2420 dib8000_set_subchannel_prbs(state, init_prbs); dib8000_set_isdbt_common_channel()
2424 if ((((~state->seg_diff_mask) >> i) & 1) == 1) { dib8000_set_isdbt_common_channel()
2425 p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0)); dib8000_set_isdbt_common_channel()
2426 p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0)); dib8000_set_isdbt_common_channel()
2429 dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */ dib8000_set_isdbt_common_channel()
2430 dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */ dib8000_set_isdbt_common_channel()
2433 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */ dib8000_set_isdbt_common_channel()
2434 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */ dib8000_set_isdbt_common_channel()
2435 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */ dib8000_set_isdbt_common_channel()
2438 dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */ dib8000_set_isdbt_common_channel()
2440 dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */ dib8000_set_isdbt_common_channel()
2442 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */ dib8000_set_isdbt_common_channel()
2443 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */ dib8000_set_isdbt_common_channel()
2445 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ dib8000_set_isdbt_common_channel()
2454 dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */ dib8000_set_isdbt_common_channel()
2455 dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */ dib8000_set_isdbt_common_channel()
2456 dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */ dib8000_set_isdbt_common_channel()
2457 /*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */ dib8000_set_isdbt_common_channel()
2460 if (state->isdbt_cfg_loaded == 0) dib8000_set_isdbt_common_channel()
2461 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */ dib8000_set_isdbt_common_channel()
2463 state->isdbt_cfg_loaded = 0; dib8000_set_isdbt_common_channel()
2466 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal, dib8000_wait_lock() argument
2474 if (state->revision == 0x8090) dib8000_wait_lock()
2482 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff)); dib8000_wait_lock()
2483 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff)); dib8000_wait_lock()
2490 struct dib8000_state *state = fe->demodulator_priv; dib8000_autosearch_start() local
2491 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_autosearch_start()
2493 u32 value, internal = state->cfg.pll->internal; dib8000_autosearch_start()
2495 if (state->revision == 0x8090) dib8000_autosearch_start()
2496 internal = dib8000_read32(state, 23) / 1000; dib8000_autosearch_start()
2498 if ((state->revision >= 0x8002) && dib8000_autosearch_start()
2499 (state->autosearch_state == AS_SEARCHING_FFT)) { dib8000_autosearch_start()
2500 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */ dib8000_autosearch_start()
2501 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */ dib8000_autosearch_start()
2503 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */ dib8000_autosearch_start()
2504 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */ dib8000_autosearch_start()
2505 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */ dib8000_autosearch_start()
2506 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */ dib8000_autosearch_start()
2507 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */ dib8000_autosearch_start()
2508 dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */ dib8000_autosearch_start()
2510 if (state->revision == 0x8090) dib8000_autosearch_start()
2511 value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ dib8000_autosearch_start()
2513 value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ dib8000_autosearch_start()
2515 dib8000_write_word(state, 17, 0); dib8000_autosearch_start()
2516 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */ dib8000_autosearch_start()
2517 dib8000_write_word(state, 19, 0); dib8000_autosearch_start()
2518 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */ dib8000_autosearch_start()
2519 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */ dib8000_autosearch_start()
2520 dib8000_write_word(state, 22, value & 0xffff); dib8000_autosearch_start()
2522 if (state->revision == 0x8090) dib8000_autosearch_start()
2523 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */ dib8000_autosearch_start()
2525 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */ dib8000_autosearch_start()
2526 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */ dib8000_autosearch_start()
2529 dib8000_write_word(state, 356, 0); dib8000_autosearch_start()
2530 dib8000_write_word(state, 357, 0x111); dib8000_autosearch_start()
2532 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */ dib8000_autosearch_start()
2533 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */ dib8000_autosearch_start()
2534 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */ dib8000_autosearch_start()
2535 } else if ((state->revision >= 0x8002) && dib8000_autosearch_start()
2536 (state->autosearch_state == AS_SEARCHING_GUARD)) { dib8000_autosearch_start()
2546 c->transmission_mode = state->found_nfft; dib8000_autosearch_start()
2548 dib8000_set_isdbt_common_channel(state, slist, 1); dib8000_autosearch_start()
2551 dib8000_write_word(state, 6, 0x4); dib8000_autosearch_start()
2552 if (state->revision == 0x8090) dib8000_autosearch_start()
2553 dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */ dib8000_autosearch_start()
2555 dib8000_write_word(state, 7, 0x8); dib8000_autosearch_start()
2556 dib8000_write_word(state, 8, 0x1000); dib8000_autosearch_start()
2559 if (state->revision == 0x8090) dib8000_autosearch_start()
2560 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ dib8000_autosearch_start()
2562 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ dib8000_autosearch_start()
2564 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */ dib8000_autosearch_start()
2567 dib8000_write_word(state, 356, 0); dib8000_autosearch_start()
2568 dib8000_write_word(state, 357, 0xf); dib8000_autosearch_start()
2570 value = dib8000_read_word(state, 0); dib8000_autosearch_start()
2571 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); dib8000_autosearch_start()
2572 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ dib8000_autosearch_start()
2573 dib8000_write_word(state, 0, (u16)value); dib8000_autosearch_start()
2586 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); dib8000_autosearch_start()
2593 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 to have autosearch start ok with mode2 */ dib8000_autosearch_start()
2602 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */ dib8000_autosearch_start()
2609 dib8000_set_isdbt_common_channel(state, slist, 1); dib8000_autosearch_start()
2612 dib8000_write_word(state, 6, 0x4); dib8000_autosearch_start()
2613 if (state->revision == 0x8090) dib8000_autosearch_start()
2614 dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10)); dib8000_autosearch_start()
2616 dib8000_write_word(state, 7, 0x8); dib8000_autosearch_start()
2617 dib8000_write_word(state, 8, 0x1000); dib8000_autosearch_start()
2620 if (state->revision == 0x8090) dib8000_autosearch_start()
2621 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ dib8000_autosearch_start()
2623 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */ dib8000_autosearch_start()
2625 value = dib8000_read_word(state, 0); dib8000_autosearch_start()
2626 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); dib8000_autosearch_start()
2627 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ dib8000_autosearch_start()
2628 dib8000_write_word(state, 0, (u16)value); dib8000_autosearch_start()
2635 struct dib8000_state *state = fe->demodulator_priv; dib8000_autosearch_irq() local
2636 u16 irq_pending = dib8000_read_word(state, 1284); dib8000_autosearch_irq()
2638 if ((state->revision >= 0x8002) && dib8000_autosearch_irq()
2639 (state->autosearch_state == AS_SEARCHING_FFT)) { dib8000_autosearch_irq()
2659 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff) dib8000_viterbi_state() argument
2663 tmp = dib8000_read_word(state, 771); dib8000_viterbi_state()
2665 dib8000_write_word(state, 771, tmp & 0xfffd); dib8000_viterbi_state()
2667 dib8000_write_word(state, 771, tmp | (1<<1)); dib8000_viterbi_state()
2670 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz) dib8000_set_dds() argument
2674 u32 dds = state->cfg.pll->ifreq & 0x1ffffff; dib8000_set_dds()
2675 u8 invert = !!(state->cfg.pll->ifreq & (1 << 25)); dib8000_set_dds()
2678 if (state->revision == 0x8090) { dib8000_set_dds()
2680 unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000); dib8000_set_dds()
2690 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal); dib8000_set_dds()
2704 if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) { dib8000_set_dds()
2706 dib8000_write_word(state, 26, invert); dib8000_set_dds()
2707 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff); dib8000_set_dds()
2708 dib8000_write_word(state, 28, (u16)(dds & 0xffff)); dib8000_set_dds()
2712 static void dib8000_set_frequency_offset(struct dib8000_state *state) dib8000_set_frequency_offset() argument
2714 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_set_frequency_offset()
2719 if (state->fe[0]->ops.tuner_ops.get_frequency) dib8000_set_frequency_offset()
2720 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], &current_rf); dib8000_set_frequency_offset()
2727 state->subchannel = c->isdbt_sb_subchannel; dib8000_set_frequency_offset()
2729 i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */ dib8000_set_frequency_offset()
2730 dib8000_write_word(state, 26, c->inversion ^ i); dib8000_set_frequency_offset()
2732 if (state->cfg.pll->ifreq == 0) { /* low if tuner */ dib8000_set_frequency_offset()
2734 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); dib8000_set_frequency_offset()
2744 dib8000_set_dds(state, total_dds_offset_khz); dib8000_set_frequency_offset()
2749 static u32 dib8000_get_symbol_duration(struct dib8000_state *state) dib8000_get_symbol_duration() argument
2751 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_get_symbol_duration()
2771 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_step) dib8000_set_isdbt_loop_params() argument
2773 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_set_isdbt_loop_params()
2780 reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */ dib8000_set_isdbt_loop_params()
2781 reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */ dib8000_set_isdbt_loop_params()
2783 reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */ dib8000_set_isdbt_loop_params()
2784 reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (9-P_mode) */ dib8000_set_isdbt_loop_params()
2787 reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */ dib8000_set_isdbt_loop_params()
2788 reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */ dib8000_set_isdbt_loop_params()
2794 reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/ dib8000_set_isdbt_loop_params()
2795 reg_37 = (12-state->mode) | ((5 + state->mode) << 5); dib8000_set_isdbt_loop_params()
2797 reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */ dib8000_set_isdbt_loop_params()
2798 reg_37 = (11-state->mode) | ((5 + state->mode) << 5); dib8000_set_isdbt_loop_params()
2801 reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */ dib8000_set_isdbt_loop_params()
2802 reg_37 = ((5+state->mode) << 5) | (10 - state->mode); dib8000_set_isdbt_loop_params()
2806 dib8000_write_word(state, 32, reg_32); dib8000_set_isdbt_loop_params()
2807 dib8000_write_word(state, 37, reg_37); dib8000_set_isdbt_loop_params()
2810 static void dib8000_demod_restart(struct dib8000_state *state) dib8000_demod_restart() argument
2812 dib8000_write_word(state, 770, 0x4000); dib8000_demod_restart()
2813 dib8000_write_word(state, 770, 0x0000); dib8000_demod_restart()
2817 static void dib8000_set_sync_wait(struct dib8000_state *state) dib8000_set_sync_wait() argument
2819 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_set_sync_wait()
2836 if (state->cfg.diversity_delay == 0) dib8000_set_sync_wait()
2839 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */ dib8000_set_sync_wait()
2841 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4)); dib8000_set_sync_wait()
2844 static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode) dib8000_get_timeout() argument
2847 delay *= state->symbol_duration; dib8000_get_timeout()
2854 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_status() local
2855 return state->status; dib8000_get_status()
2860 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_tune_state() local
2861 return state->tune_state; dib8000_get_tune_state()
2866 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_tune_state() local
2868 state->tune_state = tune_state; dib8000_set_tune_state()
2874 struct dib8000_state *state = fe->demodulator_priv; dib8000_tune_restart_from_demod() local
2876 state->status = FE_STATUS_TUNE_PENDING; dib8000_tune_restart_from_demod()
2877 state->tune_state = CT_DEMOD_START; dib8000_tune_restart_from_demod()
2883 struct dib8000_state *state = fe->demodulator_priv; dib8000_read_lock() local
2885 if (state->revision == 0x8090) dib8000_read_lock()
2886 return dib8000_read_word(state, 570); dib8000_read_lock()
2887 return dib8000_read_word(state, 568); dib8000_read_lock()
2890 static int dib8090p_init_sdram(struct dib8000_state *state) dib8090p_init_sdram() argument
2895 reg = dib8000_read_word(state, 274) & 0xfff0; dib8090p_init_sdram()
2896 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */ dib8090p_init_sdram()
2898 dib8000_write_word(state, 1803, (7 << 2)); dib8090p_init_sdram()
2900 reg = dib8000_read_word(state, 1280); dib8090p_init_sdram()
2901 dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */ dib8090p_init_sdram()
2902 dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */ dib8090p_init_sdram()
2915 * On manual mode, the current dib8000_tune state machine is very restrict:
2994 struct dib8000_state *state = fe->demodulator_priv; dib8000_tune() local
2995 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_tune()
2996 enum frontend_tune_state *tune_state = &state->tune_state; dib8000_tune()
3001 unsigned long *timeout = &state->timeout; dib8000_tune()
3013 state->channel_parameters_set, *tune_state, state->autosearch_state, now); dib8000_tune()
3020 if (state->revision == 0x8090) dib8000_tune()
3021 dib8090p_init_sdram(state); dib8000_tune()
3022 state->status = FE_STATUS_TUNE_PENDING; dib8000_tune()
3023 state->channel_parameters_set = is_manual_mode(c); dib8000_tune()
3026 state->channel_parameters_set ? "manual" : "auto"); dib8000_tune()
3028 dib8000_viterbi_state(state, 0); /* force chan dec in restart */ dib8000_tune()
3031 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); dib8000_tune()
3033 dib8000_set_frequency_offset(state); dib8000_tune()
3036 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */ dib8000_tune()
3038 if (state->revision != 0x8090) { dib8000_tune()
3039 state->agc1_max = dib8000_read_word(state, 108); dib8000_tune()
3040 state->agc1_min = dib8000_read_word(state, 109); dib8000_tune()
3041 state->agc2_max = dib8000_read_word(state, 110); dib8000_tune()
3042 state->agc2_min = dib8000_read_word(state, 111); dib8000_tune()
3043 agc1 = dib8000_read_word(state, 388); dib8000_tune()
3044 agc2 = dib8000_read_word(state, 389); dib8000_tune()
3045 dib8000_write_word(state, 108, agc1); dib8000_tune()
3046 dib8000_write_word(state, 109, agc1); dib8000_tune()
3047 dib8000_write_word(state, 110, agc2); dib8000_tune()
3048 dib8000_write_word(state, 111, agc2); dib8000_tune()
3051 state->autosearch_state = AS_SEARCHING_FFT; dib8000_tune()
3052 state->found_nfft = TRANSMISSION_MODE_AUTO; dib8000_tune()
3053 state->found_guard = GUARD_INTERVAL_AUTO; dib8000_tune()
3056 state->autosearch_state = AS_DONE; dib8000_tune()
3059 state->symbol_duration = dib8000_get_symbol_duration(state); dib8000_tune()
3064 if (state->revision == 0x8090) dib8000_tune()
3074 state->status = FE_STATUS_TUNE_FAILED; dib8000_tune()
3075 state->autosearch_state = AS_DONE; dib8000_tune()
3079 state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */ dib8000_tune()
3081 if (state->autosearch_state == AS_SEARCHING_GUARD) dib8000_tune()
3084 state->autosearch_state = AS_DONE; dib8000_tune()
3093 switch (state->autosearch_state) { dib8000_tune()
3096 if (state->revision == 0x8090) { dib8000_tune()
3097 corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); dib8000_tune()
3098 corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); dib8000_tune()
3099 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601)); dib8000_tune()
3101 corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595)); dib8000_tune()
3102 corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); dib8000_tune()
3103 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); dib8000_tune()
3115 state->found_nfft = TRANSMISSION_MODE_2K; dib8000_tune()
3118 state->found_nfft = TRANSMISSION_MODE_4K; dib8000_tune()
3122 state->found_nfft = TRANSMISSION_MODE_8K; dib8000_tune()
3128 state->autosearch_state = AS_SEARCHING_GUARD; dib8000_tune()
3129 if (state->revision == 0x8090) dib8000_tune()
3136 if (state->revision == 0x8090) dib8000_tune()
3137 state->found_guard = dib8000_read_word(state, 572) & 0x3; dib8000_tune()
3139 state->found_guard = dib8000_read_word(state, 570) & 0x3; dib8000_tune()
3140 /* dprintk("guard interval found=%i", state->found_guard); */ dib8000_tune()
3145 /* the demod should never be in this state */ dib8000_tune()
3146 state->status = FE_STATUS_TUNE_FAILED; dib8000_tune()
3147 state->autosearch_state = AS_DONE; dib8000_tune()
3154 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1); dib8000_tune()
3155 dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */ dib8000_tune()
3160 dib8000_demod_restart(state); dib8000_tune()
3162 dib8000_set_sync_wait(state); dib8000_tune()
3163 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); dib8000_tune()
3165 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */ dib8000_tune()
3167 *timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON); dib8000_tune()
3174 dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */ dib8000_tune()
3175 if (!state->differential_constellation) { dib8000_tune()
3177 *timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON); dib8000_tune()
3188 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) { dib8000_tune()
3190 if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */ dib8000_tune()
3192 else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failled also, break the current one */ dib8000_tune()
3194 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ dib8000_tune()
3195 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); dib8000_tune()
3196 state->status = FE_STATUS_TUNE_FAILED; dib8000_tune()
3199 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ dib8000_tune()
3200 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); dib8000_tune()
3202 state->status = FE_STATUS_TUNE_FAILED; dib8000_tune()
3216 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ dib8000_tune()
3217 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); dib8000_tune()
3222 && !state->differential_constellation) { dib8000_tune()
3223 state->subchannel = 0; dib8000_tune()
3227 state->status = FE_STATUS_LOCKED; dib8000_tune()
3232 if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */ dib8000_tune()
3239 state->longest_intlv_layer = i; dib8000_tune()
3251 if (state->diversity_onoff != 0) /* because of diversity sync */ dib8000_tune()
3256 deeper_interleaver, state->longest_intlv_layer, locks, *timeout); dib8000_tune()
3265 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */ dib8000_tune()
3272 && !state->differential_constellation) dib8000_tune()
3274 state->status = FE_STATUS_DEMOD_SUCCESS; dib8000_tune()
3276 state->status = FE_STATUS_DATA_LOCKED; dib8000_tune()
3281 && !state->differential_constellation) { /* continue to try init prbs autosearch */ dib8000_tune()
3282 state->subchannel += 3; dib8000_tune()
3292 state->status = FE_STATUS_DATA_LOCKED; dib8000_tune()
3294 state->status = FE_STATUS_TUNE_FAILED; dib8000_tune()
3301 if (state->subchannel <= 41) { dib8000_tune()
3302 dib8000_set_subchannel_prbs(state, dib8000_get_init_prbs(state, state->subchannel)); dib8000_tune()
3306 state->status = FE_STATUS_TUNE_FAILED; dib8000_tune()
3318 if ((state->revision != 0x8090) && (state->agc1_max != 0)) { dib8000_tune()
3319 dib8000_write_word(state, 108, state->agc1_max); dib8000_tune()
3320 dib8000_write_word(state, 109, state->agc1_min); dib8000_tune()
3321 dib8000_write_word(state, 110, state->agc2_max); dib8000_tune()
3322 dib8000_write_word(state, 111, state->agc2_min); dib8000_tune()
3323 state->agc1_max = 0; dib8000_tune()
3324 state->agc1_min = 0; dib8000_tune()
3325 state->agc2_max = 0; dib8000_tune()
3326 state->agc2_min = 0; dib8000_tune()
3336 return ret * state->symbol_duration; dib8000_tune()
3337 if ((ret > 0) && (ret < state->symbol_duration)) dib8000_tune()
3338 return state->symbol_duration; /* at least one symbol */ dib8000_tune()
3344 struct dib8000_state *state = fe->demodulator_priv; dib8000_wakeup() local
3348 dib8000_set_power_mode(state, DIB8000_POWER_ALL); dib8000_wakeup()
3349 dib8000_set_adc_state(state, DIBX000_ADC_ON); dib8000_wakeup()
3350 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) dib8000_wakeup()
3353 if (state->revision == 0x8090) dib8000_wakeup()
3354 dib8000_sad_calib(state); dib8000_wakeup()
3356 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_wakeup()
3357 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); dib8000_wakeup()
3367 struct dib8000_state *state = fe->demodulator_priv; dib8000_sleep() local
3371 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_sleep()
3372 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); dib8000_sleep()
3377 if (state->revision != 0x8090) dib8000_sleep()
3379 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); dib8000_sleep()
3380 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF); dib8000_sleep()
3387 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_frontend() local
3404 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_get_frontend()
3405 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); dib8000_get_frontend()
3409 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]); dib8000_get_frontend()
3410 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) { dib8000_get_frontend()
3412 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode; dib8000_get_frontend()
3413 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion; dib8000_get_frontend()
3414 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode; dib8000_get_frontend()
3415 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval; dib8000_get_frontend()
3416 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception; dib8000_get_frontend()
3418 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count; dib8000_get_frontend()
3419 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving; dib8000_get_frontend()
3420 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec; dib8000_get_frontend()
3421 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation; dib8000_get_frontend()
3429 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; dib8000_get_frontend()
3431 if (state->revision == 0x8090) dib8000_get_frontend()
3432 val = dib8000_read_word(state, 572); dib8000_get_frontend()
3434 val = dib8000_read_word(state, 570); dib8000_get_frontend()
3471 val = dib8000_read_word(state, 505); dib8000_get_frontend()
3478 val = dib8000_read_word(state, 493 + i) & 0x0f; dib8000_get_frontend()
3490 val = dib8000_read_word(state, 499 + i) & 0x3; dib8000_get_frontend()
3499 val = dib8000_read_word(state, 481 + i); dib8000_get_frontend()
3528 val = dib8000_read_word(state, 487 + i); dib8000_get_frontend()
3555 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_get_frontend()
3556 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode; dib8000_get_frontend()
3557 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion; dib8000_get_frontend()
3558 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode; dib8000_get_frontend()
3559 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval; dib8000_get_frontend()
3560 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isdbt_partial_reception; dib8000_get_frontend()
3562 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.layer[i].segment_count; dib8000_get_frontend()
3563 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer[i].interleaving; dib8000_get_frontend()
3564 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec; dib8000_get_frontend()
3565 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i].modulation; dib8000_get_frontend()
3573 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_frontend() local
3574 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_set_frontend()
3589 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_set_frontend()
3591 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; dib8000_set_frontend()
3592 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties)); dib8000_set_frontend()
3595 if (state->revision != 0x8090) { dib8000_set_frontend()
3596 dib8000_set_diversity_in(state->fe[index_frontend], 1); dib8000_set_frontend()
3598 dib8000_set_output_mode(state->fe[index_frontend], dib8000_set_frontend()
3601 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); dib8000_set_frontend()
3603 dib8096p_set_diversity_in(state->fe[index_frontend], 1); dib8000_set_frontend()
3605 dib8096p_set_output_mode(state->fe[index_frontend], dib8000_set_frontend()
3608 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); dib8000_set_frontend()
3612 if (state->fe[index_frontend]->ops.tuner_ops.set_params) dib8000_set_frontend()
3613 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]); dib8000_set_frontend()
3615 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START); dib8000_set_frontend()
3619 if (state->revision != 0x8090) dib8000_set_frontend()
3620 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0); dib8000_set_frontend()
3622 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0); dib8000_set_frontend()
3626 time = dib8000_agc_startup(state->fe[0]); dib8000_set_frontend()
3627 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_set_frontend()
3628 time_slave = dib8000_agc_startup(state->fe[index_frontend]); dib8000_set_frontend()
3648 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_set_frontend()
3649 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) { dib8000_set_frontend()
3656 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) dib8000_set_frontend()
3657 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); dib8000_set_frontend()
3662 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_set_frontend()
3663 delay = dib8000_tune(state->fe[index_frontend]); dib8000_set_frontend()
3671 if (state->channel_parameters_set == 0) { /* searching */ dib8000_set_frontend()
3672 if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) { dib8000_set_frontend()
3674 dib8000_get_frontend(state->fe[index_frontend]); /* we read the channel parameters from the frontend which was successful */ dib8000_set_frontend()
3675 state->channel_parameters_set = 1; dib8000_set_frontend()
3677 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) { dib8000_set_frontend()
3680 dib8000_tune_restart_from_demod(state->fe[l]); dib8000_set_frontend()
3682 state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode; dib8000_set_frontend()
3683 state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion; dib8000_set_frontend()
3684 state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode; dib8000_set_frontend()
3685 state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval; dib8000_set_frontend()
3686 state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception; dib8000_set_frontend()
3688 state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count; dib8000_set_frontend()
3689 state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving; dib8000_set_frontend()
3690 state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec; dib8000_set_frontend()
3691 state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation; dib8000_set_frontend()
3700 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED || dib8000_set_frontend()
3701 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED || dib8000_set_frontend()
3702 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) { dib8000_set_frontend()
3705 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_set_frontend()
3706 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP) dib8000_set_frontend()
3710 dprintk("tuning done with status %d", dib8000_get_status(state->fe[0])); dib8000_set_frontend()
3723 if (state->revision != 0x8090) dib8000_set_frontend()
3724 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); dib8000_set_frontend()
3726 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode); dib8000_set_frontend()
3727 if (state->cfg.enMpegOutput == 0) { dib8000_set_frontend()
3728 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX); dib8000_set_frontend()
3729 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); dib8000_set_frontend()
3740 struct dib8000_state *state = fe->demodulator_priv; dib8000_read_status() local
3745 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) dib8000_read_status()
3746 lock_slave |= dib8000_read_lock(state->fe[index_frontend]); dib8000_read_status()
3763 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */ dib8000_read_status()
3767 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */ dib8000_read_status()
3771 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */ dib8000_read_status()
3782 struct dib8000_state *state = fe->demodulator_priv; dib8000_read_ber() local
3785 if (state->revision == 0x8090) dib8000_read_ber()
3786 *ber = (dib8000_read_word(state, 562) << 16) | dib8000_read_ber()
3787 dib8000_read_word(state, 563); dib8000_read_ber()
3789 *ber = (dib8000_read_word(state, 560) << 16) | dib8000_read_ber()
3790 dib8000_read_word(state, 561); dib8000_read_ber()
3796 struct dib8000_state *state = fe->demodulator_priv; dib8000_read_unc_blocks() local
3799 if (state->revision == 0x8090) dib8000_read_unc_blocks()
3800 *unc = dib8000_read_word(state, 567); dib8000_read_unc_blocks()
3802 *unc = dib8000_read_word(state, 565); dib8000_read_unc_blocks()
3808 struct dib8000_state *state = fe->demodulator_priv; dib8000_read_signal_strength() local
3813 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { dib8000_read_signal_strength()
3814 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); dib8000_read_signal_strength()
3821 val = 65535 - dib8000_read_word(state, 390); dib8000_read_signal_strength()
3831 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_snr() local
3835 if (state->revision != 0x8090) dib8000_get_snr()
3836 val = dib8000_read_word(state, 542); dib8000_get_snr()
3838 val = dib8000_read_word(state, 544); dib8000_get_snr()
3845 if (state->revision != 0x8090) dib8000_get_snr()
3846 val = dib8000_read_word(state, 543); dib8000_get_snr()
3848 val = dib8000_read_word(state, 545); dib8000_get_snr()
3864 struct dib8000_state *state = fe->demodulator_priv; dib8000_read_snr() local
3869 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) dib8000_read_snr()
3870 snr_master += dib8000_get_snr(state->fe[index_frontend]); dib8000_read_snr()
3980 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_time_us() local
3981 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_get_time_us()
4094 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_stats() local
4095 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; dib8000_get_stats()
4127 if (time_after(jiffies, state->per_jiffies_stats)) { dib8000_get_stats()
4128 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000); dib8000_get_stats()
4133 if (state->fe[i]) dib8000_get_stats()
4134 snr += dib8000_get_snr(state->fe[i]); dib8000_get_stats()
4149 if (val < state->init_ucb) dib8000_get_stats()
4150 state->init_ucb += 0x100000000LL; dib8000_get_stats()
4153 c->block_error.stat[0].uvalue = val + state->init_ucb; dib8000_get_stats()
4170 if (time_after(jiffies, state->ber_jiffies_stats)) { dib8000_get_stats()
4172 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000); dib8000_get_stats()
4184 if (state->revision < 0x8002) dib8000_get_stats()
4199 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) { dib8000_get_stats()
4202 state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000); dib8000_get_stats()
4206 val = dib8000_read_word(state, per_layer_regs[i].ber); dib8000_get_stats()
4215 val = dib8000_read_word(state, per_layer_regs[i].per); dib8000_get_stats()
4235 struct dib8000_state *state = fe->demodulator_priv; dib8000_set_slave_frontend() local
4238 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) dib8000_set_slave_frontend()
4242 state->fe[index_frontend] = fe_slave; dib8000_set_slave_frontend()
4252 struct dib8000_state *state = fe->demodulator_priv; dib8000_remove_slave_frontend() local
4255 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) dib8000_remove_slave_frontend()
4258 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1); dib8000_remove_slave_frontend()
4259 state->fe[index_frontend] = NULL; dib8000_remove_slave_frontend()
4269 struct dib8000_state *state = fe->demodulator_priv; dib8000_get_slave_frontend() local
4273 return state->fe[slave_index]; dib8000_get_slave_frontend()
4431 struct dib8000_state *state; dib8000_init() local
4435 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL); dib8000_init()
4436 if (state == NULL) dib8000_init()
4442 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); dib8000_init()
4443 state->i2c.adap = i2c_adap; dib8000_init()
4444 state->i2c.addr = i2c_addr; dib8000_init()
4445 state->i2c.i2c_write_buffer = state->i2c_write_buffer; dib8000_init()
4446 state->i2c.i2c_read_buffer = state->i2c_read_buffer; dib8000_init()
4447 mutex_init(&state->i2c_buffer_lock); dib8000_init()
4448 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock; dib8000_init()
4449 state->gpio_val = cfg->gpio_val; dib8000_init()
4450 state->gpio_dir = cfg->gpio_dir; dib8000_init()
4455 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) dib8000_init()
4456 state->cfg.output_mode = OUTMODE_MPEG2_FIFO; dib8000_init()
4458 state->fe[0] = fe; dib8000_init()
4459 fe->demodulator_priv = state; dib8000_init()
4460 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); dib8000_init()
4462 state->timf_default = cfg->pll->timf; dib8000_init()
4464 if (dib8000_identify(&state->i2c) == 0) dib8000_init()
4467 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr); dib8000_init()
4470 strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface", dib8000_init()
4471 sizeof(state->dib8096p_tuner_adap.name)); dib8000_init()
4472 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo; dib8000_init()
4473 state->dib8096p_tuner_adap.algo_data = NULL; dib8000_init()
4474 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent; dib8000_init()
4475 i2c_set_adapdata(&state->dib8096p_tuner_adap, state); dib8000_init()
4476 i2c_add_adapter(&state->dib8096p_tuner_adap); dib8000_init()
4480 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */ dib8000_init()
4481 state->current_demod_bw = 6000; dib8000_init()
4486 kfree(state); dib8000_init()
H A Ddib0090.c216 static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) dib0090_read_reg() argument
220 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib0090_read_reg()
225 state->i2c_write_buffer[0] = reg; dib0090_read_reg()
227 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); dib0090_read_reg()
228 state->msg[0].addr = state->config->i2c_address; dib0090_read_reg()
229 state->msg[0].flags = 0; dib0090_read_reg()
230 state->msg[0].buf = state->i2c_write_buffer; dib0090_read_reg()
231 state->msg[0].len = 1; dib0090_read_reg()
232 state->msg[1].addr = state->config->i2c_address; dib0090_read_reg()
233 state->msg[1].flags = I2C_M_RD; dib0090_read_reg()
234 state->msg[1].buf = state->i2c_read_buffer; dib0090_read_reg()
235 state->msg[1].len = 2; dib0090_read_reg()
237 if (i2c_transfer(state->i2c, state->msg, 2) != 2) { dib0090_read_reg()
241 ret = (state->i2c_read_buffer[0] << 8) dib0090_read_reg()
242 | state->i2c_read_buffer[1]; dib0090_read_reg()
244 mutex_unlock(&state->i2c_buffer_lock); dib0090_read_reg()
248 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) dib0090_write_reg() argument
252 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib0090_write_reg()
257 state->i2c_write_buffer[0] = reg & 0xff; dib0090_write_reg()
258 state->i2c_write_buffer[1] = val >> 8; dib0090_write_reg()
259 state->i2c_write_buffer[2] = val & 0xff; dib0090_write_reg()
261 memset(state->msg, 0, sizeof(struct i2c_msg)); dib0090_write_reg()
262 state->msg[0].addr = state->config->i2c_address; dib0090_write_reg()
263 state->msg[0].flags = 0; dib0090_write_reg()
264 state->msg[0].buf = state->i2c_write_buffer; dib0090_write_reg()
265 state->msg[0].len = 3; dib0090_write_reg()
267 if (i2c_transfer(state->i2c, state->msg, 1) != 1) { dib0090_write_reg()
273 mutex_unlock(&state->i2c_buffer_lock); dib0090_write_reg()
277 static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg) dib0090_fw_read_reg() argument
281 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib0090_fw_read_reg()
286 state->i2c_write_buffer[0] = reg; dib0090_fw_read_reg()
288 memset(&state->msg, 0, sizeof(struct i2c_msg)); dib0090_fw_read_reg()
289 state->msg.addr = reg; dib0090_fw_read_reg()
290 state->msg.flags = I2C_M_RD; dib0090_fw_read_reg()
291 state->msg.buf = state->i2c_read_buffer; dib0090_fw_read_reg()
292 state->msg.len = 2; dib0090_fw_read_reg()
293 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { dib0090_fw_read_reg()
297 ret = (state->i2c_read_buffer[0] << 8) dib0090_fw_read_reg()
298 | state->i2c_read_buffer[1]; dib0090_fw_read_reg()
300 mutex_unlock(&state->i2c_buffer_lock); dib0090_fw_read_reg()
304 static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val) dib0090_fw_write_reg() argument
308 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { dib0090_fw_write_reg()
313 state->i2c_write_buffer[0] = val >> 8; dib0090_fw_write_reg()
314 state->i2c_write_buffer[1] = val & 0xff; dib0090_fw_write_reg()
316 memset(&state->msg, 0, sizeof(struct i2c_msg)); dib0090_fw_write_reg()
317 state->msg.addr = reg; dib0090_fw_write_reg()
318 state->msg.flags = 0; dib0090_fw_write_reg()
319 state->msg.buf = state->i2c_write_buffer; dib0090_fw_write_reg()
320 state->msg.len = 2; dib0090_fw_write_reg()
321 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { dib0090_fw_write_reg()
327 mutex_unlock(&state->i2c_buffer_lock); dib0090_fw_write_reg()
331 #define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0)
336 static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c) dib0090_write_regs() argument
339 dib0090_write_reg(state, r++, *b++); dib0090_write_regs()
345 struct dib0090_state *state = fe->tuner_priv; dib0090_identify() local
347 struct dib0090_identity *identity = &state->identity; dib0090_identify()
349 v = dib0090_read_reg(state, 0x1a); dib0090_identify()
437 struct dib0090_fw_state *state = fe->tuner_priv; dib0090_fw_identify() local
438 struct dib0090_identity *identity = &state->identity; dib0090_fw_identify()
440 u16 v = dib0090_fw_read_reg(state, 0x1a); dib0090_fw_identify()
527 struct dib0090_state *state = fe->tuner_priv; dib0090_reset_digital() local
530 HARD_RESET(state); dib0090_reset_digital()
531 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); dib0090_reset_digital()
535 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */ dib0090_reset_digital()
537 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0); dib0090_reset_digital()
539 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8) dib0090_reset_digital()
542 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8) dib0090_reset_digital()
546 PllCfg = dib0090_read_reg(state, 0x21); dib0090_reset_digital()
554 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
558 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
560 /*** Set new Pll configuration in bypass and reset state ***/ dib0090_reset_digital()
562 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
566 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
571 v = !!(dib0090_read_reg(state, 0x1a) & 0x800); dib0090_reset_digital()
583 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
588 dib0090_write_reg(state, 0x21, PllCfg); dib0090_reset_digital()
594 struct dib0090_fw_state *state = fe->tuner_priv; dib0090_fw_reset_digital() local
600 HARD_RESET(state); dib0090_fw_reset_digital()
602 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); dib0090_fw_reset_digital()
603 dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */ dib0090_fw_reset_digital()
605 dib0090_fw_write_reg(state, 0x20, dib0090_fw_reset_digital()
615 dib0090_fw_write_reg(state, 0x23, v); dib0090_fw_reset_digital()
618 PllCfg = dib0090_fw_read_reg(state, 0x21); dib0090_fw_reset_digital()
625 dib0090_fw_write_reg(state, 0x21, PllCfg); dib0090_fw_reset_digital()
629 dib0090_fw_write_reg(state, 0x21, PllCfg); dib0090_fw_reset_digital()
631 /*** Set new Pll configuration in bypass and reset state ***/ dib0090_fw_reset_digital()
633 dib0090_fw_write_reg(state, 0x21, PllCfg); dib0090_fw_reset_digital()
637 dib0090_fw_write_reg(state, 0x21, PllCfg); dib0090_fw_reset_digital()
642 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800); dib0090_fw_reset_digital()
654 dib0090_fw_write_reg(state, 0x21, PllCfg); dib0090_fw_reset_digital()
659 dib0090_fw_write_reg(state, 0x21, PllCfg); dib0090_fw_reset_digital()
667 struct dib0090_state *state = fe->tuner_priv; dib0090_wakeup() local
668 if (state->config->sleep) dib0090_wakeup()
669 state->config->sleep(fe, 0); dib0090_wakeup()
672 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_wakeup()
678 struct dib0090_state *state = fe->tuner_priv; dib0090_sleep() local
679 if (state->config->sleep) dib0090_sleep()
680 state->config->sleep(fe, 1); dib0090_sleep()
686 struct dib0090_state *state = fe->tuner_priv; dib0090_dcc_freq() local
688 dib0090_write_reg(state, 0x04, 0); dib0090_dcc_freq()
690 dib0090_write_reg(state, 0x04, 1); dib0090_dcc_freq()
892 static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd) dib0090_wbd_to_db() argument
895 if (wbd < state->wbd_offset) dib0090_wbd_to_db()
898 wbd -= state->wbd_offset; dib0090_wbd_to_db()
903 static void dib0090_wbd_target(struct dib0090_state *state, u32 rf) dib0090_wbd_target() argument
909 if (state->current_band == BAND_VHF) dib0090_wbd_target()
912 if (state->current_band == BAND_VHF) dib0090_wbd_target()
913 offset = state->config->wbd_vhf_offset; dib0090_wbd_target()
914 if (state->current_band == BAND_CBAND) dib0090_wbd_target()
915 offset = state->config->wbd_cband_offset; dib0090_wbd_target()
918 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset); dib0090_wbd_target()
919 dprintk("wbd-target: %d dB", (u32) state->wbd_target); dib0090_wbd_target()
926 static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force) dib0090_gain_apply() argument
942 if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */ dib0090_gain_apply()
943 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; dib0090_gain_apply()
945 state->rf_gain_limit += top_delta; dib0090_gain_apply()
947 if (state->rf_gain_limit < 0) /*underflow */ dib0090_gain_apply()
948 state->rf_gain_limit = 0; dib0090_gain_apply()
951 gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA; dib0090_gain_apply()
952 if (gain_delta >= ((s16) gain - state->current_gain)) /* overflow */ dib0090_gain_apply()
953 state->current_gain = gain; dib0090_gain_apply()
955 state->current_gain += gain_delta; dib0090_gain_apply()
957 if (state->current_gain < 0) dib0090_gain_apply()
958 state->current_gain = 0; dib0090_gain_apply()
961 gain = state->current_gain >> GAIN_ALPHA; dib0090_gain_apply()
964 if (gain > (state->rf_gain_limit >> WBD_ALPHA)) { dib0090_gain_apply()
965 rf = state->rf_gain_limit >> WBD_ALPHA; dib0090_gain_apply()
967 if (bb > state->bb_ramp[0]) dib0090_gain_apply()
968 bb = state->bb_ramp[0]; dib0090_gain_apply()
974 state->gain[0] = rf; dib0090_gain_apply()
975 state->gain[1] = bb; dib0090_gain_apply()
979 g = state->rf_ramp + 1; /* point on RF LNA1 max gain */ dib0090_gain_apply()
998 gain_reg[2] = v | state->rf_lt_def; dib0090_gain_apply()
1008 g = state->bb_ramp + 1; /* point on BB gain 1 max gain */ dib0090_gain_apply()
1012 gain_reg[3] |= state->bb_1_def; dib0090_gain_apply()
1023 if (force || state->gain_reg[i] != v) { dib0090_gain_apply()
1024 state->gain_reg[i] = v; dib0090_gain_apply()
1025 dib0090_write_reg(state, gain_reg_addr[i], v); dib0090_gain_apply()
1030 static void dib0090_set_boost(struct dib0090_state *state, int onoff) dib0090_set_boost() argument
1032 state->bb_1_def &= 0xdfff; dib0090_set_boost()
1033 state->bb_1_def |= onoff << 13; dib0090_set_boost()
1036 static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg) dib0090_set_rframp() argument
1038 state->rf_ramp = cfg; dib0090_set_rframp()
1041 static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg) dib0090_set_rframp_pwm() argument
1043 state->rf_ramp = cfg; dib0090_set_rframp_pwm()
1045 dib0090_write_reg(state, 0x2a, 0xffff); dib0090_set_rframp_pwm()
1047 dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a)); dib0090_set_rframp_pwm()
1049 dib0090_write_regs(state, 0x2c, cfg + 3, 6); dib0090_set_rframp_pwm()
1050 dib0090_write_regs(state, 0x3e, cfg + 9, 2); dib0090_set_rframp_pwm()
1053 static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg) dib0090_set_bbramp() argument
1055 state->bb_ramp = cfg; dib0090_set_bbramp()
1056 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ dib0090_set_bbramp()
1059 static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg) dib0090_set_bbramp_pwm() argument
1061 state->bb_ramp = cfg; dib0090_set_bbramp_pwm()
1063 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ dib0090_set_bbramp_pwm()
1065 dib0090_write_reg(state, 0x33, 0xffff); dib0090_set_bbramp_pwm()
1066 dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33)); dib0090_set_bbramp_pwm()
1067 dib0090_write_regs(state, 0x35, cfg + 3, 4); dib0090_set_bbramp_pwm()
1072 struct dib0090_state *state = fe->tuner_priv; dib0090_pwm_gain_reset() local
1078 if (state->config->use_pwm_agc) { dib0090_pwm_gain_reset()
1079 if (state->current_band == BAND_CBAND) { dib0090_pwm_gain_reset()
1080 if (state->identity.in_soc) { dib0090_pwm_gain_reset()
1082 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) dib0090_pwm_gain_reset()
1084 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) { dib0090_pwm_gain_reset()
1085 if (state->config->is_dib7090e) { dib0090_pwm_gain_reset()
1086 if (state->rf_ramp == NULL) dib0090_pwm_gain_reset()
1089 rf_ramp = (u16 *)state->rf_ramp; dib0090_pwm_gain_reset()
1097 if (state->current_band == BAND_VHF) { dib0090_pwm_gain_reset()
1098 if (state->identity.in_soc) { dib0090_pwm_gain_reset()
1103 } else if (state->current_band == BAND_UHF) { dib0090_pwm_gain_reset()
1104 if (state->identity.in_soc) { dib0090_pwm_gain_reset()
1106 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) dib0090_pwm_gain_reset()
1108 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) dib0090_pwm_gain_reset()
1114 dib0090_set_rframp_pwm(state, rf_ramp); dib0090_pwm_gain_reset()
1115 dib0090_set_bbramp_pwm(state, bb_ramp); dib0090_pwm_gain_reset()
1118 dprintk("ramp RF gain = %d BAND = %s version = %d", state->rf_ramp[0], (state->current_band == BAND_CBAND) ? "CBAND" : "NOT CBAND", state->identity.version & 0x1f); dib0090_pwm_gain_reset()
1120 if ((state->rf_ramp[0] == 0) || (state->current_band == BAND_CBAND && (state->identity.version & 0x1f) <= P1D_E_F)) { dib0090_pwm_gain_reset()
1126 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11)); dib0090_pwm_gain_reset()
1129 if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) dib0090_pwm_gain_reset()
1130 dib0090_write_reg(state, 0x04, 3); dib0090_pwm_gain_reset()
1132 dib0090_write_reg(state, 0x04, 1); dib0090_pwm_gain_reset()
1133 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */ dib0090_pwm_gain_reset()
1140 struct dib0090_state *state = fe->tuner_priv; dib0090_set_dc_servo() local
1142 dib0090_write_reg(state, 0x04, DC_servo_cutoff); dib0090_set_dc_servo()
1146 static u32 dib0090_get_slow_adc_val(struct dib0090_state *state) dib0090_get_slow_adc_val() argument
1148 u16 adc_val = dib0090_read_reg(state, 0x1d); dib0090_get_slow_adc_val()
1149 if (state->identity.in_soc) dib0090_get_slow_adc_val()
1156 struct dib0090_state *state = fe->tuner_priv; dib0090_gain_control() local
1157 enum frontend_tune_state *tune_state = &state->tune_state; dib0090_gain_control()
1165 state->agc_freeze = 0; dib0090_gain_control()
1166 dib0090_write_reg(state, 0x04, 0x0); dib0090_gain_control()
1169 if (state->current_band == BAND_SBAND) { dib0090_gain_control()
1170 dib0090_set_rframp(state, rf_ramp_sband); dib0090_gain_control()
1171 dib0090_set_bbramp(state, bb_ramp_boost); dib0090_gain_control()
1175 if (state->current_band == BAND_VHF && !state->identity.p1g) { dib0090_gain_control()
1176 dib0090_set_rframp(state, rf_ramp_pwm_vhf); dib0090_gain_control()
1177 dib0090_set_bbramp(state, bb_ramp_pwm_normal); dib0090_gain_control()
1181 if (state->current_band == BAND_CBAND && !state->identity.p1g) { dib0090_gain_control()
1182 dib0090_set_rframp(state, rf_ramp_pwm_cband); dib0090_gain_control()
1183 dib0090_set_bbramp(state, bb_ramp_pwm_normal); dib0090_gain_control()
1186 if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) { dib0090_gain_control()
1187 dib0090_set_rframp(state, rf_ramp_pwm_cband_7090p); dib0090_gain_control()
1188 dib0090_set_bbramp(state, bb_ramp_pwm_normal_socs); dib0090_gain_control()
1190 dib0090_set_rframp(state, rf_ramp_pwm_uhf); dib0090_gain_control()
1191 dib0090_set_bbramp(state, bb_ramp_pwm_normal); dib0090_gain_control()
1194 dib0090_write_reg(state, 0x32, 0); dib0090_gain_control()
1195 dib0090_write_reg(state, 0x39, 0); dib0090_gain_control()
1197 dib0090_wbd_target(state, state->current_rf); dib0090_gain_control()
1199 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; dib0090_gain_control()
1200 state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA; dib0090_gain_control()
1203 } else if (!state->agc_freeze) { dib0090_gain_control()
1207 wbd_val = dib0090_get_slow_adc_val(state); dib0090_gain_control()
1215 wbd_val = dib0090_get_slow_adc_val(state); dib0090_gain_control()
1216 wbd += dib0090_wbd_to_db(state, wbd_val); dib0090_gain_control()
1219 wbd_error = state->wbd_target - wbd; dib0090_gain_control()
1222 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) { dib0090_gain_control()
1225 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; dib0090_gain_control()
1226 if (state->current_band == BAND_CBAND && ltg2) { dib0090_gain_control()
1228 state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */ dib0090_gain_control()
1232 state->agc_step = 0; dib0090_gain_control()
1237 adc = state->config->get_adc_power(fe); dib0090_gain_control()
1242 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) dib0090_gain_control()
1246 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT && dib0090_gain_control()
1247 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16)) dib0090_gain_control()
1251 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > dib0090_gain_control()
1254 ((state->fe->dtv_property_cache.layer[0].modulation == dib0090_gain_control()
1256 || (state->fe->dtv_property_cache. dib0090_gain_control()
1259 ((state->fe->dtv_property_cache.layer[1].segment_count > dib0090_gain_control()
1262 ((state->fe->dtv_property_cache.layer[1].modulation == dib0090_gain_control()
1264 || (state->fe->dtv_property_cache. dib0090_gain_control()
1267 ((state->fe->dtv_property_cache.layer[2].segment_count > dib0090_gain_control()
1270 ((state->fe->dtv_property_cache.layer[2].modulation == dib0090_gain_control()
1272 || (state->fe->dtv_property_cache. dib0090_gain_control()
1280 if (ABS(adc_error) < 50 || state->agc_step++ > 5) { dib0090_gain_control()
1283 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) { dib0090_gain_control()
1284 dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */ dib0090_gain_control()
1285 dib0090_write_reg(state, 0x04, 0x0); dib0090_gain_control()
1289 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32)); dib0090_gain_control()
1290 dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */ dib0090_gain_control()
1303 ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm", dib0090_gain_control()
1305 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); dib0090_gain_control()
1310 if (!state->agc_freeze) dib0090_gain_control()
1311 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); dib0090_gain_control()
1319 struct dib0090_state *state = fe->tuner_priv; dib0090_get_current_gain() local
1321 *rf = state->gain[0]; dib0090_get_current_gain()
1323 *bb = state->gain[1]; dib0090_get_current_gain()
1325 *rf_gain_limit = state->rf_gain_limit; dib0090_get_current_gain()
1327 *rflt = (state->rf_lt_def >> 10) & 0x7; dib0090_get_current_gain()
1334 struct dib0090_state *state = fe->tuner_priv; dib0090_get_wbd_target() local
1335 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000; dib0090_get_wbd_target()
1336 s32 current_temp = state->temperature; dib0090_get_wbd_target()
1338 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; dib0090_get_wbd_target()
1350 state->wbdmux &= ~(7 << 13); dib0090_get_wbd_target()
1352 state->wbdmux |= (wbd->wbd_gain << 13); dib0090_get_wbd_target()
1354 state->wbdmux |= (4 << 13); dib0090_get_wbd_target()
1356 dib0090_write_reg(state, 0x10, state->wbdmux); dib0090_get_wbd_target()
1363 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold); dib0090_get_wbd_target()
1364 dprintk("wbd-target: %d dB", (u32) state->wbd_target); dib0090_get_wbd_target()
1367 return state->wbd_offset + wbd_tcold; dib0090_get_wbd_target()
1373 struct dib0090_state *state = fe->tuner_priv; dib0090_get_wbd_offset() local
1374 return state->wbd_offset; dib0090_get_wbd_offset()
1380 struct dib0090_state *state = fe->tuner_priv; dib0090_set_switch() local
1382 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) dib0090_set_switch()
1391 struct dib0090_state *state = fe->tuner_priv; dib0090_set_vga() local
1393 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) dib0090_set_vga()
1401 struct dib0090_state *state = fe->tuner_priv; dib0090_update_rframp_7090() local
1403 if ((!state->identity.p1g) || (!state->identity.in_soc) dib0090_update_rframp_7090()
1404 || ((state->identity.version != SOC_7090_P1G_21R1) dib0090_update_rframp_7090()
1405 && (state->identity.version != SOC_7090_P1G_11R1))) { dib0090_update_rframp_7090()
1411 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_sensitivity; dib0090_update_rframp_7090()
1413 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_aci; dib0090_update_rframp_7090()
1483 static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n) dib0090_set_default_config() argument
1491 dib0090_write_reg(state, r, pgm_read_word(n++)); dib0090_set_default_config()
1505 static void dib0090_set_EFUSE(struct dib0090_state *state) dib0090_set_EFUSE() argument
1511 e2 = dib0090_read_reg(state, 0x26); dib0090_set_EFUSE()
1512 e4 = dib0090_read_reg(state, 0x28); dib0090_set_EFUSE()
1514 if ((state->identity.version == P1D_E_F) || dib0090_set_EFUSE()
1515 (state->identity.version == P1G) || (e2 == 0xffff)) { dib0090_set_EFUSE()
1517 dib0090_write_reg(state, 0x22, 0x10); dib0090_set_EFUSE()
1518 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff; dib0090_set_EFUSE()
1543 dib0090_write_reg(state, 0x13, (h << 10)); dib0090_set_EFUSE()
1545 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */ dib0090_set_EFUSE()
1551 struct dib0090_state *state = fe->tuner_priv; dib0090_reset() local
1553 dib0090_reset_digital(fe, state->config); dib0090_reset()
1558 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */ dib0090_reset()
1562 if (!state->identity.in_soc) { dib0090_reset()
1563 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2) dib0090_reset()
1564 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL)); dib0090_reset()
1566 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL)); dib0090_reset()
1569 dib0090_set_default_config(state, dib0090_defaults); dib0090_reset()
1571 if (state->identity.in_soc) dib0090_reset()
1572 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */ dib0090_reset()
1574 if (state->identity.p1g) dib0090_reset()
1575 dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults); dib0090_reset()
1578 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) dib0090_reset()
1579 dib0090_set_EFUSE(state); dib0090_reset()
1582 if (state->config->force_crystal_mode != 0) dib0090_reset()
1583 dib0090_write_reg(state, 0x14, dib0090_reset()
1584 state->config->force_crystal_mode & 3); dib0090_reset()
1585 else if (state->config->io.clock_khz >= 24000) dib0090_reset()
1586 dib0090_write_reg(state, 0x14, 1); dib0090_reset()
1588 dib0090_write_reg(state, 0x14, 2); dib0090_reset()
1589 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); dib0090_reset()
1591 state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */ dib0090_reset()
1598 static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state) dib0090_get_offset() argument
1605 dib0090_write_reg(state, 0x1f, 0x7); dib0090_get_offset()
1610 state->adc_diff = dib0090_read_reg(state, 0x1d); dib0090_get_offset()
1613 dib0090_write_reg(state, 0x1f, 0x4); dib0090_get_offset()
1618 state->adc_diff -= dib0090_read_reg(state, 0x1d); dib0090_get_offset()
1659 static void dib0090_set_trim(struct dib0090_state *state) dib0090_set_trim() argument
1663 if (state->dc->addr == 0x07) dib0090_set_trim()
1664 val = &state->bb7; dib0090_set_trim()
1666 val = &state->bb6; dib0090_set_trim()
1668 *val &= ~(0x1f << state->dc->offset); dib0090_set_trim()
1669 *val |= state->step << state->dc->offset; dib0090_set_trim()
1671 dib0090_write_reg(state, state->dc->addr, *val); dib0090_set_trim()
1674 static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) dib0090_dc_offset_calibration() argument
1684 state->bb6 = 0; dib0090_dc_offset_calibration()
1685 state->bb7 = 0x040d; dib0090_dc_offset_calibration()
1688 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */ dib0090_dc_offset_calibration()
1689 dib0090_write_reg(state, 0x24, reg); dib0090_dc_offset_calibration()
1691 state->wbdmux = dib0090_read_reg(state, 0x10); dib0090_dc_offset_calibration()
1692 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); dib0090_dc_offset_calibration()
1693 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); dib0090_dc_offset_calibration()
1695 state->dc = dc_table; dib0090_dc_offset_calibration()
1697 if (state->identity.p1g) dib0090_dc_offset_calibration()
1698 state->dc = dc_p1g_table; dib0090_dc_offset_calibration()
1704 dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q"); dib0090_dc_offset_calibration()
1705 dib0090_write_reg(state, 0x01, state->dc->bb1); dib0090_dc_offset_calibration()
1706 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); dib0090_dc_offset_calibration()
1708 state->step = 0; dib0090_dc_offset_calibration()
1709 state->min_adc_diff = 1023; dib0090_dc_offset_calibration()
1715 dib0090_set_trim(state); dib0090_dc_offset_calibration()
1722 ret = dib0090_get_offset(state, tune_state); dib0090_dc_offset_calibration()
1726 dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step); dib0090_dc_offset_calibration()
1727 if (state->step == 0 && state->adc_diff < 0) { dib0090_dc_offset_calibration()
1728 state->min_adc_diff = -1023; dib0090_dc_offset_calibration()
1732 dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state->step); dib0090_dc_offset_calibration()
1735 if (state->step == 0) { dib0090_dc_offset_calibration()
1736 if (state->dc->pga && state->adc_diff < 0) dib0090_dc_offset_calibration()
1737 state->step = 0x10; dib0090_dc_offset_calibration()
1738 if (state->dc->pga == 0 && state->adc_diff > 0) dib0090_dc_offset_calibration()
1739 state->step = 0x10; dib0090_dc_offset_calibration()
1743 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) { dib0090_dc_offset_calibration()
1745 state->step++; dib0090_dc_offset_calibration()
1746 state->min_adc_diff = state->adc_diff; dib0090_dc_offset_calibration()
1750 if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) { dib0090_dc_offset_calibration()
1751 dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff); dib0090_dc_offset_calibration()
1752 state->step--; dib0090_dc_offset_calibration()
1755 dib0090_set_trim(state); dib0090_dc_offset_calibration()
1756 dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->step); dib0090_dc_offset_calibration()
1758 state->dc++; dib0090_dc_offset_calibration()
1759 if (state->dc->addr == 0) /* done */ dib0090_dc_offset_calibration()
1768 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); dib0090_dc_offset_calibration()
1769 dib0090_write_reg(state, 0x1f, 0x7); dib0090_dc_offset_calibration()
1771 state->calibrate &= ~DC_CAL; dib0090_dc_offset_calibration()
1778 static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) dib0090_wbd_calibration() argument
1781 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; dib0090_wbd_calibration()
1785 while (state->current_rf / 1000 > wbd->max_freq) dib0090_wbd_calibration()
1792 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) dib0090_wbd_calibration()
1797 if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */ dib0090_wbd_calibration()
1799 state->calibrate &= ~WBD_CAL; dib0090_wbd_calibration()
1803 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); dib0090_wbd_calibration()
1805 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); dib0090_wbd_calibration()
1807 state->wbd_calibration_gain = wbd_gain; dib0090_wbd_calibration()
1811 state->wbd_offset = dib0090_get_slow_adc_val(state); dib0090_wbd_calibration()
1812 dprintk("WBD calibration offset = %d", state->wbd_offset); dib0090_wbd_calibration()
1814 state->calibrate &= ~WBD_CAL; dib0090_wbd_calibration()
1823 static void dib0090_set_bandwidth(struct dib0090_state *state) dib0090_set_bandwidth() argument
1827 if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000) dib0090_set_bandwidth()
1829 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000) dib0090_set_bandwidth()
1831 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000) dib0090_set_bandwidth()
1836 state->bb_1_def &= 0x3fff; dib0090_set_bandwidth()
1837 state->bb_1_def |= tmp; dib0090_set_bandwidth()
1839 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ dib0090_set_bandwidth()
1841 dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */ dib0090_set_bandwidth()
1842 dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */ dib0090_set_bandwidth()
1843 if (state->identity.in_soc) { dib0090_set_bandwidth()
1844 dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */ dib0090_set_bandwidth()
1846 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */ dib0090_set_bandwidth()
1847 dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */ dib0090_set_bandwidth()
2045 struct dib0090_state *state = fe->tuner_priv; dib0090_update_tuning_table_7090() local
2054 if ((!state->identity.p1g) || (!state->identity.in_soc) dib0090_update_tuning_table_7090()
2055 || ((state->identity.version != SOC_7090_P1G_21R1) dib0090_update_tuning_table_7090()
2056 && (state->identity.version != SOC_7090_P1G_11R1))) { dib0090_update_tuning_table_7090()
2066 while (state->rf_request > tune->max_freq) dib0090_update_tuning_table_7090()
2069 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) dib0090_update_tuning_table_7090()
2071 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) dib0090_update_tuning_table_7090()
2077 static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state) dib0090_captrim_search() argument
2087 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) dib0090_captrim_search()
2092 dib0090_write_reg(state, 0x10, 0x2B1); dib0090_captrim_search()
2093 dib0090_write_reg(state, 0x1e, 0x0032); dib0090_captrim_search()
2095 if (!state->tuner_is_tuned) { dib0090_captrim_search()
2097 if (!state->identity.p1g || force_soft_search) dib0090_captrim_search()
2098 state->step = state->captrim = state->fcaptrim = 64; dib0090_captrim_search()
2100 state->current_rf = state->rf_request; dib0090_captrim_search()
2102 if (!state->identity.p1g || force_soft_search) { dib0090_captrim_search()
2104 state->step = 4; dib0090_captrim_search()
2105 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f; dib0090_captrim_search()
2108 state->adc_diff = 3000; dib0090_captrim_search()
2112 if (state->identity.p1g && !force_soft_search) { dib0090_captrim_search()
2115 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1); dib0090_captrim_search()
2116 dib0090_read_reg(state, 0x40); dib0090_captrim_search()
2119 state->step /= 2; dib0090_captrim_search()
2120 dib0090_write_reg(state, 0x18, lo4 | state->captrim); dib0090_captrim_search()
2122 if (state->identity.in_soc) dib0090_captrim_search()
2128 if (state->identity.p1g && !force_soft_search) { dib0090_captrim_search()
2129 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0); dib0090_captrim_search()
2130 dib0090_read_reg(state, 0x40); dib0090_captrim_search()
2132 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F; dib0090_captrim_search()
2133 dprintk("***Final Captrim= 0x%x", state->fcaptrim); dib0090_captrim_search()
2138 adc = dib0090_get_slow_adc_val(state); dib0090_captrim_search()
2139 dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024); dib0090_captrim_search()
2141 if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */ dib0090_captrim_search()
2154 if (adc < state->adc_diff) { dib0090_captrim_search()
2155 dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff); dib0090_captrim_search()
2156 state->adc_diff = adc; dib0090_captrim_search()
2157 state->fcaptrim = state->captrim; dib0090_captrim_search()
2160 state->captrim += step_sign * state->step; dib0090_captrim_search()
2161 if (state->step >= 1) dib0090_captrim_search()
2170 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim); dib0090_captrim_search()
2175 state->calibrate &= ~CAPTRIM_CAL; dib0090_captrim_search()
2182 static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state) dib0090_get_temperature() argument
2189 state->wbdmux = dib0090_read_reg(state, 0x10); dib0090_get_temperature()
2190 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); dib0090_get_temperature()
2192 state->bias = dib0090_read_reg(state, 0x13); dib0090_get_temperature()
2193 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); dib0090_get_temperature()
2200 state->adc_diff = dib0090_get_slow_adc_val(state); dib0090_get_temperature()
2201 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); dib0090_get_temperature()
2206 val = dib0090_get_slow_adc_val(state); dib0090_get_temperature()
2207 state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55; dib0090_get_temperature()
2209 dprintk("temperature: %d C", state->temperature - 30); dib0090_get_temperature()
2215 dib0090_write_reg(state, 0x13, state->bias); dib0090_get_temperature()
2216 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */ dib0090_get_temperature()
2219 state->calibrate &= ~TEMP_CAL; dib0090_get_temperature()
2220 if (state->config->analog_output == 0) dib0090_get_temperature()
2221 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_get_temperature()
2235 struct dib0090_state *state = fe->tuner_priv; dib0090_tune() local
2236 const struct dib0090_tuning *tune = state->current_tune_table_index; dib0090_tune()
2237 const struct dib0090_pll *pll = state->current_pll_table_index; dib0090_tune()
2238 enum frontend_tune_state *tune_state = &state->tune_state; dib0090_tune()
2253 if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL)) dib0090_tune()
2254 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); dib0090_tune()
2257 if (state->config->analog_output == 0) dib0090_tune()
2258 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_tune()
2261 if (state->calibrate & DC_CAL) dib0090_tune()
2262 return dib0090_dc_offset_calibration(state, tune_state); dib0090_tune()
2263 else if (state->calibrate & WBD_CAL) { dib0090_tune()
2264 if (state->current_rf == 0) dib0090_tune()
2265 state->current_rf = state->fe->dtv_property_cache.frequency / 1000; dib0090_tune()
2266 return dib0090_wbd_calibration(state, tune_state); dib0090_tune()
2267 } else if (state->calibrate & TEMP_CAL) dib0090_tune()
2268 return dib0090_get_temperature(state, tune_state); dib0090_tune()
2269 else if (state->calibrate & CAPTRIM_CAL) dib0090_tune()
2270 return dib0090_captrim_search(state, tune_state); dib0090_tune()
2274 if (state->config->use_pwm_agc && state->identity.in_soc) { dib0090_tune()
2275 tmp = dib0090_read_reg(state, 0x39); dib0090_tune()
2277 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); dib0090_tune()
2280 state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000); dib0090_tune()
2281 state->rf_request = dib0090_tune()
2282 state->fe->dtv_property_cache.frequency / 1000 + (state->current_band == dib0090_tune()
2283 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config-> dib0090_tune()
2287 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1 dib0090_tune()
2288 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) { dib0090_tune()
2289 const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if; dib0090_tune()
2295 if (((state->rf_request > (LUT_offset->RF_freq - margin_khz)) dib0090_tune()
2296 && (state->rf_request < (LUT_offset->RF_freq + margin_khz))) dib0090_tune()
2297 && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) { dib0090_tune()
2298 state->rf_request += LUT_offset->offset_khz; dib0090_tune()
2307 state->rf_request += 400; dib0090_tune()
2309 if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) { dib0090_tune()
2310 state->tuner_is_tuned = 0; dib0090_tune()
2311 state->current_rf = 0; dib0090_tune()
2312 state->current_standard = 0; dib0090_tune()
2315 if (state->identity.p1g) dib0090_tune()
2318 tmp = (state->identity.version >> 5) & 0x7; dib0090_tune()
2320 if (state->identity.in_soc) { dib0090_tune()
2321 if (state->config->force_cband_input) { /* Use the CBAND input for all band */ dib0090_tune()
2322 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF dib0090_tune()
2323 || state->current_band & BAND_UHF) { dib0090_tune()
2324 state->current_band = BAND_CBAND; dib0090_tune()
2325 if (state->config->is_dib7090e) dib0090_tune()
2331 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) { dib0090_tune()
2332 state->current_band = BAND_CBAND; dib0090_tune()
2333 if (state->config->is_dib7090e) dib0090_tune()
2342 if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) { dib0090_tune()
2343 state->current_band = BAND_CBAND; /* Force CBAND */ dib0090_tune()
2346 if (state->identity.p1g) dib0090_tune()
2352 if (state->identity.p1g) dib0090_tune()
2356 while (state->rf_request > tune->max_freq) dib0090_tune()
2358 while (state->rf_request > pll->max_freq) dib0090_tune()
2361 state->current_tune_table_index = tune; dib0090_tune()
2362 state->current_pll_table_index = pll; dib0090_tune()
2364 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); dib0090_tune()
2366 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2; dib0090_tune()
2368 FREF = state->config->io.clock_khz; dib0090_tune()
2369 if (state->config->fref_clock_ratio != 0) dib0090_tune()
2370 FREF /= state->config->fref_clock_ratio; dib0090_tune()
2385 state->rest = Rest; dib0090_tune()
2399 else if (state->config->analog_output) dib0090_tune()
2405 if (state->identity.p1g) { /* Bias is done automatically in P1G */ dib0090_tune()
2406 if (state->identity.in_soc) { dib0090_tune()
2407 if (state->identity.version == SOC_8090_P1G_11R1) dib0090_tune()
2417 if (!state->config->io.pll_int_loop_filt) { dib0090_tune()
2418 if (state->identity.in_soc) dib0090_tune()
2420 else if (state->identity.p1g || (Rest == 0)) dib0090_tune()
2425 lo6 = (state->config->io.pll_int_loop_filt << 3); dib0090_tune()
2430 if (state->config->analog_output) dib0090_tune()
2433 if (state->identity.in_soc) dib0090_tune()
2440 dib0090_write_reg(state, 0x15, (u16) FBDiv); dib0090_tune()
2441 if (state->config->fref_clock_ratio != 0) dib0090_tune()
2442 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio); dib0090_tune()
2444 dib0090_write_reg(state, 0x16, (Den << 8) | 1); dib0090_tune()
2445 dib0090_write_reg(state, 0x17, (u16) Rest); dib0090_tune()
2446 dib0090_write_reg(state, 0x19, lo5); dib0090_tune()
2447 dib0090_write_reg(state, 0x1c, lo6); dib0090_tune()
2450 if (state->config->analog_output) dib0090_tune()
2453 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL); dib0090_tune()
2457 state->current_rf = state->rf_request; dib0090_tune()
2458 state->current_standard = state->fe->dtv_property_cache.delivery_system; dib0090_tune()
2461 state->calibrate = CAPTRIM_CAL; /* captrim serach now */ dib0090_tune()
2464 else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */ dib0090_tune()
2465 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; dib0090_tune()
2467 while (state->current_rf / 1000 > wbd->max_freq) dib0090_tune()
2470 dib0090_write_reg(state, 0x1e, 0x07ff); dib0090_tune()
2471 dprintk("Final Captrim: %d", (u32) state->fcaptrim); dib0090_tune()
2474 dprintk("VCOF in kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request); dib0090_tune()
2475 dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz); dib0090_tune()
2476 dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17)); dib0090_tune()
2477 dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8), dib0090_tune()
2478 (u32) dib0090_read_reg(state, 0x1c) & 0x3); dib0090_tune()
2487 state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1)); dib0090_tune()
2488 dib0090_write_reg(state, 0x10, state->wbdmux); dib0090_tune()
2490 if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) { dib0090_tune()
2492 dib0090_write_reg(state, 0x09, tune->lna_bias); dib0090_tune()
2493 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim)); dib0090_tune()
2495 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias); dib0090_tune()
2497 dib0090_write_reg(state, 0x0c, tune->v2i); dib0090_tune()
2498 dib0090_write_reg(state, 0x0d, tune->mix); dib0090_tune()
2499 dib0090_write_reg(state, 0x0e, tune->load); dib0090_tune()
2504 state->rf_lt_def = 0x7c00; dib0090_tune()
2506 dib0090_set_bandwidth(state); dib0090_tune()
2507 state->tuner_is_tuned = 1; dib0090_tune()
2509 state->calibrate |= WBD_CAL; dib0090_tune()
2510 state->calibrate |= TEMP_CAL; dib0090_tune()
2526 struct dib0090_state *state = fe->tuner_priv; dib0090_get_tune_state() local
2528 return state->tune_state; dib0090_get_tune_state()
2535 struct dib0090_state *state = fe->tuner_priv; dib0090_set_tune_state() local
2537 state->tune_state = tune_state; dib0090_set_tune_state()
2545 struct dib0090_state *state = fe->tuner_priv; dib0090_get_frequency() local
2547 *frequency = 1000 * state->current_rf; dib0090_get_frequency()
2553 struct dib0090_state *state = fe->tuner_priv; dib0090_set_params() local
2556 state->tune_state = CT_TUNER_START; dib0090_set_params()
2573 } while (state->tune_state != CT_TUNER_STOP); dib0090_set_params()
H A Ds5h1409.c48 /* QAM tuning state goes through the following state transitions */
313 static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data) s5h1409_writereg() argument
318 struct i2c_msg msg = { .addr = state->config->demod_address, s5h1409_writereg()
321 ret = i2c_transfer(state->i2c, &msg, 1); s5h1409_writereg()
330 static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg) s5h1409_readreg() argument
337 { .addr = state->config->demod_address, .flags = 0, s5h1409_readreg()
339 { .addr = state->config->demod_address, .flags = I2C_M_RD, s5h1409_readreg()
342 ret = i2c_transfer(state->i2c, msg, 2); s5h1409_readreg()
351 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_softreset() local
355 s5h1409_writereg(state, 0xf5, 0); s5h1409_softreset()
356 s5h1409_writereg(state, 0xf5, 1); s5h1409_softreset()
357 state->is_qam_locked = 0; s5h1409_softreset()
358 state->qam_state = QAM_STATE_UNTUNED; s5h1409_softreset()
363 #define S5H1409_QAM_IF_FREQ (state->config->qam_if)
367 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_if_freq() local
373 s5h1409_writereg(state, 0x87, 0x014b); s5h1409_set_if_freq()
374 s5h1409_writereg(state, 0x88, 0x0cb5); s5h1409_set_if_freq()
375 s5h1409_writereg(state, 0x89, 0x03e2); s5h1409_set_if_freq()
380 s5h1409_writereg(state, 0x87, 0x01be); s5h1409_set_if_freq()
381 s5h1409_writereg(state, 0x88, 0x0436); s5h1409_set_if_freq()
382 s5h1409_writereg(state, 0x89, 0x054d); s5h1409_set_if_freq()
385 state->if_freq = KHz; s5h1409_set_if_freq()
392 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_spectralinversion() local
397 return s5h1409_writereg(state, 0x1b, 0x1101); /* Inverted */ s5h1409_set_spectralinversion()
399 return s5h1409_writereg(state, 0x1b, 0x0110); /* Normal */ s5h1409_set_spectralinversion()
405 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_enable_modulation() local
412 if (state->if_freq != S5H1409_VSB_IF_FREQ) s5h1409_enable_modulation()
414 s5h1409_writereg(state, 0xf4, 0); s5h1409_enable_modulation()
420 if (state->if_freq != S5H1409_QAM_IF_FREQ) s5h1409_enable_modulation()
422 s5h1409_writereg(state, 0xf4, 1); s5h1409_enable_modulation()
423 s5h1409_writereg(state, 0x85, 0x110); s5h1409_enable_modulation()
430 state->current_modulation = m; s5h1409_enable_modulation()
438 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_i2c_gate_ctrl() local
443 return s5h1409_writereg(state, 0xf3, 1); s5h1409_i2c_gate_ctrl()
445 return s5h1409_writereg(state, 0xf3, 0); s5h1409_i2c_gate_ctrl()
450 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_gpio() local
455 return s5h1409_writereg(state, 0xe3, s5h1409_set_gpio()
456 s5h1409_readreg(state, 0xe3) | 0x1100); s5h1409_set_gpio()
458 return s5h1409_writereg(state, 0xe3, s5h1409_set_gpio()
459 s5h1409_readreg(state, 0xe3) & 0xfeff); s5h1409_set_gpio()
464 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_sleep() local
468 return s5h1409_writereg(state, 0xf2, enable); s5h1409_sleep()
473 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_register_reset() local
477 return s5h1409_writereg(state, 0xfa, 0); s5h1409_register_reset()
482 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_qam_amhum_mode() local
485 if (state->qam_state < QAM_STATE_INTERLEAVE_SET) { s5h1409_set_qam_amhum_mode()
491 if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) { s5h1409_set_qam_amhum_mode()
498 reg = s5h1409_readreg(state, 0xf0); s5h1409_set_qam_amhum_mode()
503 s5h1409_writereg(state, 0x96, 0x000c); s5h1409_set_qam_amhum_mode()
505 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) { s5h1409_set_qam_amhum_mode()
506 dprintk("%s() setting QAM state to OPT_L3\n", s5h1409_set_qam_amhum_mode()
508 s5h1409_writereg(state, 0x93, 0x3130); s5h1409_set_qam_amhum_mode()
509 s5h1409_writereg(state, 0x9e, 0x2836); s5h1409_set_qam_amhum_mode()
510 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3; s5h1409_set_qam_amhum_mode()
513 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) { s5h1409_set_qam_amhum_mode()
514 dprintk("%s() setting QAM state to OPT_L2\n", s5h1409_set_qam_amhum_mode()
516 s5h1409_writereg(state, 0x93, 0x3332); s5h1409_set_qam_amhum_mode()
517 s5h1409_writereg(state, 0x9e, 0x2c37); s5h1409_set_qam_amhum_mode()
518 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2; s5h1409_set_qam_amhum_mode()
523 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) { s5h1409_set_qam_amhum_mode()
524 dprintk("%s() setting QAM state to OPT_L1\n", __func__); s5h1409_set_qam_amhum_mode()
525 s5h1409_writereg(state, 0x96, 0x0008); s5h1409_set_qam_amhum_mode()
526 s5h1409_writereg(state, 0x93, 0x3332); s5h1409_set_qam_amhum_mode()
527 s5h1409_writereg(state, 0x9e, 0x2c37); s5h1409_set_qam_amhum_mode()
528 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1; s5h1409_set_qam_amhum_mode()
535 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_qam_amhum_mode_legacy() local
538 if (state->is_qam_locked) s5h1409_set_qam_amhum_mode_legacy()
542 reg = s5h1409_readreg(state, 0xf0); s5h1409_set_qam_amhum_mode_legacy()
546 state->is_qam_locked = 1; s5h1409_set_qam_amhum_mode_legacy()
549 s5h1409_writereg(state, 0x96, 0x00c); s5h1409_set_qam_amhum_mode_legacy()
551 s5h1409_writereg(state, 0x93, 0x3332); s5h1409_set_qam_amhum_mode_legacy()
552 s5h1409_writereg(state, 0x9e, 0x2c37); s5h1409_set_qam_amhum_mode_legacy()
554 s5h1409_writereg(state, 0x93, 0x3130); s5h1409_set_qam_amhum_mode_legacy()
555 s5h1409_writereg(state, 0x9e, 0x2836); s5h1409_set_qam_amhum_mode_legacy()
559 s5h1409_writereg(state, 0x96, 0x0008); s5h1409_set_qam_amhum_mode_legacy()
560 s5h1409_writereg(state, 0x93, 0x3332); s5h1409_set_qam_amhum_mode_legacy()
561 s5h1409_writereg(state, 0x9e, 0x2c37); s5h1409_set_qam_amhum_mode_legacy()
567 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_qam_interleave_mode() local
570 if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) { s5h1409_set_qam_interleave_mode()
575 reg = s5h1409_readreg(state, 0xf1); s5h1409_set_qam_interleave_mode()
579 if (state->qam_state == QAM_STATE_UNTUNED || s5h1409_set_qam_interleave_mode()
580 state->qam_state == QAM_STATE_TUNING_STARTED) { s5h1409_set_qam_interleave_mode()
581 dprintk("%s() setting QAM state to INTERLEAVE_SET\n", s5h1409_set_qam_interleave_mode()
583 reg1 = s5h1409_readreg(state, 0xb2); s5h1409_set_qam_interleave_mode()
584 reg2 = s5h1409_readreg(state, 0xad); s5h1409_set_qam_interleave_mode()
586 s5h1409_writereg(state, 0x96, 0x0020); s5h1409_set_qam_interleave_mode()
587 s5h1409_writereg(state, 0xad, s5h1409_set_qam_interleave_mode()
589 state->qam_state = QAM_STATE_INTERLEAVE_SET; s5h1409_set_qam_interleave_mode()
592 if (state->qam_state == QAM_STATE_UNTUNED) { s5h1409_set_qam_interleave_mode()
593 dprintk("%s() setting QAM state to TUNING_STARTED\n", s5h1409_set_qam_interleave_mode()
595 s5h1409_writereg(state, 0x96, 0x08); s5h1409_set_qam_interleave_mode()
596 s5h1409_writereg(state, 0xab, s5h1409_set_qam_interleave_mode()
597 s5h1409_readreg(state, 0xab) | 0x1001); s5h1409_set_qam_interleave_mode()
598 state->qam_state = QAM_STATE_TUNING_STARTED; s5h1409_set_qam_interleave_mode()
605 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_qam_interleave_mode_legacy() local
608 reg = s5h1409_readreg(state, 0xf1); s5h1409_set_qam_interleave_mode_legacy()
612 if (state->qam_state != 2) { s5h1409_set_qam_interleave_mode_legacy()
613 state->qam_state = 2; s5h1409_set_qam_interleave_mode_legacy()
614 reg1 = s5h1409_readreg(state, 0xb2); s5h1409_set_qam_interleave_mode_legacy()
615 reg2 = s5h1409_readreg(state, 0xad); s5h1409_set_qam_interleave_mode_legacy()
617 s5h1409_writereg(state, 0x96, 0x20); s5h1409_set_qam_interleave_mode_legacy()
618 s5h1409_writereg(state, 0xad, s5h1409_set_qam_interleave_mode_legacy()
620 s5h1409_writereg(state, 0xab, s5h1409_set_qam_interleave_mode_legacy()
621 s5h1409_readreg(state, 0xab) & 0xeffe); s5h1409_set_qam_interleave_mode_legacy()
624 if (state->qam_state != 1) { s5h1409_set_qam_interleave_mode_legacy()
625 state->qam_state = 1; s5h1409_set_qam_interleave_mode_legacy()
626 s5h1409_writereg(state, 0x96, 0x08); s5h1409_set_qam_interleave_mode_legacy()
627 s5h1409_writereg(state, 0xab, s5h1409_set_qam_interleave_mode_legacy()
628 s5h1409_readreg(state, 0xab) | 0x1001); s5h1409_set_qam_interleave_mode_legacy()
637 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_frontend() local
643 state->current_frequency = p->frequency; s5h1409_set_frontend()
660 if (state->current_modulation != VSB_8) { s5h1409_set_frontend()
664 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) { s5h1409_set_frontend()
678 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_set_mpeg_timing() local
683 val = s5h1409_readreg(state, 0xac) & 0xcfff; s5h1409_set_mpeg_timing()
703 return s5h1409_writereg(state, 0xac, val); s5h1409_set_mpeg_timing()
707 to a default state. */ s5h1409_init()
712 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_init() local
719 s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data); s5h1409_init()
722 state->current_modulation = VSB_8; s5h1409_init()
727 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) { s5h1409_init()
729 s5h1409_writereg(state, 0x09, 0x0050); s5h1409_init()
732 s5h1409_writereg(state, 0x21, 0x0001); s5h1409_init()
733 s5h1409_writereg(state, 0x50, 0x030e); s5h1409_init()
736 s5h1409_writereg(state, 0x82, 0x0800); s5h1409_init()
739 if (state->config->output_mode == S5H1409_SERIAL_OUTPUT) s5h1409_init()
740 s5h1409_writereg(state, 0xab, s5h1409_init()
741 s5h1409_readreg(state, 0xab) | 0x100); /* Serial */ s5h1409_init()
743 s5h1409_writereg(state, 0xab, s5h1409_init()
744 s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */ s5h1409_init()
746 s5h1409_set_spectralinversion(fe, state->config->inversion); s5h1409_init()
747 s5h1409_set_if_freq(fe, state->if_freq); s5h1409_init()
748 s5h1409_set_gpio(fe, state->config->gpio); s5h1409_init()
749 s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing); s5h1409_init()
760 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_read_status() local
767 if (state->current_modulation != VSB_8) { s5h1409_read_status()
771 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) { s5h1409_read_status()
778 reg = s5h1409_readreg(state, 0xf1); s5h1409_read_status()
784 switch (state->config->status_mode) { s5h1409_read_status()
858 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_read_snr() local
862 switch (state->current_modulation) { s5h1409_read_snr()
864 reg = s5h1409_readreg(state, 0xf0) & 0xff; s5h1409_read_snr()
867 reg = s5h1409_readreg(state, 0xf0) & 0xff; s5h1409_read_snr()
870 reg = s5h1409_readreg(state, 0xf1) & 0x3ff; s5h1409_read_snr()
916 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_read_ucblocks() local
918 *ucblocks = s5h1409_readreg(state, 0xb5); s5h1409_read_ucblocks()
931 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_get_frontend() local
933 p->frequency = state->current_frequency; s5h1409_get_frontend()
934 p->modulation = state->current_modulation; s5h1409_get_frontend()
948 struct s5h1409_state *state = fe->demodulator_priv; s5h1409_release() local
949 kfree(state); s5h1409_release()
957 struct s5h1409_state *state = NULL; s5h1409_attach() local
960 /* allocate memory for the internal state */ s5h1409_attach()
961 state = kzalloc(sizeof(struct s5h1409_state), GFP_KERNEL); s5h1409_attach()
962 if (state == NULL) s5h1409_attach()
965 /* setup the state */ s5h1409_attach()
966 state->config = config; s5h1409_attach()
967 state->i2c = i2c; s5h1409_attach()
968 state->current_modulation = 0; s5h1409_attach()
969 state->if_freq = S5H1409_VSB_IF_FREQ; s5h1409_attach()
972 reg = s5h1409_readreg(state, 0x04); s5h1409_attach()
977 memcpy(&state->frontend.ops, &s5h1409_ops, s5h1409_attach()
979 state->frontend.demodulator_priv = state; s5h1409_attach()
981 if (s5h1409_init(&state->frontend) != 0) { s5h1409_attach()
988 s5h1409_i2c_gate_ctrl(&state->frontend, 1); s5h1409_attach()
990 return &state->frontend; s5h1409_attach()
993 kfree(state); s5h1409_attach()
H A Dnxt6000.c44 static int nxt6000_writereg(struct nxt6000_state* state, u8 reg, u8 data) nxt6000_writereg() argument
47 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 }; nxt6000_writereg()
50 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) nxt6000_writereg()
56 static u8 nxt6000_readreg(struct nxt6000_state* state, u8 reg) nxt6000_readreg() argument
62 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1}, nxt6000_readreg()
63 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1} nxt6000_readreg()
66 ret = i2c_transfer(state->i2c, msgs, 2); nxt6000_readreg()
74 static void nxt6000_reset(struct nxt6000_state* state) nxt6000_reset() argument
78 val = nxt6000_readreg(state, OFDM_COR_CTL); nxt6000_reset()
80 nxt6000_writereg(state, OFDM_COR_CTL, val & ~COREACT); nxt6000_reset()
81 nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT); nxt6000_reset()
84 static int nxt6000_set_bandwidth(struct nxt6000_state *state, u32 bandwidth) nxt6000_set_bandwidth() argument
106 if ((result = nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, nominal_rate & 0xFF)) < 0) nxt6000_set_bandwidth()
109 return nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, (nominal_rate >> 8) & 0xFF); nxt6000_set_bandwidth()
112 static int nxt6000_set_guard_interval(struct nxt6000_state* state, fe_guard_interval_t guard_interval) nxt6000_set_guard_interval() argument
117 return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x00 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03)); nxt6000_set_guard_interval()
120 return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x01 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03)); nxt6000_set_guard_interval()
124 return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x02 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03)); nxt6000_set_guard_interval()
127 return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x03 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03)); nxt6000_set_guard_interval()
134 static int nxt6000_set_inversion(struct nxt6000_state* state, fe_spectral_inversion_t inversion) nxt6000_set_inversion() argument
139 return nxt6000_writereg(state, OFDM_ITB_CTL, 0x00); nxt6000_set_inversion()
142 return nxt6000_writereg(state, OFDM_ITB_CTL, ITBINV); nxt6000_set_inversion()
150 static int nxt6000_set_transmission_mode(struct nxt6000_state* state, fe_transmit_mode_t transmission_mode) nxt6000_set_transmission_mode() argument
157 if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x00 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0) nxt6000_set_transmission_mode()
160 return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x00 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04)); nxt6000_set_transmission_mode()
164 if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x02 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0) nxt6000_set_transmission_mode()
167 return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x01 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04)); nxt6000_set_transmission_mode()
177 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_setup() local
179 nxt6000_writereg(state, RS_COR_SYNC_PARAM, SYNC_PARAM); nxt6000_setup()
180 nxt6000_writereg(state, BER_CTRL, /*(1 << 2) | */ (0x01 << 1) | 0x01); nxt6000_setup()
181 nxt6000_writereg(state, VIT_BERTIME_2, 0x00); // BER Timer = 0x000200 * 256 = 131072 bits nxt6000_setup()
182 nxt6000_writereg(state, VIT_BERTIME_1, 0x02); // nxt6000_setup()
183 nxt6000_writereg(state, VIT_BERTIME_0, 0x00); // nxt6000_setup()
184 nxt6000_writereg(state, VIT_COR_INTEN, 0x98); // Enable BER interrupts nxt6000_setup()
185 nxt6000_writereg(state, VIT_COR_CTL, 0x82); // Enable BER measurement nxt6000_setup()
186 nxt6000_writereg(state, VIT_COR_CTL, VIT_COR_RESYNC | 0x02 ); nxt6000_setup()
187 nxt6000_writereg(state, OFDM_COR_CTL, (0x01 << 5) | (nxt6000_readreg(state, OFDM_COR_CTL) & 0x0F)); nxt6000_setup()
188 nxt6000_writereg(state, OFDM_COR_MODEGUARD, FORCEMODE8K | 0x02); nxt6000_setup()
189 nxt6000_writereg(state, OFDM_AGC_CTL, AGCLAST | INITIAL_AGC_BW); nxt6000_setup()
190 nxt6000_writereg(state, OFDM_ITB_FREQ_1, 0x06); nxt6000_setup()
191 nxt6000_writereg(state, OFDM_ITB_FREQ_2, 0x31); nxt6000_setup()
192 nxt6000_writereg(state, OFDM_CAS_CTL, (0x01 << 7) | (0x02 << 3) | 0x04); nxt6000_setup()
193 nxt6000_writereg(state, CAS_FREQ, 0xBB); /* CHECKME */ nxt6000_setup()
194 nxt6000_writereg(state, OFDM_SYR_CTL, 1 << 2); nxt6000_setup()
195 nxt6000_writereg(state, OFDM_PPM_CTL_1, PPM256); nxt6000_setup()
196 nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, 0x49); nxt6000_setup()
197 nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, 0x72); nxt6000_setup()
198 nxt6000_writereg(state, ANALOG_CONTROL_0, 1 << 5); nxt6000_setup()
199 nxt6000_writereg(state, EN_DMD_RACQ, (1 << 7) | (3 << 4) | 2); nxt6000_setup()
200 nxt6000_writereg(state, DIAG_CONFIG, TB_SET); nxt6000_setup()
202 if (state->config->clock_inversion) nxt6000_setup()
203 nxt6000_writereg(state, SUB_DIAG_MODE_SEL, CLKINVERSION); nxt6000_setup()
205 nxt6000_writereg(state, SUB_DIAG_MODE_SEL, 0); nxt6000_setup()
207 nxt6000_writereg(state, TS_FORMAT, 0); nxt6000_setup()
210 static void nxt6000_dump_status(struct nxt6000_state *state) nxt6000_dump_status() argument
228 val = nxt6000_readreg(state, RS_COR_STAT); nxt6000_dump_status()
233 val = nxt6000_readreg(state, VIT_SYNC_STATUS); nxt6000_dump_status()
264 val = nxt6000_readreg(state, OFDM_COR_STAT); nxt6000_dump_status()
306 val = nxt6000_readreg(state, OFDM_SYR_STAT); nxt6000_dump_status()
330 val = nxt6000_readreg(state, OFDM_TPS_RCVD_3); nxt6000_dump_status()
386 val = nxt6000_readreg(state, OFDM_TPS_RCVD_4); nxt6000_dump_status()
411 nxt6000_readreg(state, RF_AGC_VAL_1); nxt6000_dump_status()
412 val = nxt6000_readreg(state, RF_AGC_STATUS); nxt6000_dump_status()
413 val = nxt6000_readreg(state, RF_AGC_STATUS); nxt6000_dump_status()
422 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_read_status() local
426 core_status = nxt6000_readreg(state, OFDM_COR_STAT); nxt6000_read_status()
431 if (nxt6000_readreg(state, OFDM_SYR_STAT) & GI14_SYR_LOCK) nxt6000_read_status()
434 if (nxt6000_readreg(state, VIT_SYNC_STATUS) & VITINSYNC) nxt6000_read_status()
437 if (nxt6000_readreg(state, RS_COR_STAT) & RSCORESTATUS) nxt6000_read_status()
444 nxt6000_dump_status(state); nxt6000_read_status()
451 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_init() local
453 nxt6000_reset(state); nxt6000_init()
462 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_set_frontend() local
470 result = nxt6000_set_bandwidth(state, p->bandwidth_hz); nxt6000_set_frontend()
474 result = nxt6000_set_guard_interval(state, p->guard_interval); nxt6000_set_frontend()
478 result = nxt6000_set_transmission_mode(state, p->transmission_mode); nxt6000_set_frontend()
482 result = nxt6000_set_inversion(state, p->inversion); nxt6000_set_frontend()
492 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_release() local
493 kfree(state); nxt6000_release()
498 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_read_snr() local
500 *snr = nxt6000_readreg( state, OFDM_CHC_SNR) / 8; nxt6000_read_snr()
507 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_read_ber() local
509 nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18 ); nxt6000_read_ber()
511 *ber = (nxt6000_readreg( state, VIT_BER_1 ) << 8 ) | nxt6000_read_ber()
512 nxt6000_readreg( state, VIT_BER_0 ); nxt6000_read_ber()
514 nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18); // Clear BER Done interrupts nxt6000_read_ber()
521 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_read_signal_strength() local
524 (nxt6000_readreg(state, AGC_GAIN_1) + nxt6000_read_signal_strength()
525 ((nxt6000_readreg(state, AGC_GAIN_2) & 0x03) << 8))); nxt6000_read_signal_strength()
538 struct nxt6000_state* state = fe->demodulator_priv; nxt6000_i2c_gate_ctrl() local
541 return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x01); nxt6000_i2c_gate_ctrl()
543 return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x00); nxt6000_i2c_gate_ctrl()
552 struct nxt6000_state* state = NULL; nxt6000_attach() local
554 /* allocate memory for the internal state */ nxt6000_attach()
555 state = kzalloc(sizeof(struct nxt6000_state), GFP_KERNEL); nxt6000_attach()
556 if (state == NULL) goto error; nxt6000_attach()
558 /* setup the state */ nxt6000_attach()
559 state->config = config; nxt6000_attach()
560 state->i2c = i2c; nxt6000_attach()
563 if (nxt6000_readreg(state, OFDM_MSC_REV) != NXT6000ASICDEVICE) goto error; nxt6000_attach()
566 memcpy(&state->frontend.ops, &nxt6000_ops, sizeof(struct dvb_frontend_ops)); nxt6000_attach()
567 state->frontend.demodulator_priv = state; nxt6000_attach()
568 return &state->frontend; nxt6000_attach()
571 kfree(state); nxt6000_attach()
H A Dcx24117.c269 static int cx24117_writereg(struct cx24117_state *state, u8 reg, u8 data) cx24117_writereg() argument
272 struct i2c_msg msg = { .addr = state->priv->demod_address, cx24117_writereg()
276 dev_dbg(&state->priv->i2c->dev, cx24117_writereg()
278 __func__, state->demod, reg, data); cx24117_writereg()
280 ret = i2c_transfer(state->priv->i2c, &msg, 1); cx24117_writereg()
282 dev_warn(&state->priv->i2c->dev, cx24117_writereg()
284 KBUILD_MODNAME, state->demod, ret, reg, data); cx24117_writereg()
290 static int cx24117_writecmd(struct cx24117_state *state, cx24117_writecmd() argument
297 dev_dbg(&state->priv->i2c->dev, cx24117_writecmd()
299 __func__, state->demod, cmd->len); cx24117_writecmd()
304 msg.addr = state->priv->demod_address; cx24117_writecmd()
308 ret = i2c_transfer(state->priv->i2c, &msg, 1); cx24117_writecmd()
310 dev_warn(&state->priv->i2c->dev, cx24117_writecmd()
312 KBUILD_MODNAME, state->demod, ret, cmd->len); cx24117_writecmd()
318 static int cx24117_readreg(struct cx24117_state *state, u8 reg) cx24117_readreg() argument
323 { .addr = state->priv->demod_address, .flags = 0, cx24117_readreg()
325 { .addr = state->priv->demod_address, .flags = I2C_M_RD, cx24117_readreg()
329 ret = i2c_transfer(state->priv->i2c, msg, 2); cx24117_readreg()
331 dev_warn(&state->priv->i2c->dev, cx24117_readreg()
333 KBUILD_MODNAME, state->demod, ret, reg); cx24117_readreg()
337 dev_dbg(&state->priv->i2c->dev, "%s() demod%d i2c rd @0x%02x=0x%02x\n", cx24117_readreg()
338 __func__, state->demod, reg, recv); cx24117_readreg()
343 static int cx24117_readregN(struct cx24117_state *state, cx24117_readregN() argument
348 { .addr = state->priv->demod_address, .flags = 0, cx24117_readregN()
350 { .addr = state->priv->demod_address, .flags = I2C_M_RD, cx24117_readregN()
354 ret = i2c_transfer(state->priv->i2c, msg, 2); cx24117_readregN()
356 dev_warn(&state->priv->i2c->dev, cx24117_readregN()
358 KBUILD_MODNAME, state->demod, ret, reg); cx24117_readregN()
364 static int cx24117_set_inversion(struct cx24117_state *state, cx24117_set_inversion() argument
367 dev_dbg(&state->priv->i2c->dev, "%s(%d) demod%d\n", cx24117_set_inversion()
368 __func__, inversion, state->demod); cx24117_set_inversion()
372 state->dnxt.inversion_val = 0x00; cx24117_set_inversion()
375 state->dnxt.inversion_val = 0x04; cx24117_set_inversion()
378 state->dnxt.inversion_val = 0x0C; cx24117_set_inversion()
384 state->dnxt.inversion = inversion; cx24117_set_inversion()
389 static int cx24117_lookup_fecmod(struct cx24117_state *state, cx24117_lookup_fecmod() argument
394 dev_dbg(&state->priv->i2c->dev, cx24117_lookup_fecmod()
396 __func__, m, f, state->demod); cx24117_lookup_fecmod()
410 static int cx24117_set_fec(struct cx24117_state *state, cx24117_set_fec() argument
415 dev_dbg(&state->priv->i2c->dev, cx24117_set_fec()
417 __func__, mod, fec, state->demod); cx24117_set_fec()
419 ret = cx24117_lookup_fecmod(state, delsys, mod, fec); cx24117_set_fec()
423 state->dnxt.fec = fec; cx24117_set_fec()
424 state->dnxt.fec_val = cx24117_modfec_modes[ret].val; cx24117_set_fec()
425 state->dnxt.fec_mask = cx24117_modfec_modes[ret].mask; cx24117_set_fec()
426 dev_dbg(&state->priv->i2c->dev, cx24117_set_fec()
428 state->demod, state->dnxt.fec_mask, state->dnxt.fec_val); cx24117_set_fec()
433 static int cx24117_set_symbolrate(struct cx24117_state *state, u32 rate) cx24117_set_symbolrate() argument
435 dev_dbg(&state->priv->i2c->dev, "%s(%d) demod%d\n", cx24117_set_symbolrate()
436 __func__, rate, state->demod); cx24117_set_symbolrate()
438 state->dnxt.symbol_rate = rate; cx24117_set_symbolrate()
440 dev_dbg(&state->priv->i2c->dev, cx24117_set_symbolrate()
442 __func__, state->demod, rate); cx24117_set_symbolrate()
452 struct cx24117_state *state = fe->demodulator_priv; cx24117_firmware_ondemand() local
456 dev_dbg(&state->priv->i2c->dev, "%s() demod%d skip_fw_load=%d\n", cx24117_firmware_ondemand()
457 __func__, state->demod, state->priv->skip_fw_load); cx24117_firmware_ondemand()
459 if (state->priv->skip_fw_load) cx24117_firmware_ondemand()
463 if (cx24117_readreg(state, 0xeb) != 0xa) { cx24117_firmware_ondemand()
466 dev_dbg(&state->priv->i2c->dev, cx24117_firmware_ondemand()
470 state->priv->i2c->dev.parent); cx24117_firmware_ondemand()
471 dev_dbg(&state->priv->i2c->dev, cx24117_firmware_ondemand()
474 dev_err(&state->priv->i2c->dev, cx24117_firmware_ondemand()
482 state->priv->skip_fw_load = 1; cx24117_firmware_ondemand()
486 dev_err(&state->priv->i2c->dev, cx24117_firmware_ondemand()
490 dev_info(&state->priv->i2c->dev, cx24117_firmware_ondemand()
495 state->priv->skip_fw_load = 0; cx24117_firmware_ondemand()
507 struct cx24117_state *state = fe->demodulator_priv; cx24117_cmd_execute_nolock() local
510 dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n", cx24117_cmd_execute_nolock()
511 __func__, state->demod); cx24117_cmd_execute_nolock()
519 cx24117_writecmd(state, cmd); cx24117_cmd_execute_nolock()
522 cx24117_writereg(state, CX24117_REG_EXECUTE, 0x01); cx24117_cmd_execute_nolock()
524 while (cx24117_readreg(state, CX24117_REG_EXECUTE)) { cx24117_cmd_execute_nolock()
529 dev_warn(&state->priv->i2c->dev, cx24117_cmd_execute_nolock()
539 struct cx24117_state *state = fe->demodulator_priv; cx24117_cmd_execute() local
542 mutex_lock(&state->priv->fe_lock); cx24117_cmd_execute()
544 mutex_unlock(&state->priv->fe_lock); cx24117_cmd_execute()
552 struct cx24117_state *state = fe->demodulator_priv; cx24117_load_firmware() local
560 dev_dbg(&state->priv->i2c->dev, cx24117_load_firmware()
562 __func__, state->demod, fw->size, fw->data[0], fw->data[1], cx24117_load_firmware()
565 cx24117_writereg(state, 0xea, 0x00); cx24117_load_firmware()
566 cx24117_writereg(state, 0xea, 0x01); cx24117_load_firmware()
567 cx24117_writereg(state, 0xea, 0x00); cx24117_load_firmware()
569 cx24117_writereg(state, 0xce, 0x92); cx24117_load_firmware()
571 cx24117_writereg(state, 0xfb, 0x00); cx24117_load_firmware()
572 cx24117_writereg(state, 0xfc, 0x00); cx24117_load_firmware()
574 cx24117_writereg(state, 0xc3, 0x04); cx24117_load_firmware()
575 cx24117_writereg(state, 0xc4, 0x04); cx24117_load_firmware()
577 cx24117_writereg(state, 0xce, 0x00); cx24117_load_firmware()
578 cx24117_writereg(state, 0xcf, 0x00); cx24117_load_firmware()
580 cx24117_writereg(state, 0xea, 0x00); cx24117_load_firmware()
581 cx24117_writereg(state, 0xeb, 0x0c); cx24117_load_firmware()
582 cx24117_writereg(state, 0xec, 0x06); cx24117_load_firmware()
583 cx24117_writereg(state, 0xed, 0x05); cx24117_load_firmware()
584 cx24117_writereg(state, 0xee, 0x03); cx24117_load_firmware()
585 cx24117_writereg(state, 0xef, 0x05); cx24117_load_firmware()
587 cx24117_writereg(state, 0xf3, 0x03); cx24117_load_firmware()
588 cx24117_writereg(state, 0xf4, 0x44); cx24117_load_firmware()
590 cx24117_writereg(state, CX24117_REG_RATEDIV0, 0x04); cx24117_load_firmware()
591 cx24117_writereg(state, CX24117_REG_CLKDIV0, 0x02); cx24117_load_firmware()
593 cx24117_writereg(state, CX24117_REG_RATEDIV1, 0x04); cx24117_load_firmware()
594 cx24117_writereg(state, CX24117_REG_CLKDIV1, 0x02); cx24117_load_firmware()
596 cx24117_writereg(state, 0xf2, 0x04); cx24117_load_firmware()
597 cx24117_writereg(state, 0xe8, 0x02); cx24117_load_firmware()
598 cx24117_writereg(state, 0xea, 0x01); cx24117_load_firmware()
599 cx24117_writereg(state, 0xc8, 0x00); cx24117_load_firmware()
600 cx24117_writereg(state, 0xc9, 0x00); cx24117_load_firmware()
601 cx24117_writereg(state, 0xca, 0x00); cx24117_load_firmware()
602 cx24117_writereg(state, 0xcb, 0x00); cx24117_load_firmware()
603 cx24117_writereg(state, 0xcc, 0x00); cx24117_load_firmware()
604 cx24117_writereg(state, 0xcd, 0x00); cx24117_load_firmware()
605 cx24117_writereg(state, 0xe4, 0x03); cx24117_load_firmware()
606 cx24117_writereg(state, 0xeb, 0x0a); cx24117_load_firmware()
608 cx24117_writereg(state, 0xfb, 0x00); cx24117_load_firmware()
609 cx24117_writereg(state, 0xe0, 0x76); cx24117_load_firmware()
610 cx24117_writereg(state, 0xf7, 0x81); cx24117_load_firmware()
611 cx24117_writereg(state, 0xf8, 0x00); cx24117_load_firmware()
612 cx24117_writereg(state, 0xf9, 0x00); cx24117_load_firmware()
616 state->priv->skip_fw_load = 0; cx24117_load_firmware()
625 msg.addr = state->priv->demod_address; cx24117_load_firmware()
631 ret = i2c_transfer(state->priv->i2c, &msg, 1); cx24117_load_firmware()
637 cx24117_writereg(state, 0xf7, 0x0c); cx24117_load_firmware()
638 cx24117_writereg(state, 0xe0, 0x00); cx24117_load_firmware()
716 cx24117_writereg(state, 0xce, 0xc0); cx24117_load_firmware()
717 cx24117_writereg(state, 0xcf, 0x00); cx24117_load_firmware()
718 cx24117_writereg(state, 0xe5, 0x04); cx24117_load_firmware()
728 vers[i] = cx24117_readreg(state, 0x33); cx24117_load_firmware()
730 dev_info(&state->priv->i2c->dev, cx24117_load_firmware()
735 state->priv->skip_fw_load = 0; cx24117_load_firmware()
736 dev_err(&state->priv->i2c->dev, "%s() Error running FW.\n", __func__); cx24117_load_firmware()
742 struct cx24117_state *state = fe->demodulator_priv; cx24117_read_status() local
745 lock = cx24117_readreg(state, cx24117_read_status()
746 (state->demod == 0) ? CX24117_REG_SSTATUS0 : cx24117_read_status()
750 dev_dbg(&state->priv->i2c->dev, "%s() demod%d status = 0x%02x\n", cx24117_read_status()
751 __func__, state->demod, lock); cx24117_read_status()
769 struct cx24117_state *state = fe->demodulator_priv; cx24117_read_ber() local
772 u8 base_reg = (state->demod == 0) ? cx24117_read_ber()
776 ret = cx24117_readregN(state, base_reg, buf, 4); cx24117_read_ber()
783 dev_dbg(&state->priv->i2c->dev, "%s() demod%d ber=0x%04x\n", cx24117_read_ber()
784 __func__, state->demod, *ber); cx24117_read_ber()
792 struct cx24117_state *state = fe->demodulator_priv; cx24117_read_signal_strength() local
797 u8 reg = (state->demod == 0) ? cx24117_read_signal_strength()
802 cmd.args[1] = (u8) state->demod; cx24117_read_signal_strength()
808 ret = cx24117_readregN(state, reg, buf, 2); cx24117_read_signal_strength()
815 dev_dbg(&state->priv->i2c->dev, cx24117_read_signal_strength()
817 __func__, state->demod, sig_reading, *signal_strength); cx24117_read_signal_strength()
824 struct cx24117_state *state = fe->demodulator_priv; cx24117_read_snr() local
827 u8 reg = (state->demod == 0) ? cx24117_read_snr()
830 ret = cx24117_readregN(state, reg, buf, 2); cx24117_read_snr()
836 dev_dbg(&state->priv->i2c->dev, cx24117_read_snr()
838 __func__, state->demod, *snr); cx24117_read_snr()
845 struct cx24117_state *state = fe->demodulator_priv; cx24117_read_ucblocks() local
849 u8 reg = (state->demod == 0) ? cx24117_read_ucblocks()
863 ret = cx24117_readregN(state, reg, buf, 2); cx24117_read_ucblocks()
868 dev_dbg(&state->priv->i2c->dev, "%s() demod%d ucb=0x%04x\n", cx24117_read_ucblocks()
869 __func__, state->demod, *ucblocks); cx24117_read_ucblocks()
877 struct cx24117_state *state = fe->demodulator_priv; cx24117_clone_params() local
878 state->dcur = state->dnxt; cx24117_clone_params()
884 struct cx24117_state *state = fe->demodulator_priv; cx24117_wait_for_lnb() local
886 u8 val, reg = (state->demod == 0) ? CX24117_REG_QSTATUS0 : cx24117_wait_for_lnb()
889 dev_dbg(&state->priv->i2c->dev, "%s() demod%d qstatus = 0x%02x\n", cx24117_wait_for_lnb()
890 __func__, state->demod, cx24117_readreg(state, reg)); cx24117_wait_for_lnb()
894 val = cx24117_readreg(state, reg) & 0x01; cx24117_wait_for_lnb()
900 dev_warn(&state->priv->i2c->dev, "%s: demod%d LNB not ready\n", cx24117_wait_for_lnb()
901 KBUILD_MODNAME, state->demod); cx24117_wait_for_lnb()
909 struct cx24117_state *state = fe->demodulator_priv; cx24117_set_voltage() local
912 u8 reg = (state->demod == 0) ? 0x10 : 0x20; cx24117_set_voltage()
914 dev_dbg(&state->priv->i2c->dev, "%s() demod%d %s\n", cx24117_set_voltage()
915 __func__, state->demod, cx24117_set_voltage()
942 cmd.args[1] = state->demod ? 0 : 1; cx24117_set_voltage()
961 struct cx24117_state *state = fe->demodulator_priv; cx24117_set_tone() local
965 dev_dbg(&state->priv->i2c->dev, "%s(%d) demod%d\n", cx24117_set_tone()
966 __func__, state->demod, tone); cx24117_set_tone()
968 dev_warn(&state->priv->i2c->dev, "%s: demod%d invalid tone=%d\n", cx24117_set_tone()
969 KBUILD_MODNAME, state->demod, tone); cx24117_set_tone()
983 cmd.args[1] = (state->demod ? 0 : 1); cx24117_set_tone()
1004 struct cx24117_state *state = fe->demodulator_priv; cx24117_diseqc_init() local
1007 state->dsec_cmd.args[0] = CMD_LNBSEND; cx24117_diseqc_init()
1010 state->dsec_cmd.args[CX24117_DISEQC_DEMOD] = state->demod ? 0 : 1; cx24117_diseqc_init()
1013 state->dsec_cmd.args[CX24117_DISEQC_BURST] = CX24117_DISEQC_MINI_A; cx24117_diseqc_init()
1016 state->dsec_cmd.args[CX24117_DISEQC_ARG3_2] = 0x02; cx24117_diseqc_init()
1017 state->dsec_cmd.args[CX24117_DISEQC_ARG4_0] = 0x00; cx24117_diseqc_init()
1020 state->dsec_cmd.args[CX24117_DISEQC_ARG5_0] = 0x00; cx24117_diseqc_init()
1023 state->dsec_cmd.args[CX24117_DISEQC_MSGLEN] = 0x00; cx24117_diseqc_init()
1026 state->dsec_cmd.len = 7; cx24117_diseqc_init()
1035 struct cx24117_state *state = fe->demodulator_priv; cx24117_send_diseqc_msg() local
1039 dev_dbg(&state->priv->i2c->dev, "%s: demod %d (", cx24117_send_diseqc_msg()
1040 __func__, state->demod); cx24117_send_diseqc_msg()
1042 dev_dbg(&state->priv->i2c->dev, "0x%02x ", d->msg[i]); cx24117_send_diseqc_msg()
1043 dev_dbg(&state->priv->i2c->dev, ")\n"); cx24117_send_diseqc_msg()
1051 state->dsec_cmd.args[CX24117_DISEQC_MSGOFS + i] = d->msg[i]; cx24117_send_diseqc_msg()
1054 state->dsec_cmd.args[CX24117_DISEQC_MSGLEN] = d->msg_len; cx24117_send_diseqc_msg()
1057 state->dsec_cmd.len = CX24117_DISEQC_MSGOFS + cx24117_send_diseqc_msg()
1058 state->dsec_cmd.args[CX24117_DISEQC_MSGLEN]; cx24117_send_diseqc_msg()
1079 state->dsec_cmd.args[CX24117_DISEQC_BURST] = cx24117_send_diseqc_msg()
1082 dev_dbg(&state->priv->i2c->dev, "%s() demod%d burst=%d\n", cx24117_send_diseqc_msg()
1083 __func__, state->demod, cx24117_send_diseqc_msg()
1084 state->dsec_cmd.args[CX24117_DISEQC_BURST]); cx24117_send_diseqc_msg()
1095 ret = cx24117_cmd_execute(fe, &state->dsec_cmd); cx24117_send_diseqc_msg()
1108 msleep((state->dsec_cmd.args[CX24117_DISEQC_MSGLEN] << 4) + 60); cx24117_send_diseqc_msg()
1117 struct cx24117_state *state = fe->demodulator_priv; cx24117_diseqc_send_burst() local
1119 dev_dbg(&state->priv->i2c->dev, "%s(%d) demod=%d\n", cx24117_diseqc_send_burst()
1120 __func__, burst, state->demod); cx24117_diseqc_send_burst()
1124 state->dsec_cmd.args[CX24117_DISEQC_BURST] = cx24117_diseqc_send_burst()
1127 state->dsec_cmd.args[CX24117_DISEQC_BURST] = cx24117_diseqc_send_burst()
1158 struct cx24117_state *state = fe->demodulator_priv; cx24117_release() local
1159 dev_dbg(&state->priv->i2c->dev, "%s demod%d\n", cx24117_release()
1160 __func__, state->demod); cx24117_release()
1161 cx24117_release_priv(state->priv); cx24117_release()
1162 kfree(state); cx24117_release()
1170 struct cx24117_state *state = NULL; cx24117_attach() local
1195 /* allocate memory for the internal state */ cx24117_attach()
1196 state = kzalloc(sizeof(struct cx24117_state), GFP_KERNEL); cx24117_attach()
1197 if (state == NULL) cx24117_attach()
1200 state->demod = demod - 1; cx24117_attach()
1201 state->priv = priv; cx24117_attach()
1203 dev_info(&state->priv->i2c->dev, cx24117_attach()
1205 KBUILD_MODNAME, state->demod); cx24117_attach()
1208 memcpy(&state->frontend.ops, &cx24117_ops, cx24117_attach()
1210 state->frontend.demodulator_priv = state; cx24117_attach()
1211 return &state->frontend; cx24117_attach()
1227 struct cx24117_state *state = fe->demodulator_priv; cx24117_initfe() local
1231 dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n", cx24117_initfe()
1232 __func__, state->demod); cx24117_initfe()
1234 mutex_lock(&state->priv->fe_lock); cx24117_initfe()
1238 cmd.args[1] = (state->demod ? 1 : 0); cx24117_initfe()
1251 cmd.args[1] = (state->demod ? 1 : 0); cx24117_initfe()
1261 cmd.args[1] = (state->demod ? 1 : 0); cx24117_initfe()
1277 mutex_unlock(&state->priv->fe_lock); cx24117_initfe()
1287 struct cx24117_state *state = fe->demodulator_priv; cx24117_sleep() local
1290 dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n", cx24117_sleep()
1291 __func__, state->demod); cx24117_sleep()
1295 cmd.args[1] = (state->demod ? 1 : 0); cx24117_sleep()
1306 struct cx24117_state *state = fe->demodulator_priv; cx24117_set_frontend() local
1313 dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n", cx24117_set_frontend()
1314 __func__, state->demod); cx24117_set_frontend()
1318 dev_dbg(&state->priv->i2c->dev, "%s() demod%d DVB-S\n", cx24117_set_frontend()
1319 __func__, state->demod); cx24117_set_frontend()
1323 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1325 __func__, state->demod, c->modulation); cx24117_set_frontend()
1330 state->dnxt.pilot_val = CX24117_PILOT_OFF; cx24117_set_frontend()
1333 state->dnxt.rolloff_val = CX24117_ROLLOFF_035; cx24117_set_frontend()
1337 dev_dbg(&state->priv->i2c->dev, "%s() demod%d DVB-S2\n", cx24117_set_frontend()
1338 __func__, state->demod); cx24117_set_frontend()
1345 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1347 __func__, state->demod, c->modulation); cx24117_set_frontend()
1353 state->dnxt.pilot_val = CX24117_PILOT_AUTO; cx24117_set_frontend()
1356 state->dnxt.pilot_val = CX24117_PILOT_OFF; cx24117_set_frontend()
1359 state->dnxt.pilot_val = CX24117_PILOT_ON; cx24117_set_frontend()
1362 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1364 __func__, state->demod, c->pilot); cx24117_set_frontend()
1370 state->dnxt.rolloff_val = CX24117_ROLLOFF_020; cx24117_set_frontend()
1373 state->dnxt.rolloff_val = CX24117_ROLLOFF_025; cx24117_set_frontend()
1376 state->dnxt.rolloff_val = CX24117_ROLLOFF_035; cx24117_set_frontend()
1379 state->dnxt.rolloff_val = CX24117_ROLLOFF_035; cx24117_set_frontend()
1384 dev_warn(&state->priv->i2c->dev, cx24117_set_frontend()
1386 KBUILD_MODNAME, state->demod, c->rolloff); cx24117_set_frontend()
1392 dev_warn(&state->priv->i2c->dev, cx24117_set_frontend()
1394 KBUILD_MODNAME, state->demod, c->delivery_system); cx24117_set_frontend()
1398 state->dnxt.delsys = c->delivery_system; cx24117_set_frontend()
1399 state->dnxt.modulation = c->modulation; cx24117_set_frontend()
1400 state->dnxt.frequency = c->frequency; cx24117_set_frontend()
1401 state->dnxt.pilot = c->pilot; cx24117_set_frontend()
1402 state->dnxt.rolloff = c->rolloff; cx24117_set_frontend()
1404 ret = cx24117_set_inversion(state, c->inversion); cx24117_set_frontend()
1408 ret = cx24117_set_fec(state, cx24117_set_frontend()
1413 ret = cx24117_set_symbolrate(state, c->symbol_rate); cx24117_set_frontend()
1420 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1421 "%s: delsys = %d\n", __func__, state->dcur.delsys); cx24117_set_frontend()
1422 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1423 "%s: modulation = %d\n", __func__, state->dcur.modulation); cx24117_set_frontend()
1424 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1425 "%s: frequency = %d\n", __func__, state->dcur.frequency); cx24117_set_frontend()
1426 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1428 state->dcur.pilot, state->dcur.pilot_val); cx24117_set_frontend()
1429 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1431 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1433 state->dcur.rolloff, state->dcur.rolloff_val); cx24117_set_frontend()
1434 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1435 "%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate); cx24117_set_frontend()
1436 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1438 state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val); cx24117_set_frontend()
1439 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1441 state->dcur.inversion, state->dcur.inversion_val); cx24117_set_frontend()
1447 cmd.args[1] = state->demod; cx24117_set_frontend()
1450 cmd.args[2] = (state->dcur.frequency & 0xff0000) >> 16; cx24117_set_frontend()
1451 cmd.args[3] = (state->dcur.frequency & 0x00ff00) >> 8; cx24117_set_frontend()
1452 cmd.args[4] = (state->dcur.frequency & 0x0000ff); cx24117_set_frontend()
1455 cmd.args[5] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8; cx24117_set_frontend()
1456 cmd.args[6] = ((state->dcur.symbol_rate / 1000) & 0x00ff); cx24117_set_frontend()
1459 cmd.args[7] = state->dcur.inversion_val; cx24117_set_frontend()
1462 cmd.args[8] = state->dcur.fec_val | state->dcur.pilot_val; cx24117_set_frontend()
1467 cmd.args[11] = state->dcur.rolloff_val; cx24117_set_frontend()
1468 cmd.args[12] = state->dcur.fec_mask; cx24117_set_frontend()
1470 if (state->dcur.symbol_rate > 30000000) { cx24117_set_frontend()
1473 } else if (state->dcur.symbol_rate > 10000000) { cx24117_set_frontend()
1484 cx24117_writereg(state, (state->demod == 0) ? cx24117_set_frontend()
1486 cx24117_writereg(state, (state->demod == 0) ? cx24117_set_frontend()
1494 status = cx24117_readreg(state, (state->demod == 0) ? cx24117_set_frontend()
1498 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1500 __func__, state->demod, status); cx24117_set_frontend()
1502 cx24117_writereg(state, (state->demod == 0) ? cx24117_set_frontend()
1520 dev_dbg(&state->priv->i2c->dev, cx24117_set_frontend()
1522 __func__, state->demod); cx24117_set_frontend()
1528 dev_dbg(&state->priv->i2c->dev, "%s() demod%d not tuned\n", cx24117_set_frontend()
1529 __func__, state->demod); cx24117_set_frontend()
1532 if (state->dcur.rolloff == 3) cx24117_set_frontend()
1542 struct cx24117_state *state = fe->demodulator_priv; cx24117_tune() local
1544 dev_dbg(&state->priv->i2c->dev, "%s() demod%d\n", cx24117_tune()
1545 __func__, state->demod); cx24117_tune()
1563 struct cx24117_state *state = fe->demodulator_priv; cx24117_get_frontend() local
1575 cmd.args[1] = (u8) state->demod; cx24117_get_frontend()
1582 reg = (state->demod == 0) ? CX24117_REG_FREQ3_0 : CX24117_REG_FREQ3_1; cx24117_get_frontend()
1583 ret = cx24117_readregN(state, reg, buf, 0x1f-4); cx24117_get_frontend()
1590 inv = (((state->demod == 0) ? ~st : st) >> 6) & 1; cx24117_get_frontend()
1615 c->symbol_rate = -1000 * srate_os + state->dcur.symbol_rate; cx24117_get_frontend()
H A Ds5h1432.c55 static int s5h1432_writereg(struct s5h1432_state *state, s5h1432_writereg() argument
63 ret = i2c_transfer(state->i2c, &msg, 1); s5h1432_writereg()
72 static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg) s5h1432_readreg() argument
83 ret = i2c_transfer(state->i2c, msg, 2); s5h1432_readreg()
99 struct s5h1432_state *state = fe->demodulator_priv; s5h1432_set_channel_bandwidth() local
104 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E); s5h1432_set_channel_bandwidth()
119 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg); s5h1432_set_channel_bandwidth()
125 struct s5h1432_state *state = fe->demodulator_priv; s5h1432_set_IF() local
129 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55); s5h1432_set_IF()
130 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55); s5h1432_set_IF()
131 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15); s5h1432_set_IF()
134 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00); s5h1432_set_IF()
135 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00); s5h1432_set_IF()
136 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40); s5h1432_set_IF()
139 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00); s5h1432_set_IF()
140 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00); s5h1432_set_IF()
141 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0); s5h1432_set_IF()
144 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66); s5h1432_set_IF()
145 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66); s5h1432_set_IF()
146 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE); s5h1432_set_IF()
149 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55); s5h1432_set_IF()
150 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55); s5h1432_set_IF()
151 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED); s5h1432_set_IF()
154 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA); s5h1432_set_IF()
155 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA); s5h1432_set_IF()
156 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA); s5h1432_set_IF()
166 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, s5h1432_set_IF()
168 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, s5h1432_set_IF()
170 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, s5h1432_set_IF()
185 struct s5h1432_state *state = fe->demodulator_priv; s5h1432_set_frontend() local
187 if (p->frequency == state->current_frequency) { s5h1432_set_frontend()
189 /*state->current_frequency = p->frequency; */ s5h1432_set_frontend()
213 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); s5h1432_set_frontend()
215 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); s5h1432_set_frontend()
237 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); s5h1432_set_frontend()
239 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); s5h1432_set_frontend()
243 state->current_frequency = p->frequency; s5h1432_set_frontend()
250 struct s5h1432_state *state = fe->demodulator_priv; s5h1432_init() local
253 state->current_frequency = 0; s5h1432_init()
259 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8); s5h1432_init()
260 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01); s5h1432_init()
261 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70); s5h1432_init()
262 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80); s5h1432_init()
263 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D); s5h1432_init()
264 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30); s5h1432_init()
265 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20); s5h1432_init()
266 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B); s5h1432_init()
267 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40); s5h1432_init()
268 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84); s5h1432_init()
269 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a); s5h1432_init()
270 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3); s5h1432_init()
271 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50); s5h1432_init()
272 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c); s5h1432_init()
273 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10); s5h1432_init()
274 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c); s5h1432_init()
275 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00); s5h1432_init()
276 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94); s5h1432_init()
277 /* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */ s5h1432_init()
278 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00); s5h1432_init()
283 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66); s5h1432_init()
284 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66); s5h1432_init()
285 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE); s5h1432_init()
287 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31); s5h1432_init()
290 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42); s5h1432_init()
292 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg); s5h1432_init()
297 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); s5h1432_init()
299 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); s5h1432_init()
340 struct s5h1432_state *state = fe->demodulator_priv; s5h1432_release() local
341 kfree(state); s5h1432_release()
349 struct s5h1432_state *state = NULL; s5h1432_attach() local
352 /* allocate memory for the internal state */ s5h1432_attach()
353 state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL); s5h1432_attach()
354 if (!state) s5h1432_attach()
357 /* setup the state */ s5h1432_attach()
358 state->config = config; s5h1432_attach()
359 state->i2c = i2c; s5h1432_attach()
360 state->current_modulation = QAM_16; s5h1432_attach()
361 state->inversion = state->config->inversion; s5h1432_attach()
364 memcpy(&state->frontend.ops, &s5h1432_ops, s5h1432_attach()
367 state->frontend.demodulator_priv = state; s5h1432_attach()
369 return &state->frontend; s5h1432_attach()
H A Dlgdt3306a.c112 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
113 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
117 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) lgdt3306a_write_reg() argument
122 .addr = state->cfg->i2c_addr, .flags = 0, lgdt3306a_write_reg()
128 ret = i2c_transfer(state->i2c_adap, &msg, 1); lgdt3306a_write_reg()
141 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) lgdt3306a_read_reg() argument
146 { .addr = state->cfg->i2c_addr, lgdt3306a_read_reg()
148 { .addr = state->cfg->i2c_addr, lgdt3306a_read_reg()
152 ret = i2c_transfer(state->i2c_adap, msg, 2); lgdt3306a_read_reg()
156 state->cfg->i2c_addr, reg, ret); lgdt3306a_read_reg()
167 #define read_reg(state, reg) \
170 int ret = lgdt3306a_read_reg(state, reg, &__val); \
176 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state, lgdt3306a_set_reg_bit() argument
184 ret = lgdt3306a_read_reg(state, reg, &val); lgdt3306a_set_reg_bit()
191 ret = lgdt3306a_write_reg(state, reg, val); lgdt3306a_set_reg_bit()
199 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state) lgdt3306a_soft_reset() argument
205 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); lgdt3306a_soft_reset()
210 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); lgdt3306a_soft_reset()
217 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state, lgdt3306a_mpeg_mode() argument
225 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, lgdt3306a_mpeg_mode()
234 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); lgdt3306a_mpeg_mode()
238 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_mode()
247 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_mode()
254 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state, lgdt3306a_mpeg_mode_polarity() argument
263 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_mode_polarity()
274 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_mode_polarity()
281 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state, lgdt3306a_mpeg_tristate() argument
290 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_tristate()
298 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_tristate()
303 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); lgdt3306a_mpeg_tristate()
309 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); lgdt3306a_mpeg_tristate()
313 ret = lgdt3306a_read_reg(state, 0x0070, &val); lgdt3306a_mpeg_tristate()
318 ret = lgdt3306a_write_reg(state, 0x0070, val); lgdt3306a_mpeg_tristate()
329 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_ts_bus_ctrl() local
333 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1); lgdt3306a_ts_bus_ctrl()
337 static int lgdt3306a_power(struct lgdt3306a_state *state, lgdt3306a_power() argument
346 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); lgdt3306a_power()
351 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); lgdt3306a_power()
357 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); lgdt3306a_power()
362 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); lgdt3306a_power()
368 lgdt3306a_DumpAllRegs(state); lgdt3306a_power()
375 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state) lgdt3306a_set_vsb() argument
383 ret = lgdt3306a_read_reg(state, 0x0002, &val); lgdt3306a_set_vsb()
386 ret = lgdt3306a_write_reg(state, 0x0002, val); lgdt3306a_set_vsb()
391 ret = lgdt3306a_write_reg(state, 0x0008, 0x80); lgdt3306a_set_vsb()
396 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_vsb()
399 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_vsb()
404 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_vsb()
406 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_vsb()
411 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_set_vsb()
413 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_set_vsb()
420 ret = lgdt3306a_write_reg(state, 0x0024, 0x00); lgdt3306a_set_vsb()
425 ret = lgdt3306a_write_reg(state, 0x002e, 0x00); lgdt3306a_set_vsb()
426 ret = lgdt3306a_write_reg(state, 0x002f, 0x00); lgdt3306a_set_vsb()
427 ret = lgdt3306a_write_reg(state, 0x0030, 0x00); lgdt3306a_set_vsb()
430 ret = lgdt3306a_write_reg(state, 0x002b, 0x00); lgdt3306a_set_vsb()
431 ret = lgdt3306a_write_reg(state, 0x002c, 0x00); lgdt3306a_set_vsb()
432 ret = lgdt3306a_write_reg(state, 0x002d, 0x00); lgdt3306a_set_vsb()
435 ret = lgdt3306a_write_reg(state, 0x0028, 0x00); lgdt3306a_set_vsb()
436 ret = lgdt3306a_write_reg(state, 0x0029, 0x00); lgdt3306a_set_vsb()
437 ret = lgdt3306a_write_reg(state, 0x002a, 0x00); lgdt3306a_set_vsb()
440 ret = lgdt3306a_write_reg(state, 0x0025, 0x00); lgdt3306a_set_vsb()
441 ret = lgdt3306a_write_reg(state, 0x0026, 0x00); lgdt3306a_set_vsb()
442 ret = lgdt3306a_write_reg(state, 0x0027, 0x00); lgdt3306a_set_vsb()
448 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A); lgdt3306a_set_vsb()
453 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A); lgdt3306a_set_vsb()
454 ret = lgdt3306a_write_reg(state, 0x002f, 0x00); lgdt3306a_set_vsb()
455 ret = lgdt3306a_write_reg(state, 0x0030, 0x00); lgdt3306a_set_vsb()
458 ret = lgdt3306a_write_reg(state, 0x002b, 0x36); lgdt3306a_set_vsb()
459 ret = lgdt3306a_write_reg(state, 0x002c, 0x00); lgdt3306a_set_vsb()
460 ret = lgdt3306a_write_reg(state, 0x002d, 0x00); lgdt3306a_set_vsb()
463 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A); lgdt3306a_set_vsb()
464 ret = lgdt3306a_write_reg(state, 0x0029, 0x00); lgdt3306a_set_vsb()
465 ret = lgdt3306a_write_reg(state, 0x002a, 0x00); lgdt3306a_set_vsb()
468 ret = lgdt3306a_write_reg(state, 0x0025, 0x06); lgdt3306a_set_vsb()
469 ret = lgdt3306a_write_reg(state, 0x0026, 0x00); lgdt3306a_set_vsb()
470 ret = lgdt3306a_write_reg(state, 0x0027, 0x00); lgdt3306a_set_vsb()
473 ret = lgdt3306a_read_reg(state, 0x001e, &val); lgdt3306a_set_vsb()
476 ret = lgdt3306a_write_reg(state, 0x001e, val); lgdt3306a_set_vsb()
478 ret = lgdt3306a_write_reg(state, 0x0022, 0x08); lgdt3306a_set_vsb()
480 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF); lgdt3306a_set_vsb()
482 ret = lgdt3306a_read_reg(state, 0x211f, &val); lgdt3306a_set_vsb()
484 ret = lgdt3306a_write_reg(state, 0x211f, val); lgdt3306a_set_vsb()
486 ret = lgdt3306a_write_reg(state, 0x2173, 0x01); lgdt3306a_set_vsb()
488 ret = lgdt3306a_read_reg(state, 0x1061, &val); lgdt3306a_set_vsb()
491 ret = lgdt3306a_write_reg(state, 0x1061, val); lgdt3306a_set_vsb()
493 ret = lgdt3306a_read_reg(state, 0x103d, &val); lgdt3306a_set_vsb()
495 ret = lgdt3306a_write_reg(state, 0x103d, val); lgdt3306a_set_vsb()
497 ret = lgdt3306a_write_reg(state, 0x2122, 0x40); lgdt3306a_set_vsb()
499 ret = lgdt3306a_read_reg(state, 0x2141, &val); lgdt3306a_set_vsb()
501 ret = lgdt3306a_write_reg(state, 0x2141, val); lgdt3306a_set_vsb()
503 ret = lgdt3306a_read_reg(state, 0x2135, &val); lgdt3306a_set_vsb()
506 ret = lgdt3306a_write_reg(state, 0x2135, val); lgdt3306a_set_vsb()
508 ret = lgdt3306a_read_reg(state, 0x0003, &val); lgdt3306a_set_vsb()
510 ret = lgdt3306a_write_reg(state, 0x0003, val); lgdt3306a_set_vsb()
512 ret = lgdt3306a_read_reg(state, 0x001c, &val); lgdt3306a_set_vsb()
514 ret = lgdt3306a_write_reg(state, 0x001c, val); lgdt3306a_set_vsb()
517 ret = lgdt3306a_read_reg(state, 0x2179, &val); lgdt3306a_set_vsb()
519 ret = lgdt3306a_write_reg(state, 0x2179, val); lgdt3306a_set_vsb()
521 ret = lgdt3306a_read_reg(state, 0x217a, &val); lgdt3306a_set_vsb()
523 ret = lgdt3306a_write_reg(state, 0x217a, val); lgdt3306a_set_vsb()
526 ret = lgdt3306a_soft_reset(state); lgdt3306a_set_vsb()
535 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation) lgdt3306a_set_qam() argument
543 ret = lgdt3306a_write_reg(state, 0x0008, 0x08); lgdt3306a_set_qam()
548 ret = lgdt3306a_read_reg(state, 0x0002, &val); lgdt3306a_set_qam()
551 ret = lgdt3306a_write_reg(state, 0x0002, val); lgdt3306a_set_qam()
556 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_qam()
558 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_qam()
563 ret = lgdt3306a_read_reg(state, 0x0009, &val); lgdt3306a_set_qam()
566 ret = lgdt3306a_write_reg(state, 0x0009, val); lgdt3306a_set_qam()
571 ret = lgdt3306a_read_reg(state, 0x101a, &val); lgdt3306a_set_qam()
578 ret = lgdt3306a_write_reg(state, 0x101a, val); lgdt3306a_set_qam()
583 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_set_qam()
586 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_set_qam()
591 ret = lgdt3306a_read_reg(state, 0x0024, &val); lgdt3306a_set_qam()
593 ret = lgdt3306a_write_reg(state, 0x0024, val); lgdt3306a_set_qam()
598 ret = lgdt3306a_soft_reset(state); lgdt3306a_set_qam()
607 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state, lgdt3306a_set_modulation() argument
616 ret = lgdt3306a_set_vsb(state); lgdt3306a_set_modulation()
619 ret = lgdt3306a_set_qam(state, QAM_64); lgdt3306a_set_modulation()
622 ret = lgdt3306a_set_qam(state, QAM_256); lgdt3306a_set_modulation()
630 state->current_modulation = p->modulation; lgdt3306a_set_modulation()
638 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state, lgdt3306a_agc_setup() argument
658 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state, lgdt3306a_set_inversion() argument
665 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0); lgdt3306a_set_inversion()
669 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state, lgdt3306a_set_inversion_auto() argument
677 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled); lgdt3306a_set_inversion_auto()
681 static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state, lgdt3306a_spectral_inversion() argument
694 ret = lgdt3306a_set_inversion(state, inversion); lgdt3306a_spectral_inversion()
699 ret = lgdt3306a_set_inversion_auto(state, 0); lgdt3306a_spectral_inversion()
704 ret = lgdt3306a_set_inversion_auto(state, 1); lgdt3306a_spectral_inversion()
713 static int lgdt3306a_set_if(struct lgdt3306a_state *state, lgdt3306a_set_if() argument
722 if_freq_khz = state->cfg->vsb_if_khz; lgdt3306a_set_if()
726 if_freq_khz = state->cfg->qam_if_khz; lgdt3306a_set_if()
758 ret = lgdt3306a_write_reg(state, 0x0010, nco1); lgdt3306a_set_if()
761 ret = lgdt3306a_write_reg(state, 0x0011, nco2); lgdt3306a_set_if()
774 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_i2c_gate_ctrl() local
776 if (state->cfg->deny_i2c_rptr) { lgdt3306a_i2c_gate_ctrl()
777 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr); lgdt3306a_i2c_gate_ctrl()
783 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); lgdt3306a_i2c_gate_ctrl()
786 static int lgdt3306a_sleep(struct lgdt3306a_state *state) lgdt3306a_sleep() argument
791 state->current_frequency = -1; /* force re-tune, when we wake */ lgdt3306a_sleep()
793 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */ lgdt3306a_sleep()
797 ret = lgdt3306a_power(state, 0); /* power down */ lgdt3306a_sleep()
806 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_fe_sleep() local
808 return lgdt3306a_sleep(state); lgdt3306a_fe_sleep()
813 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_init() local
820 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */ lgdt3306a_init()
825 ret = lgdt3306a_set_inversion_auto(state, 0); lgdt3306a_init()
830 ret = lgdt3306a_set_inversion(state, 1); lgdt3306a_init()
837 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); lgdt3306a_init()
844 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); lgdt3306a_init()
851 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); lgdt3306a_init()
858 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); lgdt3306a_init()
862 if (state->cfg->xtalMHz == 24) { /* 24MHz */ lgdt3306a_init()
864 ret = lgdt3306a_read_reg(state, 0x0005, &val); lgdt3306a_init()
869 ret = lgdt3306a_write_reg(state, 0x0005, val); lgdt3306a_init()
872 ret = lgdt3306a_write_reg(state, 0x0006, 0x64); lgdt3306a_init()
877 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_init()
882 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_init()
886 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */ lgdt3306a_init()
888 ret = lgdt3306a_read_reg(state, 0x0005, &val); lgdt3306a_init()
893 ret = lgdt3306a_write_reg(state, 0x0005, val); lgdt3306a_init()
896 ret = lgdt3306a_write_reg(state, 0x0006, 0x64); lgdt3306a_init()
901 ret = lgdt3306a_read_reg(state, 0x000d, &val); lgdt3306a_init()
906 ret = lgdt3306a_write_reg(state, 0x000d, val); lgdt3306a_init()
910 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz); lgdt3306a_init()
913 ret = lgdt3306a_write_reg(state, 0x000e, 0x00); lgdt3306a_init()
914 ret = lgdt3306a_write_reg(state, 0x000f, 0x00); lgdt3306a_init()
918 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */ lgdt3306a_init()
919 ret = lgdt3306a_write_reg(state, 0x0011, 0x00); lgdt3306a_init()
922 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */ lgdt3306a_init()
925 ret = lgdt3306a_read_reg(state, 0x103c, &val); lgdt3306a_init()
928 ret = lgdt3306a_write_reg(state, 0x103c, val); lgdt3306a_init()
931 ret = lgdt3306a_read_reg(state, 0x103d, &val); lgdt3306a_init()
934 ret = lgdt3306a_write_reg(state, 0x103d, val); lgdt3306a_init()
937 ret = lgdt3306a_read_reg(state, 0x1036, &val); lgdt3306a_init()
940 ret = lgdt3306a_write_reg(state, 0x1036, val); lgdt3306a_init()
943 ret = lgdt3306a_read_reg(state, 0x211f, &val); lgdt3306a_init()
945 ret = lgdt3306a_write_reg(state, 0x211f, val); lgdt3306a_init()
948 ret = lgdt3306a_read_reg(state, 0x2849, &val); lgdt3306a_init()
950 ret = lgdt3306a_write_reg(state, 0x2849, val); lgdt3306a_init()
953 ret = lgdt3306a_set_vsb(state); lgdt3306a_init()
956 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode); lgdt3306a_init()
959 ret = lgdt3306a_mpeg_tristate(state, 1); lgdt3306a_init()
962 ret = lgdt3306a_sleep(state); lgdt3306a_init()
972 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_set_parameters() local
977 if (state->current_frequency == p->frequency && lgdt3306a_set_parameters()
978 state->current_modulation == p->modulation) { lgdt3306a_set_parameters()
982 state->current_frequency = -1; lgdt3306a_set_parameters()
983 state->current_modulation = -1; lgdt3306a_set_parameters()
985 ret = lgdt3306a_power(state, 1); /* power up */ lgdt3306a_set_parameters()
996 state->current_frequency = p->frequency; lgdt3306a_set_parameters()
1000 ret = lgdt3306a_set_modulation(state, p); lgdt3306a_set_parameters()
1004 ret = lgdt3306a_agc_setup(state, p); lgdt3306a_set_parameters()
1008 ret = lgdt3306a_set_if(state, p); lgdt3306a_set_parameters()
1012 ret = lgdt3306a_spectral_inversion(state, p, lgdt3306a_set_parameters()
1013 state->cfg->spectral_inversion ? 1 : 0); lgdt3306a_set_parameters()
1017 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode); lgdt3306a_set_parameters()
1021 ret = lgdt3306a_mpeg_mode_polarity(state, lgdt3306a_set_parameters()
1022 state->cfg->tpclk_edge, lgdt3306a_set_parameters()
1023 state->cfg->tpvalid_polarity); lgdt3306a_set_parameters()
1027 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */ lgdt3306a_set_parameters()
1031 ret = lgdt3306a_soft_reset(state); lgdt3306a_set_parameters()
1036 lgdt3306a_DumpAllRegs(state); lgdt3306a_set_parameters()
1038 state->current_frequency = p->frequency; lgdt3306a_set_parameters()
1045 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_get_frontend() local
1049 state->current_frequency, state->current_modulation); lgdt3306a_get_frontend()
1051 p->modulation = state->current_modulation; lgdt3306a_get_frontend()
1052 p->frequency = state->current_frequency; lgdt3306a_get_frontend()
1066 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state) lgdt3306a_monitor_vsb() argument
1073 ret = lgdt3306a_read_reg(state, 0x21a1, &val); lgdt3306a_monitor_vsb()
1078 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan); lgdt3306a_monitor_vsb()
1082 ret = lgdt3306a_read_reg(state, 0x2191, &val); lgdt3306a_monitor_vsb()
1087 ret = lgdt3306a_read_reg(state, 0x2180, &val); lgdt3306a_monitor_vsb()
1092 ret = lgdt3306a_read_reg(state, 0x2181, &val); lgdt3306a_monitor_vsb()
1101 ret = lgdt3306a_read_reg(state, 0x1061, &val); lgdt3306a_monitor_vsb()
1113 ret = lgdt3306a_write_reg(state, 0x1061, val); lgdt3306a_monitor_vsb()
1118 ret = lgdt3306a_read_reg(state, 0x0024, &val); lgdt3306a_monitor_vsb()
1125 ret = lgdt3306a_write_reg(state, 0x0024, val); lgdt3306a_monitor_vsb()
1130 ret = lgdt3306a_read_reg(state, 0x103d, &val); lgdt3306a_monitor_vsb()
1135 ret = lgdt3306a_write_reg(state, 0x103d, val); lgdt3306a_monitor_vsb()
1141 lgdt3306a_check_oper_mode(struct lgdt3306a_state *state) lgdt3306a_check_oper_mode() argument
1146 ret = lgdt3306a_read_reg(state, 0x0081, &val); lgdt3306a_check_oper_mode()
1155 ret = lgdt3306a_read_reg(state, 0x00a6, &val); lgdt3306a_check_oper_mode()
1172 lgdt3306a_check_lock_status(struct lgdt3306a_state *state, lgdt3306a_check_lock_status() argument
1185 ret = lgdt3306a_read_reg(state, 0x00a6, &val); lgdt3306a_check_lock_status()
1199 ret = lgdt3306a_read_reg(state, 0x0080, &val); lgdt3306a_check_lock_status()
1213 modeOper = lgdt3306a_check_oper_mode(state); lgdt3306a_check_lock_status()
1215 ret = lgdt3306a_read_reg(state, 0x1094, &val); lgdt3306a_check_lock_status()
1231 modeOper = lgdt3306a_check_oper_mode(state); lgdt3306a_check_lock_status()
1233 ret = lgdt3306a_read_reg(state, 0x0080, &val); lgdt3306a_check_lock_status()
1258 lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state) lgdt3306a_check_neverlock_status() argument
1264 ret = lgdt3306a_read_reg(state, 0x0080, &val); lgdt3306a_check_neverlock_status()
1274 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state) lgdt3306a_pre_monitoring() argument
1281 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ); lgdt3306a_pre_monitoring()
1286 ret = lgdt3306a_read_reg(state, 0x21a1, &val); lgdt3306a_pre_monitoring()
1292 ret = lgdt3306a_read_reg(state, 0x2199, &val); lgdt3306a_pre_monitoring()
1297 ret = lgdt3306a_read_reg(state, 0x0090, &val); lgdt3306a_pre_monitoring()
1310 ret = lgdt3306a_read_reg(state, 0x2135, &val); lgdt3306a_pre_monitoring()
1315 ret = lgdt3306a_write_reg(state, 0x2135, val); lgdt3306a_pre_monitoring()
1319 ret = lgdt3306a_read_reg(state, 0x2141, &val); lgdt3306a_pre_monitoring()
1324 ret = lgdt3306a_write_reg(state, 0x2141, val); lgdt3306a_pre_monitoring()
1328 ret = lgdt3306a_write_reg(state, 0x2122, 0x70); lgdt3306a_pre_monitoring()
1332 ret = lgdt3306a_read_reg(state, 0x2135, &val); lgdt3306a_pre_monitoring()
1337 ret = lgdt3306a_write_reg(state, 0x2135, val); lgdt3306a_pre_monitoring()
1341 ret = lgdt3306a_read_reg(state, 0x2141, &val); lgdt3306a_pre_monitoring()
1346 ret = lgdt3306a_write_reg(state, 0x2141, val); lgdt3306a_pre_monitoring()
1350 ret = lgdt3306a_write_reg(state, 0x2122, 0x40); lgdt3306a_pre_monitoring()
1358 lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state) lgdt3306a_sync_lock_poll() argument
1366 syncLockStatus = lgdt3306a_check_lock_status(state, lgdt3306a_sync_lock_poll()
1379 lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state) lgdt3306a_fec_lock_poll() argument
1387 FECLockStatus = lgdt3306a_check_lock_status(state, lgdt3306a_fec_lock_poll()
1400 lgdt3306a_neverlock_poll(struct lgdt3306a_state *state) lgdt3306a_neverlock_poll() argument
1408 NLLockStatus = lgdt3306a_check_neverlock_status(state); lgdt3306a_neverlock_poll()
1419 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state) lgdt3306a_get_packet_error() argument
1424 ret = lgdt3306a_read_reg(state, 0x00fa, &val); lgdt3306a_get_packet_error()
1483 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state) lgdt3306a_calculate_snr_x100() argument
1489 mse = (read_reg(state, 0x00ec) << 8) | lgdt3306a_calculate_snr_x100()
1490 (read_reg(state, 0x00ed)); lgdt3306a_calculate_snr_x100()
1491 pwr = (read_reg(state, 0x00e8) << 8) | lgdt3306a_calculate_snr_x100()
1492 (read_reg(state, 0x00e9)); lgdt3306a_calculate_snr_x100()
1504 lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state) lgdt3306a_vsb_lock_poll() argument
1512 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) { lgdt3306a_vsb_lock_poll()
1518 ret = lgdt3306a_pre_monitoring(state); lgdt3306a_vsb_lock_poll()
1522 packet_error = lgdt3306a_get_packet_error(state); lgdt3306a_vsb_lock_poll()
1523 snr = lgdt3306a_calculate_snr_x100(state); lgdt3306a_vsb_lock_poll()
1535 lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state) lgdt3306a_qam_lock_poll() argument
1542 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) { lgdt3306a_qam_lock_poll()
1549 packet_error = lgdt3306a_get_packet_error(state); lgdt3306a_qam_lock_poll()
1550 snr = lgdt3306a_calculate_snr_x100(state); lgdt3306a_qam_lock_poll()
1563 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_read_status() local
1576 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) { lgdt3306a_read_status()
1580 switch (state->current_modulation) { lgdt3306a_read_status()
1583 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) { lgdt3306a_read_status()
1591 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) { lgdt3306a_read_status()
1597 ret = lgdt3306a_monitor_vsb(state); lgdt3306a_read_status()
1610 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_read_snr() local
1612 state->snr = lgdt3306a_calculate_snr_x100(state); lgdt3306a_read_snr()
1614 *snr = state->snr/10; lgdt3306a_read_snr()
1625 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_read_signal_strength() local
1633 switch (state->current_modulation) { lgdt3306a_read_signal_strength()
1651 if (state->snr <= (ref_snr - 100)) lgdt3306a_read_signal_strength()
1653 else if (state->snr <= ref_snr) lgdt3306a_read_signal_strength()
1656 str = state->snr - ref_snr; lgdt3306a_read_signal_strength()
1674 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_read_ber() local
1681 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */ lgdt3306a_read_ber()
1682 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */ lgdt3306a_read_ber()
1683 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */ lgdt3306a_read_ber()
1684 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */ lgdt3306a_read_ber()
1693 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_read_ucblocks() local
1699 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */ lgdt3306a_read_ucblocks()
1711 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_tune() local
1716 state->current_frequency = -1; /* force re-tune */ lgdt3306a_tune()
1771 struct lgdt3306a_state *state = fe->demodulator_priv; lgdt3306a_release() local
1774 kfree(state); lgdt3306a_release()
1782 struct lgdt3306a_state *state = NULL; lgdt3306a_attach() local
1790 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL); lgdt3306a_attach()
1791 if (state == NULL) lgdt3306a_attach()
1794 state->cfg = config; lgdt3306a_attach()
1795 state->i2c_adap = i2c_adap; lgdt3306a_attach()
1797 memcpy(&state->frontend.ops, &lgdt3306a_ops, lgdt3306a_attach()
1799 state->frontend.demodulator_priv = state; lgdt3306a_attach()
1804 ret = lgdt3306a_read_reg(state, 0x0000, &val); lgdt3306a_attach()
1814 ret = lgdt3306a_read_reg(state, 0x0001, &val); lgdt3306a_attach()
1824 ret = lgdt3306a_read_reg(state, 0x0002, &val); lgdt3306a_attach()
1835 state->current_frequency = -1; lgdt3306a_attach()
1836 state->current_modulation = -1; lgdt3306a_attach()
1838 lgdt3306a_sleep(state); lgdt3306a_attach()
1840 return &state->frontend; lgdt3306a_attach()
1844 kfree(state); lgdt3306a_attach()
2083 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state) lgdt3306a_DumpAllRegs() argument
2086 lgdt3306a_DumpRegs(state); lgdt3306a_DumpAllRegs()
2089 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state) lgdt3306a_DumpRegs() argument
2101 lgdt3306a_read_reg(state, regtab[i], &regval1[i]); lgdt3306a_DumpRegs()
H A Dcx24110.c91 {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
116 static int cx24110_writereg (struct cx24110_state* state, int reg, int data) cx24110_writereg() argument
119 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; cx24110_writereg()
122 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { cx24110_writereg()
131 static int cx24110_readreg (struct cx24110_state* state, u8 reg) cx24110_readreg() argument
136 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, cx24110_readreg()
137 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; cx24110_readreg()
139 ret = i2c_transfer(state->i2c, msg, 2); cx24110_readreg()
146 static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion) cx24110_set_inversion() argument
152 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1); cx24110_set_inversion()
154 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7); cx24110_set_inversion()
156 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef); cx24110_set_inversion()
162 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1); cx24110_set_inversion()
164 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08); cx24110_set_inversion()
166 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10); cx24110_set_inversion()
170 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe); cx24110_set_inversion()
180 static int cx24110_set_fec(struct cx24110_state* state, fe_code_rate_t fec) cx24110_set_fec() argument
194 cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf); cx24110_set_fec()
196 cx24110_writereg(state, 0x18, 0xae); cx24110_set_fec()
198 cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3); cx24110_set_fec()
200 cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3); cx24110_set_fec()
202 cx24110_writereg(state, 0x1a, 0x05); cx24110_set_fec()
203 cx24110_writereg(state, 0x1b, 0x06); cx24110_set_fec()
207 cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20); cx24110_set_fec()
212 cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]); cx24110_set_fec()
214 cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]); cx24110_set_fec()
216 cx24110_writereg(state, 0x1a, g1[fec]); cx24110_set_fec()
217 cx24110_writereg(state, 0x1b, g2[fec]); cx24110_set_fec()
223 static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state) cx24110_get_fec() argument
227 i=cx24110_readreg(state,0x22)&0x0f; cx24110_get_fec()
239 static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate) cx24110_set_symbolrate() argument
259 tmp=cx24110_readreg(state,0x07)&0xfc; cx24110_set_symbolrate()
261 cx24110_writereg(state,0x07,tmp); cx24110_set_symbolrate()
262 cx24110_writereg(state,0x06,0x78); cx24110_set_symbolrate()
265 cx24110_writereg(state,0x07,tmp|0x1); cx24110_set_symbolrate()
266 cx24110_writereg(state,0x06,0xa5); cx24110_set_symbolrate()
269 cx24110_writereg(state,0x07,tmp|0x2); cx24110_set_symbolrate()
270 cx24110_writereg(state,0x06,0x87); cx24110_set_symbolrate()
273 cx24110_writereg(state,0x07,tmp|0x3); cx24110_set_symbolrate()
274 cx24110_writereg(state,0x06,0x78); cx24110_set_symbolrate()
303 cx24110_writereg(state, 0x1, (ratio>>16)&0xff); cx24110_set_symbolrate()
304 cx24110_writereg(state, 0x2, (ratio>>8)&0xff); cx24110_set_symbolrate()
305 cx24110_writereg(state, 0x3, (ratio)&0xff); cx24110_set_symbolrate()
313 struct cx24110_state *state = fe->demodulator_priv; _cx24110_pll_write() local
322 cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */ _cx24110_pll_write()
323 cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */ _cx24110_pll_write()
326 while (cx24110_readreg(state,0x6d)&0x80) _cx24110_pll_write()
327 cx24110_writereg(state,0x72,0); _cx24110_pll_write()
330 cx24110_writereg(state,0x72,buf[0]); _cx24110_pll_write()
333 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) _cx24110_pll_write()
337 cx24110_writereg(state,0x72,buf[1]); _cx24110_pll_write()
338 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) _cx24110_pll_write()
342 cx24110_writereg(state,0x72,buf[2]); _cx24110_pll_write()
343 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) _cx24110_pll_write()
347 cx24110_writereg(state,0x6d,0x32); _cx24110_pll_write()
348 cx24110_writereg(state,0x6d,0x30); _cx24110_pll_write()
355 struct cx24110_state *state = fe->demodulator_priv; cx24110_initfe() local
362 cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data); cx24110_initfe()
370 struct cx24110_state *state = fe->demodulator_priv; cx24110_set_voltage() local
374 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0); cx24110_set_voltage()
376 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40); cx24110_set_voltage()
385 struct cx24110_state *state = fe->demodulator_priv; cx24110_diseqc_send_burst() local
395 rv = cx24110_readreg(state, 0x77); cx24110_diseqc_send_burst()
397 cx24110_writereg(state, 0x77, rv | 0x04); cx24110_diseqc_send_burst()
399 rv = cx24110_readreg(state, 0x76); cx24110_diseqc_send_burst()
400 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit)); cx24110_diseqc_send_burst()
402 while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40)) cx24110_diseqc_send_burst()
412 struct cx24110_state *state = fe->demodulator_priv; cx24110_send_diseqc_msg() local
419 cx24110_writereg(state, 0x79 + i, cmd->msg[i]); cx24110_send_diseqc_msg()
421 rv = cx24110_readreg(state, 0x77); cx24110_send_diseqc_msg()
423 cx24110_writereg(state, 0x77, rv & ~0x04); cx24110_send_diseqc_msg()
427 rv = cx24110_readreg(state, 0x76); cx24110_send_diseqc_msg()
429 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); cx24110_send_diseqc_msg()
431 while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40)) cx24110_send_diseqc_msg()
439 struct cx24110_state *state = fe->demodulator_priv; cx24110_read_status() local
441 int sync = cx24110_readreg (state, 0x55); cx24110_read_status()
451 sync = cx24110_readreg (state, 0x08); cx24110_read_status()
467 struct cx24110_state *state = fe->demodulator_priv; cx24110_read_ber() local
470 if(cx24110_readreg(state,0x24)&0x10) { cx24110_read_ber()
472 cx24110_writereg(state,0x24,0x04); /* select the ber reg */ cx24110_read_ber()
473 state->lastber=cx24110_readreg(state,0x25)| cx24110_read_ber()
474 (cx24110_readreg(state,0x26)<<8); cx24110_read_ber()
475 cx24110_writereg(state,0x24,0x04); /* start new count window */ cx24110_read_ber()
476 cx24110_writereg(state,0x24,0x14); cx24110_read_ber()
478 *ber = state->lastber; cx24110_read_ber()
485 struct cx24110_state *state = fe->demodulator_priv; cx24110_read_signal_strength() local
488 u8 signal = cx24110_readreg (state, 0x27)+128; cx24110_read_signal_strength()
496 struct cx24110_state *state = fe->demodulator_priv; cx24110_read_snr() local
499 if(cx24110_readreg(state,0x6a)&0x80) { cx24110_read_snr()
501 state->lastesn0=cx24110_readreg(state,0x69)| cx24110_read_snr()
502 (cx24110_readreg(state,0x68)<<8); cx24110_read_snr()
503 cx24110_writereg(state,0x6a,0x84); /* start new count window */ cx24110_read_snr()
505 *snr = state->lastesn0; cx24110_read_snr()
512 struct cx24110_state *state = fe->demodulator_priv; cx24110_read_ucblocks() local
514 if(cx24110_readreg(state,0x10)&0x40) { cx24110_read_ucblocks()
516 cx24110_writereg(state,0x10,0x60); /* select the byer reg */ cx24110_read_ucblocks()
517 (void)(cx24110_readreg(state, 0x12) | cx24110_read_ucblocks()
518 (cx24110_readreg(state, 0x13) << 8) | cx24110_read_ucblocks()
519 (cx24110_readreg(state, 0x14) << 16)); cx24110_read_ucblocks()
520 cx24110_writereg(state,0x10,0x70); /* select the bler reg */ cx24110_read_ucblocks()
521 state->lastbler=cx24110_readreg(state,0x12)| cx24110_read_ucblocks()
522 (cx24110_readreg(state,0x13)<<8)| cx24110_read_ucblocks()
523 (cx24110_readreg(state,0x14)<<16); cx24110_read_ucblocks()
524 cx24110_writereg(state,0x10,0x20); /* start new count window */ cx24110_read_ucblocks()
526 *ucblocks = state->lastbler; cx24110_read_ucblocks()
533 struct cx24110_state *state = fe->demodulator_priv; cx24110_set_frontend() local
541 cx24110_set_inversion(state, p->inversion); cx24110_set_frontend()
542 cx24110_set_fec(state, p->fec_inner); cx24110_set_frontend()
543 cx24110_set_symbolrate(state, p->symbol_rate); cx24110_set_frontend()
544 cx24110_writereg(state,0x04,0x05); /* start acquisition */ cx24110_set_frontend()
552 struct cx24110_state *state = fe->demodulator_priv; cx24110_get_frontend() local
557 sclk = cx24110_readreg (state, 0x07) & 0x03; cx24110_get_frontend()
565 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ cx24110_get_frontend()
566 ((sclk*cx24110_readreg (state, 0x45))>>8)+ cx24110_get_frontend()
567 ((sclk*cx24110_readreg (state, 0x46))>>16); cx24110_get_frontend()
570 p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ? cx24110_get_frontend()
572 p->fec_inner = cx24110_get_fec(state); cx24110_get_frontend()
579 struct cx24110_state *state = fe->demodulator_priv; cx24110_set_tone() local
581 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0)); cx24110_set_tone()
586 struct cx24110_state* state = fe->demodulator_priv; cx24110_release() local
587 kfree(state); cx24110_release()
595 struct cx24110_state* state = NULL; cx24110_attach() local
598 /* allocate memory for the internal state */ cx24110_attach()
599 state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL); cx24110_attach()
600 if (state == NULL) goto error; cx24110_attach()
602 /* setup the state */ cx24110_attach()
603 state->config = config; cx24110_attach()
604 state->i2c = i2c; cx24110_attach()
605 state->lastber = 0; cx24110_attach()
606 state->lastbler = 0; cx24110_attach()
607 state->lastesn0 = 0; cx24110_attach()
610 ret = cx24110_readreg(state, 0x00); cx24110_attach()
614 memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops)); cx24110_attach()
615 state->frontend.demodulator_priv = state; cx24110_attach()
616 return &state->frontend; cx24110_attach()
619 kfree(state); cx24110_attach()
H A Dnxt200x.c72 static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len) i2c_writebytes() argument
77 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { i2c_writebytes()
85 static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len) i2c_readbytes() argument
90 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { i2c_readbytes()
98 static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg, nxt200x_writebytes() argument
103 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 }; nxt200x_writebytes()
114 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { nxt200x_writebytes()
116 __func__, state->config->demod_address, err); nxt200x_writebytes()
122 static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len) nxt200x_readbytes() argument
126 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 }, nxt200x_readbytes()
127 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } }; nxt200x_readbytes()
131 if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) { nxt200x_readbytes()
133 __func__, state->config->demod_address, err); nxt200x_readbytes()
155 static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) nxt200x_writereg_multibyte() argument
161 nxt200x_writebytes(state, 0x35, &reg, 1); nxt200x_writereg_multibyte()
164 nxt200x_writebytes(state, 0x36, data, len); nxt200x_writereg_multibyte()
166 switch (state->demod_chip) { nxt200x_writereg_multibyte()
189 nxt200x_writebytes(state, 0x34, &len2, 1); nxt200x_writereg_multibyte()
192 nxt200x_writebytes(state, 0x21, &buf, 1); nxt200x_writereg_multibyte()
194 nxt200x_readbytes(state, 0x21, &buf, 1); nxt200x_writereg_multibyte()
196 switch (state->demod_chip) { nxt200x_writereg_multibyte()
215 static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) nxt200x_readreg_multibyte() argument
222 nxt200x_writebytes(state, 0x35, &reg, 1); nxt200x_readreg_multibyte()
224 switch (state->demod_chip) { nxt200x_readreg_multibyte()
228 nxt200x_writebytes(state, 0x34, &len2, 1); nxt200x_readreg_multibyte()
231 nxt200x_readbytes(state, reg, data, len); nxt200x_readreg_multibyte()
245 nxt200x_writebytes(state, 0x34, &len2, 1); nxt200x_readreg_multibyte()
249 nxt200x_writebytes(state, 0x21, &buf, 1); nxt200x_readreg_multibyte()
253 nxt200x_readbytes(state, 0x36 + i, &data[i], 1); nxt200x_readreg_multibyte()
263 static void nxt200x_microcontroller_stop (struct nxt200x_state* state) nxt200x_microcontroller_stop() argument
269 switch (state->demod_chip) { nxt200x_microcontroller_stop()
282 nxt200x_writebytes(state, 0x22, &buf, 1); nxt200x_microcontroller_stop()
285 nxt200x_readbytes(state, 0x31, &buf, 1); nxt200x_microcontroller_stop()
297 static void nxt200x_microcontroller_start (struct nxt200x_state* state) nxt200x_microcontroller_start() argument
303 nxt200x_writebytes(state, 0x22, &buf, 1); nxt200x_microcontroller_start()
306 static void nxt2004_microcontroller_init (struct nxt200x_state* state) nxt2004_microcontroller_init() argument
313 nxt200x_writebytes(state, 0x2b, buf, 1); nxt2004_microcontroller_init()
315 nxt200x_writebytes(state, 0x34, buf, 1); nxt2004_microcontroller_init()
317 nxt200x_writebytes(state, 0x35, buf, 1); nxt2004_microcontroller_init()
320 nxt200x_writebytes(state, 0x36, buf, 9); nxt2004_microcontroller_init()
322 nxt200x_writebytes(state, 0x21, buf, 1); nxt2004_microcontroller_init()
325 nxt200x_readbytes(state, 0x21, buf, 1); nxt2004_microcontroller_init()
337 static int nxt200x_writetuner (struct nxt200x_state* state, u8* data) nxt200x_writetuner() argument
347 switch (state->demod_chip) { nxt200x_writetuner()
349 if (i2c_writebytes(state, data[0], data+1, 4)) nxt200x_writetuner()
353 i2c_readbytes(state, data[0], &buf, 1); nxt200x_writetuner()
364 nxt200x_writebytes(state, 0x20, &buf, 1); nxt200x_writetuner()
368 nxt200x_writebytes(state, 0x34, &buf, 1); nxt200x_writetuner()
371 nxt200x_writebytes(state, 0x36, data+1, 4); nxt200x_writetuner()
375 nxt200x_writebytes(state, 0x35, &buf, 1); nxt200x_writetuner()
379 nxt200x_writebytes(state, 0x21, &buf, 1); nxt200x_writetuner()
382 nxt200x_readbytes(state, 0x21, &buf, 1); nxt200x_writetuner()
397 static void nxt200x_agc_reset(struct nxt200x_state* state) nxt200x_agc_reset() argument
402 switch (state->demod_chip) { nxt200x_agc_reset()
405 nxt200x_writebytes(state, 0x08, &buf, 1); nxt200x_agc_reset()
407 nxt200x_writebytes(state, 0x08, &buf, 1); nxt200x_agc_reset()
410 nxt200x_readreg_multibyte(state, 0x08, &buf, 1); nxt200x_agc_reset()
412 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); nxt200x_agc_reset()
414 nxt200x_writereg_multibyte(state, 0x08, &buf, 1); nxt200x_agc_reset()
425 struct nxt200x_state* state = fe->demodulator_priv; nxt2002_load_firmware() local
433 nxt200x_readbytes(state, 0x10, buf, 1); nxt2002_load_firmware()
444 nxt200x_writebytes(state, 0x2B, buf, 1); nxt2002_load_firmware()
454 nxt200x_writebytes(state, 0x29, buf, 3); nxt2002_load_firmware()
460 nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4); nxt2002_load_firmware()
466 nxt200x_writebytes(state, chunkpos+4-(written %4), nxt2002_load_firmware()
473 nxt200x_writebytes(state, 0x2C, buf, 2); nxt2002_load_firmware()
476 nxt200x_readbytes(state, 0x2A, buf, 1); nxt2002_load_firmware()
480 nxt200x_writebytes(state, 0x2B, buf, 1); nxt2002_load_firmware()
492 struct nxt200x_state* state = fe->demodulator_priv; nxt2004_load_firmware() local
504 nxt200x_writebytes(state, 0x2B, buf,1); nxt2004_load_firmware()
515 nxt200x_writebytes(state,0x29,buf,3); nxt2004_load_firmware()
518 nxt200x_writebytes(state, 0x2C, &fw->data[position], nxt2004_load_firmware()
528 nxt200x_writebytes(state, 0x2C, buf,2); nxt2004_load_firmware()
531 nxt200x_readbytes(state, 0x2C, buf, 1); nxt2004_load_firmware()
535 nxt200x_writebytes(state, 0x2B, buf,1); nxt2004_load_firmware()
543 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_setup_frontend_parameters() local
547 nxt200x_microcontroller_stop(state); nxt200x_setup_frontend_parameters()
549 if (state->demod_chip == NXT2004) { nxt200x_setup_frontend_parameters()
552 nxt200x_writebytes(state, 0x14, buf, 1); nxt200x_setup_frontend_parameters()
554 nxt200x_writebytes(state, 0x17, buf, 1); nxt200x_setup_frontend_parameters()
563 if (state->config->set_ts_params) nxt200x_setup_frontend_parameters()
564 state->config->set_ts_params(fe, 1); nxt200x_setup_frontend_parameters()
568 if (state->config->set_ts_params) nxt200x_setup_frontend_parameters()
569 state->config->set_ts_params(fe, 0); nxt200x_setup_frontend_parameters()
581 nxt200x_writetuner(state, buf); nxt200x_setup_frontend_parameters()
585 nxt200x_agc_reset(state); nxt200x_setup_frontend_parameters()
600 nxt200x_writebytes(state, 0x42, buf, 1); nxt200x_setup_frontend_parameters()
603 switch (state->demod_chip) { nxt200x_setup_frontend_parameters()
614 nxt200x_writebytes(state, 0x57, buf, 1); nxt200x_setup_frontend_parameters()
619 switch (state->demod_chip) { nxt200x_setup_frontend_parameters()
621 nxt200x_writereg_multibyte(state, 0x58, buf, 2); nxt200x_setup_frontend_parameters()
624 nxt200x_writebytes(state, 0x58, buf, 2); nxt200x_setup_frontend_parameters()
647 switch (state->demod_chip) { nxt200x_setup_frontend_parameters()
649 nxt200x_writereg_multibyte(state, 0x5C, buf, 2); nxt200x_setup_frontend_parameters()
652 nxt200x_writebytes(state, 0x5C, buf, 2); nxt200x_setup_frontend_parameters()
661 nxt200x_writebytes(state, 0x43, buf, 1); nxt200x_setup_frontend_parameters()
663 if (state->demod_chip == NXT2004) { nxt200x_setup_frontend_parameters()
667 nxt200x_writebytes(state, 0x46, buf, 2); nxt200x_setup_frontend_parameters()
673 switch (state->demod_chip) { nxt200x_setup_frontend_parameters()
675 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); nxt200x_setup_frontend_parameters()
678 nxt200x_writebytes(state, 0x4B, buf, 2); nxt200x_setup_frontend_parameters()
687 nxt200x_writebytes(state, 0x4D, buf, 1); nxt200x_setup_frontend_parameters()
691 nxt200x_writebytes(state, 0x55, buf, 1); nxt200x_setup_frontend_parameters()
695 nxt200x_writebytes(state, 0x41, buf, 1); nxt200x_setup_frontend_parameters()
697 if (state->demod_chip == NXT2004) { nxt200x_setup_frontend_parameters()
698 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt200x_setup_frontend_parameters()
700 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt200x_setup_frontend_parameters()
703 nxt200x_readreg_multibyte(state, 0x08, buf, 1); nxt200x_setup_frontend_parameters()
705 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt200x_setup_frontend_parameters()
706 nxt200x_readreg_multibyte(state, 0x08, buf, 1); nxt200x_setup_frontend_parameters()
708 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt200x_setup_frontend_parameters()
710 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt200x_setup_frontend_parameters()
712 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt200x_setup_frontend_parameters()
714 nxt200x_writereg_multibyte(state, 0x81, buf, 1); nxt200x_setup_frontend_parameters()
716 nxt200x_writereg_multibyte(state, 0x82, buf, 3); nxt200x_setup_frontend_parameters()
717 nxt200x_readreg_multibyte(state, 0x88, buf, 1); nxt200x_setup_frontend_parameters()
719 nxt200x_writereg_multibyte(state, 0x88, buf, 1); nxt200x_setup_frontend_parameters()
720 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt200x_setup_frontend_parameters()
722 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt200x_setup_frontend_parameters()
740 nxt200x_writebytes(state, 0x30, buf, 1); nxt200x_setup_frontend_parameters()
744 nxt200x_writebytes(state, 0x41, buf, 1); nxt200x_setup_frontend_parameters()
749 switch (state->demod_chip) { nxt200x_setup_frontend_parameters()
751 nxt200x_writereg_multibyte(state, 0x49, buf, 2); nxt200x_setup_frontend_parameters()
752 nxt200x_writereg_multibyte(state, 0x4B, buf, 2); nxt200x_setup_frontend_parameters()
755 nxt200x_writebytes(state, 0x49, buf, 2); nxt200x_setup_frontend_parameters()
756 nxt200x_writebytes(state, 0x4B, buf, 2); nxt200x_setup_frontend_parameters()
765 nxt200x_writebytes(state, 0x41, buf, 1); nxt200x_setup_frontend_parameters()
767 nxt200x_microcontroller_start(state); nxt200x_setup_frontend_parameters()
769 if (state->demod_chip == NXT2004) { nxt200x_setup_frontend_parameters()
770 nxt2004_microcontroller_init(state); nxt200x_setup_frontend_parameters()
775 nxt200x_writebytes(state, 0x5C, buf, 2); nxt200x_setup_frontend_parameters()
786 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_read_status() local
788 nxt200x_readbytes(state, 0x31, &lock, 1); nxt200x_read_status()
803 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_read_ber() local
806 nxt200x_readreg_multibyte(state, 0xE6, b, 3); nxt200x_read_ber()
815 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_read_signal_strength() local
821 nxt200x_writebytes(state, 0xA1, b, 1); nxt200x_read_signal_strength()
824 nxt200x_readreg_multibyte(state, 0xA6, b, 2); nxt200x_read_signal_strength()
835 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_read_snr() local
842 nxt200x_writebytes(state, 0xA1, b, 1); nxt200x_read_snr()
845 nxt200x_readreg_multibyte(state, 0xA6, b, 2); nxt200x_read_snr()
868 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_read_ucblocks() local
871 nxt200x_readreg_multibyte(state, 0xE6, b, 3); nxt200x_read_ucblocks()
884 struct nxt200x_state* state = fe->demodulator_priv; nxt2002_init() local
893 state->i2c->dev.parent); nxt2002_init()
910 nxt200x_microcontroller_stop(state); nxt2002_init()
914 nxt200x_writebytes(state, 0x2B, buf, 1); nxt2002_init()
917 nxt200x_microcontroller_stop(state); nxt2002_init()
921 nxt200x_writebytes(state, 0x08, buf, 1); nxt2002_init()
923 nxt200x_writebytes(state, 0x08, buf, 1); nxt2002_init()
927 nxt200x_writebytes(state, 0x57, buf, 1); nxt2002_init()
931 nxt200x_writebytes(state, 0x09, buf, 1); nxt2002_init()
936 nxt200x_writebytes(state, 0xE9, buf, 2); nxt2002_init()
940 nxt200x_writebytes(state, 0xCC, buf, 1); nxt2002_init()
947 struct nxt200x_state* state = fe->demodulator_priv; nxt2004_init() local
954 nxt200x_writebytes(state, 0x1E, buf, 1); nxt2004_init()
960 state->i2c->dev.parent); nxt2004_init()
978 nxt200x_writebytes(state, 0x19, buf, 1); nxt2004_init()
980 nxt2004_microcontroller_init(state); nxt2004_init()
981 nxt200x_microcontroller_stop(state); nxt2004_init()
982 nxt200x_microcontroller_stop(state); nxt2004_init()
983 nxt2004_microcontroller_init(state); nxt2004_init()
984 nxt200x_microcontroller_stop(state); nxt2004_init()
988 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt2004_init()
990 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt2004_init()
994 nxt200x_writebytes(state, 0x57, buf, 1); nxt2004_init()
999 nxt200x_writebytes(state, 0x35, buf, 2); nxt2004_init()
1001 nxt200x_writebytes(state, 0x34, buf, 1); nxt2004_init()
1003 nxt200x_writebytes(state, 0x21, buf, 1); nxt2004_init()
1007 nxt200x_writebytes(state, 0x0A, buf, 1); nxt2004_init()
1011 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1016 nxt200x_writebytes(state, 0xE9, buf, 2); nxt2004_init()
1020 nxt200x_writebytes(state, 0xCC, buf, 1); nxt2004_init()
1023 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1025 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1028 nxt200x_readreg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1030 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1031 nxt200x_readreg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1033 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1036 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1038 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1040 nxt200x_writereg_multibyte(state, 0x81, buf, 1); nxt2004_init()
1042 nxt200x_writereg_multibyte(state, 0x82, buf, 3); nxt2004_init()
1044 nxt200x_readreg_multibyte(state, 0x88, buf, 1); nxt2004_init()
1046 nxt200x_writereg_multibyte(state, 0x88, buf, 1); nxt2004_init()
1047 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1049 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1051 nxt200x_readbytes(state, 0x10, buf, 1); nxt2004_init()
1053 nxt200x_writebytes(state, 0x10, buf, 1); nxt2004_init()
1054 nxt200x_readbytes(state, 0x0A, buf, 1); nxt2004_init()
1056 nxt200x_writebytes(state, 0x0A, buf, 1); nxt2004_init()
1058 nxt2004_microcontroller_init(state); nxt2004_init()
1061 nxt200x_writebytes(state, 0x0A, buf, 1); nxt2004_init()
1063 nxt200x_writebytes(state, 0xE9, buf, 1); nxt2004_init()
1065 nxt200x_writebytes(state, 0xEA, buf, 1); nxt2004_init()
1067 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1069 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1070 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1072 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1075 nxt200x_readreg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1077 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1078 nxt200x_readreg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1080 nxt200x_writereg_multibyte(state, 0x08, buf, 1); nxt2004_init()
1082 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1084 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1086 nxt200x_writereg_multibyte(state, 0x81, buf, 1); nxt2004_init()
1088 nxt200x_writereg_multibyte(state, 0x82, buf, 3); nxt2004_init()
1090 nxt200x_readreg_multibyte(state, 0x88, buf, 1); nxt2004_init()
1092 nxt200x_writereg_multibyte(state, 0x88, buf, 1); nxt2004_init()
1094 nxt200x_readreg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1096 nxt200x_writereg_multibyte(state, 0x80, buf, 1); nxt2004_init()
1099 nxt200x_readbytes(state, 0x10, buf, 1); nxt2004_init()
1101 nxt200x_writebytes(state, 0x10, buf, 1); nxt2004_init()
1103 nxt200x_writebytes(state, 0x13, buf, 1); nxt2004_init()
1105 nxt200x_writebytes(state, 0x16, buf, 1); nxt2004_init()
1107 nxt200x_writebytes(state, 0x14, buf, 1); nxt2004_init()
1109 nxt200x_writebytes(state, 0x14, buf, 1); nxt2004_init()
1110 nxt200x_writebytes(state, 0x17, buf, 1); nxt2004_init()
1111 nxt200x_writebytes(state, 0x14, buf, 1); nxt2004_init()
1112 nxt200x_writebytes(state, 0x17, buf, 1); nxt2004_init()
1119 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_init() local
1122 if (!state->initialised) { nxt200x_init()
1123 switch (state->demod_chip) { nxt200x_init()
1134 state->initialised = 1; nxt200x_init()
1149 struct nxt200x_state* state = fe->demodulator_priv; nxt200x_release() local
1150 kfree(state); nxt200x_release()
1158 struct nxt200x_state* state = NULL; nxt200x_attach() local
1161 /* allocate memory for the internal state */ nxt200x_attach()
1162 state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL); nxt200x_attach()
1163 if (state == NULL) nxt200x_attach()
1166 /* setup the state */ nxt200x_attach()
1167 state->config = config; nxt200x_attach()
1168 state->i2c = i2c; nxt200x_attach()
1169 state->initialised = 0; nxt200x_attach()
1172 nxt200x_readbytes(state, 0x00, buf, 5); nxt200x_attach()
1178 state->demod_chip = NXT2002; nxt200x_attach()
1182 state->demod_chip = NXT2004; nxt200x_attach()
1190 switch (state->demod_chip) { nxt200x_attach()
1206 memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops)); nxt200x_attach()
1207 state->frontend.demodulator_priv = state; nxt200x_attach()
1208 return &state->frontend; nxt200x_attach()
1211 kfree(state); nxt200x_attach()
H A Daf9013.c181 static int af9013_write_ofsm_regs(struct af9013_state *state, u16 reg, u8 *val, af9013_write_ofsm_regs() argument
185 return af9013_wr_regs_i2c(state, mbox, reg, val, len); af9013_write_ofsm_regs()
188 static int af9013_wr_reg_bits(struct af9013_state *state, u16 reg, int pos, af9013_wr_reg_bits() argument
196 ret = af9013_rd_reg(state, reg, &tmp); af9013_wr_reg_bits()
206 return af9013_wr_reg(state, reg, val); af9013_wr_reg_bits()
209 static int af9013_rd_reg_bits(struct af9013_state *state, u16 reg, int pos, af9013_rd_reg_bits() argument
215 ret = af9013_rd_reg(state, reg, &tmp); af9013_rd_reg_bits()
225 static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval) af9013_set_gpio() argument
231 dev_dbg(&state->i2c->dev, "%s: gpio=%d gpioval=%02x\n", af9013_set_gpio()
250 dev_err(&state->i2c->dev, "%s: invalid gpio=%d\n", af9013_set_gpio()
268 ret = af9013_wr_reg_bits(state, addr, pos, 4, gpioval); af9013_set_gpio()
274 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_set_gpio()
278 static u32 af9013_div(struct af9013_state *state, u32 a, u32 b, u32 x) af9013_div() argument
282 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x); af9013_div()
299 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n", af9013_div()
305 static int af9013_power_ctrl(struct af9013_state *state, u8 onoff) af9013_power_ctrl() argument
310 dev_dbg(&state->i2c->dev, "%s: onoff=%d\n", __func__, onoff); af9013_power_ctrl()
313 ret = af9013_wr_reg_bits(state, 0xd417, 4, 1, 1); af9013_power_ctrl()
318 ret = af9013_wr_reg(state, 0xaeff, 1); af9013_power_ctrl()
324 ret = af9013_rd_reg_bits(state, 0xd417, 1, 1, &tmp); af9013_power_ctrl()
339 ret = af9013_wr_reg_bits(state, 0xd417, 1, 1, 0); af9013_power_ctrl()
344 ret = af9013_wr_reg_bits(state, 0xd417, 4, 1, 0); af9013_power_ctrl()
347 ret = af9013_wr_reg_bits(state, 0xd73a, 3, 1, 0); af9013_power_ctrl()
350 ret = af9013_wr_reg_bits(state, 0xd73a, 3, 1, 1); af9013_power_ctrl()
355 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_power_ctrl()
361 struct af9013_state *state = fe->demodulator_priv; af9013_statistics_ber_unc_start() local
364 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_statistics_ber_unc_start()
367 ret = af9013_wr_reg_bits(state, 0xd391, 4, 1, 1); af9013_statistics_ber_unc_start()
373 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_statistics_ber_unc_start()
379 struct af9013_state *state = fe->demodulator_priv; af9013_statistics_ber_unc_result() local
383 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_statistics_ber_unc_result()
386 ret = af9013_rd_reg_bits(state, 0xd391, 4, 1, &buf[0]); af9013_statistics_ber_unc_result()
391 dev_dbg(&state->i2c->dev, "%s: not ready\n", __func__); af9013_statistics_ber_unc_result()
395 ret = af9013_rd_regs(state, 0xd387, buf, 5); af9013_statistics_ber_unc_result()
399 state->ber = (buf[2] << 16) | (buf[1] << 8) | buf[0]; af9013_statistics_ber_unc_result()
400 state->ucblocks += (buf[4] << 8) | buf[3]; af9013_statistics_ber_unc_result()
404 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_statistics_ber_unc_result()
410 struct af9013_state *state = fe->demodulator_priv; af9013_statistics_snr_start() local
413 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_statistics_snr_start()
416 ret = af9013_wr_reg_bits(state, 0xd2e1, 3, 1, 1); af9013_statistics_snr_start()
422 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_statistics_snr_start()
428 struct af9013_state *state = fe->demodulator_priv; af9013_statistics_snr_result() local
434 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_statistics_snr_result()
437 ret = af9013_rd_reg_bits(state, 0xd2e1, 3, 1, &tmp); af9013_statistics_snr_result()
442 dev_dbg(&state->i2c->dev, "%s: not ready\n", __func__); af9013_statistics_snr_result()
447 ret = af9013_rd_regs(state, 0xd2e3, buf, 3); af9013_statistics_snr_result()
454 ret = af9013_rd_reg(state, 0xd3c1, &tmp); af9013_statistics_snr_result()
481 state->snr = tmp * 10; /* dB/10 */ af9013_statistics_snr_result()
485 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_statistics_snr_result()
491 struct af9013_state *state = fe->demodulator_priv; af9013_statistics_signal_strength() local
496 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_statistics_signal_strength()
498 if (!state->signal_strength_en) af9013_statistics_signal_strength()
501 ret = af9013_rd_regs(state, 0xd07c, buf, 2); af9013_statistics_signal_strength()
509 (9 * (state->rf_50 + state->if_50) - \ af9013_statistics_signal_strength()
510 11 * (state->rf_80 + state->if_80))) * \ af9013_statistics_signal_strength()
512 11 * (state->rf_80 + state->if_80)); af9013_statistics_signal_strength()
518 state->signal_strength = signal_strength; af9013_statistics_signal_strength()
522 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_statistics_signal_strength()
528 struct af9013_state *state = container_of(work, af9013_statistics_work() local
533 if (!(state->fe_status & FE_HAS_LOCK)) { af9013_statistics_work()
534 state->statistics_step = 0; af9013_statistics_work()
535 state->ber = 0; af9013_statistics_work()
536 state->snr = 0; af9013_statistics_work()
539 switch (state->statistics_step) { af9013_statistics_work()
541 state->statistics_step = 0; af9013_statistics_work()
543 af9013_statistics_signal_strength(&state->fe); af9013_statistics_work()
544 state->statistics_step++; af9013_statistics_work()
548 af9013_statistics_snr_start(&state->fe); af9013_statistics_work()
549 state->statistics_step++; af9013_statistics_work()
553 af9013_statistics_ber_unc_start(&state->fe); af9013_statistics_work()
554 state->statistics_step++; af9013_statistics_work()
558 af9013_statistics_snr_result(&state->fe); af9013_statistics_work()
559 state->statistics_step++; af9013_statistics_work()
563 af9013_statistics_ber_unc_result(&state->fe); af9013_statistics_work()
564 state->statistics_step++; af9013_statistics_work()
569 schedule_delayed_work(&state->statistics_work, af9013_statistics_work()
585 struct af9013_state *state = fe->demodulator_priv; af9013_set_frontend() local
592 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", af9013_set_frontend()
600 if (c->bandwidth_hz != state->bandwidth_hz) { af9013_set_frontend()
602 if (coeff_lut[i].clock == state->config.clock && af9013_set_frontend()
612 ret = af9013_wr_regs(state, 0xae00, coeff_lut[i].val, af9013_set_frontend()
617 if (c->bandwidth_hz != state->bandwidth_hz || state->first_tune) { af9013_set_frontend()
622 if_frequency = state->config.if_frequency; af9013_set_frontend()
624 dev_dbg(&state->i2c->dev, "%s: if_frequency=%d\n", af9013_set_frontend()
629 while (sampling_freq > (state->config.clock / 2)) af9013_set_frontend()
630 sampling_freq -= state->config.clock; af9013_set_frontend()
634 spec_inv = state->config.spec_inv; af9013_set_frontend()
636 spec_inv = !state->config.spec_inv; af9013_set_frontend()
639 freq_cw = af9013_div(state, sampling_freq, state->config.clock, af9013_set_frontend()
655 ret = af9013_wr_regs(state, 0xd140, buf, 3); af9013_set_frontend()
659 ret = af9013_wr_regs(state, 0x9be7, buf, 6); af9013_set_frontend()
665 ret = af9013_wr_reg_bits(state, 0xd330, 3, 1, 1); af9013_set_frontend()
670 ret = af9013_wr_reg_bits(state, 0xd507, 6, 1, 0); af9013_set_frontend()
675 ret = af9013_wr_reg_bits(state, 0x9bfe, 0, 1, 0); af9013_set_frontend()
680 ret = af9013_wr_reg_bits(state, 0x9bc2, 0, 1, 0); af9013_set_frontend()
698 dev_dbg(&state->i2c->dev, "%s: invalid transmission_mode\n", af9013_set_frontend()
719 dev_dbg(&state->i2c->dev, "%s: invalid guard_interval\n", af9013_set_frontend()
740 dev_dbg(&state->i2c->dev, "%s: invalid hierarchy\n", __func__); af9013_set_frontend()
757 dev_dbg(&state->i2c->dev, "%s: invalid modulation\n", __func__); af9013_set_frontend()
783 dev_dbg(&state->i2c->dev, "%s: invalid code_rate_HP\n", af9013_set_frontend()
809 dev_dbg(&state->i2c->dev, "%s: invalid code_rate_LP\n", af9013_set_frontend()
824 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n", af9013_set_frontend()
830 ret = af9013_wr_regs(state, 0xd3c0, buf, 3); af9013_set_frontend()
836 ret = af9013_wr_reg(state, 0xaefd, 0); af9013_set_frontend()
840 dev_dbg(&state->i2c->dev, "%s: auto params\n", __func__); af9013_set_frontend()
843 ret = af9013_wr_reg(state, 0xaefd, 1); af9013_set_frontend()
847 ret = af9013_wr_reg(state, 0xaefe, 0); af9013_set_frontend()
851 dev_dbg(&state->i2c->dev, "%s: manual params\n", __func__); af9013_set_frontend()
855 ret = af9013_wr_reg(state, 0xffff, 0); af9013_set_frontend()
859 state->bandwidth_hz = c->bandwidth_hz; af9013_set_frontend()
860 state->set_frontend_jiffies = jiffies; af9013_set_frontend()
861 state->first_tune = false; af9013_set_frontend()
865 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_set_frontend()
872 struct af9013_state *state = fe->demodulator_priv; af9013_get_frontend() local
876 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_get_frontend()
878 ret = af9013_rd_regs(state, 0xd3c0, buf, 3); af9013_get_frontend()
982 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_get_frontend()
988 struct af9013_state *state = fe->demodulator_priv; af9013_read_status() local
997 state->read_status_jiffies + msecs_to_jiffies(2000)) && af9013_read_status()
999 state->set_frontend_jiffies + msecs_to_jiffies(4000)) af9013_read_status()
1001 *status = state->fe_status; af9013_read_status()
1008 ret = af9013_rd_reg_bits(state, 0xd507, 6, 1, &tmp); af9013_read_status()
1018 ret = af9013_rd_reg_bits(state, 0xd330, 3, 1, &tmp); af9013_read_status()
1027 state->fe_status = *status; af9013_read_status()
1028 state->read_status_jiffies = jiffies; af9013_read_status()
1032 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_read_status()
1038 struct af9013_state *state = fe->demodulator_priv; af9013_read_snr() local
1039 *snr = state->snr; af9013_read_snr()
1045 struct af9013_state *state = fe->demodulator_priv; af9013_read_signal_strength() local
1046 *strength = state->signal_strength; af9013_read_signal_strength()
1052 struct af9013_state *state = fe->demodulator_priv; af9013_read_ber() local
1053 *ber = state->ber; af9013_read_ber()
1059 struct af9013_state *state = fe->demodulator_priv; af9013_read_ucblocks() local
1060 *ucblocks = state->ucblocks; af9013_read_ucblocks()
1066 struct af9013_state *state = fe->demodulator_priv; af9013_init() local
1072 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_init()
1075 ret = af9013_power_ctrl(state, 1); af9013_init()
1080 ret = af9013_wr_reg(state, 0xd73a, 0xa4); af9013_init()
1085 ret = af9013_wr_regs(state, 0x9bf2, state->config.api_version, 4); af9013_init()
1090 switch (state->config.clock) { af9013_init()
1104 dev_err(&state->i2c->dev, "%s: invalid clock\n", af9013_init()
1109 adc_cw = af9013_div(state, state->config.clock, 1000000ul, 19); af9013_init()
1114 ret = af9013_wr_regs(state, 0xd180, buf, 3); af9013_init()
1118 ret = af9013_wr_reg_bits(state, 0x9bd2, 0, 4, tmp); af9013_init()
1123 ret = af9013_wr_reg(state, 0xd416, 0x14); af9013_init()
1128 ret = af9013_wr_reg_bits(state, 0xd700, 1, 1, 1); af9013_init()
1133 ret = af9013_wr_reg_bits(state, 0xd700, 2, 1, 0); af9013_init()
1138 ret = af9013_wr_reg_bits(state, 0xd371, 1, 1, 1); af9013_init()
1143 if (state->config.ts_mode == AF9013_TS_USB) { af9013_init()
1145 ret = af9013_wr_reg_bits(state, 0xd50b, 2, 1, 1); af9013_init()
1150 ret = af9013_wr_reg_bits(state, 0xd500, 3, 1, 1); af9013_init()
1155 ret = af9013_wr_reg_bits(state, 0xd502, 4, 1, 1); af9013_init()
1160 ret = af9013_wr_reg_bits(state, 0xd520, 4, 1, 1); af9013_init()
1165 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__); af9013_init()
1169 ret = af9013_wr_reg_bits(state, init[i].addr, init[i].pos, af9013_init()
1176 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n", af9013_init()
1178 switch (state->config.tuner) { af9013_init()
1223 ret = af9013_wr_reg_bits(state, init[i].addr, init[i].pos, af9013_init()
1230 ret = af9013_wr_reg_bits(state, 0xd500, 1, 2, state->config.ts_mode); af9013_init()
1235 ret = af9013_wr_reg_bits(state, 0xd730, 0, 1, 1); af9013_init()
1240 if (!state->signal_strength_en) { af9013_init()
1241 ret = af9013_rd_reg_bits(state, 0x9bee, 0, 1, af9013_init()
1242 &state->signal_strength_en); af9013_init()
1248 if (state->signal_strength_en && !state->rf_50) { af9013_init()
1249 ret = af9013_rd_reg(state, 0x9bbd, &state->rf_50); af9013_init()
1253 ret = af9013_rd_reg(state, 0x9bd0, &state->rf_80); af9013_init()
1257 ret = af9013_rd_reg(state, 0x9be2, &state->if_50); af9013_init()
1261 ret = af9013_rd_reg(state, 0x9be4, &state->if_80); af9013_init()
1267 ret = af9013_wr_reg(state, 0xd2e2, 1); af9013_init()
1274 ret = af9013_wr_regs(state, 0xd385, buf, 2); af9013_init()
1279 ret = af9013_wr_reg_bits(state, 0xd392, 1, 1, 1); af9013_init()
1283 state->first_tune = true; af9013_init()
1284 schedule_delayed_work(&state->statistics_work, msecs_to_jiffies(400)); af9013_init()
1288 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_init()
1294 struct af9013_state *state = fe->demodulator_priv; af9013_sleep() local
1297 dev_dbg(&state->i2c->dev, "%s:\n", __func__); af9013_sleep()
1300 cancel_delayed_work_sync(&state->statistics_work); af9013_sleep()
1303 ret = af9013_wr_reg_bits(state, 0xd730, 0, 1, 0); af9013_sleep()
1308 ret = af9013_power_ctrl(state, 0); af9013_sleep()
1314 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_sleep()
1321 struct af9013_state *state = fe->demodulator_priv; af9013_i2c_gate_ctrl() local
1323 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable); af9013_i2c_gate_ctrl()
1326 if (state->i2c_gate_state == enable) af9013_i2c_gate_ctrl()
1329 if (state->config.ts_mode == AF9013_TS_USB) af9013_i2c_gate_ctrl()
1330 ret = af9013_wr_reg_bits(state, 0xd417, 3, 1, enable); af9013_i2c_gate_ctrl()
1332 ret = af9013_wr_reg_bits(state, 0xd607, 2, 1, enable); af9013_i2c_gate_ctrl()
1336 state->i2c_gate_state = enable; af9013_i2c_gate_ctrl()
1340 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); af9013_i2c_gate_ctrl()
1346 struct af9013_state *state = fe->demodulator_priv; af9013_release() local
1347 kfree(state); af9013_release()
1352 static int af9013_download_firmware(struct af9013_state *state) af9013_download_firmware() argument
1363 ret = af9013_rd_reg(state, 0x98be, &val); af9013_download_firmware()
1367 dev_dbg(&state->i2c->dev, "%s: firmware status=%02x\n", af9013_download_firmware()
1373 dev_info(&state->i2c->dev, "%s: found a '%s' in cold state, will try " \ af9013_download_firmware()
1378 ret = request_firmware(&fw, fw_file, state->i2c->dev.parent); af9013_download_firmware()
1380 dev_info(&state->i2c->dev, "%s: did not find the firmware " \ af9013_download_firmware()
1387 dev_info(&state->i2c->dev, "%s: downloading firmware from file '%s'\n", af9013_download_firmware()
1400 ret = af9013_write_ofsm_regs(state, 0x50fc, af9013_download_firmware()
1412 ret = af9013_write_ofsm_regs(state, af9013_download_firmware()
1416 dev_err(&state->i2c->dev, af9013_download_firmware()
1424 ret = af9013_wr_reg(state, 0xe205, 1); af9013_download_firmware()
1432 ret = af9013_rd_reg(state, 0x98be, &val); af9013_download_firmware()
1436 dev_dbg(&state->i2c->dev, "%s: firmware status=%02x\n", af9013_download_firmware()
1444 dev_err(&state->i2c->dev, "%s: firmware did not run\n", af9013_download_firmware()
1448 dev_err(&state->i2c->dev, "%s: firmware boot timeout\n", af9013_download_firmware()
1458 dev_info(&state->i2c->dev, "%s: found a '%s' in warm state\n", af9013_download_firmware()
1467 struct af9013_state *state = NULL; af9013_attach() local
1470 /* allocate memory for the internal state */ af9013_attach()
1471 state = kzalloc(sizeof(struct af9013_state), GFP_KERNEL); af9013_attach()
1472 if (state == NULL) af9013_attach()
1475 /* setup the state */ af9013_attach()
1476 state->i2c = i2c; af9013_attach()
1477 memcpy(&state->config, config, sizeof(struct af9013_config)); af9013_attach()
1480 if (state->config.ts_mode != AF9013_TS_USB) { af9013_attach()
1481 ret = af9013_download_firmware(state); af9013_attach()
1487 ret = af9013_rd_regs(state, 0x5103, buf, 4); af9013_attach()
1491 dev_info(&state->i2c->dev, "%s: firmware version %d.%d.%d.%d\n", af9013_attach()
1495 for (i = 0; i < sizeof(state->config.gpio); i++) { af9013_attach()
1496 ret = af9013_set_gpio(state, i, state->config.gpio[i]); af9013_attach()
1502 memcpy(&state->fe.ops, &af9013_ops, af9013_attach()
1504 state->fe.demodulator_priv = state; af9013_attach()
1506 INIT_DELAYED_WORK(&state->statistics_work, af9013_statistics_work); af9013_attach()
1508 return &state->fe; af9013_attach()
1510 kfree(state); af9013_attach()
H A Dsp887x.c39 static int i2c_writebytes (struct sp887x_state* state, u8 *buf, u8 len) i2c_writebytes() argument
41 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len }; i2c_writebytes()
44 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { i2c_writebytes()
46 __func__, state->config->demod_address, err); i2c_writebytes()
53 static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data) sp887x_writereg() argument
56 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 }; sp887x_writereg()
59 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) { sp887x_writereg()
76 static int sp887x_readreg (struct sp887x_state* state, u16 reg) sp887x_readreg() argument
81 struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, sp887x_readreg()
82 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 2 }}; sp887x_readreg()
84 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) { sp887x_readreg()
92 static void sp887x_microcontroller_stop (struct sp887x_state* state) sp887x_microcontroller_stop() argument
95 sp887x_writereg(state, 0xf08, 0x000); sp887x_microcontroller_stop()
96 sp887x_writereg(state, 0xf09, 0x000); sp887x_microcontroller_stop()
99 sp887x_writereg(state, 0xf00, 0x000); sp887x_microcontroller_stop()
102 static void sp887x_microcontroller_start (struct sp887x_state* state) sp887x_microcontroller_start() argument
105 sp887x_writereg(state, 0xf08, 0x000); sp887x_microcontroller_start()
106 sp887x_writereg(state, 0xf09, 0x000); sp887x_microcontroller_start()
109 sp887x_writereg(state, 0xf00, 0x001); sp887x_microcontroller_start()
112 static void sp887x_setup_agc (struct sp887x_state* state) sp887x_setup_agc() argument
116 sp887x_writereg(state, 0x33c, 0x054); sp887x_setup_agc()
117 sp887x_writereg(state, 0x33b, 0x04c); sp887x_setup_agc()
118 sp887x_writereg(state, 0x328, 0x000); sp887x_setup_agc()
119 sp887x_writereg(state, 0x327, 0x005); sp887x_setup_agc()
120 sp887x_writereg(state, 0x326, 0x001); sp887x_setup_agc()
121 sp887x_writereg(state, 0x325, 0x001); sp887x_setup_agc()
122 sp887x_writereg(state, 0x324, 0x001); sp887x_setup_agc()
123 sp887x_writereg(state, 0x318, 0x050); sp887x_setup_agc()
124 sp887x_writereg(state, 0x317, 0x3fe); sp887x_setup_agc()
125 sp887x_writereg(state, 0x316, 0x001); sp887x_setup_agc()
126 sp887x_writereg(state, 0x313, 0x005); sp887x_setup_agc()
127 sp887x_writereg(state, 0x312, 0x002); sp887x_setup_agc()
128 sp887x_writereg(state, 0x306, 0x000); sp887x_setup_agc()
129 sp887x_writereg(state, 0x303, 0x000); sp887x_setup_agc()
139 struct sp887x_state* state = fe->demodulator_priv; sp887x_initial_setup() local
154 sp887x_writereg(state, 0xf1a, 0x000); sp887x_initial_setup()
156 sp887x_microcontroller_stop (state); sp887x_initial_setup()
162 sp887x_writereg(state, 0x8f08, 0x1fff); sp887x_initial_setup()
165 sp887x_writereg(state, 0x8f0a, 0x0000); sp887x_initial_setup()
182 if ((err = i2c_writebytes (state, buf, c+2)) < 0) { sp887x_initial_setup()
190 sp887x_writereg(state, 0xc13, 0x001); sp887x_initial_setup()
193 sp887x_writereg(state, 0xc14, 0x000); sp887x_initial_setup()
196 sp887x_writereg(state, 0xc1a, 0x872); sp887x_initial_setup()
197 sp887x_writereg(state, 0xc1b, 0x001); sp887x_initial_setup()
198 sp887x_writereg(state, 0xc1c, 0x000); /* parallel mode (serial mode == 1) */ sp887x_initial_setup()
199 sp887x_writereg(state, 0xc1a, 0x871); sp887x_initial_setup()
202 sp887x_writereg(state, 0x301, 0x002); sp887x_initial_setup()
204 sp887x_setup_agc(state); sp887x_initial_setup()
207 sp887x_writereg(state, 0xd00, 0x010); sp887x_initial_setup()
208 sp887x_writereg(state, 0x0d1, 0x000); sp887x_initial_setup()
305 static void sp887x_correct_offsets (struct sp887x_state* state, sp887x_correct_offsets() argument
341 sp887x_writereg(state, 0x319, srate_correction[bw_index] >> 12); sp887x_correct_offsets()
342 sp887x_writereg(state, 0x31a, srate_correction[bw_index] & 0xfff); sp887x_correct_offsets()
345 sp887x_writereg(state, 0x309, frequency_shift >> 12); sp887x_correct_offsets()
346 sp887x_writereg(state, 0x30a, frequency_shift & 0xfff); sp887x_correct_offsets()
352 struct sp887x_state* state = fe->demodulator_priv; sp887x_setup_frontend_parameters() local
365 sp887x_microcontroller_stop(state); sp887x_setup_frontend_parameters()
380 sp887x_readreg(state, 0x200); sp887x_setup_frontend_parameters()
382 sp887x_correct_offsets(state, p, actual_freq); sp887x_setup_frontend_parameters()
392 sp887x_writereg(state, 0x311, val); sp887x_setup_frontend_parameters()
396 sp887x_writereg(state, 0x338, 0x000); sp887x_setup_frontend_parameters()
398 sp887x_writereg(state, 0x338, 0x001); sp887x_setup_frontend_parameters()
400 sp887x_writereg(state, 0xc05, reg0xc05); sp887x_setup_frontend_parameters()
412 sp887x_writereg(state, 0xf14, 0x160 | val); sp887x_setup_frontend_parameters()
413 sp887x_writereg(state, 0xf15, 0x000); sp887x_setup_frontend_parameters()
415 sp887x_microcontroller_start(state); sp887x_setup_frontend_parameters()
421 struct sp887x_state* state = fe->demodulator_priv; sp887x_read_status() local
422 u16 snr12 = sp887x_readreg(state, 0xf16); sp887x_read_status()
423 u16 sync0x200 = sp887x_readreg(state, 0x200); sp887x_read_status()
424 u16 sync0xf17 = sp887x_readreg(state, 0xf17); sp887x_read_status()
455 struct sp887x_state* state = fe->demodulator_priv; sp887x_read_ber() local
457 *ber = (sp887x_readreg(state, 0xc08) & 0x3f) | sp887x_read_ber()
458 (sp887x_readreg(state, 0xc07) << 6); sp887x_read_ber()
459 sp887x_writereg(state, 0xc08, 0x000); sp887x_read_ber()
460 sp887x_writereg(state, 0xc07, 0x000); sp887x_read_ber()
469 struct sp887x_state* state = fe->demodulator_priv; sp887x_read_signal_strength() local
471 u16 snr12 = sp887x_readreg(state, 0xf16); sp887x_read_signal_strength()
480 struct sp887x_state* state = fe->demodulator_priv; sp887x_read_snr() local
482 u16 snr12 = sp887x_readreg(state, 0xf16); sp887x_read_snr()
490 struct sp887x_state* state = fe->demodulator_priv; sp887x_read_ucblocks() local
492 *ucblocks = sp887x_readreg(state, 0xc0c); sp887x_read_ucblocks()
501 struct sp887x_state* state = fe->demodulator_priv; sp887x_i2c_gate_ctrl() local
504 return sp887x_writereg(state, 0x206, 0x001); sp887x_i2c_gate_ctrl()
506 return sp887x_writereg(state, 0x206, 0x000); sp887x_i2c_gate_ctrl()
512 struct sp887x_state* state = fe->demodulator_priv; sp887x_sleep() local
515 sp887x_writereg(state, 0xc18, 0x000); sp887x_sleep()
522 struct sp887x_state* state = fe->demodulator_priv; sp887x_init() local
526 if (!state->initialised) { sp887x_init()
529 ret = state->config->request_firmware(fe, &fw, SP887X_DEFAULT_FIRMWARE); sp887x_init()
542 state->initialised = 1; sp887x_init()
546 sp887x_writereg(state, 0xc18, 0x00d); sp887x_init()
561 struct sp887x_state* state = fe->demodulator_priv; sp887x_release() local
562 kfree(state); sp887x_release()
570 struct sp887x_state* state = NULL; sp887x_attach() local
572 /* allocate memory for the internal state */ sp887x_attach()
573 state = kzalloc(sizeof(struct sp887x_state), GFP_KERNEL); sp887x_attach()
574 if (state == NULL) goto error; sp887x_attach()
576 /* setup the state */ sp887x_attach()
577 state->config = config; sp887x_attach()
578 state->i2c = i2c; sp887x_attach()
579 state->initialised = 0; sp887x_attach()
582 if (sp887x_readreg(state, 0x0200) < 0) goto error; sp887x_attach()
585 memcpy(&state->frontend.ops, &sp887x_ops, sizeof(struct dvb_frontend_ops)); sp887x_attach()
586 state->frontend.demodulator_priv = state; sp887x_attach()
587 return &state->frontend; sp887x_attach()
590 kfree(state); sp887x_attach()
H A Dves1x93.c95 static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data) ves1x93_writereg() argument
98 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 }; ves1x93_writereg()
101 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { ves1x93_writereg()
109 static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg) ves1x93_readreg() argument
114 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, ves1x93_readreg()
115 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; ves1x93_readreg()
117 ret = i2c_transfer (state->i2c, msg, 2); ves1x93_readreg()
124 static int ves1x93_clr_bit (struct ves1x93_state* state) ves1x93_clr_bit() argument
127 ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe); ves1x93_clr_bit()
128 ves1x93_writereg (state, 0, state->init_1x93_tab[0]); ves1x93_clr_bit()
133 static int ves1x93_set_inversion (struct ves1x93_state* state, fe_spectral_inversion_t inversion) ves1x93_set_inversion() argument
156 return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val); ves1x93_set_inversion()
159 static int ves1x93_set_fec (struct ves1x93_state* state, fe_code_rate_t fec) ves1x93_set_fec() argument
162 return ves1x93_writereg (state, 0x0d, 0x08); ves1x93_set_fec()
166 return ves1x93_writereg (state, 0x0d, fec - FEC_1_2); ves1x93_set_fec()
169 static fe_code_rate_t ves1x93_get_fec (struct ves1x93_state* state) ves1x93_get_fec() argument
171 return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7); ves1x93_get_fec()
174 static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate) ves1x93_set_symbolrate() argument
185 if (srate > state->config->xin/2) ves1x93_set_symbolrate()
186 srate = state->config->xin/2; ves1x93_set_symbolrate()
193 FIN = (state->config->xin + 6000) >> 4; ves1x93_set_symbolrate()
238 ves1x93_writereg (state, 0x06, 0xff & BDR); ves1x93_set_symbolrate()
239 ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8)); ves1x93_set_symbolrate()
240 ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16)); ves1x93_set_symbolrate()
242 ves1x93_writereg (state, 0x09, BDRI); ves1x93_set_symbolrate()
243 ves1x93_writereg (state, 0x20, ADCONF); ves1x93_set_symbolrate()
244 ves1x93_writereg (state, 0x21, FCONF); ves1x93_set_symbolrate()
246 AGCR = state->init_1x93_tab[0x05]; ves1x93_set_symbolrate()
247 if (state->config->invert_pwm) ves1x93_set_symbolrate()
255 ves1x93_writereg (state, 0x05, AGCR); ves1x93_set_symbolrate()
258 if (state->demod_type != DEMOD_VES1993) ves1x93_set_symbolrate()
259 ves1x93_clr_bit (state); ves1x93_set_symbolrate()
266 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_init() local
272 for (i = 0; i < state->tab_size; i++) { ves1x93_init()
273 if (state->init_1x93_wtab[i]) { ves1x93_init()
274 val = state->init_1x93_tab[i]; ves1x93_init()
276 if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */ ves1x93_init()
277 ves1x93_writereg (state, i, val); ves1x93_init()
286 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_set_voltage() local
290 return ves1x93_writereg (state, 0x1f, 0x20); ves1x93_set_voltage()
292 return ves1x93_writereg (state, 0x1f, 0x30); ves1x93_set_voltage()
294 return ves1x93_writereg (state, 0x1f, 0x00); ves1x93_set_voltage()
302 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_read_status() local
304 u8 sync = ves1x93_readreg (state, 0x0e); ves1x93_read_status()
318 sync = ves1x93_readreg (state, 0x0e); ves1x93_read_status()
343 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_read_ber() local
345 *ber = ves1x93_readreg (state, 0x15); ves1x93_read_ber()
346 *ber |= (ves1x93_readreg (state, 0x16) << 8); ves1x93_read_ber()
347 *ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16); ves1x93_read_ber()
355 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_read_signal_strength() local
357 u8 signal = ~ves1x93_readreg (state, 0x0b); ves1x93_read_signal_strength()
365 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_read_snr() local
367 u8 _snr = ~ves1x93_readreg (state, 0x1c); ves1x93_read_snr()
375 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_read_ucblocks() local
377 *ucblocks = ves1x93_readreg (state, 0x18) & 0x7f; ves1x93_read_ucblocks()
382 ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */ ves1x93_read_ucblocks()
383 ves1x93_writereg (state, 0x18, 0x80); /* dto. */ ves1x93_read_ucblocks()
391 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_set_frontend() local
397 ves1x93_set_inversion (state, p->inversion); ves1x93_set_frontend()
398 ves1x93_set_fec(state, p->fec_inner); ves1x93_set_frontend()
399 ves1x93_set_symbolrate(state, p->symbol_rate); ves1x93_set_frontend()
400 state->inversion = p->inversion; ves1x93_set_frontend()
401 state->frequency = p->frequency; ves1x93_set_frontend()
409 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_get_frontend() local
412 afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2; ves1x93_get_frontend()
415 p->frequency = state->frequency - afc; ves1x93_get_frontend()
421 if (state->inversion == INVERSION_AUTO) ves1x93_get_frontend()
422 p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ? ves1x93_get_frontend()
424 p->fec_inner = ves1x93_get_fec(state); ves1x93_get_frontend()
432 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_sleep() local
434 return ves1x93_writereg (state, 0x00, 0x08); ves1x93_sleep()
439 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_release() local
440 kfree(state); ves1x93_release()
445 struct ves1x93_state* state = fe->demodulator_priv; ves1x93_i2c_gate_ctrl() local
448 return ves1x93_writereg(state, 0x00, 0x11); ves1x93_i2c_gate_ctrl()
450 return ves1x93_writereg(state, 0x00, 0x01); ves1x93_i2c_gate_ctrl()
459 struct ves1x93_state* state = NULL; ves1x93_attach() local
462 /* allocate memory for the internal state */ ves1x93_attach()
463 state = kzalloc(sizeof(struct ves1x93_state), GFP_KERNEL); ves1x93_attach()
464 if (state == NULL) goto error; ves1x93_attach()
466 /* setup the state */ ves1x93_attach()
467 state->config = config; ves1x93_attach()
468 state->i2c = i2c; ves1x93_attach()
469 state->inversion = INVERSION_OFF; ves1x93_attach()
472 identity = ves1x93_readreg(state, 0x1e); ves1x93_attach()
476 state->demod_type = DEMOD_VES1893; ves1x93_attach()
477 state->init_1x93_tab = init_1893_tab; ves1x93_attach()
478 state->init_1x93_wtab = init_1893_wtab; ves1x93_attach()
479 state->tab_size = sizeof(init_1893_tab); ves1x93_attach()
484 state->demod_type = DEMOD_VES1893; ves1x93_attach()
485 state->init_1x93_tab = init_1893_tab; ves1x93_attach()
486 state->init_1x93_wtab = init_1893_wtab; ves1x93_attach()
487 state->tab_size = sizeof(init_1893_tab); ves1x93_attach()
492 state->demod_type = DEMOD_VES1993; ves1x93_attach()
493 state->init_1x93_tab = init_1993_tab; ves1x93_attach()
494 state->init_1x93_wtab = init_1993_wtab; ves1x93_attach()
495 state->tab_size = sizeof(init_1993_tab); ves1x93_attach()
503 memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops)); ves1x93_attach()
504 state->frontend.demodulator_priv = state; ves1x93_attach()
505 return &state->frontend; ves1x93_attach()
508 kfree(state); ves1x93_attach()
H A Dstv0299.c81 static int stv0299_writeregI (struct stv0299_state* state, u8 reg, u8 data) stv0299_writeregI() argument
85 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; stv0299_writeregI()
87 ret = i2c_transfer (state->i2c, &msg, 1); stv0299_writeregI()
98 struct stv0299_state* state = fe->demodulator_priv; stv0299_write() local
103 return stv0299_writeregI(state, buf[0], buf[1]); stv0299_write()
106 static u8 stv0299_readreg (struct stv0299_state* state, u8 reg) stv0299_readreg() argument
111 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, stv0299_readreg()
112 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; stv0299_readreg()
114 ret = i2c_transfer (state->i2c, msg, 2); stv0299_readreg()
123 static int stv0299_readregs (struct stv0299_state* state, u8 reg1, u8 *b, u8 len) stv0299_readregs() argument
126 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = &reg1, .len = 1 }, stv0299_readregs()
127 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = len } }; stv0299_readregs()
129 ret = i2c_transfer (state->i2c, msg, 2); stv0299_readregs()
137 static int stv0299_set_FEC (struct stv0299_state* state, fe_code_rate_t fec) stv0299_set_FEC() argument
144 return stv0299_writeregI (state, 0x31, 0x1f); stv0299_set_FEC()
148 return stv0299_writeregI (state, 0x31, 0x01); stv0299_set_FEC()
152 return stv0299_writeregI (state, 0x31, 0x02); stv0299_set_FEC()
156 return stv0299_writeregI (state, 0x31, 0x04); stv0299_set_FEC()
160 return stv0299_writeregI (state, 0x31, 0x08); stv0299_set_FEC()
164 return stv0299_writeregI (state, 0x31, 0x10); stv0299_set_FEC()
173 static fe_code_rate_t stv0299_get_fec (struct stv0299_state* state) stv0299_get_fec() argument
181 index = stv0299_readreg (state, 0x1b); stv0299_get_fec()
190 static int stv0299_wait_diseqc_fifo (struct stv0299_state* state, int timeout) stv0299_wait_diseqc_fifo() argument
196 while (stv0299_readreg(state, 0x0a) & 1) { stv0299_wait_diseqc_fifo()
207 static int stv0299_wait_diseqc_idle (struct stv0299_state* state, int timeout) stv0299_wait_diseqc_idle() argument
213 while ((stv0299_readreg(state, 0x0a) & 3) != 2 ) { stv0299_wait_diseqc_idle()
226 struct stv0299_state* state = fe->demodulator_priv; stv0299_set_symbolrate() local
235 big += (state->config->mclk-1); // round correctly stv0299_set_symbolrate()
236 do_div(big, state->config->mclk); stv0299_set_symbolrate()
239 return state->config->set_symbol_rate(fe, srate, ratio); stv0299_set_symbolrate()
242 static int stv0299_get_symbolrate (struct stv0299_state* state) stv0299_get_symbolrate() argument
244 u32 Mclk = state->config->mclk / 4096L; stv0299_get_symbolrate()
252 stv0299_readregs (state, 0x1f, sfr, 3); stv0299_get_symbolrate()
253 stv0299_readregs (state, 0x1a, (u8 *)&rtf, 1); stv0299_get_symbolrate()
277 struct stv0299_state* state = fe->demodulator_priv; stv0299_send_diseqc_msg() local
283 if (stv0299_wait_diseqc_idle (state, 100) < 0) stv0299_send_diseqc_msg()
286 val = stv0299_readreg (state, 0x08); stv0299_send_diseqc_msg()
288 if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x6)) /* DiSEqC mode */ stv0299_send_diseqc_msg()
292 if (stv0299_wait_diseqc_fifo (state, 100) < 0) stv0299_send_diseqc_msg()
295 if (stv0299_writeregI (state, 0x09, m->msg[i])) stv0299_send_diseqc_msg()
299 if (stv0299_wait_diseqc_idle (state, 100) < 0) stv0299_send_diseqc_msg()
307 struct stv0299_state* state = fe->demodulator_priv; stv0299_send_diseqc_burst() local
312 if (stv0299_wait_diseqc_idle (state, 100) < 0) stv0299_send_diseqc_burst()
315 val = stv0299_readreg (state, 0x08); stv0299_send_diseqc_burst()
317 if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x2)) /* burst mode */ stv0299_send_diseqc_burst()
320 if (stv0299_writeregI (state, 0x09, burst == SEC_MINI_A ? 0x00 : 0xff)) stv0299_send_diseqc_burst()
323 if (stv0299_wait_diseqc_idle (state, 100) < 0) stv0299_send_diseqc_burst()
326 if (stv0299_writeregI (state, 0x08, val)) stv0299_send_diseqc_burst()
334 struct stv0299_state* state = fe->demodulator_priv; stv0299_set_tone() local
337 if (stv0299_wait_diseqc_idle (state, 100) < 0) stv0299_set_tone()
340 val = stv0299_readreg (state, 0x08); stv0299_set_tone()
344 return stv0299_writeregI (state, 0x08, val | 0x3); stv0299_set_tone()
347 return stv0299_writeregI (state, 0x08, (val & ~0x3) | 0x02); stv0299_set_tone()
356 struct stv0299_state* state = fe->demodulator_priv; stv0299_set_voltage() local
364 reg0x08 = stv0299_readreg (state, 0x08); stv0299_set_voltage()
365 reg0x0c = stv0299_readreg (state, 0x0c); stv0299_set_voltage()
371 reg0x08 = (reg0x08 & 0x3f) | (state->config->lock_output << 6); stv0299_set_voltage()
375 if (state->config->volt13_op0_op1 == STV0299_VOLT13_OP0) stv0299_set_voltage()
392 if (state->config->op0_off) stv0299_set_voltage()
395 stv0299_writeregI(state, 0x08, reg0x08); stv0299_set_voltage()
396 return stv0299_writeregI(state, 0x0c, reg0x0c); stv0299_set_voltage()
401 struct stv0299_state* state = fe->demodulator_priv; stv0299_send_legacy_dish_cmd() local
410 reg0x08 = stv0299_readreg (state, 0x08); stv0299_send_legacy_dish_cmd()
411 reg0x0c = stv0299_readreg (state, 0x0c); stv0299_send_legacy_dish_cmd()
413 stv0299_writeregI (state, 0x08, (reg0x08 & 0x3f) | (state->config->lock_output << 6)); stv0299_send_legacy_dish_cmd()
414 if (state->config->volt13_op0_op1 == STV0299_VOLT13_OP0) stv0299_send_legacy_dish_cmd()
424 stv0299_writeregI (state, 0x0c, reg0x0c | 0x50); /* set LNB to 18V */ stv0299_send_legacy_dish_cmd()
433 stv0299_writeregI (state, 0x0c, reg0x0c | (last ? lv_mask : 0x50)); stv0299_send_legacy_dish_cmd()
454 struct stv0299_state* state = fe->demodulator_priv; stv0299_init() local
461 stv0299_writeregI(state, 0x02, 0x30 | state->mcr_reg); stv0299_init()
465 reg = state->config->inittab[i]; stv0299_init()
466 val = state->config->inittab[i+1]; stv0299_init()
469 if (reg == 0x0c && state->config->op0_off) stv0299_init()
472 state->mcr_reg = val & 0xf; stv0299_init()
473 stv0299_writeregI(state, reg, val); stv0299_init()
481 struct stv0299_state* state = fe->demodulator_priv; stv0299_read_status() local
483 u8 signal = 0xff - stv0299_readreg (state, 0x18); stv0299_read_status()
484 u8 sync = stv0299_readreg (state, 0x1b); stv0299_read_status()
509 struct stv0299_state* state = fe->demodulator_priv; stv0299_read_ber() local
511 if (state->errmode != STATUS_BER) stv0299_read_ber()
514 *ber = stv0299_readreg(state, 0x1e) | (stv0299_readreg(state, 0x1d) << 8); stv0299_read_ber()
521 struct stv0299_state* state = fe->demodulator_priv; stv0299_read_signal_strength() local
523 s32 signal = 0xffff - ((stv0299_readreg (state, 0x18) << 8) stv0299_read_signal_strength()
524 | stv0299_readreg (state, 0x19)); stv0299_read_signal_strength()
527 stv0299_readreg (state, 0x18), stv0299_read_signal_strength()
528 stv0299_readreg (state, 0x19), (int) signal); stv0299_read_signal_strength()
538 struct stv0299_state* state = fe->demodulator_priv; stv0299_read_snr() local
540 s32 xsnr = 0xffff - ((stv0299_readreg (state, 0x24) << 8) stv0299_read_snr()
541 | stv0299_readreg (state, 0x25)); stv0299_read_snr()
550 struct stv0299_state* state = fe->demodulator_priv; stv0299_read_ucblocks() local
552 if (state->errmode != STATUS_UCBLOCKS) stv0299_read_ucblocks()
555 state->ucblocks += stv0299_readreg(state, 0x1e); stv0299_read_ucblocks()
556 state->ucblocks += (stv0299_readreg(state, 0x1d) << 8); stv0299_read_ucblocks()
557 *ucblocks = state->ucblocks; stv0299_read_ucblocks()
565 struct stv0299_state* state = fe->demodulator_priv; stv0299_set_frontend() local
569 if (state->config->set_ts_params) stv0299_set_frontend()
570 state->config->set_ts_params(fe, 0); stv0299_set_frontend()
579 if (state->config->invert) invval = (~invval) & 1; stv0299_set_frontend()
580 stv0299_writeregI(state, 0x0c, (stv0299_readreg(state, 0x0c) & 0xfe) | invval); stv0299_set_frontend()
587 stv0299_set_FEC(state, p->fec_inner); stv0299_set_frontend()
589 stv0299_writeregI(state, 0x22, 0x00); stv0299_set_frontend()
590 stv0299_writeregI(state, 0x23, 0x00); stv0299_set_frontend()
592 state->tuner_frequency = p->frequency; stv0299_set_frontend()
593 state->fec_inner = p->fec_inner; stv0299_set_frontend()
594 state->symbol_rate = p->symbol_rate; stv0299_set_frontend()
602 struct stv0299_state* state = fe->demodulator_priv; stv0299_get_frontend() local
606 derot_freq = (s32)(s16) ((stv0299_readreg (state, 0x22) << 8) stv0299_get_frontend()
607 | stv0299_readreg (state, 0x23)); stv0299_get_frontend()
609 derot_freq *= (state->config->mclk >> 16); stv0299_get_frontend()
615 invval = stv0299_readreg (state, 0x0c) & 1; stv0299_get_frontend()
616 if (state->config->invert) invval = (~invval) & 1; stv0299_get_frontend()
619 p->fec_inner = stv0299_get_fec(state); stv0299_get_frontend()
620 p->symbol_rate = stv0299_get_symbolrate(state); stv0299_get_frontend()
627 struct stv0299_state* state = fe->demodulator_priv; stv0299_sleep() local
629 stv0299_writeregI(state, 0x02, 0xb0 | state->mcr_reg); stv0299_sleep()
630 state->initialised = 0; stv0299_sleep()
637 struct stv0299_state* state = fe->demodulator_priv; stv0299_i2c_gate_ctrl() local
640 stv0299_writeregI(state, 0x05, 0xb5); stv0299_i2c_gate_ctrl()
642 stv0299_writeregI(state, 0x05, 0x35); stv0299_i2c_gate_ctrl()
650 struct stv0299_state* state = fe->demodulator_priv; stv0299_get_tune_settings() local
653 fesettings->min_delay_ms = state->config->min_delay_ms; stv0299_get_tune_settings()
666 struct stv0299_state* state = fe->demodulator_priv; stv0299_release() local
667 kfree(state); stv0299_release()
675 struct stv0299_state* state = NULL; stv0299_attach() local
678 /* allocate memory for the internal state */ stv0299_attach()
679 state = kzalloc(sizeof(struct stv0299_state), GFP_KERNEL); stv0299_attach()
680 if (state == NULL) goto error; stv0299_attach()
682 /* setup the state */ stv0299_attach()
683 state->config = config; stv0299_attach()
684 state->i2c = i2c; stv0299_attach()
685 state->initialised = 0; stv0299_attach()
686 state->tuner_frequency = 0; stv0299_attach()
687 state->symbol_rate = 0; stv0299_attach()
688 state->fec_inner = 0; stv0299_attach()
689 state->errmode = STATUS_BER; stv0299_attach()
692 stv0299_writeregI(state, 0x02, 0x30); /* standby off */ stv0299_attach()
694 id = stv0299_readreg(state, 0x00); stv0299_attach()
701 memcpy(&state->frontend.ops, &stv0299_ops, sizeof(struct dvb_frontend_ops)); stv0299_attach()
702 state->frontend.demodulator_priv = state; stv0299_attach()
703 return &state->frontend; stv0299_attach()
706 kfree(state); stv0299_attach()
H A Dcx22700.c70 static int cx22700_writereg (struct cx22700_state* state, u8 reg, u8 data) cx22700_writereg() argument
74 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; cx22700_writereg()
78 ret = i2c_transfer (state->i2c, &msg, 1); cx22700_writereg()
87 static int cx22700_readreg (struct cx22700_state* state, u8 reg) cx22700_readreg() argument
92 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, cx22700_readreg()
93 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; cx22700_readreg()
97 ret = i2c_transfer (state->i2c, msg, 2); cx22700_readreg()
104 static int cx22700_set_inversion (struct cx22700_state* state, int inversion) cx22700_set_inversion() argument
114 val = cx22700_readreg (state, 0x09); cx22700_set_inversion()
115 return cx22700_writereg (state, 0x09, val | 0x01); cx22700_set_inversion()
117 val = cx22700_readreg (state, 0x09); cx22700_set_inversion()
118 return cx22700_writereg (state, 0x09, val & 0xfe); cx22700_set_inversion()
124 static int cx22700_set_tps(struct cx22700_state *state, cx22700_set_tps() argument
163 cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 | 0x10)); cx22700_set_tps()
165 cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 & ~0x10)); cx22700_set_tps()
170 cx22700_writereg (state, 0x04, val); cx22700_set_tps()
178 cx22700_writereg (state, 0x05, val); cx22700_set_tps()
183 cx22700_writereg (state, 0x06, val); cx22700_set_tps()
185 cx22700_writereg (state, 0x08, 0x04 | 0x02); /* use user tps parameters */ cx22700_set_tps()
186 cx22700_writereg (state, 0x08, 0x04); /* restart acquisition */ cx22700_set_tps()
191 static int cx22700_get_tps(struct cx22700_state *state, cx22700_get_tps() argument
201 if (!(cx22700_readreg(state, 0x07) & 0x20)) /* tps valid? */ cx22700_get_tps()
204 val = cx22700_readreg (state, 0x01); cx22700_get_tps()
216 val = cx22700_readreg (state, 0x02); cx22700_get_tps()
228 val = cx22700_readreg (state, 0x03); cx22700_get_tps()
238 { struct cx22700_state* state = fe->demodulator_priv; cx22700_init() local
243 cx22700_writereg (state, 0x00, 0x02); /* soft reset */ cx22700_init()
244 cx22700_writereg (state, 0x00, 0x00); cx22700_init()
249 cx22700_writereg (state, init_tab[i], init_tab[i+1]); cx22700_init()
251 cx22700_writereg (state, 0x00, 0x01); cx22700_init()
258 struct cx22700_state* state = fe->demodulator_priv; cx22700_read_status() local
260 u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9) cx22700_read_status()
261 | (cx22700_readreg (state, 0x0e) << 1); cx22700_read_status()
262 u8 sync = cx22700_readreg (state, 0x07); cx22700_read_status()
286 struct cx22700_state* state = fe->demodulator_priv; cx22700_read_ber() local
288 *ber = cx22700_readreg (state, 0x0c) & 0x7f; cx22700_read_ber()
289 cx22700_writereg (state, 0x0c, 0x00); cx22700_read_ber()
296 struct cx22700_state* state = fe->demodulator_priv; cx22700_read_signal_strength() local
298 u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9) cx22700_read_signal_strength()
299 | (cx22700_readreg (state, 0x0e) << 1); cx22700_read_signal_strength()
307 struct cx22700_state* state = fe->demodulator_priv; cx22700_read_snr() local
309 u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9) cx22700_read_snr()
310 | (cx22700_readreg (state, 0x0e) << 1); cx22700_read_snr()
318 struct cx22700_state* state = fe->demodulator_priv; cx22700_read_ucblocks() local
320 *ucblocks = cx22700_readreg (state, 0x0f); cx22700_read_ucblocks()
321 cx22700_writereg (state, 0x0f, 0x00); cx22700_read_ucblocks()
329 struct cx22700_state* state = fe->demodulator_priv; cx22700_set_frontend() local
331 cx22700_writereg (state, 0x00, 0x02); /* XXX CHECKME: soft reset*/ cx22700_set_frontend()
332 cx22700_writereg (state, 0x00, 0x00); cx22700_set_frontend()
339 cx22700_set_inversion(state, c->inversion); cx22700_set_frontend()
340 cx22700_set_tps(state, c); cx22700_set_frontend()
341 cx22700_writereg (state, 0x37, 0x01); /* PAL loop filter off */ cx22700_set_frontend()
342 cx22700_writereg (state, 0x00, 0x01); /* restart acquire */ cx22700_set_frontend()
350 struct cx22700_state* state = fe->demodulator_priv; cx22700_get_frontend() local
351 u8 reg09 = cx22700_readreg (state, 0x09); cx22700_get_frontend()
354 return cx22700_get_tps(state, c); cx22700_get_frontend()
359 struct cx22700_state* state = fe->demodulator_priv; cx22700_i2c_gate_ctrl() local
362 return cx22700_writereg(state, 0x0a, 0x00); cx22700_i2c_gate_ctrl()
364 return cx22700_writereg(state, 0x0a, 0x01); cx22700_i2c_gate_ctrl()
378 struct cx22700_state* state = fe->demodulator_priv; cx22700_release() local
379 kfree(state); cx22700_release()
387 struct cx22700_state* state = NULL; cx22700_attach() local
389 /* allocate memory for the internal state */ cx22700_attach()
390 state = kzalloc(sizeof(struct cx22700_state), GFP_KERNEL); cx22700_attach()
391 if (state == NULL) goto error; cx22700_attach()
393 /* setup the state */ cx22700_attach()
394 state->config = config; cx22700_attach()
395 state->i2c = i2c; cx22700_attach()
398 if (cx22700_readreg(state, 0x07) < 0) goto error; cx22700_attach()
401 memcpy(&state->frontend.ops, &cx22700_ops, sizeof(struct dvb_frontend_ops)); cx22700_attach()
402 state->frontend.demodulator_priv = state; cx22700_attach()
403 return &state->frontend; cx22700_attach()
406 kfree(state); cx22700_attach()
H A Dl64781.c52 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data) l64781_writereg() argument
56 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; l64781_writereg()
58 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) l64781_writereg()
65 static int l64781_readreg (struct l64781_state* state, u8 reg) l64781_readreg() argument
70 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, l64781_readreg()
71 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; l64781_readreg()
73 ret = i2c_transfer(state->i2c, msg, 2); l64781_readreg()
80 static void apply_tps (struct l64781_state* state) apply_tps() argument
82 l64781_writereg (state, 0x2a, 0x00); apply_tps()
83 l64781_writereg (state, 0x2a, 0x01); apply_tps()
90 l64781_writereg (state, 0x2a, 0x02); apply_tps()
94 static void reset_afc (struct l64781_state* state) reset_afc() argument
98 l64781_writereg (state, 0x07, 0x9e); /* stall AFC */ reset_afc()
99 l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */ reset_afc()
100 l64781_writereg (state, 0x09, 0); reset_afc()
101 l64781_writereg (state, 0x0a, 0); reset_afc()
102 l64781_writereg (state, 0x07, 0x8e); reset_afc()
103 l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */ reset_afc()
104 l64781_writereg (state, 0x11, 0x80); /* stall TIM */ reset_afc()
105 l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */ reset_afc()
106 l64781_writereg (state, 0x12, 0); reset_afc()
107 l64781_writereg (state, 0x13, 0); reset_afc()
108 l64781_writereg (state, 0x11, 0x00); reset_afc()
111 static int reset_and_configure (struct l64781_state* state) reset_and_configure() argument
117 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV; reset_and_configure()
123 struct l64781_state* state = fe->demodulator_priv; apply_frontend_param() local
217 l64781_writereg (state, 0x04, val0x04); apply_frontend_param()
218 l64781_writereg (state, 0x05, val0x05); apply_frontend_param()
219 l64781_writereg (state, 0x06, val0x06); apply_frontend_param()
221 reset_afc (state); apply_frontend_param()
224 l64781_writereg (state, 0x15, apply_frontend_param()
226 l64781_writereg (state, 0x16, init_freq & 0xff); apply_frontend_param()
227 l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff); apply_frontend_param()
228 l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff); apply_frontend_param()
230 l64781_writereg (state, 0x1b, spi_bias & 0xff); apply_frontend_param()
231 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff); apply_frontend_param()
232 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) | apply_frontend_param()
235 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff); apply_frontend_param()
236 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f); apply_frontend_param()
238 l64781_readreg (state, 0x00); /* clear interrupt registers... */ apply_frontend_param()
239 l64781_readreg (state, 0x01); /* dto. */ apply_frontend_param()
241 apply_tps (state); apply_frontend_param()
249 struct l64781_state* state = fe->demodulator_priv; get_frontend() local
253 tmp = l64781_readreg(state, 0x04); get_frontend()
279 tmp = l64781_readreg(state, 0x05); get_frontend()
319 tmp = l64781_readreg(state, 0x06); get_frontend()
351 tmp = l64781_readreg (state, 0x1d); get_frontend()
354 tmp = (int) (l64781_readreg (state, 0x08) | get_frontend()
355 (l64781_readreg (state, 0x09) << 8) | get_frontend()
356 (l64781_readreg (state, 0x0a) << 16)); get_frontend()
364 struct l64781_state* state = fe->demodulator_priv; l64781_read_status() local
365 int sync = l64781_readreg (state, 0x32); l64781_read_status()
366 int gain = l64781_readreg (state, 0x0e); l64781_read_status()
368 l64781_readreg (state, 0x00); /* clear interrupt registers... */ l64781_read_status()
369 l64781_readreg (state, 0x01); /* dto. */ l64781_read_status()
393 struct l64781_state* state = fe->demodulator_priv; l64781_read_ber() local
397 *ber = l64781_readreg (state, 0x39) l64781_read_ber()
398 | (l64781_readreg (state, 0x3a) << 8); l64781_read_ber()
405 struct l64781_state* state = fe->demodulator_priv; l64781_read_signal_strength() local
407 u8 gain = l64781_readreg (state, 0x0e); l64781_read_signal_strength()
415 struct l64781_state* state = fe->demodulator_priv; l64781_read_snr() local
417 u8 avg_quality = 0xff - l64781_readreg (state, 0x33); l64781_read_snr()
425 struct l64781_state* state = fe->demodulator_priv; l64781_read_ucblocks() local
427 *ucblocks = l64781_readreg (state, 0x37) l64781_read_ucblocks()
428 | (l64781_readreg (state, 0x38) << 8); l64781_read_ucblocks()
435 struct l64781_state* state = fe->demodulator_priv; l64781_sleep() local
438 return l64781_writereg (state, 0x3e, 0x5a); l64781_sleep()
443 struct l64781_state* state = fe->demodulator_priv; l64781_init() local
445 reset_and_configure (state); l64781_init()
448 l64781_writereg (state, 0x3e, 0xa5); l64781_init()
451 l64781_writereg (state, 0x2a, 0x04); l64781_init()
452 l64781_writereg (state, 0x2a, 0x00); l64781_init()
456 l64781_writereg (state, 0x07, 0x8e); l64781_init()
459 l64781_writereg (state, 0x0b, 0x81); l64781_init()
462 l64781_writereg (state, 0x0c, 0x84); l64781_init()
465 l64781_writereg (state, 0x0d, 0x8c); l64781_init()
470 /*l64781_writereg (state, 0x19, 0x92);*/ l64781_init()
473 l64781_writereg (state, 0x1e, 0x09); l64781_init()
476 if (state->first) { l64781_init()
477 state->first = 0; l64781_init()
495 struct l64781_state* state = fe->demodulator_priv; l64781_release() local
496 kfree(state); l64781_release()
504 struct l64781_state* state = NULL; l64781_attach() local
511 /* allocate memory for the internal state */ l64781_attach()
512 state = kzalloc(sizeof(struct l64781_state), GFP_KERNEL); l64781_attach()
513 if (state == NULL) goto error; l64781_attach()
515 /* setup the state */ l64781_attach()
516 state->config = config; l64781_attach()
517 state->i2c = i2c; l64781_attach()
518 state->first = 1; l64781_attach()
524 if (reset_and_configure(state) < 0) { l64781_attach()
530 if (i2c_transfer(state->i2c, msg, 2) != 2) { l64781_attach()
536 reg0x3e = l64781_readreg(state, 0x3e); l64781_attach()
545 l64781_writereg (state, 0x3e, 0x5a); l64781_attach()
548 if (l64781_readreg(state, 0x1a) != 0) { l64781_attach()
554 l64781_writereg (state, 0x3e, 0xa5); l64781_attach()
557 if (l64781_readreg(state, 0x1a) != 0xa1) { l64781_attach()
563 memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops)); l64781_attach()
564 state->frontend.demodulator_priv = state; l64781_attach()
565 return &state->frontend; l64781_attach()
569 l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */ l64781_attach()
570 kfree(state); l64781_attach()
H A Dtda10086.c52 static int tda10086_write_byte(struct tda10086_state *state, int reg, int data) tda10086_write_byte() argument
58 msg.addr = state->config->demod_address; tda10086_write_byte()
59 ret = i2c_transfer(state->i2c, &msg, 1); tda10086_write_byte()
68 static int tda10086_read_byte(struct tda10086_state *state, int reg) tda10086_read_byte() argument
76 msg[0].addr = state->config->demod_address; tda10086_read_byte()
77 msg[1].addr = state->config->demod_address; tda10086_read_byte()
78 ret = i2c_transfer(state->i2c, msg, 2); tda10086_read_byte()
89 static int tda10086_write_mask(struct tda10086_state *state, int reg, int mask, int data) tda10086_write_mask() argument
94 val = tda10086_read_byte(state, reg); tda10086_write_mask()
103 return tda10086_write_byte(state, reg, val); tda10086_write_mask()
108 struct tda10086_state* state = fe->demodulator_priv; tda10086_init() local
113 if (state->config->diseqc_tone) tda10086_init()
116 tda10086_write_byte(state, 0x00, 0x00); tda10086_init()
120 tda10086_write_byte(state, 0x01, 0x94); tda10086_init()
121 tda10086_write_byte(state, 0x02, 0x35); /* NOTE: TT drivers appear to disable CSWP */ tda10086_init()
122 tda10086_write_byte(state, 0x03, 0xe4); tda10086_init()
123 tda10086_write_byte(state, 0x04, 0x43); tda10086_init()
124 tda10086_write_byte(state, 0x0c, 0x0c); tda10086_init()
125 tda10086_write_byte(state, 0x1b, 0xb0); /* noise threshold */ tda10086_init()
126 tda10086_write_byte(state, 0x20, 0x89); /* misc */ tda10086_init()
127 tda10086_write_byte(state, 0x30, 0x04); /* acquisition period length */ tda10086_init()
128 tda10086_write_byte(state, 0x32, 0x00); /* irq off */ tda10086_init()
129 tda10086_write_byte(state, 0x31, 0x56); /* setup AFC */ tda10086_init()
132 tda10086_write_byte(state, 0x55, 0x2c); /* misc PLL setup */ tda10086_init()
133 if (state->config->xtal_freq == TDA10086_XTAL_16M) { tda10086_init()
134 tda10086_write_byte(state, 0x3a, 0x0b); /* M=12 */ tda10086_init()
135 tda10086_write_byte(state, 0x3b, 0x01); /* P=2 */ tda10086_init()
137 tda10086_write_byte(state, 0x3a, 0x17); /* M=24 */ tda10086_init()
138 tda10086_write_byte(state, 0x3b, 0x00); /* P=1 */ tda10086_init()
140 tda10086_write_mask(state, 0x55, 0x20, 0x00); /* powerup PLL */ tda10086_init()
143 tda10086_write_byte(state, 0x11, 0x81); tda10086_init()
144 tda10086_write_byte(state, 0x12, 0x81); tda10086_init()
145 tda10086_write_byte(state, 0x19, 0x40); /* parallel mode A + MSBFIRST */ tda10086_init()
146 tda10086_write_byte(state, 0x56, 0x80); /* powerdown WPLL - unused in the mode we use */ tda10086_init()
147 tda10086_write_byte(state, 0x57, 0x08); /* bypass WPLL - unused in the mode we use */ tda10086_init()
148 tda10086_write_byte(state, 0x10, 0x2a); tda10086_init()
151 tda10086_write_byte(state, 0x58, 0x61); /* ADC setup */ tda10086_init()
152 tda10086_write_mask(state, 0x58, 0x01, 0x00); /* powerup ADC */ tda10086_init()
155 tda10086_write_byte(state, 0x05, 0x0B); tda10086_init()
156 tda10086_write_byte(state, 0x37, 0x63); tda10086_init()
157 tda10086_write_byte(state, 0x3f, 0x0a); /* NOTE: flydvb varies it */ tda10086_init()
158 tda10086_write_byte(state, 0x40, 0x64); tda10086_init()
159 tda10086_write_byte(state, 0x41, 0x4f); tda10086_init()
160 tda10086_write_byte(state, 0x42, 0x43); tda10086_init()
163 tda10086_write_byte(state, 0x1a, 0x11); /* VBER 10^6, DVB, QPSK */ tda10086_init()
166 tda10086_write_byte(state, 0x3d, 0x80); tda10086_init()
169 tda10086_write_byte(state, 0x36, t22k_off); /* all SEC off, 22k tone */ tda10086_init()
170 tda10086_write_byte(state, 0x34, (((1<<19) * (22000/1000)) / (SACLK/1000))); tda10086_init()
171 tda10086_write_byte(state, 0x35, (((1<<19) * (22000/1000)) / (SACLK/1000)) >> 8); tda10086_init()
176 static void tda10086_diseqc_wait(struct tda10086_state *state) tda10086_diseqc_wait() argument
179 while (!(tda10086_read_byte(state, 0x50) & 0x01)) { tda10086_diseqc_wait()
190 struct tda10086_state* state = fe->demodulator_priv; tda10086_set_tone() local
195 if (state->config->diseqc_tone) tda10086_set_tone()
200 tda10086_write_byte(state, 0x36, t22k_off); tda10086_set_tone()
204 tda10086_write_byte(state, 0x36, 0x01 + t22k_off); tda10086_set_tone()
214 struct tda10086_state* state = fe->demodulator_priv; tda10086_send_master_cmd() local
221 if (state->config->diseqc_tone) tda10086_send_master_cmd()
226 oldval = tda10086_read_byte(state, 0x36); tda10086_send_master_cmd()
229 tda10086_write_byte(state, 0x48+i, cmd->msg[i]); tda10086_send_master_cmd()
231 tda10086_write_byte(state, 0x36, (0x08 + t22k_off) tda10086_send_master_cmd()
234 tda10086_diseqc_wait(state); tda10086_send_master_cmd()
236 tda10086_write_byte(state, 0x36, oldval); tda10086_send_master_cmd()
243 struct tda10086_state* state = fe->demodulator_priv; tda10086_send_burst() local
244 u8 oldval = tda10086_read_byte(state, 0x36); tda10086_send_burst()
249 if (state->config->diseqc_tone) tda10086_send_burst()
254 tda10086_write_byte(state, 0x36, 0x04 + t22k_off); tda10086_send_burst()
258 tda10086_write_byte(state, 0x36, 0x06 + t22k_off); tda10086_send_burst()
262 tda10086_diseqc_wait(state); tda10086_send_burst()
264 tda10086_write_byte(state, 0x36, oldval); tda10086_send_burst()
269 static int tda10086_set_inversion(struct tda10086_state *state, tda10086_set_inversion() argument
274 dprintk ("%s %i %i\n", __func__, fe_params->inversion, state->config->invert); tda10086_set_inversion()
278 if (state->config->invert) tda10086_set_inversion()
282 if (!state->config->invert) tda10086_set_inversion()
289 tda10086_write_mask(state, 0x0c, 0xc0, invval); tda10086_set_inversion()
294 static int tda10086_set_symbol_rate(struct tda10086_state *state, tda10086_set_symbol_rate() argument
357 tda10086_write_byte(state, 0x21, (afs << 7) | dfn); tda10086_set_symbol_rate()
358 tda10086_write_mask(state, 0x20, 0x08, byp << 3); tda10086_set_symbol_rate()
359 tda10086_write_byte(state, 0x06, bdr); tda10086_set_symbol_rate()
360 tda10086_write_byte(state, 0x07, bdr >> 8); tda10086_set_symbol_rate()
361 tda10086_write_byte(state, 0x08, bdr >> 16); tda10086_set_symbol_rate()
362 tda10086_write_byte(state, 0x09, bdri); tda10086_set_symbol_rate()
363 tda10086_write_byte(state, 0x37, reg37); tda10086_set_symbol_rate()
364 tda10086_write_byte(state, 0x42, reg42); tda10086_set_symbol_rate()
369 static int tda10086_set_fec(struct tda10086_state *state, tda10086_set_fec() argument
407 tda10086_write_byte(state, 0x0d, fecval); tda10086_set_fec()
415 struct tda10086_state *state = fe->demodulator_priv; tda10086_set_frontend() local
423 tda10086_write_byte(state, 0x02, 0x35); tda10086_set_frontend()
424 state->has_lock = false; tda10086_set_frontend()
441 tda10086_write_byte(state, 0x3d, 0x80 | ((freqoff >> 8) & 0x7f)); tda10086_set_frontend()
442 tda10086_write_byte(state, 0x3e, freqoff); tda10086_set_frontend()
444 if ((ret = tda10086_set_inversion(state, fe_params)) < 0) tda10086_set_frontend()
446 if ((ret = tda10086_set_symbol_rate(state, fe_params)) < 0) tda10086_set_frontend()
448 if ((ret = tda10086_set_fec(state, fe_params)) < 0) tda10086_set_frontend()
452 tda10086_write_mask(state, 0x10, 0x40, 0x40); tda10086_set_frontend()
453 tda10086_write_mask(state, 0x00, 0x01, 0x00); tda10086_set_frontend()
455 state->symbol_rate = fe_params->symbol_rate; tda10086_set_frontend()
456 state->frequency = fe_params->frequency; tda10086_set_frontend()
463 struct tda10086_state* state = fe->demodulator_priv; tda10086_get_frontend() local
475 tmp64 = tda10086_read_byte(state, 0x52); tda10086_get_frontend()
476 tmp64 |= (tda10086_read_byte(state, 0x51) << 8); tda10086_get_frontend()
481 fe_params->frequency = (int) state->frequency + (int) tmp64; tda10086_get_frontend()
484 val = tda10086_read_byte(state, 0x0c); tda10086_get_frontend()
489 if (state->config->invert) tda10086_get_frontend()
494 if (state->config->invert) tda10086_get_frontend()
499 tda10086_read_byte(state, 0x0f); tda10086_get_frontend()
503 if (state->config->invert) tda10086_get_frontend()
508 if (state->config->invert) tda10086_get_frontend()
515 tmp = tda10086_read_byte(state, 0x1d); tda10086_get_frontend()
519 tmp = ((state->symbol_rate/1000) * tmp) / (1000000/1000); tda10086_get_frontend()
520 fe_params->symbol_rate = state->symbol_rate + tmp; tda10086_get_frontend()
523 val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4; tda10086_get_frontend()
556 struct tda10086_state* state = fe->demodulator_priv; tda10086_read_status() local
561 val = tda10086_read_byte(state, 0x0e); tda10086_read_status()
573 if (!state->has_lock) { tda10086_read_status()
574 state->has_lock = true; tda10086_read_status()
576 tda10086_write_byte(state, 0x02, 0x00); tda10086_read_status()
585 struct tda10086_state* state = fe->demodulator_priv; tda10086_read_signal_strength() local
590 _str = 0xff - tda10086_read_byte(state, 0x43); tda10086_read_signal_strength()
598 struct tda10086_state* state = fe->demodulator_priv; tda10086_read_snr() local
603 _snr = 0xff - tda10086_read_byte(state, 0x1c); tda10086_read_snr()
611 struct tda10086_state* state = fe->demodulator_priv; tda10086_read_ucblocks() local
616 *ucblocks = tda10086_read_byte(state, 0x18) & 0x7f; tda10086_read_ucblocks()
619 tda10086_write_byte(state, 0x18, 0x00); tda10086_read_ucblocks()
620 tda10086_write_byte(state, 0x18, 0x80); tda10086_read_ucblocks()
627 struct tda10086_state* state = fe->demodulator_priv; tda10086_read_ber() local
633 *ber |= tda10086_read_byte(state, 0x15); tda10086_read_ber()
634 *ber |= tda10086_read_byte(state, 0x16) << 8; tda10086_read_ber()
635 *ber |= (tda10086_read_byte(state, 0x17) & 0xf) << 16; tda10086_read_ber()
642 struct tda10086_state* state = fe->demodulator_priv; tda10086_sleep() local
646 tda10086_write_mask(state, 0x00, 0x08, 0x08); tda10086_sleep()
653 struct tda10086_state* state = fe->demodulator_priv; tda10086_i2c_gate_ctrl() local
658 tda10086_write_mask(state, 0x00, 0x10, 0x10); tda10086_i2c_gate_ctrl()
660 tda10086_write_mask(state, 0x00, 0x10, 0x00); tda10086_i2c_gate_ctrl()
701 struct tda10086_state *state = fe->demodulator_priv; tda10086_release() local
703 kfree(state); tda10086_release()
745 struct tda10086_state *state; tda10086_attach() local
749 /* allocate memory for the internal state */ tda10086_attach()
750 state = kzalloc(sizeof(struct tda10086_state), GFP_KERNEL); tda10086_attach()
751 if (!state) tda10086_attach()
754 /* setup the state */ tda10086_attach()
755 state->config = config; tda10086_attach()
756 state->i2c = i2c; tda10086_attach()
759 if (tda10086_read_byte(state, 0x1e) != 0xe1) { tda10086_attach()
760 kfree(state); tda10086_attach()
765 memcpy(&state->frontend.ops, &tda10086_ops, sizeof(struct dvb_frontend_ops)); tda10086_attach()
766 state->frontend.demodulator_priv = state; tda10086_attach()
767 return &state->frontend; tda10086_attach()
H A Dm88rs2000.c63 static int m88rs2000_writereg(struct m88rs2000_state *state, m88rs2000_writereg() argument
69 .addr = state->config->demod_addr, m88rs2000_writereg()
75 ret = i2c_transfer(state->i2c, &msg, 1); m88rs2000_writereg()
84 static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg) m88rs2000_readreg() argument
92 .addr = state->config->demod_addr, m88rs2000_readreg()
97 .addr = state->config->demod_addr, m88rs2000_readreg()
104 ret = i2c_transfer(state->i2c, msg, 2); m88rs2000_readreg()
115 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_get_mclk() local
119 reg = m88rs2000_readreg(state, 0x86); m88rs2000_get_mclk()
133 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_set_carrieroffset() local
148 ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4)); m88rs2000_set_carrieroffset()
150 reg = m88rs2000_readreg(state, 0x9d); m88rs2000_set_carrieroffset()
154 ret |= m88rs2000_writereg(state, 0x9d, reg); m88rs2000_set_carrieroffset()
161 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_set_symbolrate() local
183 ret = m88rs2000_writereg(state, 0x93, b[2]); m88rs2000_set_symbolrate()
184 ret |= m88rs2000_writereg(state, 0x94, b[1]); m88rs2000_set_symbolrate()
185 ret |= m88rs2000_writereg(state, 0x95, b[0]); m88rs2000_set_symbolrate()
188 ret |= m88rs2000_writereg(state, 0xa0, 0x20); m88rs2000_set_symbolrate()
190 ret |= m88rs2000_writereg(state, 0xa0, 0x60); m88rs2000_set_symbolrate()
192 ret |= m88rs2000_writereg(state, 0xa1, 0xe0); m88rs2000_set_symbolrate()
195 ret |= m88rs2000_writereg(state, 0xa3, 0x20); m88rs2000_set_symbolrate()
197 ret |= m88rs2000_writereg(state, 0xa3, 0x98); m88rs2000_set_symbolrate()
199 ret |= m88rs2000_writereg(state, 0xa3, 0x90); m88rs2000_set_symbolrate()
208 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_send_diseqc_msg() local
213 m88rs2000_writereg(state, 0x9a, 0x30); m88rs2000_send_diseqc_msg()
214 reg = m88rs2000_readreg(state, 0xb2); m88rs2000_send_diseqc_msg()
216 m88rs2000_writereg(state, 0xb2, reg); m88rs2000_send_diseqc_msg()
218 m88rs2000_writereg(state, 0xb3 + i, m->msg[i]); m88rs2000_send_diseqc_msg()
220 reg = m88rs2000_readreg(state, 0xb1); m88rs2000_send_diseqc_msg()
224 m88rs2000_writereg(state, 0xb1, reg); m88rs2000_send_diseqc_msg()
227 if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0) m88rs2000_send_diseqc_msg()
232 reg = m88rs2000_readreg(state, 0xb1); m88rs2000_send_diseqc_msg()
236 m88rs2000_writereg(state, 0xb1, reg); m88rs2000_send_diseqc_msg()
239 reg = m88rs2000_readreg(state, 0xb2); m88rs2000_send_diseqc_msg()
242 m88rs2000_writereg(state, 0xb2, reg); m88rs2000_send_diseqc_msg()
243 m88rs2000_writereg(state, 0x9a, 0xb0); m88rs2000_send_diseqc_msg()
252 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_send_diseqc_burst() local
255 m88rs2000_writereg(state, 0x9a, 0x30); m88rs2000_send_diseqc_burst()
257 reg0 = m88rs2000_readreg(state, 0xb1); m88rs2000_send_diseqc_burst()
258 reg1 = m88rs2000_readreg(state, 0xb2); m88rs2000_send_diseqc_burst()
260 m88rs2000_writereg(state, 0xb2, reg1); m88rs2000_send_diseqc_burst()
261 m88rs2000_writereg(state, 0xb1, reg0); m88rs2000_send_diseqc_burst()
262 m88rs2000_writereg(state, 0x9a, 0xb0); m88rs2000_send_diseqc_burst()
269 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_set_tone() local
271 m88rs2000_writereg(state, 0x9a, 0x30); m88rs2000_set_tone()
272 reg0 = m88rs2000_readreg(state, 0xb1); m88rs2000_set_tone()
273 reg1 = m88rs2000_readreg(state, 0xb2); m88rs2000_set_tone()
288 m88rs2000_writereg(state, 0xb2, reg1); m88rs2000_set_tone()
289 m88rs2000_writereg(state, 0xb1, reg0); m88rs2000_set_tone()
290 m88rs2000_writereg(state, 0x9a, 0xb0); m88rs2000_set_tone()
383 static int m88rs2000_tab_set(struct m88rs2000_state *state, m88rs2000_tab_set() argument
394 ret = m88rs2000_writereg(state, tab[i].reg, m88rs2000_tab_set()
417 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_set_voltage() local
420 data = m88rs2000_readreg(state, 0xb2); m88rs2000_set_voltage()
435 m88rs2000_writereg(state, 0xb2, data); m88rs2000_set_voltage()
442 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_init() local
447 if (state->config->inittab) m88rs2000_init()
448 ret = m88rs2000_tab_set(state, m88rs2000_init()
449 (struct inittab *)state->config->inittab); m88rs2000_init()
451 ret = m88rs2000_tab_set(state, m88rs2000_setup); m88rs2000_init()
458 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_sleep() local
461 ret = m88rs2000_tab_set(state, m88rs2000_shutdown); m88rs2000_sleep()
467 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_read_status() local
468 u8 reg = m88rs2000_readreg(state, 0x8c); m88rs2000_read_status()
475 if (state->config->set_ts_params) m88rs2000_read_status()
476 state->config->set_ts_params(fe, CALL_IS_READ); m88rs2000_read_status()
483 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_read_ber() local
486 m88rs2000_writereg(state, 0x9a, 0x30); m88rs2000_read_ber()
487 tmp0 = m88rs2000_readreg(state, 0xd8); m88rs2000_read_ber()
489 m88rs2000_writereg(state, 0x9a, 0xb0); m88rs2000_read_ber()
494 *ber = (m88rs2000_readreg(state, 0xd7) << 8) | m88rs2000_read_ber()
495 m88rs2000_readreg(state, 0xd6); m88rs2000_read_ber()
497 tmp1 = m88rs2000_readreg(state, 0xd9); m88rs2000_read_ber()
498 m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4); m88rs2000_read_ber()
500 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30); m88rs2000_read_ber()
501 m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30); m88rs2000_read_ber()
502 m88rs2000_writereg(state, 0x9a, 0xb0); m88rs2000_read_ber()
518 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_read_snr() local
520 *snr = 512 * m88rs2000_readreg(state, 0x65); m88rs2000_read_snr()
527 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_read_ucblocks() local
530 *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) | m88rs2000_read_ucblocks()
531 m88rs2000_readreg(state, 0xd4); m88rs2000_read_ucblocks()
532 tmp = m88rs2000_readreg(state, 0xd8); m88rs2000_read_ucblocks()
533 m88rs2000_writereg(state, 0xd8, tmp & ~0x20); m88rs2000_read_ucblocks()
535 m88rs2000_writereg(state, 0xd8, tmp | 0x20); m88rs2000_read_ucblocks()
536 m88rs2000_writereg(state, 0xd8, tmp | 0x20); m88rs2000_read_ucblocks()
541 static int m88rs2000_set_fec(struct m88rs2000_state *state, m88rs2000_set_fec() argument
568 reg = m88rs2000_readreg(state, 0x70); m88rs2000_set_fec()
570 ret = m88rs2000_writereg(state, 0x70, reg | fec_set); m88rs2000_set_fec()
572 ret |= m88rs2000_writereg(state, 0x76, 0x8); m88rs2000_set_fec()
577 static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state) m88rs2000_get_fec() argument
580 m88rs2000_writereg(state, 0x9a, 0x30); m88rs2000_get_fec()
581 reg = m88rs2000_readreg(state, 0x76); m88rs2000_get_fec()
582 m88rs2000_writereg(state, 0x9a, 0xb0); m88rs2000_get_fec()
607 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_set_frontend() local
615 state->no_lock_count = 0; m88rs2000_set_frontend()
642 ret = m88rs2000_writereg(state, 0x86, 0xc2); m88rs2000_set_frontend()
644 ret = m88rs2000_writereg(state, 0x86, 0xc6); m88rs2000_set_frontend()
652 ret = m88rs2000_writereg(state, 0xf1, 0xa4); m88rs2000_set_frontend()
654 ret = m88rs2000_writereg(state, 0xf1, 0xbf); m88rs2000_set_frontend()
656 ret |= m88rs2000_tab_set(state, fe_reset); m88rs2000_set_frontend()
661 ret = m88rs2000_set_fec(state, c->fec_inner); m88rs2000_set_frontend()
662 ret |= m88rs2000_writereg(state, 0x85, 0x1); m88rs2000_set_frontend()
663 ret |= m88rs2000_writereg(state, 0x8a, 0xbf); m88rs2000_set_frontend()
664 ret |= m88rs2000_writereg(state, 0x8d, 0x1e); m88rs2000_set_frontend()
665 ret |= m88rs2000_writereg(state, 0x90, 0xf1); m88rs2000_set_frontend()
666 ret |= m88rs2000_writereg(state, 0x91, 0x08); m88rs2000_set_frontend()
677 ret = m88rs2000_tab_set(state, fe_trigger); m88rs2000_set_frontend()
682 reg = m88rs2000_readreg(state, 0x8c); m88rs2000_set_frontend()
687 state->no_lock_count++; m88rs2000_set_frontend()
688 if (state->no_lock_count == 15) { m88rs2000_set_frontend()
689 reg = m88rs2000_readreg(state, 0x70); m88rs2000_set_frontend()
691 m88rs2000_writereg(state, 0x70, reg); m88rs2000_set_frontend()
692 state->no_lock_count = 0; m88rs2000_set_frontend()
698 state->fec_inner = m88rs2000_get_fec(state); m88rs2000_set_frontend()
700 reg = m88rs2000_readreg(state, 0x65); m88rs2000_set_frontend()
703 state->tuner_frequency = c->frequency; m88rs2000_set_frontend()
704 state->symbol_rate = c->symbol_rate; m88rs2000_set_frontend()
711 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_get_frontend() local
712 c->fec_inner = state->fec_inner; m88rs2000_get_frontend()
713 c->frequency = state->tuner_frequency; m88rs2000_get_frontend()
714 c->symbol_rate = state->symbol_rate; m88rs2000_get_frontend()
736 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_i2c_gate_ctrl() local
739 m88rs2000_writereg(state, 0x81, 0x84); m88rs2000_i2c_gate_ctrl()
741 m88rs2000_writereg(state, 0x81, 0x81); m88rs2000_i2c_gate_ctrl()
748 struct m88rs2000_state *state = fe->demodulator_priv; m88rs2000_release() local
749 kfree(state); m88rs2000_release()
791 struct m88rs2000_state *state = NULL; m88rs2000_attach() local
793 /* allocate memory for the internal state */ m88rs2000_attach()
794 state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL); m88rs2000_attach()
795 if (state == NULL) m88rs2000_attach()
798 /* setup the state */ m88rs2000_attach()
799 state->config = config; m88rs2000_attach()
800 state->i2c = i2c; m88rs2000_attach()
801 state->tuner_frequency = 0; m88rs2000_attach()
802 state->symbol_rate = 0; m88rs2000_attach()
803 state->fec_inner = 0; m88rs2000_attach()
806 memcpy(&state->frontend.ops, &m88rs2000_ops, m88rs2000_attach()
808 state->frontend.demodulator_priv = state; m88rs2000_attach()
809 return &state->frontend; m88rs2000_attach()
812 kfree(state); m88rs2000_attach()
H A Dstb0899_algo.c60 static u32 stb0899_get_srate(struct stb0899_state *state)
62 struct stb0899_internal *internal = &state->internal;
65 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
78 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate) stb0899_set_srate() argument
83 dprintk(state->verbose, FE_DEBUG, 1, "-->"); stb0899_set_srate()
108 stb0899_write_regs(state, STB0899_SFRH, sfr, 3); stb0899_set_srate()
132 long stb0899_carr_width(struct stb0899_state *state) stb0899_carr_width() argument
134 struct stb0899_internal *internal = &state->internal; stb0899_carr_width()
143 static void stb0899_first_subrange(struct stb0899_state *state) stb0899_first_subrange() argument
145 struct stb0899_internal *internal = &state->internal; stb0899_first_subrange()
146 struct stb0899_params *params = &state->params; stb0899_first_subrange()
147 struct stb0899_config *config = state->config; stb0899_first_subrange()
153 stb0899_i2c_gate_ctrl(&state->frontend, 1); stb0899_first_subrange()
154 config->tuner_get_bandwidth(&state->frontend, &bandwidth); stb0899_first_subrange()
155 stb0899_i2c_gate_ctrl(&state->frontend, 0); stb0899_first_subrange()
156 range = bandwidth - stb0899_carr_width(state) / 2; stb0899_first_subrange()
174 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state) stb0899_check_tmg() argument
176 struct stb0899_internal *internal = &state->internal; stb0899_check_tmg()
183 stb0899_write_reg(state, STB0899_RTF, 0xf2); stb0899_check_tmg()
184 reg = stb0899_read_reg(state, STB0899_TLIR); stb0899_check_tmg()
186 timing = stb0899_read_reg(state, STB0899_RTF); stb0899_check_tmg()
191 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !"); stb0899_check_tmg()
194 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !"); stb0899_check_tmg()
198 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !"); stb0899_check_tmg()
207 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state) stb0899_search_tmg() argument
209 struct stb0899_internal *internal = &state->internal; stb0899_search_tmg()
210 struct stb0899_params *params = &state->params; stb0899_search_tmg()
222 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) { stb0899_search_tmg()
232 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ stb0899_search_tmg()
238 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ stb0899_search_tmg()
240 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq); stb0899_search_tmg()
250 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state) stb0899_check_carrier() argument
252 struct stb0899_internal *internal = &state->internal; stb0899_check_carrier()
257 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_check_carrier()
259 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_check_carrier()
261 reg = stb0899_read_reg(state, STB0899_DSTATUS); stb0899_check_carrier()
262 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg); stb0899_check_carrier()
265 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !"); stb0899_check_carrier()
268 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !"); stb0899_check_carrier()
278 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state) stb0899_search_carrier() argument
280 struct stb0899_internal *internal = &state->internal; stb0899_search_carrier()
291 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_search_carrier()
293 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_search_carrier()
296 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk); stb0899_search_carrier()
297 if (stb0899_check_carrier(state) == NOCARRIER) { stb0899_search_carrier()
306 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_search_carrier()
308 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_search_carrier()
312 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ stb0899_search_carrier()
320 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ stb0899_search_carrier()
322 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq); stb0899_search_carrier()
334 static enum stb0899_status stb0899_check_data(struct stb0899_state *state) stb0899_check_data() argument
336 struct stb0899_internal *internal = &state->internal; stb0899_check_data()
337 struct stb0899_params *params = &state->params; stb0899_check_data()
345 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_check_data()
347 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_check_data()
349 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_check_data()
351 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_check_data()
363 stb0899_read_reg(state, STB0899_VSTATUS); stb0899_check_data()
365 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */ stb0899_check_data()
368 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_check_data()
379 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !"); stb0899_check_data()
389 static enum stb0899_status stb0899_search_data(struct stb0899_state *state) stb0899_search_data() argument
396 struct stb0899_internal *internal = &state->internal; stb0899_search_data()
397 struct stb0899_params *params = &state->params; stb0899_search_data()
404 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) { stb0899_search_data()
411 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk); stb0899_search_data()
412 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_search_data()
414 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_search_data()
418 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ stb0899_search_data()
420 stb0899_check_carrier(state); stb0899_search_data()
428 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ stb0899_search_data()
431 reg = stb0899_read_reg(state, STB0899_IQSWAP); stb0899_search_data()
438 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq); stb0899_search_data()
448 static enum stb0899_status stb0899_check_range(struct stb0899_state *state) stb0899_check_range() argument
450 struct stb0899_internal *internal = &state->internal; stb0899_check_range()
451 struct stb0899_params *params = &state->params; stb0899_check_range()
460 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !"); stb0899_check_range()
463 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !"); stb0899_check_range()
473 static void next_sub_range(struct stb0899_state *state) next_sub_range() argument
475 struct stb0899_internal *internal = &state->internal; next_sub_range()
476 struct stb0899_params *params = &state->params; next_sub_range()
501 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state) stb0899_dvbs_algo() argument
503 struct stb0899_params *params = &state->params; stb0899_dvbs_algo()
504 struct stb0899_internal *internal = &state->internal; stb0899_dvbs_algo()
505 struct stb0899_config *config = state->config; stb0899_dvbs_algo()
525 stb0899_set_srate(state, internal->master_clk, params->srate); stb0899_dvbs_algo()
528 stb0899_write_reg(state, STB0899_ACLC, 0x89); stb0899_dvbs_algo()
529 bclc = stb0899_read_reg(state, STB0899_BCLC); stb0899_dvbs_algo()
531 stb0899_write_reg(state, STB0899_BCLC, bclc); stb0899_dvbs_algo()
534 stb0899_write_reg(state, STB0899_ACLC, 0xc9); stb0899_dvbs_algo()
535 bclc = stb0899_read_reg(state, STB0899_BCLC); stb0899_dvbs_algo()
537 stb0899_write_reg(state, STB0899_BCLC, bclc); stb0899_dvbs_algo()
540 stb0899_write_reg(state, STB0899_ACLC, 0x89); stb0899_dvbs_algo()
541 bclc = stb0899_read_reg(state, STB0899_BCLC); stb0899_dvbs_algo()
543 stb0899_write_reg(state, STB0899_BCLC, bclc); stb0899_dvbs_algo()
546 stb0899_write_reg(state, STB0899_ACLC, 0xc8); stb0899_dvbs_algo()
547 bclc = stb0899_read_reg(state, STB0899_BCLC); stb0899_dvbs_algo()
549 stb0899_write_reg(state, STB0899_BCLC, bclc); stb0899_dvbs_algo()
553 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition"); stb0899_dvbs_algo()
555 stb0899_write_reg(state, STB0899_RTC, 0x46); stb0899_dvbs_algo()
556 stb0899_write_reg(state, STB0899_CFD, 0xee); stb0899_dvbs_algo()
564 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d", stb0899_dvbs_algo()
572 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger"); stb0899_dvbs_algo()
574 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs_algo()
576 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs_algo()
582 reg = stb0899_read_reg(state, STB0899_DEMAPVIT); stb0899_dvbs_algo()
584 stb0899_write_reg(state, STB0899_DEMAPVIT, reg); stb0899_dvbs_algo()
586 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */ stb0899_dvbs_algo()
587 stb0899_write_reg(state, STB0899_VITSYNC, 0x19); stb0899_dvbs_algo()
589 stb0899_first_subrange(state); stb0899_dvbs_algo()
593 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */ stb0899_dvbs_algo()
595 stb0899_write_reg(state, STB0899_RTF, 0); stb0899_dvbs_algo()
596 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_dvbs_algo()
598 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_dvbs_algo()
604 stb0899_i2c_gate_ctrl(&state->frontend, 1); stb0899_dvbs_algo()
607 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency"); stb0899_dvbs_algo()
608 if (state->config->tuner_set_frequency) stb0899_dvbs_algo()
609 state->config->tuner_set_frequency(&state->frontend, internal->freq); stb0899_dvbs_algo()
611 if (state->config->tuner_get_frequency) stb0899_dvbs_algo()
612 state->config->tuner_get_frequency(&state->frontend, &internal->freq); stb0899_dvbs_algo()
615 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq); stb0899_dvbs_algo()
620 config->tuner_get_bandwidth(&state->frontend, &bandwidth); stb0899_dvbs_algo()
623 stb0899_i2c_gate_ctrl(&state->frontend, 0); stb0899_dvbs_algo()
626 stb0899_search_tmg(state); /* For low rates (SCPC) */ stb0899_dvbs_algo()
628 stb0899_check_tmg(state); /* For high rates (MCPC) */ stb0899_dvbs_algo()
631 dprintk(state->verbose, FE_DEBUG, 1, stb0899_dvbs_algo()
635 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */ stb0899_dvbs_algo()
636 dprintk(state->verbose, FE_DEBUG, 1, stb0899_dvbs_algo()
640 if (stb0899_search_data(state) == DATAOK) { /* Check for data */ stb0899_dvbs_algo()
641 dprintk(state->verbose, FE_DEBUG, 1, stb0899_dvbs_algo()
645 if (stb0899_check_range(state) == RANGEOK) { stb0899_dvbs_algo()
646 dprintk(state->verbose, FE_DEBUG, 1, stb0899_dvbs_algo()
651 reg = stb0899_read_reg(state, STB0899_PLPARM); stb0899_dvbs_algo()
653 dprintk(state->verbose, FE_DEBUG, 1, stb0899_dvbs_algo()
657 dprintk(state->verbose, FE_DEBUG, 1, stb0899_dvbs_algo()
665 next_sub_range(state); stb0899_dvbs_algo()
670 stb0899_write_reg(state, STB0899_RTC, 0x33); stb0899_dvbs_algo()
671 stb0899_write_reg(state, STB0899_CFD, 0xf7); stb0899_dvbs_algo()
674 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !"); stb0899_dvbs_algo()
675 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */ stb0899_dvbs_algo()
676 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */ stb0899_dvbs_algo()
682 reg = stb0899_read_reg(state, STB0899_BCLC); stb0899_dvbs_algo()
685 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a); stb0899_dvbs_algo()
687 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
690 stb0899_write_reg(state, STB0899_DEMAPVIT, 44); stb0899_dvbs_algo()
692 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
695 stb0899_write_reg(state, STB0899_DEMAPVIT, 60); stb0899_dvbs_algo()
697 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
700 stb0899_write_reg(state, STB0899_DEMAPVIT, 75); stb0899_dvbs_algo()
702 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
705 stb0899_write_reg(state, STB0899_DEMAPVIT, 88); stb0899_dvbs_algo()
706 stb0899_write_reg(state, STB0899_ACLC, 0x88); stb0899_dvbs_algo()
707 stb0899_write_reg(state, STB0899_BCLC, 0x9a); stb0899_dvbs_algo()
710 stb0899_write_reg(state, STB0899_DEMAPVIT, 94); stb0899_dvbs_algo()
712 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
715 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate"); stb0899_dvbs_algo()
719 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs_algo()
721 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs_algo()
724 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_dvbs_algo()
726 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_dvbs_algo()
728 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10); stb0899_dvbs_algo()
736 * Configure UWP state machine
738 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state) stb0899_dvbs2_config_uwp() argument
740 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_config_uwp()
741 struct stb0899_config *config = state->config; stb0899_dvbs2_config_uwp()
759 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1); stb0899_dvbs2_config_uwp()
760 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2); stb0899_dvbs2_config_uwp()
761 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3); stb0899_dvbs2_config_uwp()
765 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg); stb0899_dvbs2_config_uwp()
772 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state) stb0899_dvbs2_config_csm_auto() argument
778 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg); stb0899_dvbs2_config_csm_auto()
799 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state) stb0899_dvbs2_calc_srate() argument
801 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_calc_srate()
802 struct stb0899_config *config = state->config; stb0899_dvbs2_calc_srate()
830 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state) stb0899_dvbs2_calc_dev() argument
832 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_calc_dev()
849 static void stb0899_dvbs2_set_srate(struct stb0899_state *state) stb0899_dvbs2_set_srate() argument
851 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_set_srate()
876 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl); stb0899_dvbs2_set_srate()
885 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias); stb0899_dvbs2_set_srate()
886 btr_nom_freq = stb0899_dvbs2_calc_srate(state); stb0899_dvbs2_set_srate()
887 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq); stb0899_dvbs2_set_srate()
889 correction = stb0899_dvbs2_calc_dev(state); stb0899_dvbs2_set_srate()
892 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); stb0899_dvbs2_set_srate()
896 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj); stb0899_dvbs2_set_srate()
903 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state) stb0899_dvbs2_set_btr_loopbw() argument
905 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_set_btr_loopbw()
906 struct stb0899_config *config = state->config; stb0899_dvbs2_set_btr_loopbw()
954 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg); stb0899_dvbs2_set_btr_loopbw()
956 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f); stb0899_dvbs2_set_btr_loopbw()
963 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk) stb0899_dvbs2_set_carr_freq() argument
965 struct stb0899_config *config = state->config; stb0899_dvbs2_set_carr_freq()
973 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); stb0899_dvbs2_set_carr_freq()
980 static void stb0899_dvbs2_init_calc(struct stb0899_state *state) stb0899_dvbs2_init_calc() argument
982 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_init_calc()
987 stb0899_dvbs2_config_uwp(state); stb0899_dvbs2_init_calc()
988 stb0899_dvbs2_config_csm_auto(state); stb0899_dvbs2_init_calc()
991 stb0899_dvbs2_set_srate(state); stb0899_dvbs2_init_calc()
992 stb0899_dvbs2_set_btr_loopbw(state); stb0899_dvbs2_init_calc()
1008 stb0899_dvbs2_set_carr_freq(state, internal->center_freq - stb0899_dvbs2_init_calc()
1012 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000); stb0899_dvbs2_init_calc()
1019 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg); stb0899_dvbs2_init_calc()
1026 static void stb0899_dvbs2_btr_init(struct stb0899_state *state) stb0899_dvbs2_btr_init() argument
1034 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); stb0899_dvbs2_btr_init()
1037 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000); stb0899_dvbs2_btr_init()
1038 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000); stb0899_dvbs2_btr_init()
1041 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000); stb0899_dvbs2_btr_init()
1042 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000); stb0899_dvbs2_btr_init()
1049 static void stb0899_dvbs2_reacquire(struct stb0899_state *state) stb0899_dvbs2_reacquire() argument
1055 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); stb0899_dvbs2_reacquire()
1058 stb0899_dvbs2_btr_init(state); stb0899_dvbs2_reacquire()
1061 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30)); stb0899_dvbs2_reacquire()
1062 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0); stb0899_dvbs2_reacquire()
1063 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0); stb0899_dvbs2_reacquire()
1064 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30)); stb0899_dvbs2_reacquire()
1065 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0); stb0899_dvbs2_reacquire()
1070 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); stb0899_dvbs2_reacquire()
1073 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1); stb0899_dvbs2_reacquire()
1074 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0); stb0899_dvbs2_reacquire()
1077 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1); stb0899_dvbs2_reacquire()
1080 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0); stb0899_dvbs2_reacquire()
1087 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); stb0899_dvbs2_reacquire()
1090 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a); stb0899_dvbs2_reacquire()
1097 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout) stb0899_dvbs2_get_dmd_status() argument
1104 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg); stb0899_dvbs2_get_dmd_status()
1106 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !"); stb0899_dvbs2_get_dmd_status()
1108 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg); stb0899_dvbs2_get_dmd_status()
1120 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !"); stb0899_dvbs2_get_dmd_status()
1131 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout) stb0899_dvbs2_get_data_lock() argument
1137 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); stb0899_dvbs2_get_data_lock()
1138 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg); stb0899_dvbs2_get_data_lock()
1150 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout) stb0899_dvbs2_get_fec_status() argument
1155 Locked = stb0899_dvbs2_get_data_lock(state, 1); stb0899_dvbs2_get_fec_status()
1162 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !"); stb0899_dvbs2_get_fec_status()
1174 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod) stb0899_dvbs2_init_csm() argument
1176 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_init_csm()
1251 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); stb0899_dvbs2_init_csm()
1270 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); stb0899_dvbs2_init_csm()
1271 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2); stb0899_dvbs2_init_csm()
1272 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3); stb0899_dvbs2_init_csm()
1273 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4); stb0899_dvbs2_init_csm()
1281 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state) stb0899_dvbs2_get_srate() argument
1283 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_get_srate()
1284 struct stb0899_config *config = state->config; stb0899_dvbs2_get_srate()
1315 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state) stb0899_dvbs2_algo() argument
1317 struct stb0899_internal *internal = &state->internal; stb0899_dvbs2_algo()
1348 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs2_algo()
1350 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs2_algo()
1353 stb0899_i2c_gate_ctrl(&state->frontend, 1); stb0899_dvbs2_algo()
1356 if (state->config->tuner_set_frequency) stb0899_dvbs2_algo()
1357 state->config->tuner_set_frequency(&state->frontend, internal->freq); stb0899_dvbs2_algo()
1358 if (state->config->tuner_get_frequency) stb0899_dvbs2_algo()
1359 state->config->tuner_get_frequency(&state->frontend, &internal->freq); stb0899_dvbs2_algo()
1362 stb0899_i2c_gate_ctrl(&state->frontend, 0); stb0899_dvbs2_algo()
1368 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); stb0899_dvbs2_algo()
1372 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); stb0899_dvbs2_algo()
1375 stb0899_dvbs2_init_calc(state); stb0899_dvbs2_algo()
1386 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); stb0899_dvbs2_algo()
1387 stb0899_dvbs2_reacquire(state); stb0899_dvbs2_algo()
1390 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime); stb0899_dvbs2_algo()
1393 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !"); stb0899_dvbs2_algo()
1396 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); stb0899_dvbs2_algo()
1406 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); stb0899_dvbs2_algo()
1407 stb0899_dvbs2_reacquire(state); stb0899_dvbs2_algo()
1408 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime); stb0899_dvbs2_algo()
1418 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); stb0899_dvbs2_algo()
1420 stb0899_dvbs2_reacquire(state); stb0899_dvbs2_algo()
1423 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime); stb0899_dvbs2_algo()
1427 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); stb0899_dvbs2_algo()
1436 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); stb0899_dvbs2_algo()
1438 stb0899_dvbs2_reacquire(state); stb0899_dvbs2_algo()
1439 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime); stb0899_dvbs2_algo()
1449 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !"); stb0899_dvbs2_algo()
1458 stb0899_dvbs2_init_csm(state, pilots, modcod); stb0899_dvbs2_algo()
1460 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); stb0899_dvbs2_algo()
1466 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); stb0899_dvbs2_algo()
1469 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); stb0899_dvbs2_algo()
1471 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); stb0899_dvbs2_algo()
1483 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); stb0899_dvbs2_algo()
1489 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); stb0899_dvbs2_algo()
1507 internal->srate = stb0899_dvbs2_get_srate(state); stb0899_dvbs2_algo()
1522 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); stb0899_dvbs2_algo()
1526 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); stb0899_dvbs2_algo()
1530 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs2_algo()
1532 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs2_algo()
H A Dtda10048.c221 static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data) tda10048_writereg() argument
223 struct tda10048_config *config = &state->config; tda10048_writereg()
232 ret = i2c_transfer(state->i2c, &msg, 1); tda10048_writereg()
240 static u8 tda10048_readreg(struct tda10048_state *state, u8 reg) tda10048_readreg() argument
242 struct tda10048_config *config = &state->config; tda10048_readreg()
254 ret = i2c_transfer(state->i2c, msg, 2); tda10048_readreg()
263 static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg, tda10048_writeregbulk() argument
266 struct tda10048_config *config = &state->config; tda10048_writeregbulk()
290 ret = i2c_transfer(state->i2c, &msg, 1); tda10048_writeregbulk()
306 struct tda10048_state *state = fe->demodulator_priv; tda10048_set_phy2() local
333 tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t); tda10048_set_phy2()
334 tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8)); tda10048_set_phy2()
342 struct tda10048_state *state = fe->demodulator_priv; tda10048_set_wref() local
361 tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t); tda10048_set_wref()
362 tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8)); tda10048_set_wref()
363 tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16)); tda10048_set_wref()
364 tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24)); tda10048_set_wref()
372 struct tda10048_state *state = fe->demodulator_priv; tda10048_set_invwref() local
389 tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t); tda10048_set_invwref()
390 tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8)); tda10048_set_invwref()
398 struct tda10048_state *state = fe->demodulator_priv; tda10048_set_bandwidth() local
406 tda10048_set_wref(fe, state->sample_freq, bw); tda10048_set_bandwidth()
407 tda10048_set_invwref(fe, state->sample_freq, bw); tda10048_set_bandwidth()
414 state->bandwidth = bw; tda10048_set_bandwidth()
421 struct tda10048_state *state = fe->demodulator_priv; tda10048_set_if() local
422 struct tda10048_config *config = &state->config; tda10048_set_if()
448 state->freq_if_hz = pll_tab[i].if_freq_khz * 1000; tda10048_set_if()
449 state->xtal_hz = pll_tab[i].clk_freq_khz * 1000; tda10048_set_if()
459 dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz); tda10048_set_if()
460 dprintk(1, "- xtal_hz = %d\n", state->xtal_hz); tda10048_set_if()
461 dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor); tda10048_set_if()
462 dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor); tda10048_set_if()
463 dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor); tda10048_set_if()
466 state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45); tda10048_set_if()
467 state->sample_freq /= (state->pll_nfactor + 1); tda10048_set_if()
468 state->sample_freq /= (state->pll_pfactor + 4); tda10048_set_if()
469 dprintk(1, "- sample_freq = %d\n", state->sample_freq); tda10048_set_if()
472 tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz); tda10048_set_if()
479 struct tda10048_state *state = fe->demodulator_priv; tda10048_firmware_upload() local
480 struct tda10048_config *config = &state->config; tda10048_firmware_upload()
496 state->i2c->dev.parent); tda10048_firmware_upload()
515 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, tda10048_firmware_upload()
516 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) tda10048_firmware_upload()
518 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, tda10048_firmware_upload()
519 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) tda10048_firmware_upload()
523 tda10048_writereg(state, TDA10048_CONF_C4_1, tda10048_firmware_upload()
524 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9); tda10048_firmware_upload()
527 tda10048_writereg(state, TDA10048_CONF_C4_1, tda10048_firmware_upload()
528 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08); tda10048_firmware_upload()
531 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0); tda10048_firmware_upload()
541 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN, tda10048_firmware_upload()
553 if (tda10048_readreg(state, TDA10048_SYNC_STATUS) tda10048_firmware_upload()
565 state->fwloaded = 1; tda10048_firmware_upload()
574 struct tda10048_state *state = fe->demodulator_priv; tda10048_set_inversion() local
579 tda10048_writereg(state, TDA10048_CONF_C1_1, tda10048_set_inversion()
580 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20); tda10048_set_inversion()
582 tda10048_writereg(state, TDA10048_CONF_C1_1, tda10048_set_inversion()
583 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf); tda10048_set_inversion()
589 static int tda10048_get_tps(struct tda10048_state *state, tda10048_get_tps() argument
595 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01)) tda10048_get_tps()
598 val = tda10048_readreg(state, TDA10048_OUT_CONF2); tda10048_get_tps()
642 val = tda10048_readreg(state, TDA10048_OUT_CONF3); tda10048_get_tps()
661 val = tda10048_readreg(state, TDA10048_OUT_CONF1); tda10048_get_tps()
690 struct tda10048_state *state = fe->demodulator_priv; tda10048_i2c_gate_ctrl() local
691 struct tda10048_config *config = &state->config; tda10048_i2c_gate_ctrl()
698 return tda10048_writereg(state, TDA10048_CONF_C4_1, tda10048_i2c_gate_ctrl()
699 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02); tda10048_i2c_gate_ctrl()
701 return tda10048_writereg(state, TDA10048_CONF_C4_1, tda10048_i2c_gate_ctrl()
702 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd); tda10048_i2c_gate_ctrl()
707 struct tda10048_state *state = fe->demodulator_priv; tda10048_output_mode() local
710 /* Ensure pins are out of tri-state */ tda10048_output_mode()
711 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21); tda10048_output_mode()
712 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00); tda10048_output_mode()
715 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20); tda10048_output_mode()
716 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0); tda10048_output_mode()
718 tda10048_writereg(state, TDA10048_IC_MODE, 0x00); tda10048_output_mode()
719 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01); tda10048_output_mode()
730 struct tda10048_state *state = fe->demodulator_priv; tda10048_set_frontend() local
735 if (p->bandwidth_hz != state->bandwidth) { tda10048_set_frontend()
752 tda10048_writereg(state, TDA10048_AUTO, 0x57); tda10048_set_frontend()
754 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B); tda10048_set_frontend()
762 struct tda10048_state *state = fe->demodulator_priv; tda10048_init() local
763 struct tda10048_config *config = &state->config; tda10048_init()
769 init_tab[4].data = (u8)(state->pll_mfactor); tda10048_init()
770 init_tab[5].data = (u8)(state->pll_nfactor) | 0x40; tda10048_init()
774 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data); tda10048_init()
776 if (state->fwloaded == 0) tda10048_init()
797 struct tda10048_state *state = fe->demodulator_priv; tda10048_read_status() local
802 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS); tda10048_read_status()
823 struct tda10048_state *state = fe->demodulator_priv; tda10048_read_ber() local
831 if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) { tda10048_read_ber()
832 cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 | tda10048_read_ber()
833 tda10048_readreg(state, TDA10048_CBER_LSB); tda10048_read_ber()
834 cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 | tda10048_read_ber()
835 tda10048_readreg(state, TDA10048_CBER_NMAX_LSB); tda10048_read_ber()
841 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39); tda10048_read_ber()
852 struct tda10048_state *state = fe->demodulator_priv; tda10048_read_signal_strength() local
859 v = tda10048_readreg(state, TDA10048_NP_OUT); tda10048_read_signal_strength()
998 struct tda10048_state *state = fe->demodulator_priv; tda10048_read_snr() local
1004 v = tda10048_readreg(state, TDA10048_NP_OUT); tda10048_read_snr()
1018 struct tda10048_state *state = fe->demodulator_priv; tda10048_read_ucblocks() local
1022 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | tda10048_read_ucblocks()
1023 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); tda10048_read_ucblocks()
1026 tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80); tda10048_read_ucblocks()
1034 struct tda10048_state *state = fe->demodulator_priv; tda10048_get_frontend() local
1038 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1) tda10048_get_frontend()
1041 return tda10048_get_tps(state, p); tda10048_get_frontend()
1053 struct tda10048_state *state = fe->demodulator_priv; tda10048_release() local
1055 kfree(state); tda10048_release()
1060 struct tda10048_state *state = fe->demodulator_priv; tda10048_establish_defaults() local
1061 struct tda10048_config *config = &state->config; tda10048_establish_defaults()
1102 struct tda10048_state *state = NULL; tda10048_attach() local
1106 /* allocate memory for the internal state */ tda10048_attach()
1107 state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL); tda10048_attach()
1108 if (state == NULL) tda10048_attach()
1111 /* setup the state and clone the config */ tda10048_attach()
1112 memcpy(&state->config, config, sizeof(*config)); tda10048_attach()
1113 state->i2c = i2c; tda10048_attach()
1114 state->fwloaded = config->no_firmware; tda10048_attach()
1115 state->bandwidth = 8000000; tda10048_attach()
1118 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048) tda10048_attach()
1122 memcpy(&state->frontend.ops, &tda10048_ops, tda10048_attach()
1124 state->frontend.demodulator_priv = state; tda10048_attach()
1128 state->pll_mfactor = config->pll_m; tda10048_attach()
1129 state->pll_nfactor = config->pll_n; tda10048_attach()
1130 state->pll_pfactor = config->pll_p; tda10048_attach()
1132 state->pll_mfactor = 10; tda10048_attach()
1133 state->pll_nfactor = 3; tda10048_attach()
1134 state->pll_pfactor = 0; tda10048_attach()
1138 tda10048_establish_defaults(&state->frontend); tda10048_attach()
1141 if (tda10048_set_if(&state->frontend, 8000000) != 0) tda10048_attach()
1145 if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0) tda10048_attach()
1149 tda10048_i2c_gate_ctrl(&state->frontend, 0); tda10048_attach()
1151 return &state->frontend; tda10048_attach()
1154 kfree(state); tda10048_attach()
H A Dtda10021.c72 static int _tda10021_writereg (struct tda10021_state* state, u8 reg, u8 data) _tda10021_writereg() argument
75 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; _tda10021_writereg()
78 ret = i2c_transfer (state->i2c, &msg, 1); _tda10021_writereg()
82 state->frontend.dvb->num, __func__, reg, data, ret); _tda10021_writereg()
88 static u8 tda10021_readreg (struct tda10021_state* state, u8 reg) tda10021_readreg() argument
92 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, tda10021_readreg()
93 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; tda10021_readreg()
96 ret = i2c_transfer (state->i2c, msg, 2); tda10021_readreg()
105 static int lock_tuner(struct tda10021_state* state) lock_tuner() argument
108 struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2}; lock_tuner()
110 if(i2c_transfer(state->i2c, &msg, 1) != 1) lock_tuner()
119 static int unlock_tuner(struct tda10021_state* state) unlock_tuner() argument
122 struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2}; unlock_tuner()
124 if(i2c_transfer(state->i2c, &msg_post, 1) != 1) unlock_tuner()
132 static int tda10021_setup_reg0 (struct tda10021_state* state, u8 reg0, tda10021_setup_reg0() argument
135 reg0 |= state->reg0 & 0x63; tda10021_setup_reg0()
137 if ((INVERSION_ON == inversion) ^ (state->config->invert == 0)) tda10021_setup_reg0()
142 _tda10021_writereg (state, 0x00, reg0 & 0xfe); tda10021_setup_reg0()
143 _tda10021_writereg (state, 0x00, reg0 | 0x01); tda10021_setup_reg0()
145 state->reg0 = reg0; tda10021_setup_reg0()
149 static int tda10021_set_symbolrate (struct tda10021_state* state, u32 symbolrate) tda10021_set_symbolrate() argument
191 _tda10021_writereg (state, 0x03, NDEC); tda10021_set_symbolrate()
192 _tda10021_writereg (state, 0x0a, BDR&0xff); tda10021_set_symbolrate()
193 _tda10021_writereg (state, 0x0b, (BDR>> 8)&0xff); tda10021_set_symbolrate()
194 _tda10021_writereg (state, 0x0c, (BDR>>16)&0x3f); tda10021_set_symbolrate()
196 _tda10021_writereg (state, 0x0d, BDRI); tda10021_set_symbolrate()
197 _tda10021_writereg (state, 0x0e, SFIL); tda10021_set_symbolrate()
204 struct tda10021_state* state = fe->demodulator_priv; tda10021_init() local
212 _tda10021_writereg (state, i, tda10021_inittab[i]); tda10021_init()
214 _tda10021_writereg (state, 0x34, state->pwm); tda10021_init()
223 _tda10021_writereg(state, 0x2a, tda10021_inittab[0x2a] & 0xef); tda10021_init()
238 struct tda10021_state* state = fe->demodulator_priv; tda10021_set_parameters() local
289 tda10021_set_symbolrate(state, c->symbol_rate); tda10021_set_parameters()
290 _tda10021_writereg(state, 0x34, state->pwm); tda10021_set_parameters()
292 _tda10021_writereg(state, 0x01, qam_params[qam].agcref); tda10021_set_parameters()
293 _tda10021_writereg(state, 0x05, qam_params[qam].lthr); tda10021_set_parameters()
294 _tda10021_writereg(state, 0x08, qam_params[qam].mseth); tda10021_set_parameters()
295 _tda10021_writereg(state, 0x09, qam_params[qam].aref); tda10021_set_parameters()
301 reg0x3d = tda10021_readreg (state, 0x3d); tda10021_set_parameters()
303 _tda10021_writereg (state, 0x3d, 0x01 | reg0x3d); tda10021_set_parameters()
305 _tda10021_writereg (state, 0x3d, 0xfe & reg0x3d); tda10021_set_parameters()
306 tda10021_setup_reg0(state, qam_params[qam].conf, c->inversion); tda10021_set_parameters()
313 struct tda10021_state* state = fe->demodulator_priv; tda10021_read_status() local
317 //0x11[0] == EQALGO -> Equalizer algorithms state tda10021_read_status()
322 sync = tda10021_readreg (state, 0x11); tda10021_read_status()
338 struct tda10021_state* state = fe->demodulator_priv; tda10021_read_ber() local
340 u32 _ber = tda10021_readreg(state, 0x14) | tda10021_read_ber()
341 (tda10021_readreg(state, 0x15) << 8) | tda10021_read_ber()
342 ((tda10021_readreg(state, 0x16) & 0x0f) << 16); tda10021_read_ber()
343 _tda10021_writereg(state, 0x10, (tda10021_readreg(state, 0x10) & ~0xc0) tda10021_read_ber()
352 struct tda10021_state* state = fe->demodulator_priv; tda10021_read_signal_strength() local
354 u8 config = tda10021_readreg(state, 0x02); tda10021_read_signal_strength()
355 u8 gain = tda10021_readreg(state, 0x17); tda10021_read_signal_strength()
366 struct tda10021_state* state = fe->demodulator_priv; tda10021_read_snr() local
368 u8 quality = ~tda10021_readreg(state, 0x18); tda10021_read_snr()
376 struct tda10021_state* state = fe->demodulator_priv; tda10021_read_ucblocks() local
378 *ucblocks = tda10021_readreg (state, 0x13) & 0x7f; tda10021_read_ucblocks()
383 _tda10021_writereg (state, 0x10, tda10021_inittab[0x10] & 0xdf); tda10021_read_ucblocks()
384 _tda10021_writereg (state, 0x10, tda10021_inittab[0x10]); tda10021_read_ucblocks()
392 struct tda10021_state* state = fe->demodulator_priv; tda10021_get_frontend() local
396 sync = tda10021_readreg(state, 0x11); tda10021_get_frontend()
397 afc = tda10021_readreg(state, 0x19); tda10021_get_frontend()
402 state->frontend.dvb->num, afc, tda10021_get_frontend()
406 p->inversion = ((state->reg0 & 0x20) == 0x20) ^ (state->config->invert != 0) ? INVERSION_ON : INVERSION_OFF; tda10021_get_frontend()
407 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16; tda10021_get_frontend()
420 struct tda10021_state* state = fe->demodulator_priv; tda10021_i2c_gate_ctrl() local
423 lock_tuner(state); tda10021_i2c_gate_ctrl()
425 unlock_tuner(state); tda10021_i2c_gate_ctrl()
432 struct tda10021_state* state = fe->demodulator_priv; tda10021_sleep() local
434 _tda10021_writereg (state, 0x1b, 0x02); /* pdown ADC */ tda10021_sleep()
435 _tda10021_writereg (state, 0x00, 0x80); /* standby */ tda10021_sleep()
442 struct tda10021_state* state = fe->demodulator_priv; tda10021_release() local
443 kfree(state); tda10021_release()
452 struct tda10021_state* state = NULL; tda10021_attach() local
455 /* allocate memory for the internal state */ tda10021_attach()
456 state = kzalloc(sizeof(struct tda10021_state), GFP_KERNEL); tda10021_attach()
457 if (state == NULL) goto error; tda10021_attach()
459 /* setup the state */ tda10021_attach()
460 state->config = config; tda10021_attach()
461 state->i2c = i2c; tda10021_attach()
462 state->pwm = pwm; tda10021_attach()
463 state->reg0 = tda10021_inittab[0]; tda10021_attach()
466 id = tda10021_readreg(state, 0x1a); tda10021_attach()
474 state->config->demod_address, id); tda10021_attach()
477 memcpy(&state->frontend.ops, &tda10021_ops, sizeof(struct dvb_frontend_ops)); tda10021_attach()
478 state->frontend.demodulator_priv = state; tda10021_attach()
479 return &state->frontend; tda10021_attach()
482 kfree(state); tda10021_attach()
H A Dlg2160.c67 static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val) lg216x_write_reg() argument
72 .addr = state->cfg->i2c_addr, .flags = 0, lg216x_write_reg()
78 ret = i2c_transfer(state->i2c_adap, &msg, 1); lg216x_write_reg()
91 static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val) lg216x_read_reg() argument
96 { .addr = state->cfg->i2c_addr, lg216x_read_reg()
98 { .addr = state->cfg->i2c_addr, lg216x_read_reg()
104 ret = i2c_transfer(state->i2c_adap, msg, 2); lg216x_read_reg()
108 state->cfg->i2c_addr, reg, ret); lg216x_read_reg()
122 static int lg216x_write_regs(struct lg216x_state *state, lg216x_write_regs() argument
130 ret = lg216x_write_reg(state, regs[i].reg, regs[i].val); lg216x_write_regs()
137 static int lg216x_set_reg_bit(struct lg216x_state *state, lg216x_set_reg_bit() argument
145 ret = lg216x_read_reg(state, reg, &val); lg216x_set_reg_bit()
152 ret = lg216x_write_reg(state, reg, val); lg216x_set_reg_bit()
162 struct lg216x_state *state = fe->demodulator_priv; lg216x_i2c_gate_ctrl() local
165 if (state->cfg->deny_i2c_rptr) lg216x_i2c_gate_ctrl()
170 ret = lg216x_set_reg_bit(state, 0x0000, 0, enable ? 0 : 1); lg216x_i2c_gate_ctrl()
177 static int lg216x_soft_reset(struct lg216x_state *state) lg216x_soft_reset() argument
183 ret = lg216x_write_reg(state, 0x0002, 0x00); lg216x_soft_reset()
188 ret = lg216x_write_reg(state, 0x0002, 0x01); lg216x_soft_reset()
192 state->last_reset = jiffies_to_msecs(jiffies); lg216x_soft_reset()
197 static int lg216x_initialize(struct lg216x_state *state) lg216x_initialize() argument
226 switch (state->cfg->lg_chip) { lg216x_initialize()
228 ret = lg216x_write_regs(state, lg216x_initialize()
232 ret = lg216x_write_regs(state, lg216x_initialize()
242 ret = lg216x_soft_reset(state); lg216x_initialize()
250 static int lg216x_set_if(struct lg216x_state *state) lg216x_set_if() argument
255 lg_dbg("%d KHz\n", state->cfg->if_khz); lg216x_set_if()
257 ret = lg216x_read_reg(state, 0x0132, &val); lg216x_set_if()
262 val |= (0 == state->cfg->if_khz) ? 0x04 : 0x00; lg216x_set_if()
264 ret = lg216x_write_reg(state, 0x0132, val); lg216x_set_if()
274 static int lg2160_agc_fix(struct lg216x_state *state, lg2160_agc_fix() argument
280 ret = lg216x_read_reg(state, 0x0100, &val); lg2160_agc_fix()
288 ret = lg216x_write_reg(state, 0x0100, val); lg2160_agc_fix()
295 static int lg2160_agc_freeze(struct lg216x_state *state,
301 ret = lg216x_read_reg(state, 0x0100, &val);
309 ret = lg216x_write_reg(state, 0x0100, val);
316 static int lg2160_agc_polarity(struct lg216x_state *state, lg2160_agc_polarity() argument
322 ret = lg216x_read_reg(state, 0x0100, &val); lg2160_agc_polarity()
330 ret = lg216x_write_reg(state, 0x0100, val); lg2160_agc_polarity()
336 static int lg2160_tuner_pwr_save_polarity(struct lg216x_state *state, lg2160_tuner_pwr_save_polarity() argument
342 ret = lg216x_read_reg(state, 0x0008, &val); lg2160_tuner_pwr_save_polarity()
349 ret = lg216x_write_reg(state, 0x0008, val); lg2160_tuner_pwr_save_polarity()
355 static int lg2160_spectrum_polarity(struct lg216x_state *state, lg2160_spectrum_polarity() argument
361 ret = lg216x_read_reg(state, 0x0132, &val); lg2160_spectrum_polarity()
368 ret = lg216x_write_reg(state, 0x0132, val); lg2160_spectrum_polarity()
371 return lg216x_soft_reset(state); lg2160_spectrum_polarity()
374 static int lg2160_tuner_pwr_save(struct lg216x_state *state, int onoff) lg2160_tuner_pwr_save() argument
379 ret = lg216x_read_reg(state, 0x0007, &val); lg2160_tuner_pwr_save()
386 ret = lg216x_write_reg(state, 0x0007, val); lg2160_tuner_pwr_save()
392 static int lg216x_set_parade(struct lg216x_state *state, int id) lg216x_set_parade() argument
396 ret = lg216x_write_reg(state, 0x013e, id & 0x7f); lg216x_set_parade()
400 state->parade_id = id & 0x7f; lg216x_set_parade()
405 static int lg216x_set_ensemble(struct lg216x_state *state, int id) lg216x_set_ensemble() argument
411 switch (state->cfg->lg_chip) { lg216x_set_ensemble()
421 ret = lg216x_read_reg(state, reg, &val); lg216x_set_ensemble()
428 ret = lg216x_write_reg(state, reg, val); lg216x_set_ensemble()
434 static int lg2160_set_spi_clock(struct lg216x_state *state) lg2160_set_spi_clock() argument
439 ret = lg216x_read_reg(state, 0x0014, &val); lg2160_set_spi_clock()
444 val |= (state->cfg->spi_clock << 2); lg2160_set_spi_clock()
446 ret = lg216x_write_reg(state, 0x0014, val); lg2160_set_spi_clock()
452 static int lg2161_set_output_interface(struct lg216x_state *state) lg2161_set_output_interface() argument
457 ret = lg216x_read_reg(state, 0x0014, &val); lg2161_set_output_interface()
462 val |= state->cfg->output_if; /* FIXME: needs sanity check */ lg2161_set_output_interface()
464 ret = lg216x_write_reg(state, 0x0014, val); lg2161_set_output_interface()
470 static int lg216x_enable_fic(struct lg216x_state *state, int onoff) lg216x_enable_fic() argument
474 ret = lg216x_write_reg(state, 0x0017, 0x23); lg216x_enable_fic()
478 ret = lg216x_write_reg(state, 0x0016, 0xfc); lg216x_enable_fic()
482 switch (state->cfg->lg_chip) { lg216x_enable_fic()
484 ret = lg216x_write_reg(state, 0x0016, lg216x_enable_fic()
488 ret = lg216x_write_reg(state, 0x0016, (onoff) ? 0x10 : 0x00); lg216x_enable_fic()
494 ret = lg216x_initialize(state); lg216x_enable_fic()
499 ret = lg216x_write_reg(state, 0x0017, 0x03); lg216x_enable_fic()
508 static int lg216x_get_fic_version(struct lg216x_state *state, u8 *ficver) lg216x_get_fic_version() argument
515 ret = lg216x_read_reg(state, 0x0128, &val); lg216x_get_fic_version()
525 static int lg2160_get_parade_id(struct lg216x_state *state, u8 *id)
532 ret = lg216x_read_reg(state, 0x0123, &val);
542 static int lg216x_get_nog(struct lg216x_state *state, u8 *nog) lg216x_get_nog() argument
549 ret = lg216x_read_reg(state, 0x0124, &val); lg216x_get_nog()
558 static int lg216x_get_tnog(struct lg216x_state *state, u8 *tnog) lg216x_get_tnog() argument
565 ret = lg216x_read_reg(state, 0x0125, &val); lg216x_get_tnog()
574 static int lg216x_get_sgn(struct lg216x_state *state, u8 *sgn) lg216x_get_sgn() argument
581 ret = lg216x_read_reg(state, 0x0124, &val); lg216x_get_sgn()
590 static int lg216x_get_prc(struct lg216x_state *state, u8 *prc) lg216x_get_prc() argument
597 ret = lg216x_read_reg(state, 0x0125, &val); lg216x_get_prc()
608 static int lg216x_get_rs_frame_mode(struct lg216x_state *state, lg216x_get_rs_frame_mode() argument
614 switch (state->cfg->lg_chip) { lg216x_get_rs_frame_mode()
616 ret = lg216x_read_reg(state, 0x0410, &val); lg216x_get_rs_frame_mode()
619 ret = lg216x_read_reg(state, 0x0513, &val); lg216x_get_rs_frame_mode()
648 int lg216x_get_rs_frame_ensemble(struct lg216x_state *state, lg216x_get_rs_frame_ensemble() argument
654 switch (state->cfg->lg_chip) { lg216x_get_rs_frame_ensemble()
656 ret = lg216x_read_reg(state, 0x0400, &val); lg216x_get_rs_frame_ensemble()
659 ret = lg216x_read_reg(state, 0x0500, &val); lg216x_get_rs_frame_ensemble()
673 static int lg216x_get_rs_code_mode(struct lg216x_state *state, lg216x_get_rs_code_mode() argument
680 switch (state->cfg->lg_chip) { lg216x_get_rs_code_mode()
682 ret = lg216x_read_reg(state, 0x0410, &val); lg216x_get_rs_code_mode()
685 ret = lg216x_read_reg(state, 0x0513, &val); lg216x_get_rs_code_mode()
699 static int lg216x_get_sccc_block_mode(struct lg216x_state *state, lg216x_get_sccc_block_mode() argument
705 switch (state->cfg->lg_chip) { lg216x_get_sccc_block_mode()
707 ret = lg216x_read_reg(state, 0x0315, &val); lg216x_get_sccc_block_mode()
710 ret = lg216x_read_reg(state, 0x0511, &val); lg216x_get_sccc_block_mode()
733 static int lg216x_get_sccc_code_mode(struct lg216x_state *state, lg216x_get_sccc_code_mode() argument
742 switch (state->cfg->lg_chip) { lg216x_get_sccc_code_mode()
744 ret = lg216x_read_reg(state, 0x0316, &val); lg216x_get_sccc_code_mode()
747 ret = lg216x_read_reg(state, 0x0512, &val); lg216x_get_sccc_code_mode()
809 static int lg216x_read_fic_err_count(struct lg216x_state *state, u8 *err)
816 switch (state->cfg->lg_chip) {
818 ret = lg216x_read_reg(state, 0x0012, &fic_err);
821 ret = lg216x_read_reg(state, 0x001e, &fic_err);
832 static int lg2160_read_crc_err_count(struct lg216x_state *state, u16 *err)
839 ret = lg216x_read_reg(state, 0x0411, &crc_err1);
843 ret = lg216x_read_reg(state, 0x0412, &crc_err2);
852 static int lg2161_read_crc_err_count(struct lg216x_state *state, u16 *err)
859 ret = lg216x_read_reg(state, 0x0612, &crc_err);
868 static int lg216x_read_crc_err_count(struct lg216x_state *state, u16 *err)
871 switch (state->cfg->lg_chip) {
873 ret = lg2160_read_crc_err_count(state, err);
876 ret = lg2161_read_crc_err_count(state, err);
885 static int lg2160_read_rs_err_count(struct lg216x_state *state, u16 *err)
892 ret = lg216x_read_reg(state, 0x0413, &rs_err1);
896 ret = lg216x_read_reg(state, 0x0414, &rs_err2);
905 static int lg2161_read_rs_err_count(struct lg216x_state *state, u16 *err)
912 ret = lg216x_read_reg(state, 0x0613, &rs_err1);
916 ret = lg216x_read_reg(state, 0x0614, &rs_err2);
925 static int lg216x_read_rs_err_count(struct lg216x_state *state, u16 *err)
928 switch (state->cfg->lg_chip) {
930 ret = lg2160_read_rs_err_count(state, err);
933 ret = lg2161_read_rs_err_count(state, err);
947 struct lg216x_state *state = fe->demodulator_priv; lg216x_get_frontend() local
953 fe->dtv_property_cache.frequency = state->current_frequency; lg216x_get_frontend()
956 ret = lg216x_get_fic_version(state, lg216x_get_frontend()
960 if (state->fic_ver != fe->dtv_property_cache.atscmh_fic_ver) { lg216x_get_frontend()
961 state->fic_ver = fe->dtv_property_cache.atscmh_fic_ver; lg216x_get_frontend()
964 ret = lg2160_get_parade_id(state, lg216x_get_frontend()
969 fe->dtv_property_cache.atscmh_parade_id = state->parade_id; lg216x_get_frontend()
971 ret = lg216x_get_nog(state, lg216x_get_frontend()
975 ret = lg216x_get_tnog(state, lg216x_get_frontend()
979 ret = lg216x_get_sgn(state, lg216x_get_frontend()
983 ret = lg216x_get_prc(state, lg216x_get_frontend()
988 ret = lg216x_get_rs_frame_mode(state, lg216x_get_frontend()
993 ret = lg216x_get_rs_frame_ensemble(state, lg216x_get_frontend()
998 ret = lg216x_get_rs_code_mode(state, lg216x_get_frontend()
1005 ret = lg216x_get_sccc_block_mode(state, lg216x_get_frontend()
1010 ret = lg216x_get_sccc_code_mode(state, lg216x_get_frontend()
1023 ret = lg216x_read_fic_err_count(state, lg216x_get_frontend()
1027 ret = lg216x_read_crc_err_count(state, lg216x_get_frontend()
1031 ret = lg216x_read_rs_err_count(state, lg216x_get_frontend()
1036 switch (state->cfg->lg_chip) { lg216x_get_frontend()
1040 ((jiffies_to_msecs(jiffies) - state->last_reset) > 6000)) lg216x_get_frontend()
1041 ret = lg216x_soft_reset(state); lg216x_get_frontend()
1064 struct lg216x_state *state = fe->demodulator_priv; lg2160_set_frontend() local
1075 state->current_frequency = fe->dtv_property_cache.frequency; lg2160_set_frontend()
1078 ret = lg2160_agc_fix(state, 0, 0); lg2160_set_frontend()
1081 ret = lg2160_agc_polarity(state, 0, 0); lg2160_set_frontend()
1084 ret = lg2160_tuner_pwr_save_polarity(state, 1); lg2160_set_frontend()
1087 ret = lg216x_set_if(state); lg2160_set_frontend()
1090 ret = lg2160_spectrum_polarity(state, state->cfg->spectral_inversion); lg2160_set_frontend()
1095 ret = lg216x_soft_reset(state); lg2160_set_frontend()
1099 ret = lg2160_tuner_pwr_save(state, 0); lg2160_set_frontend()
1103 switch (state->cfg->lg_chip) { lg2160_set_frontend()
1105 ret = lg2160_set_spi_clock(state); lg2160_set_frontend()
1110 ret = lg2161_set_output_interface(state); lg2160_set_frontend()
1116 ret = lg216x_set_parade(state, fe->dtv_property_cache.atscmh_parade_id); lg2160_set_frontend()
1120 ret = lg216x_set_ensemble(state, lg2160_set_frontend()
1125 ret = lg216x_initialize(state); lg2160_set_frontend()
1129 ret = lg216x_enable_fic(state, 1); lg2160_set_frontend()
1139 static int lg2160_read_lock_status(struct lg216x_state *state, lg2160_read_lock_status() argument
1148 ret = lg216x_read_reg(state, 0x011b, &val); lg2160_read_lock_status()
1159 static int lg2161_read_lock_status(struct lg216x_state *state, lg2161_read_lock_status() argument
1168 ret = lg216x_read_reg(state, 0x0304, &val); lg2161_read_lock_status()
1174 ret = lg216x_read_reg(state, 0x011b, &val); lg2161_read_lock_status()
1184 static int lg216x_read_lock_status(struct lg216x_state *state, lg216x_read_lock_status() argument
1189 switch (state->cfg->lg_chip) { lg216x_read_lock_status()
1191 ret = lg2160_read_lock_status(state, acq_lock, sync_lock); lg216x_read_lock_status()
1194 ret = lg2161_read_lock_status(state, acq_lock, sync_lock); lg216x_read_lock_status()
1202 return lg2160_read_lock_status(state, acq_lock, sync_lock); lg216x_read_lock_status()
1208 struct lg216x_state *state = fe->demodulator_priv; lg216x_read_status() local
1213 ret = lg216x_read_lock_status(state, &acq_lock, &sync_lock); lg216x_read_status()
1237 struct lg216x_state *state = fe->demodulator_priv; lg2160_read_snr() local
1243 ret = lg216x_read_reg(state, 0x0202, &snr1); lg2160_read_snr()
1247 ret = lg216x_read_reg(state, 0x0203, &snr2); lg2160_read_snr()
1265 struct lg216x_state *state = fe->demodulator_priv; lg2161_read_snr() local
1271 ret = lg216x_read_reg(state, 0x0302, &snr1); lg2161_read_snr()
1275 ret = lg216x_read_reg(state, 0x0303, &snr2); lg2161_read_snr()
1299 struct lg216x_state *state = fe->demodulator_priv; lg216x_read_signal_strength()
1308 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ lg216x_read_signal_strength()
1310 if (state->snr >= 8960 * 0x10000) lg216x_read_signal_strength()
1313 *strength = state->snr / 8960; lg216x_read_signal_strength()
1326 struct lg216x_state *state = fe->demodulator_priv; lg216x_read_ucblocks()
1329 ret = lg216x_read_rs_err_count(state, lg216x_read_ucblocks()
1353 struct lg216x_state *state = fe->demodulator_priv; lg216x_release() local
1355 kfree(state); lg216x_release()
1417 struct lg216x_state *state = NULL; lg2160_attach() local
1423 state = kzalloc(sizeof(struct lg216x_state), GFP_KERNEL); lg2160_attach()
1424 if (!state) lg2160_attach()
1427 state->cfg = config; lg2160_attach()
1428 state->i2c_adap = i2c_adap; lg2160_attach()
1429 state->fic_ver = 0xff; lg2160_attach()
1430 state->parade_id = 0xff; lg2160_attach()
1437 memcpy(&state->frontend.ops, &lg2160_ops, lg2160_attach()
1441 memcpy(&state->frontend.ops, &lg2161_ops, lg2160_attach()
1446 state->frontend.demodulator_priv = state; lg2160_attach()
1447 state->current_frequency = -1; lg2160_attach()
1449 state->frontend.dtv_property_cache.atscmh_parade_id = 1; lg2160_attach()
1451 return &state->frontend; lg2160_attach()
H A Dstv0367.c53 enum stv0367_cab_signal_type state; member in struct:stv0367cab_state
67 enum stv0367_ter_signal_type state; member in struct:stv0367ter_state
770 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len) stv0367_writeregs() argument
774 .addr = state->config->demod_address, stv0367_writeregs()
796 ret = i2c_transfer(state->i2c, &msg, 1); stv0367_writeregs()
803 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) stv0367_writereg() argument
805 return stv0367_writeregs(state, reg, &data, 1); stv0367_writereg()
808 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg) stv0367_readreg() argument
814 .addr = state->config->demod_address, stv0367_readreg()
819 .addr = state->config->demod_address, stv0367_readreg()
830 ret = i2c_transfer(state->i2c, msg, 2); stv0367_readreg()
854 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val) stv0367_writebits() argument
858 reg = stv0367_readreg(state, (label >> 16) & 0xffff); stv0367_writebits()
864 stv0367_writereg(state, (label >> 16) & 0xffff, reg); stv0367_writebits()
879 static u8 stv0367_readbits(struct stv0367_state *state, u32 label) stv0367_readbits() argument
886 val = stv0367_readreg(state, label >> 16); stv0367_readbits()
904 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_gate_ctrl() local
905 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT); stv0367ter_gate_ctrl()
917 stv0367_writereg(state, R367TER_I2CRPT, tmp); stv0367ter_gate_ctrl()
1022 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz) stv0367ter_get_mclk() argument
1029 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) { stv0367ter_get_mclk()
1030 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV); stv0367ter_get_mclk()
1034 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV); stv0367ter_get_mclk()
1038 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV); stv0367ter_get_mclk()
1054 static int stv0367ter_filt_coeff_init(struct stv0367_state *state, stv0367ter_filt_coeff_init() argument
1061 freq = stv0367ter_get_mclk(state, DemodXtal); stv0367ter_filt_coeff_init()
1073 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1); stv0367ter_filt_coeff_init()
1076 stv0367_writereg(state, stv0367ter_filt_coeff_init()
1079 stv0367_writereg(state, stv0367ter_filt_coeff_init()
1089 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state) stv0367ter_agc_iir_lock_detect_set() argument
1093 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00); stv0367ter_agc_iir_lock_detect_set()
1096 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00); stv0367ter_agc_iir_lock_detect_set()
1097 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); stv0367ter_agc_iir_lock_detect_set()
1098 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); stv0367ter_agc_iir_lock_detect_set()
1101 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01); stv0367ter_agc_iir_lock_detect_set()
1102 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); stv0367ter_agc_iir_lock_detect_set()
1103 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); stv0367ter_agc_iir_lock_detect_set()
1106 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02); stv0367ter_agc_iir_lock_detect_set()
1107 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); stv0367ter_agc_iir_lock_detect_set()
1108 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); stv0367ter_agc_iir_lock_detect_set()
1111 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03); stv0367ter_agc_iir_lock_detect_set()
1112 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); stv0367ter_agc_iir_lock_detect_set()
1113 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); stv0367ter_agc_iir_lock_detect_set()
1117 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth, stv0367_iir_filt_init() argument
1122 stv0367_writebits(state, F367TER_NRST_IIR, 0); stv0367_iir_filt_init()
1126 if (!stv0367ter_filt_coeff_init(state, stv0367_iir_filt_init()
1132 if (!stv0367ter_filt_coeff_init(state, stv0367_iir_filt_init()
1138 if (!stv0367ter_filt_coeff_init(state, stv0367_iir_filt_init()
1147 stv0367_writebits(state, F367TER_NRST_IIR, 1); stv0367_iir_filt_init()
1152 static void stv0367ter_agc_iir_rst(struct stv0367_state *state) stv0367ter_agc_iir_rst() argument
1159 com_n = stv0367_readbits(state, F367TER_COM_N); stv0367ter_agc_iir_rst()
1161 stv0367_writebits(state, F367TER_COM_N, 0x07); stv0367ter_agc_iir_rst()
1163 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00); stv0367ter_agc_iir_rst()
1164 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00); stv0367ter_agc_iir_rst()
1166 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01); stv0367ter_agc_iir_rst()
1167 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01); stv0367ter_agc_iir_rst()
1169 stv0367_writebits(state, F367TER_COM_N, com_n); stv0367ter_agc_iir_rst()
1196 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state) stv0367ter_check_syr() argument
1204 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); stv0367ter_check_syr()
1209 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); stv0367ter_check_syr()
1224 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state, stv0367ter_check_cpamp() argument
1253 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); stv0367ter_check_cpamp()
1257 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); stv0367ter_check_cpamp()
1273 stv0367ter_lock_algo(struct stv0367_state *state) stv0367ter_lock_algo() argument
1282 if (state == NULL) stv0367ter_lock_algo()
1289 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); stv0367ter_lock_algo()
1291 if (state->config->if_iq_mode != 0) stv0367ter_lock_algo()
1292 stv0367_writebits(state, F367TER_COM_N, 0x07); stv0367ter_lock_algo()
1294 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */ stv0367ter_lock_algo()
1295 stv0367_writebits(state, F367TER_MODE, 0); stv0367ter_lock_algo()
1296 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0); stv0367ter_lock_algo()
1299 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); stv0367ter_lock_algo()
1302 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL) stv0367ter_lock_algo()
1307 mode = stv0367_readbits(state, F367TER_SYR_MODE); stv0367ter_lock_algo()
1308 if (stv0367ter_check_cpamp(state, mode) == stv0367ter_lock_algo()
1319 tmp = stv0367_readreg(state, R367TER_SYR_STAT); stv0367ter_lock_algo()
1320 tmp2 = stv0367_readreg(state, R367TER_STATUS); stv0367ter_lock_algo()
1321 dprintk("state=%p\n", state); stv0367ter_lock_algo()
1325 tmp = stv0367_readreg(state, R367TER_PRVIT); stv0367ter_lock_algo()
1326 tmp2 = stv0367_readreg(state, R367TER_I2CRPT); stv0367ter_lock_algo()
1329 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1); stv0367ter_lock_algo()
1335 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */ stv0367ter_lock_algo()
1344 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); stv0367ter_lock_algo()
1345 stv0367_writereg(state, R367TER_CHC_CTL, 0x01); stv0367ter_lock_algo()
1349 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); stv0367ter_lock_algo()
1350 stv0367_writereg(state, R367TER_CHC_CTL, 0x11); stv0367ter_lock_algo()
1359 stv0367_writebits(state, F367TER_RST_SFEC, 1); stv0367ter_lock_algo()
1360 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1); stv0367ter_lock_algo()
1362 stv0367_writebits(state, F367TER_RST_SFEC, 0); stv0367ter_lock_algo()
1363 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0); stv0367ter_lock_algo()
1365 u_var1 = stv0367_readbits(state, F367TER_LK); stv0367ter_lock_algo()
1366 u_var2 = stv0367_readbits(state, F367TER_PRF); stv0367ter_lock_algo()
1367 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); stv0367ter_lock_algo()
1368 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */ stv0367ter_lock_algo()
1377 u_var1 = stv0367_readbits(state, F367TER_LK); stv0367ter_lock_algo()
1378 u_var2 = stv0367_readbits(state, F367TER_PRF); stv0367ter_lock_algo()
1379 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); stv0367ter_lock_algo()
1380 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */ stv0367ter_lock_algo()
1393 guard = stv0367_readbits(state, F367TER_SYR_GUARD); stv0367ter_lock_algo()
1394 stv0367_writereg(state, R367TER_CHC_CTL, 0x11); stv0367ter_lock_algo()
1398 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); stv0367ter_lock_algo()
1399 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/ stv0367ter_lock_algo()
1400 stv0367_writebits(state, F367TER_SYR_FILTER, 0); stv0367ter_lock_algo()
1404 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); stv0367ter_lock_algo()
1405 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/ stv0367ter_lock_algo()
1406 stv0367_writebits(state, F367TER_SYR_FILTER, 1); stv0367ter_lock_algo()
1414 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) && stv0367ter_lock_algo()
1416 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) { stv0367ter_lock_algo()
1417 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0); stv0367ter_lock_algo()
1418 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60); stv0367ter_lock_algo()
1419 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0); stv0367ter_lock_algo()
1421 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0); stv0367ter_lock_algo()
1424 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); stv0367ter_lock_algo()
1429 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); stv0367ter_lock_algo()
1438 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) && stv0367ter_lock_algo()
1439 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) { stv0367ter_lock_algo()
1440 ChipWaitOrAbort(state,1); stv0367ter_lock_algo()
1444 stv0367_writebits(state,F367TER_COM_N,0x17); stv0367ter_lock_algo()
1447 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1); stv0367ter_lock_algo()
1455 static void stv0367ter_set_ts_mode(struct stv0367_state *state, stv0367ter_set_ts_mode() argument
1461 if (state == NULL) stv0367ter_set_ts_mode()
1464 stv0367_writebits(state, F367TER_TS_DIS, 0); stv0367ter_set_ts_mode()
1469 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0); stv0367ter_set_ts_mode()
1470 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0); stv0367ter_set_ts_mode()
1473 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1); stv0367ter_set_ts_mode()
1474 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1); stv0367ter_set_ts_mode()
1479 static void stv0367ter_set_clk_pol(struct stv0367_state *state, stv0367ter_set_clk_pol() argument
1485 if (state == NULL) stv0367ter_set_clk_pol()
1490 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1); stv0367ter_set_clk_pol()
1493 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); stv0367ter_set_clk_pol()
1497 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); stv0367ter_set_clk_pol()
1503 static void stv0367ter_core_sw(struct stv0367_state *state)
1508 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1509 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1515 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_standby() local
1520 stv0367_writebits(state, F367TER_STDBY, 1); stv0367ter_standby()
1521 stv0367_writebits(state, F367TER_STDBY_FEC, 1); stv0367ter_standby()
1522 stv0367_writebits(state, F367TER_STDBY_CORE, 1); stv0367ter_standby()
1524 stv0367_writebits(state, F367TER_STDBY, 0); stv0367ter_standby()
1525 stv0367_writebits(state, F367TER_STDBY_FEC, 0); stv0367ter_standby()
1526 stv0367_writebits(state, F367TER_STDBY_CORE, 0); stv0367ter_standby()
1539 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_init() local
1540 struct stv0367ter_state *ter_state = state->ter_state; stv0367ter_init()
1548 stv0367_writereg(state, def0367ter[i].addr, stv0367ter_init()
1551 switch (state->config->xtal) { stv0367ter_init()
1554 stv0367_writereg(state, R367TER_PLLMDIV, 0xa); stv0367ter_init()
1555 stv0367_writereg(state, R367TER_PLLNDIV, 0x55); stv0367ter_init()
1556 stv0367_writereg(state, R367TER_PLLSETUP, 0x18); stv0367ter_init()
1561 stv0367_writereg(state, R367TER_PLLMDIV, 0x1); stv0367ter_init()
1562 stv0367_writereg(state, R367TER_PLLNDIV, 0x8); stv0367ter_init()
1563 stv0367_writereg(state, R367TER_PLLSETUP, 0x18); stv0367ter_init()
1566 stv0367_writereg(state, R367TER_PLLMDIV, 0xc); stv0367ter_init()
1567 stv0367_writereg(state, R367TER_PLLNDIV, 0x55); stv0367ter_init()
1568 stv0367_writereg(state, R367TER_PLLSETUP, 0x18); stv0367ter_init()
1572 stv0367_writereg(state, R367TER_I2CRPT, 0xa0); stv0367ter_init()
1573 stv0367_writereg(state, R367TER_ANACTRL, 0x00); stv0367ter_init()
1576 stv0367ter_set_ts_mode(state, state->config->ts_mode); stv0367ter_init()
1577 stv0367ter_set_clk_pol(state, state->config->clk_pol); stv0367ter_init()
1579 state->chip_id = stv0367_readreg(state, R367TER_ID); stv0367ter_init()
1589 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_algo() local
1590 struct stv0367ter_state *ter_state = state->ter_state; stv0367ter_algo()
1602 + stv0367_readbits(state, F367TER_FORCE) * 2; stv0367ter_algo()
1603 ter_state->if_iq_mode = state->config->if_iq_mode; stv0367ter_algo()
1604 switch (state->config->if_iq_mode) { stv0367ter_algo()
1607 stv0367_writebits(state, F367TER_TUNER_BB, 0); stv0367ter_algo()
1608 stv0367_writebits(state, F367TER_LONGPATH_IF, 0); stv0367ter_algo()
1609 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0); stv0367ter_algo()
1613 stv0367_writebits(state, F367TER_TUNER_BB, 0); stv0367ter_algo()
1614 stv0367_writebits(state, F367TER_LONGPATH_IF, 1); stv0367ter_algo()
1615 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1); stv0367ter_algo()
1619 stv0367_writebits(state, F367TER_TUNER_BB, 1); stv0367ter_algo()
1620 stv0367_writebits(state, F367TER_PPM_INVSEL, 0); stv0367ter_algo()
1634 stv0367_writebits(state, F367TER_IQ_INVERT, stv0367ter_algo()
1637 stv0367_writebits(state, F367TER_INV_SPECTR, stv0367ter_algo()
1644 stv0367_writebits(state, F367TER_IQ_INVERT, stv0367ter_algo()
1647 stv0367_writebits(state, F367TER_INV_SPECTR, stv0367ter_algo()
1655 stv0367ter_agc_iir_lock_detect_set(state); stv0367ter_algo()
1659 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1); stv0367ter_algo()
1660 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); stv0367ter_algo()
1661 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ stv0367ter_algo()
1664 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0); stv0367ter_algo()
1665 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); stv0367ter_algo()
1666 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ stv0367ter_algo()
1668 if (!stv0367_iir_filt_init(state, ter_state->bw, stv0367ter_algo()
1669 state->config->xtal)) stv0367ter_algo()
1674 stv0367ter_agc_iir_rst(state); stv0367ter_algo()
1678 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01); stv0367ter_algo()
1680 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00); stv0367ter_algo()
1682 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000; stv0367ter_algo()
1687 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2); stv0367ter_algo()
1689 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256); stv0367ter_algo()
1690 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256); stv0367ter_algo()
1692 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 + stv0367ter_algo()
1693 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 + stv0367ter_algo()
1694 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB); stv0367ter_algo()
1696 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256); stv0367ter_algo()
1697 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256); stv0367ter_algo()
1698 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 + stv0367ter_algo()
1699 stv0367_readbits(state, F367TER_GAIN_SRC_LO); stv0367ter_algo()
1702 ((InternalFreq - state->config->if_khz) * (1 << 16) stv0367ter_algo()
1706 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256); stv0367ter_algo()
1707 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256); stv0367ter_algo()
1712 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos); stv0367ter_algo()
1714 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK) stv0367ter_algo()
1717 ter_state->state = FE_TER_LOCKOK; stv0367ter_algo()
1719 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE); stv0367ter_algo()
1720 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD); stv0367ter_algo()
1725 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) + stv0367ter_algo()
1726 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) + stv0367ter_algo()
1727 stv0367_readbits(state, F367TER_AGC2_VAL_LO) + stv0367ter_algo()
1728 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8); stv0367ter_algo()
1731 stv0367_writebits(state, F367TER_FREEZE, 1); stv0367ter_algo()
1732 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ; stv0367ter_algo()
1733 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8); stv0367ter_algo()
1734 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO)); stv0367ter_algo()
1735 stv0367_writebits(state, F367TER_FREEZE, 0); stv0367ter_algo()
1748 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) { stv0367ter_algo()
1749 if ((stv0367_readbits(state, F367TER_INV_SPECTR) == stv0367ter_algo()
1750 (stv0367_readbits(state, stv0367ter_algo()
1766 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO) stv0367ter_algo()
1767 + 256 * stv0367_readbits(state, stv0367ter_algo()
1771 trl_nomrate = (512 * stv0367_readbits(state, stv0367ter_algo()
1773 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 stv0367ter_algo()
1774 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB)); stv0367ter_algo()
1791 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, stv0367ter_algo()
1793 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, stv0367ter_algo()
1801 u_var = stv0367_readbits(state, F367TER_LK); stv0367ter_algo()
1804 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); stv0367ter_algo()
1806 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); stv0367ter_algo()
1815 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_set_frontend() local
1816 struct stv0367ter_state *ter_state = state->ter_state; stv0367ter_set_frontend()
1885 ter_state->state = FE_TER_NOLOCK; stv0367ter_set_frontend()
1888 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) { stv0367ter_set_frontend()
1896 if ((ter_state->state == FE_TER_LOCKOK) && stv0367ter_set_frontend()
1912 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_read_ucblocks() local
1913 struct stv0367ter_state *ter_state = state->ter_state; stv0367ter_read_ucblocks()
1917 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) { stv0367ter_read_ucblocks()
1919 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1) stv0367ter_read_ucblocks()
1921 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI) stv0367ter_read_ucblocks()
1923 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO)); stv0367ter_read_ucblocks()
1935 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_get_frontend() local
1936 struct stv0367ter_state *ter_state = state->ter_state; stv0367ter_get_frontend()
1944 constell = stv0367_readbits(state, F367TER_TPS_CONST); stv0367ter_get_frontend()
1952 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR); stv0367ter_get_frontend()
1955 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE); stv0367ter_get_frontend()
1977 Data = stv0367_readbits(state, F367TER_TPS_LPCODE); stv0367ter_get_frontend()
1979 Data = stv0367_readbits(state, F367TER_TPS_HPCODE); stv0367ter_get_frontend()
2002 mode = stv0367_readbits(state, F367TER_SYR_MODE); stv0367ter_get_frontend()
2018 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD); stv0367ter_get_frontend()
2025 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_read_snr() local
2028 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG); stv0367ter_read_snr()
2033 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4; stv0367ter_read_snr()
2035 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR); stv0367ter_read_snr()
2051 struct stv0367_state *state = fe->demodulator_priv;
2052 struct stv0367ter_state *ter_state = state->ter_state;
2055 locked = (stv0367_readbits(state, F367TER_LK));
2062 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2063 (!stv0367_readbits(state, F367TER_LK))) {
2064 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2066 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2068 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2069 (stv0367_readbits(state, F367TER_LK));
2079 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_read_status() local
2085 if (stv0367_readbits(state, F367TER_LK)) { stv0367ter_read_status()
2095 struct stv0367_state *state = fe->demodulator_priv; stv0367ter_read_ber() local
2096 struct stv0367ter_state *ter_state = state->ter_state; stv0367ter_read_ber()
2102 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) stv0367ter_read_ber()
2103 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT) stv0367ter_read_ber()
2105 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI) stv0367ter_read_ber()
2107 + ((u32)stv0367_readbits(state, stv0367ter_read_ber()
2115 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE); stv0367ter_read_ber()
2116 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT); stv0367ter_read_ber()
2177 static u32 stv0367ter_get_per(struct stv0367_state *state)
2179 struct stv0367ter_state *ter_state = state->ter_state;
2183 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2186 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2188 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2190 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2193 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2194 def = stv0367_readbits(state, F367TER_NUM_EVT1);
2258 struct stv0367_state *state = fe->demodulator_priv; stv0367_release() local
2260 kfree(state->ter_state); stv0367_release()
2261 kfree(state->cab_state); stv0367_release()
2262 kfree(state); stv0367_release()
2299 struct stv0367_state *state = NULL; stv0367ter_attach() local
2302 /* allocate memory for the internal state */ stv0367ter_attach()
2303 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); stv0367ter_attach()
2304 if (state == NULL) stv0367ter_attach()
2310 /* setup the state */ stv0367ter_attach()
2311 state->i2c = i2c; stv0367ter_attach()
2312 state->config = config; stv0367ter_attach()
2313 state->ter_state = ter_state; stv0367ter_attach()
2314 state->fe.ops = stv0367ter_ops; stv0367ter_attach()
2315 state->fe.demodulator_priv = state; stv0367ter_attach()
2316 state->chip_id = stv0367_readreg(state, 0xf000); stv0367ter_attach()
2318 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); stv0367ter_attach()
2321 if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) stv0367ter_attach()
2324 return &state->fe; stv0367ter_attach()
2328 kfree(state); stv0367ter_attach()
2335 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_gate_ctrl() local
2339 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0); stv0367cab_gate_ctrl()
2346 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_get_mclk() local
2351 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) { stv0367cab_get_mclk()
2352 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV); stv0367cab_get_mclk()
2356 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV); stv0367cab_get_mclk()
2360 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV); stv0367cab_get_mclk()
2385 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state, stv0367cab_SetQamSize() argument
2390 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize); stv0367cab_SetQamSize()
2395 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); stv0367cab_SetQamSize()
2398 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64); stv0367cab_SetQamSize()
2399 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); stv0367cab_SetQamSize()
2400 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); stv0367cab_SetQamSize()
2401 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); stv0367cab_SetQamSize()
2402 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); stv0367cab_SetQamSize()
2403 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); stv0367cab_SetQamSize()
2404 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); stv0367cab_SetQamSize()
2405 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a); stv0367cab_SetQamSize()
2408 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); stv0367cab_SetQamSize()
2409 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e); stv0367cab_SetQamSize()
2410 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); stv0367cab_SetQamSize()
2411 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); stv0367cab_SetQamSize()
2412 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7); stv0367cab_SetQamSize()
2413 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d); stv0367cab_SetQamSize()
2414 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); stv0367cab_SetQamSize()
2415 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); stv0367cab_SetQamSize()
2418 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82); stv0367cab_SetQamSize()
2419 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); stv0367cab_SetQamSize()
2421 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); stv0367cab_SetQamSize()
2422 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); stv0367cab_SetQamSize()
2423 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5); stv0367cab_SetQamSize()
2425 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); stv0367cab_SetQamSize()
2426 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); stv0367cab_SetQamSize()
2427 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); stv0367cab_SetQamSize()
2429 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); stv0367cab_SetQamSize()
2430 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); stv0367cab_SetQamSize()
2431 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); stv0367cab_SetQamSize()
2433 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); stv0367cab_SetQamSize()
2434 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); stv0367cab_SetQamSize()
2435 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99); stv0367cab_SetQamSize()
2438 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); stv0367cab_SetQamSize()
2439 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76); stv0367cab_SetQamSize()
2440 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); stv0367cab_SetQamSize()
2441 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1); stv0367cab_SetQamSize()
2443 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); stv0367cab_SetQamSize()
2445 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); stv0367cab_SetQamSize()
2447 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97); stv0367cab_SetQamSize()
2449 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e); stv0367cab_SetQamSize()
2450 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); stv0367cab_SetQamSize()
2451 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); stv0367cab_SetQamSize()
2454 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94); stv0367cab_SetQamSize()
2455 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); stv0367cab_SetQamSize()
2456 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); stv0367cab_SetQamSize()
2458 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); stv0367cab_SetQamSize()
2460 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); stv0367cab_SetQamSize()
2462 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); stv0367cab_SetQamSize()
2464 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); stv0367cab_SetQamSize()
2465 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85); stv0367cab_SetQamSize()
2466 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); stv0367cab_SetQamSize()
2467 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); stv0367cab_SetQamSize()
2470 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); stv0367cab_SetQamSize()
2473 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); stv0367cab_SetQamSize()
2482 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state, stv0367cab_set_derot_freq() argument
2508 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if); stv0367cab_set_derot_freq()
2509 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8)); stv0367cab_set_derot_freq()
2510 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16)); stv0367cab_set_derot_freq()
2515 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz) stv0367cab_get_derot_freq() argument
2519 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) + stv0367cab_get_derot_freq()
2520 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) + stv0367cab_get_derot_freq()
2521 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16); stv0367cab_get_derot_freq()
2531 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz, stv0367cab_set_srate() argument
2576 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp); stv0367cab_set_srate()
2650 if (stv0367_readbits(state, F367CAB_ADJ_EN)) { stv0367cab_set_srate()
2651 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz, stv0367cab_set_srate()
2655 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1); stv0367cab_set_srate()
2656 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate); stv0367cab_set_srate()
2661 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); stv0367cab_set_srate()
2663 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp); stv0367cab_set_srate()
2664 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8)); stv0367cab_set_srate()
2665 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16)); stv0367cab_set_srate()
2666 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24)); stv0367cab_set_srate()
2668 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff); stv0367cab_set_srate()
2669 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff); stv0367cab_set_srate()
2674 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz) stv0367cab_GetSymbolRate() argument
2679 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) + stv0367cab_GetSymbolRate()
2680 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) + stv0367cab_GetSymbolRate()
2681 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) + stv0367cab_GetSymbolRate()
2682 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24); stv0367cab_GetSymbolRate()
2721 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_read_status() local
2727 if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) { stv0367cab_read_status()
2737 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_standby() local
2742 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03); stv0367cab_standby()
2743 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01); stv0367cab_standby()
2744 stv0367_writebits(state, F367CAB_STDBY, 1); stv0367cab_standby()
2745 stv0367_writebits(state, F367CAB_STDBY_CORE, 1); stv0367cab_standby()
2746 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0); stv0367cab_standby()
2747 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0); stv0367cab_standby()
2748 stv0367_writebits(state, F367CAB_POFFQ, 1); stv0367cab_standby()
2749 stv0367_writebits(state, F367CAB_POFFI, 1); stv0367cab_standby()
2751 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00); stv0367cab_standby()
2752 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00); stv0367cab_standby()
2753 stv0367_writebits(state, F367CAB_STDBY, 0); stv0367cab_standby()
2754 stv0367_writebits(state, F367CAB_STDBY_CORE, 0); stv0367cab_standby()
2755 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1); stv0367cab_standby()
2756 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1); stv0367cab_standby()
2757 stv0367_writebits(state, F367CAB_POFFQ, 0); stv0367cab_standby()
2758 stv0367_writebits(state, F367CAB_POFFI, 0); stv0367cab_standby()
2771 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_init() local
2772 struct stv0367cab_state *cab_state = state->cab_state; stv0367cab_init()
2778 stv0367_writereg(state, def0367cab[i].addr, stv0367cab_init()
2781 switch (state->config->ts_mode) { stv0367cab_init()
2784 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03); stv0367cab_init()
2788 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01); stv0367cab_init()
2792 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00); stv0367cab_init()
2796 switch (state->config->clk_pol) { stv0367cab_init()
2798 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00); stv0367cab_init()
2802 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01); stv0367cab_init()
2806 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00); stv0367cab_init()
2808 stv0367_writebits(state, F367CAB_CT_NBST, 0x01); stv0367cab_init()
2810 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01); stv0367cab_init()
2812 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00); stv0367cab_init()
2814 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */ stv0367cab_init()
2816 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal); stv0367cab_init()
2817 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal); stv0367cab_init()
2822 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state, stv0367cab_algo() argument
2825 struct stv0367cab_state *cab_state = state->cab_state; stv0367cab_algo()
2901 stv0367_writereg(state, R367CAB_CTRL_1, 0x04); stv0367cab_algo()
2904 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL); stv0367cab_algo()
2905 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0); stv0367cab_algo()
2907 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0); stv0367cab_algo()
2909 stv0367_writebits(state, F367CAB_SWEEP_EN, 0); stv0367cab_algo()
2912 stv0367cab_set_derot_freq(state, cab_state->adc_clk, stv0367cab_algo()
2913 (1000 * (s32)state->config->if_khz + cab_state->derot_offset)); stv0367cab_algo()
2916 stv0367_writebits(state, F367CAB_ADJ_EN, 0); stv0367cab_algo()
2917 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); stv0367cab_algo()
2928 stv0367_writereg(state, R367CAB_CTRL_1, 0x00); stv0367cab_algo()
2930 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS); stv0367cab_algo()
2947 u32_tmp = stv0367_readbits(state, stv0367cab_algo()
2949 (stv0367_readbits(state, stv0367cab_algo()
2951 (stv0367_readbits(state, stv0367cab_algo()
2955 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state, stv0367cab_algo()
2958 if (u32_tmp < stv0367_readbits(state, stv0367cab_algo()
2960 256 * stv0367_readbits(state, stv0367cab_algo()
2968 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); stv0367cab_algo()
2977 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); stv0367cab_algo()
2979 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2); stv0367cab_algo()
2982 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk); stv0367cab_algo()
2991 QAMFEC_Lock = stv0367_readbits(state, stv0367cab_algo()
2999 cab_state->spect_inv = stv0367_readbits(state, stv0367cab_algo()
3003 if (state->config->if_khz != 0) { stv0367cab_algo()
3004 if (state->config->if_khz > cab_state->adc_clk / 1000) { stv0367cab_algo()
3007 - stv0367cab_get_derot_freq(state, cab_state->adc_clk) stv0367cab_algo()
3008 - cab_state->adc_clk / 1000 + state->config->if_khz; stv0367cab_algo()
3012 - stv0367cab_get_derot_freq(state, cab_state->adc_clk) stv0367cab_algo()
3013 + state->config->if_khz; stv0367cab_algo()
3018 stv0367cab_get_derot_freq(state, stv0367cab_algo()
3023 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state, stv0367cab_algo()
3027 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/ stv0367cab_algo()
3076 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum); stv0367cab_algo()
3083 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_set_frontend() local
3084 struct stv0367cab_state *cab_state = state->cab_state; stv0367cab_set_frontend()
3124 state, stv0367cab_set_frontend()
3128 stv0367cab_set_srate(state, stv0367cab_set_frontend()
3134 cab_state->state = stv0367cab_algo(state, p); stv0367cab_set_frontend()
3141 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_get_frontend() local
3142 struct stv0367cab_state *cab_state = state->cab_state; stv0367cab_get_frontend()
3148 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk); stv0367cab_get_frontend()
3150 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); stv0367cab_get_frontend()
3175 if (state->config->if_khz == 0) { stv0367cab_get_frontend()
3177 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) - stv0367cab_get_frontend()
3182 if (state->config->if_khz > cab_state->adc_clk / 1000) stv0367cab_get_frontend()
3183 p->frequency += (state->config->if_khz stv0367cab_get_frontend()
3184 - stv0367cab_get_derot_freq(state, cab_state->adc_clk) stv0367cab_get_frontend()
3187 p->frequency += (state->config->if_khz stv0367cab_get_frontend()
3188 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)); stv0367cab_get_frontend()
3194 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3197 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3198 stv0367cab_GetPacketsCount(state, Monitor_results);
3205 struct stv0367_state *state = fe->demodulator_priv;
3210 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state) stv0367cab_get_rf_lvl() argument
3216 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0); stv0367cab_get_rf_lvl()
3219 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) + stv0367cab_get_rf_lvl()
3220 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2); stv0367cab_get_rf_lvl()
3224 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) + stv0367cab_get_rf_lvl()
3225 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8); stv0367cab_get_rf_lvl()
3258 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_read_strength() local
3260 s32 signal = stv0367cab_get_rf_lvl(state); stv0367cab_read_strength()
3276 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_read_snr() local
3282 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); stv0367cab_read_snr()
3314 regval += (stv0367_readbits(state, F367CAB_SNR_LO) stv0367cab_read_snr()
3315 + 256 * stv0367_readbits(state, F367CAB_SNR_HI)); stv0367cab_read_snr()
3321 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER))); stv0367cab_read_snr()
3366 struct stv0367_state *state = fe->demodulator_priv; stv0367cab_read_ucblcks() local
3369 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8) stv0367cab_read_ucblcks()
3370 | stv0367_readreg(state, R367CAB_RS_COUNTER_4); stv0367cab_read_ucblcks()
3371 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8) stv0367cab_read_ucblcks()
3372 | stv0367_readreg(state, R367CAB_RS_COUNTER_2); stv0367cab_read_ucblcks()
3373 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8) stv0367cab_read_ucblcks()
3374 | stv0367_readreg(state, R367CAB_RS_COUNTER_1); stv0367cab_read_ucblcks()
3413 struct stv0367_state *state = NULL; stv0367cab_attach() local
3416 /* allocate memory for the internal state */ stv0367cab_attach()
3417 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); stv0367cab_attach()
3418 if (state == NULL) stv0367cab_attach()
3424 /* setup the state */ stv0367cab_attach()
3425 state->i2c = i2c; stv0367cab_attach()
3426 state->config = config; stv0367cab_attach()
3428 state->cab_state = cab_state; stv0367cab_attach()
3429 state->fe.ops = stv0367cab_ops; stv0367cab_attach()
3430 state->fe.demodulator_priv = state; stv0367cab_attach()
3431 state->chip_id = stv0367_readreg(state, 0xf000); stv0367cab_attach()
3433 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); stv0367cab_attach()
3436 if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) stv0367cab_attach()
3439 return &state->fe; stv0367cab_attach()
3443 kfree(state); stv0367cab_attach()
H A Dec100.c34 static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val) ec100_write_reg() argument
40 .addr = state->config.demod_address, ec100_write_reg()
47 ret = i2c_transfer(state->i2c, msg, 1); ec100_write_reg()
51 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%02x\n", ec100_write_reg()
60 static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val) ec100_read_reg() argument
65 .addr = state->config.demod_address, ec100_read_reg()
70 .addr = state->config.demod_address, ec100_read_reg()
77 ret = i2c_transfer(state->i2c, msg, 2); ec100_read_reg()
81 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%02x\n", ec100_read_reg()
92 struct ec100_state *state = fe->demodulator_priv; ec100_set_frontend() local
96 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", ec100_set_frontend()
103 ret = ec100_write_reg(state, 0x04, 0x06); ec100_set_frontend()
106 ret = ec100_write_reg(state, 0x67, 0x58); ec100_set_frontend()
109 ret = ec100_write_reg(state, 0x05, 0x18); ec100_set_frontend()
136 ret = ec100_write_reg(state, 0x1b, tmp); ec100_set_frontend()
139 ret = ec100_write_reg(state, 0x1c, tmp2); ec100_set_frontend()
143 ret = ec100_write_reg(state, 0x0c, 0xbb); /* if freq */ ec100_set_frontend()
146 ret = ec100_write_reg(state, 0x0d, 0x31); /* if freq */ ec100_set_frontend()
150 ret = ec100_write_reg(state, 0x08, 0x24); ec100_set_frontend()
154 ret = ec100_write_reg(state, 0x00, 0x00); /* go */ ec100_set_frontend()
157 ret = ec100_write_reg(state, 0x00, 0x20); /* go */ ec100_set_frontend()
163 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); ec100_set_frontend()
179 struct ec100_state *state = fe->demodulator_priv; ec100_read_status() local
184 ret = ec100_read_reg(state, 0x42, &tmp); ec100_read_status()
193 ret = ec100_read_reg(state, 0x01, &tmp); ec100_read_status()
209 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); ec100_read_status()
215 struct ec100_state *state = fe->demodulator_priv; ec100_read_ber() local
222 ret = ec100_read_reg(state, 0x65, &tmp); ec100_read_ber()
225 ret = ec100_read_reg(state, 0x66, &tmp2); ec100_read_ber()
232 if (ber2 < state->ber) ec100_read_ber()
235 *ber = ber2 - state->ber; ec100_read_ber()
237 state->ber = ber2; ec100_read_ber()
241 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); ec100_read_ber()
247 struct ec100_state *state = fe->demodulator_priv; ec100_read_signal_strength() local
251 ret = ec100_read_reg(state, 0x24, &tmp); ec100_read_signal_strength()
261 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret); ec100_read_signal_strength()
279 struct ec100_state *state = fe->demodulator_priv; ec100_release() local
280 kfree(state); ec100_release()
289 struct ec100_state *state = NULL; ec100_attach() local
292 /* allocate memory for the internal state */ ec100_attach()
293 state = kzalloc(sizeof(struct ec100_state), GFP_KERNEL); ec100_attach()
294 if (state == NULL) ec100_attach()
297 /* setup the state */ ec100_attach()
298 state->i2c = i2c; ec100_attach()
299 memcpy(&state->config, config, sizeof(struct ec100_config)); ec100_attach()
302 ret = ec100_read_reg(state, 0x33, &tmp); ec100_attach()
307 memcpy(&state->frontend.ops, &ec100_ops, ec100_attach()
309 state->frontend.demodulator_priv = state; ec100_attach()
311 return &state->frontend; ec100_attach()
313 kfree(state); ec100_attach()
H A Dstv0288.c63 static int stv0288_writeregI(struct stv0288_state *state, u8 reg, u8 data) stv0288_writeregI() argument
68 .addr = state->config->demod_address, stv0288_writeregI()
74 ret = i2c_transfer(state->i2c, &msg, 1); stv0288_writeregI()
85 struct stv0288_state *state = fe->demodulator_priv; stv0288_write() local
90 return stv0288_writeregI(state, buf[0], buf[1]); stv0288_write()
93 static u8 stv0288_readreg(struct stv0288_state *state, u8 reg) stv0288_readreg() argument
100 .addr = state->config->demod_address, stv0288_readreg()
105 .addr = state->config->demod_address, stv0288_readreg()
112 ret = i2c_transfer(state->i2c, msg, 2); stv0288_readreg()
123 struct stv0288_state *state = fe->demodulator_priv; stv0288_set_symbolrate() local
130 stv0288_writeregI(state, 0x22, 0); stv0288_set_symbolrate()
131 stv0288_writeregI(state, 0x23, 0); stv0288_set_symbolrate()
132 stv0288_writeregI(state, 0x2b, 0xff); stv0288_set_symbolrate()
133 stv0288_writeregI(state, 0x2c, 0xf7); stv0288_set_symbolrate()
143 stv0288_writeregI(state, 0x28, 0x80); /* SFRH */ stv0288_set_symbolrate()
144 stv0288_writeregI(state, 0x29, 0); /* SFRM */ stv0288_set_symbolrate()
145 stv0288_writeregI(state, 0x2a, 0); /* SFRL */ stv0288_set_symbolrate()
147 stv0288_writeregI(state, 0x28, b[0]); stv0288_set_symbolrate()
148 stv0288_writeregI(state, 0x29, b[1]); stv0288_set_symbolrate()
149 stv0288_writeregI(state, 0x2a, b[2]); stv0288_set_symbolrate()
158 struct stv0288_state *state = fe->demodulator_priv; stv0288_send_diseqc_msg() local
164 stv0288_writeregI(state, 0x09, 0); stv0288_send_diseqc_msg()
166 stv0288_writeregI(state, 0x05, 0x12);/* modulated mode, single shot */ stv0288_send_diseqc_msg()
169 if (stv0288_writeregI(state, 0x06, m->msg[i])) stv0288_send_diseqc_msg()
179 struct stv0288_state *state = fe->demodulator_priv; stv0288_send_diseqc_burst() local
183 if (stv0288_writeregI(state, 0x05, 0x03))/* burst mode, single shot */ stv0288_send_diseqc_burst()
186 if (stv0288_writeregI(state, 0x06, burst == SEC_MINI_A ? 0x00 : 0xff)) stv0288_send_diseqc_burst()
190 if (stv0288_writeregI(state, 0x05, 0x12)) stv0288_send_diseqc_burst()
198 struct stv0288_state *state = fe->demodulator_priv; stv0288_set_tone() local
202 if (stv0288_writeregI(state, 0x05, 0x10))/* cont carrier */ stv0288_set_tone()
207 if (stv0288_writeregI(state, 0x05, 0x12))/* burst mode off*/ stv0288_set_tone()
337 struct stv0288_state *state = fe->demodulator_priv; stv0288_init() local
343 stv0288_writeregI(state, 0x41, 0x04); stv0288_init()
347 if (state->config->inittab == NULL) { stv0288_init()
350 stv0288_writeregI(state, stv0288_inittab[i], stv0288_init()
354 reg = state->config->inittab[i]; stv0288_init()
355 val = state->config->inittab[i+1]; stv0288_init()
358 stv0288_writeregI(state, reg, val); stv0288_init()
366 struct stv0288_state *state = fe->demodulator_priv; stv0288_read_status() local
368 u8 sync = stv0288_readreg(state, 0x24); stv0288_read_status()
389 struct stv0288_state *state = fe->demodulator_priv; stv0288_read_ber() local
391 if (state->errmode != STATUS_BER) stv0288_read_ber()
393 *ber = (stv0288_readreg(state, 0x26) << 8) | stv0288_read_ber()
394 stv0288_readreg(state, 0x27); stv0288_read_ber()
403 struct stv0288_state *state = fe->demodulator_priv; stv0288_read_signal_strength() local
405 s32 signal = 0xffff - ((stv0288_readreg(state, 0x10) << 8)); stv0288_read_signal_strength()
416 struct stv0288_state *state = fe->demodulator_priv; stv0288_sleep() local
418 stv0288_writeregI(state, 0x41, 0x84); stv0288_sleep()
419 state->initialised = 0; stv0288_sleep()
425 struct stv0288_state *state = fe->demodulator_priv; stv0288_read_snr() local
427 s32 xsnr = 0xffff - ((stv0288_readreg(state, 0x2d) << 8) stv0288_read_snr()
428 | stv0288_readreg(state, 0x2e)); stv0288_read_snr()
438 struct stv0288_state *state = fe->demodulator_priv; stv0288_read_ucblocks() local
440 if (state->errmode != STATUS_BER) stv0288_read_ucblocks()
442 *ucblocks = (stv0288_readreg(state, 0x26) << 8) | stv0288_read_ucblocks()
443 stv0288_readreg(state, 0x27); stv0288_read_ucblocks()
457 struct stv0288_state *state = fe->demodulator_priv; stv0288_set_frontend() local
473 if (state->config->set_ts_params) stv0288_set_frontend()
474 state->config->set_ts_params(fe, 0); stv0288_set_frontend()
486 stv0288_writeregI(state, 0x15, 0xc5); stv0288_set_frontend()
491 reg = stv0288_readreg(state, 0x24); stv0288_set_frontend()
507 stv0288_writeregI(state, 0x2b, tda[1]); stv0288_set_frontend()
508 stv0288_writeregI(state, 0x2c, tda[2]); stv0288_set_frontend()
511 state->tuner_frequency = c->frequency; stv0288_set_frontend()
512 state->fec_inner = FEC_AUTO; stv0288_set_frontend()
513 state->symbol_rate = c->symbol_rate; stv0288_set_frontend()
520 struct stv0288_state *state = fe->demodulator_priv; stv0288_i2c_gate_ctrl() local
523 stv0288_writeregI(state, 0x01, 0xb5); stv0288_i2c_gate_ctrl()
525 stv0288_writeregI(state, 0x01, 0x35); stv0288_i2c_gate_ctrl()
534 struct stv0288_state *state = fe->demodulator_priv; stv0288_release() local
535 kfree(state); stv0288_release()
577 struct stv0288_state *state = NULL; stv0288_attach() local
580 /* allocate memory for the internal state */ stv0288_attach()
581 state = kzalloc(sizeof(struct stv0288_state), GFP_KERNEL); stv0288_attach()
582 if (state == NULL) stv0288_attach()
585 /* setup the state */ stv0288_attach()
586 state->config = config; stv0288_attach()
587 state->i2c = i2c; stv0288_attach()
588 state->initialised = 0; stv0288_attach()
589 state->tuner_frequency = 0; stv0288_attach()
590 state->symbol_rate = 0; stv0288_attach()
591 state->fec_inner = 0; stv0288_attach()
592 state->errmode = STATUS_BER; stv0288_attach()
594 stv0288_writeregI(state, 0x41, 0x04); stv0288_attach()
596 id = stv0288_readreg(state, 0x00); stv0288_attach()
604 memcpy(&state->frontend.ops, &stv0288_ops, stv0288_attach()
606 state->frontend.demodulator_priv = state; stv0288_attach()
607 return &state->frontend; stv0288_attach()
610 kfree(state); stv0288_attach()
H A Dsi2165.c105 static int si2165_write(struct si2165_state *state, const u16 reg, si2165_write() argument
113 dev_warn(&state->i2c->dev, si2165_write()
122 msg.addr = state->config.i2c_addr; si2165_write()
130 ret = i2c_transfer(state->i2c, &msg, 1); si2165_write()
133 dev_err(&state->i2c->dev, "%s: ret == %d\n", __func__, ret); si2165_write()
143 static int si2165_read(struct si2165_state *state, si2165_read() argument
149 { .addr = state->config.i2c_addr, si2165_read()
151 { .addr = state->config.i2c_addr, si2165_read()
155 ret = i2c_transfer(state->i2c, msg, 2); si2165_read()
158 dev_err(&state->i2c->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n", si2165_read()
159 __func__, state->config.i2c_addr, reg, ret); si2165_read()
172 static int si2165_readreg8(struct si2165_state *state, si2165_readreg8() argument
177 ret = si2165_read(state, reg, val, 1); si2165_readreg8()
182 static int si2165_readreg16(struct si2165_state *state, si2165_readreg16() argument
187 int ret = si2165_read(state, reg, buf, 2); si2165_readreg16()
193 static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val) si2165_writereg8() argument
195 return si2165_write(state, reg, &val, 1); si2165_writereg8()
198 static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val) si2165_writereg16() argument
202 return si2165_write(state, reg, buf, 2); si2165_writereg16()
205 static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val) si2165_writereg24() argument
209 return si2165_write(state, reg, buf, 3); si2165_writereg24()
212 static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val) si2165_writereg32() argument
220 return si2165_write(state, reg, buf, 4); si2165_writereg32()
223 static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg, si2165_writereg_mask8() argument
230 ret = si2165_readreg8(state, reg, &tmp); si2165_writereg_mask8()
239 ret = si2165_writereg8(state, reg, val); si2165_writereg_mask8()
251 static int si2165_init_pll(struct si2165_state *state) si2165_init_pll() argument
253 u32 ref_freq_Hz = state->config.ref_freq_Hz; si2165_init_pll()
288 state->fvco_hz = ref_freq_Hz / divr si2165_init_pll()
290 state->adc_clk = state->fvco_hz / (divm * 4u); si2165_init_pll()
291 state->sys_clk = state->fvco_hz / (divl * 2u); si2165_init_pll()
298 return si2165_write(state, 0x00a0, buf, 4); si2165_init_pll()
301 static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl) si2165_adjust_pll_divl() argument
303 state->sys_clk = state->fvco_hz / (divl * 2u); si2165_adjust_pll_divl()
304 return si2165_writereg8(state, 0x00a0, divl); /* pll_divl */ si2165_adjust_pll_divl()
307 static u32 si2165_get_fe_clk(struct si2165_state *state) si2165_get_fe_clk() argument
310 return state->adc_clk; si2165_get_fe_clk()
313 static int si2165_wait_init_done(struct si2165_state *state) si2165_wait_init_done() argument
320 si2165_readreg8(state, 0x0054, &val); si2165_wait_init_done()
325 dev_err(&state->i2c->dev, "%s: init_done was not set\n", si2165_wait_init_done()
330 static int si2165_upload_firmware_block(struct si2165_state *state, si2165_upload_firmware_block() argument
352 dev_warn(&state->i2c->dev, si2165_upload_firmware_block()
359 dev_warn(&state->i2c->dev, si2165_upload_firmware_block()
367 ret = si2165_write(state, 0x0364, buf_ctrl, 4); si2165_upload_firmware_block()
370 ret = si2165_write(state, 0x0368, data+offset+4, 4); si2165_upload_firmware_block()
377 ret = si2165_write(state, 0x36c, data+offset, 4); si2165_upload_firmware_block()
400 static int si2165_upload_firmware(struct si2165_state *state) si2165_upload_firmware() argument
416 switch (state->chip_revcode) { si2165_upload_firmware()
421 dev_info(&state->i2c->dev, "%s: no firmware file for revision=%d\n", si2165_upload_firmware()
422 KBUILD_MODNAME, state->chip_revcode); si2165_upload_firmware()
427 ret = request_firmware(&fw, fw_file, state->i2c->dev.parent); si2165_upload_firmware()
429 dev_warn(&state->i2c->dev, "%s: firmware file '%s' not found\n", si2165_upload_firmware()
437 dev_info(&state->i2c->dev, "%s: downloading firmware from file '%s' size=%d\n", si2165_upload_firmware()
441 dev_warn(&state->i2c->dev, "%s: firmware size is not multiple of 4\n", si2165_upload_firmware()
449 dev_warn(&state->i2c->dev, "%s: firmware header is missing\n", si2165_upload_firmware()
456 dev_warn(&state->i2c->dev, "%s: firmware file version is wrong\n", si2165_upload_firmware()
468 ret = si2165_writereg8(state, 0x0341, 0x00); si2165_upload_firmware()
472 ret = si2165_writereg8(state, 0x00c0, 0x00); si2165_upload_firmware()
476 ret = si2165_readreg8(state, 0x0341, val); si2165_upload_firmware()
481 ret = si2165_readreg8(state, 0x035c, val); si2165_upload_firmware()
484 ret = si2165_readreg8(state, 0x035c, val); si2165_upload_firmware()
487 ret = si2165_writereg8(state, 0x035c, 0x02); si2165_upload_firmware()
494 dev_info(&state->i2c->dev, "%s: si2165_upload_firmware extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n", si2165_upload_firmware()
497 ret = si2165_upload_firmware_block(state, data, len, &offset, 1); si2165_upload_firmware()
501 ret = si2165_writereg8(state, 0x0344, patch_version); si2165_upload_firmware()
506 ret = si2165_writereg8(state, 0x0379, 0x01); si2165_upload_firmware()
510 ret = si2165_upload_firmware_block(state, data, len, si2165_upload_firmware()
513 dev_err(&state->i2c->dev, si2165_upload_firmware()
520 ret = si2165_readreg16(state, 0x037a, &val16); si2165_upload_firmware()
525 dev_err(&state->i2c->dev, si2165_upload_firmware()
532 ret = si2165_upload_firmware_block(state, data, len, &offset, 5); si2165_upload_firmware()
537 dev_err(&state->i2c->dev, si2165_upload_firmware()
545 ret = si2165_writereg_mask8(state, 0x0341, 0x02, 0x02); si2165_upload_firmware()
550 ret = si2165_writereg_mask8(state, 0x035c, 0x01, 0x01); si2165_upload_firmware()
554 dev_info(&state->i2c->dev, "%s: fw load finished\n", KBUILD_MODNAME); si2165_upload_firmware()
557 state->firmware_loaded = true; si2165_upload_firmware()
570 struct si2165_state *state = fe->demodulator_priv; si2165_init() local
577 ret = si2165_writereg8(state, 0x0000, state->config.chip_mode); si2165_init()
581 ret = si2165_writereg8(state, 0x0104, 0x01); si2165_init()
584 ret = si2165_readreg8(state, 0x0000, &val); /* verify chip_mode */ si2165_init()
587 if (val != state->config.chip_mode) { si2165_init()
588 dev_err(&state->i2c->dev, "%s: could not set chip_mode\n", si2165_init()
594 ret = si2165_writereg8(state, 0x018b, 0x00); si2165_init()
597 ret = si2165_writereg8(state, 0x0190, 0x01); si2165_init()
600 ret = si2165_writereg8(state, 0x0170, 0x00); si2165_init()
603 ret = si2165_writereg8(state, 0x0171, 0x07); si2165_init()
607 ret = si2165_writereg8(state, 0x0646, 0x00); si2165_init()
610 ret = si2165_writereg8(state, 0x0641, 0x00); si2165_init()
614 ret = si2165_init_pll(state); si2165_init()
619 ret = si2165_writereg8(state, 0x0050, 0x01); si2165_init()
623 ret = si2165_writereg8(state, 0x0096, 0x01); si2165_init()
626 ret = si2165_wait_init_done(state); si2165_init()
631 ret = si2165_writereg8(state, 0x0050, 0x00); si2165_init()
636 ret = si2165_writereg16(state, 0x0470 , 0x7530); si2165_init()
640 ret = si2165_readreg8(state, 0x0344, &patch_version); si2165_init()
644 ret = si2165_writereg8(state, 0x00cb, 0x00); si2165_init()
649 ret = si2165_writereg32(state, 0x0348, 0xf4000000); si2165_init()
653 ret = si2165_readreg8(state, 0x0341, &val); si2165_init()
658 ret = si2165_upload_firmware(state); si2165_init()
664 ret = si2165_writereg8(state, 0x012a, 0x46); si2165_init()
667 ret = si2165_writereg8(state, 0x012c, 0x00); si2165_init()
670 ret = si2165_writereg8(state, 0x012e, 0x0a); si2165_init()
673 ret = si2165_writereg8(state, 0x012f, 0xff); si2165_init()
676 ret = si2165_writereg8(state, 0x0123, 0x70); si2165_init()
688 struct si2165_state *state = fe->demodulator_priv; si2165_sleep() local
691 ret = si2165_writereg8(state, 0x0104, 0x00); si2165_sleep()
695 ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF); si2165_sleep()
705 struct si2165_state *state = fe->demodulator_priv; si2165_read_status() local
707 if (!state->has_dvbt) si2165_read_status()
711 ret = si2165_readreg8(state, 0x4e0, &fec_lock); si2165_read_status()
726 static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate) si2165_set_oversamp() argument
731 oversamp = si2165_get_fe_clk(state); si2165_set_oversamp()
737 return si2165_writereg32(state, 0x00e4, reg_value); si2165_set_oversamp()
740 static int si2165_set_if_freq_shift(struct si2165_state *state, u32 IF) si2165_set_if_freq_shift() argument
744 u32 fe_clk = si2165_get_fe_clk(state); si2165_set_if_freq_shift()
752 if (state->config.inversion) si2165_set_if_freq_shift()
758 return si2165_writereg32(state, 0x00e8, reg_value); si2165_set_if_freq_shift()
765 struct si2165_state *state = fe->demodulator_priv; si2165_set_parameters() local
774 dev_err(&state->i2c->dev, si2165_set_parameters()
780 if (!state->has_dvbt) si2165_set_parameters()
792 ret = si2165_writereg8(state, 0x00ec, 0x01); si2165_set_parameters()
795 ret = si2165_adjust_pll_divl(state, 12); si2165_set_parameters()
800 ret = si2165_set_if_freq_shift(state, IF); si2165_set_parameters()
803 ret = si2165_writereg8(state, 0x08f8, 0x00); si2165_set_parameters()
807 ret = si2165_writereg8(state, 0x04e4, 0x20); si2165_set_parameters()
810 ret = si2165_writereg16(state, 0x04ef, 0x00fe); si2165_set_parameters()
813 ret = si2165_writereg24(state, 0x04f4, 0x555555); si2165_set_parameters()
816 ret = si2165_writereg8(state, 0x04e5, 0x01); si2165_set_parameters()
820 ret = si2165_writereg16(state, 0x0308, bw10k); si2165_set_parameters()
823 ret = si2165_set_oversamp(state, dvb_rate); si2165_set_parameters()
827 ret = si2165_writereg8(state, 0x031c, 0x01); si2165_set_parameters()
830 ret = si2165_writereg8(state, 0x00cb, 0x00); si2165_set_parameters()
834 ret = si2165_writereg8(state, 0x016e, 0x41); si2165_set_parameters()
837 ret = si2165_writereg8(state, 0x016c, 0x0e); si2165_set_parameters()
840 ret = si2165_writereg8(state, 0x016d, 0x10); si2165_set_parameters()
844 ret = si2165_writereg8(state, 0x015b, 0x03); si2165_set_parameters()
847 ret = si2165_writereg8(state, 0x0150, 0x78); si2165_set_parameters()
851 ret = si2165_writereg8(state, 0x01a0, 0x78); si2165_set_parameters()
854 ret = si2165_writereg8(state, 0x01c8, 0x68); si2165_set_parameters()
858 ret = si2165_writereg16(state, 0x030c, 0x0064); si2165_set_parameters()
862 ret = si2165_readreg8(state, 0x0387, val); si2165_set_parameters()
865 ret = si2165_writereg8(state, 0x0387, 0x00); si2165_set_parameters()
869 ret = si2165_writereg32(state, 0x0348, 0xf4000000); si2165_set_parameters()
878 ret = si2165_set_if_freq_shift(state, IF); si2165_set_parameters()
883 ret = si2165_readreg8(state, 0x0341, val); si2165_set_parameters()
886 ret = si2165_writereg8(state, 0x0341, 0x00); si2165_set_parameters()
890 ret = si2165_writereg8(state, 0x00c0, 0x00); si2165_set_parameters()
894 ret = si2165_writereg32(state, 0x0384, 0x00000000); si2165_set_parameters()
898 ret = si2165_writereg8(state, 0x02e0, 0x01); si2165_set_parameters()
902 ret = si2165_readreg8(state, 0x0341, val); si2165_set_parameters()
911 struct si2165_state *state = fe->demodulator_priv; si2165_release() local
914 kfree(state); si2165_release()
955 struct si2165_state *state = NULL; si2165_attach() local
965 /* allocate memory for the internal state */ si2165_attach()
966 state = kzalloc(sizeof(struct si2165_state), GFP_KERNEL); si2165_attach()
967 if (state == NULL) si2165_attach()
970 /* setup the state */ si2165_attach()
971 state->i2c = i2c; si2165_attach()
972 state->config = *config; si2165_attach()
974 if (state->config.ref_freq_Hz < 4000000 si2165_attach()
975 || state->config.ref_freq_Hz > 27000000) { si2165_attach()
976 dev_err(&state->i2c->dev, "%s: ref_freq of %d Hz not supported by this driver\n", si2165_attach()
977 KBUILD_MODNAME, state->config.ref_freq_Hz); si2165_attach()
982 memcpy(&state->frontend.ops, &si2165_ops, si2165_attach()
984 state->frontend.demodulator_priv = state; si2165_attach()
987 io_ret = si2165_writereg8(state, 0x0000, state->config.chip_mode); si2165_attach()
991 io_ret = si2165_readreg8(state, 0x0000, &val); si2165_attach()
994 if (val != state->config.chip_mode) si2165_attach()
997 io_ret = si2165_readreg8(state, 0x0023, &state->chip_revcode); si2165_attach()
1001 io_ret = si2165_readreg8(state, 0x0118, &state->chip_type); si2165_attach()
1006 io_ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF); si2165_attach()
1010 if (state->chip_revcode < 26) si2165_attach()
1011 rev_char = 'A' + state->chip_revcode; si2165_attach()
1015 switch (state->chip_type) { si2165_attach()
1018 state->has_dvbt = true; si2165_attach()
1022 state->has_dvbt = true; si2165_attach()
1023 state->has_dvbc = true; si2165_attach()
1026 dev_err(&state->i2c->dev, "%s: Unsupported Silicon Labs chip (type %d, rev %d)\n", si2165_attach()
1027 KBUILD_MODNAME, state->chip_type, state->chip_revcode); si2165_attach()
1031 dev_info(&state->i2c->dev, si2165_attach()
1033 KBUILD_MODNAME, chip_name, rev_char, state->chip_type, si2165_attach()
1034 state->chip_revcode); si2165_attach()
1036 strlcat(state->frontend.ops.info.name, chip_name, si2165_attach()
1037 sizeof(state->frontend.ops.info.name)); si2165_attach()
1040 if (state->has_dvbt) { si2165_attach()
1041 state->frontend.ops.delsys[n++] = SYS_DVBT; si2165_attach()
1042 strlcat(state->frontend.ops.info.name, " DVB-T", si2165_attach()
1043 sizeof(state->frontend.ops.info.name)); si2165_attach()
1045 if (state->has_dvbc) si2165_attach()
1046 dev_warn(&state->i2c->dev, "%s: DVB-C is not yet supported.\n", si2165_attach()
1049 return &state->frontend; si2165_attach()
1052 kfree(state); si2165_attach()
H A Ditd1000.c56 static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len) itd1000_write_regs() argument
60 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1 itd1000_write_regs()
75 if (i2c_transfer(state->i2c, &msg, 1) != 1) { itd1000_write_regs()
82 static int itd1000_read_reg(struct itd1000_state *state, u8 reg) itd1000_read_reg() argument
86 { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 }, itd1000_read_reg()
87 { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 }, itd1000_read_reg()
91 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); itd1000_read_reg()
93 if (i2c_transfer(state->i2c, msg, 2) != 2) { itd1000_read_reg()
100 static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v) itd1000_write_reg() argument
102 int ret = itd1000_write_regs(state, r, &v, 1); itd1000_write_reg()
103 state->shadow[r] = v; itd1000_write_reg()
130 static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate) itd1000_set_lpf_bw() argument
133 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd; itd1000_set_lpf_bw()
134 u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f; itd1000_set_lpf_bw()
135 u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0; itd1000_set_lpf_bw()
136 u8 bw = itd1000_read_reg(state, BW) & 0xf0; itd1000_set_lpf_bw()
141 itd1000_write_reg(state, CON1, con1 | (1 << 1)); itd1000_set_lpf_bw()
146 itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4)); itd1000_set_lpf_bw()
147 itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin)); itd1000_set_lpf_bw()
148 itd1000_write_reg(state, BW, bw | (i & 0x0f)); itd1000_set_lpf_bw()
152 itd1000_write_reg(state, CON1, con1 | (0 << 1)); itd1000_set_lpf_bw()
176 static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz) itd1000_set_vco() argument
179 u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf; itd1000_set_vco()
180 u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f; itd1000_set_vco()
184 itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6)); itd1000_set_vco()
188 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4)); itd1000_set_vco()
191 adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f; itd1000_set_vco()
197 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4)); itd1000_set_vco()
200 itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4)); itd1000_set_vco()
226 static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz) itd1000_set_lo() argument
242 state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF; itd1000_set_lo()
243 itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln); itd1000_set_lo()
245 itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */ itd1000_set_lo()
246 itd1000_write_reg(state, PLLNL, plln & 0xff); itd1000_set_lo()
247 itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f)); itd1000_set_lo()
248 itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff); itd1000_set_lo()
249 itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff); itd1000_set_lo()
254 itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]); itd1000_set_lo()
256 itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]); itd1000_set_lo()
261 itd1000_set_vco(state, freq_khz); itd1000_set_lo()
267 struct itd1000_state *state = fe->tuner_priv; itd1000_set_parameters() local
270 itd1000_set_lo(state, c->frequency); itd1000_set_parameters()
271 itd1000_set_lpf_bw(state, c->symbol_rate); itd1000_set_parameters()
273 pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f; itd1000_set_parameters()
274 itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7)); itd1000_set_parameters()
275 itd1000_write_reg(state, PLLCON1, pllcon1); itd1000_set_parameters()
282 struct itd1000_state *state = fe->tuner_priv; itd1000_get_frequency() local
283 *frequency = state->frequency; itd1000_get_frequency()
334 struct itd1000_state *state = fe->tuner_priv; itd1000_init() local
338 itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]); itd1000_init()
341 itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]); itd1000_init()
379 struct itd1000_state *state = NULL; itd1000_attach() local
382 state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL); itd1000_attach()
383 if (state == NULL) itd1000_attach()
386 state->cfg = cfg; itd1000_attach()
387 state->i2c = i2c; itd1000_attach()
389 i = itd1000_read_reg(state, 0); itd1000_attach()
391 kfree(state); itd1000_attach()
396 memset(state->shadow, 0xff, sizeof(state->shadow)); itd1000_attach()
398 state->shadow[i] = itd1000_read_reg(state, i); itd1000_attach()
402 fe->tuner_priv = state; itd1000_attach()
H A Dcx24123.c245 static int cx24123_i2c_writereg(struct cx24123_state *state, cx24123_i2c_writereg() argument
256 err = i2c_transfer(state->i2c, &msg, 1); cx24123_i2c_writereg()
266 static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg) cx24123_i2c_readreg() argument
275 ret = i2c_transfer(state->i2c, msg, 2); cx24123_i2c_readreg()
287 #define cx24123_readreg(state, reg) \
288 cx24123_i2c_readreg(state, state->config->demod_address, reg)
289 #define cx24123_writereg(state, reg, val) \
290 cx24123_i2c_writereg(state, state->config->demod_address, reg, val)
292 static int cx24123_set_inversion(struct cx24123_state *state, cx24123_set_inversion() argument
295 u8 nom_reg = cx24123_readreg(state, 0x0e); cx24123_set_inversion()
296 u8 auto_reg = cx24123_readreg(state, 0x10); cx24123_set_inversion()
301 cx24123_writereg(state, 0x0e, nom_reg & ~0x80); cx24123_set_inversion()
302 cx24123_writereg(state, 0x10, auto_reg | 0x80); cx24123_set_inversion()
306 cx24123_writereg(state, 0x0e, nom_reg | 0x80); cx24123_set_inversion()
307 cx24123_writereg(state, 0x10, auto_reg | 0x80); cx24123_set_inversion()
311 cx24123_writereg(state, 0x10, auto_reg & ~0x80); cx24123_set_inversion()
320 static int cx24123_get_inversion(struct cx24123_state *state, cx24123_get_inversion() argument
325 val = cx24123_readreg(state, 0x1b) >> 7; cx24123_get_inversion()
338 static int cx24123_set_fec(struct cx24123_state *state, fe_code_rate_t fec) cx24123_set_fec() argument
340 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; cx24123_set_fec()
347 cx24123_writereg(state, 0x43, cx24123_set_fec()
348 cx24123_readreg(state, 0x43) | 0x01); cx24123_set_fec()
350 cx24123_writereg(state, 0x43, cx24123_set_fec()
351 cx24123_readreg(state, 0x43) & ~0x01); cx24123_set_fec()
356 cx24123_writereg(state, 0x0e, nom_reg | 0x01); cx24123_set_fec()
357 cx24123_writereg(state, 0x0f, 0x02); cx24123_set_fec()
361 cx24123_writereg(state, 0x0e, nom_reg | 0x02); cx24123_set_fec()
362 cx24123_writereg(state, 0x0f, 0x04); cx24123_set_fec()
366 cx24123_writereg(state, 0x0e, nom_reg | 0x03); cx24123_set_fec()
367 cx24123_writereg(state, 0x0f, 0x08); cx24123_set_fec()
371 cx24123_writereg(state, 0x0e, nom_reg | 0x04); cx24123_set_fec()
372 cx24123_writereg(state, 0x0f, 0x10); cx24123_set_fec()
376 cx24123_writereg(state, 0x0e, nom_reg | 0x05); cx24123_set_fec()
377 cx24123_writereg(state, 0x0f, 0x20); cx24123_set_fec()
381 cx24123_writereg(state, 0x0e, nom_reg | 0x06); cx24123_set_fec()
382 cx24123_writereg(state, 0x0f, 0x40); cx24123_set_fec()
386 cx24123_writereg(state, 0x0e, nom_reg | 0x07); cx24123_set_fec()
387 cx24123_writereg(state, 0x0f, 0x80); cx24123_set_fec()
391 cx24123_writereg(state, 0x0f, 0xfe); cx24123_set_fec()
400 static int cx24123_get_fec(struct cx24123_state *state, fe_code_rate_t *fec) cx24123_get_fec() argument
404 ret = cx24123_readreg(state, 0x1b); cx24123_get_fec()
454 static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate) cx24123_set_symbolrate() argument
461 if ((srate > state->frontend.ops.info.symbol_rate_max) || cx24123_set_symbolrate()
462 (srate < state->frontend.ops.info.symbol_rate_min)) cx24123_set_symbolrate()
493 cx24123_writereg(state, 0x01, pll_mult * 6); cx24123_set_symbolrate()
495 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f); cx24123_set_symbolrate()
496 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff); cx24123_set_symbolrate()
497 cx24123_writereg(state, 0x0a, ratio & 0xff); cx24123_set_symbolrate()
501 tmp = cx24123_readreg(state, 0x0c) & ~0xe0; cx24123_set_symbolrate()
502 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); cx24123_set_symbolrate()
518 struct cx24123_state *state = fe->demodulator_priv; cx24123_pll_calculate() local
528 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; cx24123_pll_calculate()
529 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; cx24123_pll_calculate()
530 state->bandselectarg = cx24123_bandselect_vals[0].progdata; cx24123_pll_calculate()
539 state->VCAarg = agcv->VCAprogdata; cx24123_pll_calculate()
540 state->VGAarg = agcv->VGAprogdata; cx24123_pll_calculate()
541 state->FILTune = agcv->FILTune; cx24123_pll_calculate()
556 state->bandselectarg = cx24123_bandselect_vals[band].progdata; cx24123_pll_calculate()
579 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | cx24123_pll_calculate()
592 struct cx24123_state *state = fe->demodulator_priv; cx24123_pll_writereg() local
601 cx24123_writereg(state, 0x21, 0x15); cx24123_pll_writereg()
605 cx24123_writereg(state, 0x22, (data >> 16) & 0xff); cx24123_pll_writereg()
606 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { cx24123_pll_writereg()
617 cx24123_writereg(state, 0x22, (data >> 8) & 0xff); cx24123_pll_writereg()
618 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { cx24123_pll_writereg()
630 cx24123_writereg(state, 0x22, (data) & 0xff); cx24123_pll_writereg()
631 while ((cx24123_readreg(state, 0x20) & 0x80)) { cx24123_pll_writereg()
641 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); cx24123_pll_writereg()
642 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); cx24123_pll_writereg()
650 struct cx24123_state *state = fe->demodulator_priv; cx24123_pll_tune() local
661 cx24123_pll_writereg(fe, state->VCAarg); cx24123_pll_tune()
662 cx24123_pll_writereg(fe, state->VGAarg); cx24123_pll_tune()
665 cx24123_pll_writereg(fe, state->bandselectarg); cx24123_pll_tune()
666 cx24123_pll_writereg(fe, state->pllarg); cx24123_pll_tune()
669 val = cx24123_readreg(state, 0x28) & ~0x3; cx24123_pll_tune()
670 cx24123_writereg(state, 0x27, state->FILTune >> 2); cx24123_pll_tune()
671 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); cx24123_pll_tune()
673 dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg, cx24123_pll_tune()
674 state->bandselectarg, state->pllarg); cx24123_pll_tune()
689 static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start) cx24123_repeater_mode() argument
691 u8 r = cx24123_readreg(state, 0x23) & 0x1e; cx24123_repeater_mode()
696 return cx24123_writereg(state, 0x23, r); cx24123_repeater_mode()
701 struct cx24123_state *state = fe->demodulator_priv; cx24123_initfe() local
708 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_initfe()
712 if (state->config->lnb_polarity) cx24123_initfe()
713 cx24123_writereg(state, 0x32, cx24123_initfe()
714 cx24123_readreg(state, 0x32) | 0x02); cx24123_initfe()
716 if (state->config->dont_use_pll) cx24123_initfe()
717 cx24123_repeater_mode(state, 1, 0); cx24123_initfe()
725 struct cx24123_state *state = fe->demodulator_priv; cx24123_set_voltage() local
728 val = cx24123_readreg(state, 0x29) & ~0x40; cx24123_set_voltage()
733 return cx24123_writereg(state, 0x29, val & 0x7f); cx24123_set_voltage()
736 return cx24123_writereg(state, 0x29, val | 0x80); cx24123_set_voltage()
748 static void cx24123_wait_for_diseqc(struct cx24123_state *state) cx24123_wait_for_diseqc() argument
751 while (!(cx24123_readreg(state, 0x29) & 0x40)) { cx24123_wait_for_diseqc()
764 struct cx24123_state *state = fe->demodulator_priv; cx24123_send_diseqc_msg() local
770 tone = cx24123_readreg(state, 0x29); cx24123_send_diseqc_msg()
772 cx24123_writereg(state, 0x29, tone & ~0x50); cx24123_send_diseqc_msg()
775 cx24123_wait_for_diseqc(state); cx24123_send_diseqc_msg()
778 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); cx24123_send_diseqc_msg()
781 cx24123_writereg(state, 0x2C + i, cmd->msg[i]); cx24123_send_diseqc_msg()
783 val = cx24123_readreg(state, 0x29); cx24123_send_diseqc_msg()
784 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | cx24123_send_diseqc_msg()
788 cx24123_wait_for_diseqc(state); cx24123_send_diseqc_msg()
792 cx24123_writereg(state, 0x29, tone & ~0x40); cx24123_send_diseqc_msg()
800 struct cx24123_state *state = fe->demodulator_priv; cx24123_diseqc_send_burst() local
806 tone = cx24123_readreg(state, 0x29); cx24123_diseqc_send_burst()
808 cx24123_writereg(state, 0x29, tone & ~0x50); cx24123_diseqc_send_burst()
811 cx24123_wait_for_diseqc(state); cx24123_diseqc_send_burst()
814 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); cx24123_diseqc_send_burst()
816 val = cx24123_readreg(state, 0x29); cx24123_diseqc_send_burst()
818 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); cx24123_diseqc_send_burst()
820 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); cx24123_diseqc_send_burst()
824 cx24123_wait_for_diseqc(state); cx24123_diseqc_send_burst()
825 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); cx24123_diseqc_send_burst()
829 cx24123_writereg(state, 0x29, tone & ~0x40); cx24123_diseqc_send_burst()
836 struct cx24123_state *state = fe->demodulator_priv; cx24123_read_status() local
837 int sync = cx24123_readreg(state, 0x14); cx24123_read_status()
840 if (state->config->dont_use_pll) { cx24123_read_status()
847 int lock = cx24123_readreg(state, 0x20); cx24123_read_status()
873 struct cx24123_state *state = fe->demodulator_priv; cx24123_read_ber() local
877 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | cx24123_read_ber()
878 (cx24123_readreg(state, 0x1d) << 8 | cx24123_read_ber()
879 cx24123_readreg(state, 0x1e)); cx24123_read_ber()
889 struct cx24123_state *state = fe->demodulator_priv; cx24123_read_signal_strength() local
892 *signal_strength = cx24123_readreg(state, 0x3b) << 8; cx24123_read_signal_strength()
901 struct cx24123_state *state = fe->demodulator_priv; cx24123_read_snr() local
905 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | cx24123_read_snr()
906 (u16)cx24123_readreg(state, 0x19)); cx24123_read_snr()
915 struct cx24123_state *state = fe->demodulator_priv; cx24123_set_frontend() local
920 if (state->config->set_ts_params) cx24123_set_frontend()
921 state->config->set_ts_params(fe, 0); cx24123_set_frontend()
923 state->currentfreq = p->frequency; cx24123_set_frontend()
924 state->currentsymbolrate = p->symbol_rate; cx24123_set_frontend()
926 cx24123_set_inversion(state, p->inversion); cx24123_set_frontend()
927 cx24123_set_fec(state, p->fec_inner); cx24123_set_frontend()
928 cx24123_set_symbolrate(state, p->symbol_rate); cx24123_set_frontend()
930 if (!state->config->dont_use_pll) cx24123_set_frontend()
938 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); cx24123_set_frontend()
939 cx24123_writereg(state, 0x00, 0x10); cx24123_set_frontend()
940 cx24123_writereg(state, 0x00, 0); cx24123_set_frontend()
942 if (state->config->agc_callback) cx24123_set_frontend()
943 state->config->agc_callback(fe); cx24123_set_frontend()
951 struct cx24123_state *state = fe->demodulator_priv; cx24123_get_frontend() local
955 if (cx24123_get_inversion(state, &p->inversion) != 0) { cx24123_get_frontend()
959 if (cx24123_get_fec(state, &p->fec_inner) != 0) { cx24123_get_frontend()
963 p->frequency = state->currentfreq; cx24123_get_frontend()
964 p->symbol_rate = state->currentsymbolrate; cx24123_get_frontend()
971 struct cx24123_state *state = fe->demodulator_priv; cx24123_set_tone() local
975 cx24123_wait_for_diseqc(state); cx24123_set_tone()
977 val = cx24123_readreg(state, 0x29) & ~0x40; cx24123_set_tone()
982 return cx24123_writereg(state, 0x29, val | 0x10); cx24123_set_tone()
985 return cx24123_writereg(state, 0x29, val & 0xef); cx24123_set_tone()
1019 struct cx24123_state *state = fe->demodulator_priv; cx24123_release() local
1021 i2c_del_adapter(&state->tuner_i2c_adapter); cx24123_release()
1022 kfree(state); cx24123_release()
1028 struct cx24123_state *state = i2c_get_adapdata(i2c_adap); cx24123_tuner_i2c_tuner_xfer() local
1030 cx24123_repeater_mode(state, 1, 1); cx24123_tuner_i2c_tuner_xfer()
1031 return i2c_transfer(state->i2c, msg, num); cx24123_tuner_i2c_tuner_xfer()
1047 struct cx24123_state *state = fe->demodulator_priv; cx24123_get_tuner_i2c_adapter() local
1048 return &state->tuner_i2c_adapter; cx24123_get_tuner_i2c_adapter()
1057 /* allocate memory for the internal state */ cx24123_attach()
1058 struct cx24123_state *state = cx24123_attach() local
1062 if (state == NULL) { cx24123_attach()
1067 /* setup the state */ cx24123_attach()
1068 state->config = config; cx24123_attach()
1069 state->i2c = i2c; cx24123_attach()
1072 state->demod_rev = cx24123_readreg(state, 0x00); cx24123_attach()
1073 switch (state->demod_rev) { cx24123_attach()
1081 err("wrong demod revision: %x\n", state->demod_rev); cx24123_attach()
1086 memcpy(&state->frontend.ops, &cx24123_ops, cx24123_attach()
1088 state->frontend.demodulator_priv = state; cx24123_attach()
1092 cx24123_repeater_mode(state, 1, 0); cx24123_attach()
1094 strlcpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus", cx24123_attach()
1095 sizeof(state->tuner_i2c_adapter.name)); cx24123_attach()
1096 state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo; cx24123_attach()
1097 state->tuner_i2c_adapter.algo_data = NULL; cx24123_attach()
1098 state->tuner_i2c_adapter.dev.parent = i2c->dev.parent; cx24123_attach()
1099 i2c_set_adapdata(&state->tuner_i2c_adapter, state); cx24123_attach()
1100 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { cx24123_attach()
1105 return &state->frontend; cx24123_attach()
1108 kfree(state); cx24123_attach()
H A Dor51211.c72 static int i2c_writebytes (struct or51211_state* state, u8 reg, const u8 *buf, i2c_writebytes() argument
82 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { i2c_writebytes()
90 static int i2c_readbytes(struct or51211_state *state, u8 reg, u8 *buf, int len) i2c_readbytes() argument
99 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { i2c_readbytes()
110 struct or51211_state* state = fe->demodulator_priv; or51211_load_firmware() local
118 if (i2c_writebytes(state,0x50,tudata,1)) { or51211_load_firmware()
122 if (i2c_readbytes(state,0x50,&tudata[145],192)) { or51211_load_firmware()
134 state->config->reset(fe); or51211_load_firmware()
136 if (i2c_writebytes(state,state->config->demod_address,tudata,585)) { or51211_load_firmware()
142 if (i2c_writebytes(state,state->config->demod_address, or51211_load_firmware()
149 if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) { or51211_load_firmware()
156 if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) { or51211_load_firmware()
168 struct or51211_state* state = fe->demodulator_priv; or51211_setmode() local
171 state->config->setmode(fe, mode); or51211_setmode()
173 if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) { or51211_setmode()
180 if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) { or51211_setmode()
196 if (i2c_writebytes(state,state->config->demod_address,cmd_buf,3)) { or51211_setmode()
206 if (i2c_writebytes(state,state->config->demod_address,rec_buf,3)) { or51211_setmode()
210 if (i2c_readbytes(state,state->config->demod_address,&rec_buf[10],2)) { or51211_setmode()
222 struct or51211_state* state = fe->demodulator_priv; or51211_set_parameters() local
225 if (state->current_frequency != p->frequency) { or51211_set_parameters()
235 state->current_frequency = p->frequency; or51211_set_parameters()
242 struct or51211_state* state = fe->demodulator_priv; or51211_read_status() local
248 if (i2c_writebytes(state,state->config->demod_address,snd_buf,3)) { or51211_read_status()
253 if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) { or51211_read_status()
297 struct or51211_state* state = fe->demodulator_priv; or51211_read_snr() local
306 if (i2c_writebytes(state,state->config->demod_address,snd_buf,3)) { or51211_read_snr()
310 if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) { or51211_read_snr()
315 state->snr = calculate_snr(rec_buf[0], 89599047); or51211_read_snr()
316 *snr = (state->snr) >> 16; or51211_read_snr()
319 state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16); or51211_read_snr()
329 struct or51211_state* state = (struct or51211_state*)fe->demodulator_priv; or51211_read_signal_strength() local
336 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ or51211_read_signal_strength()
338 if (state->snr >= 8960 * 0x10000) or51211_read_signal_strength()
341 *strength = state->snr / 8960; or51211_read_signal_strength()
365 struct or51211_state* state = fe->demodulator_priv; or51211_init() local
366 const struct or51211_config* config = state->config; or51211_init()
372 if (!state->initialized) { or51211_init()
402 if (i2c_writebytes(state,state->config->demod_address, or51211_init()
415 if (i2c_writebytes(state,state->config->demod_address, or51211_init()
421 if (i2c_readbytes(state,state->config->demod_address, or51211_init()
432 if (i2c_writebytes(state,state->config->demod_address, or51211_init()
438 if (i2c_readbytes(state,state->config->demod_address, or51211_init()
450 if (i2c_writebytes(state,state->config->demod_address, or51211_init()
457 if (i2c_readbytes(state,state->config->demod_address, or51211_init()
478 if (i2c_writebytes(state,state->config->demod_address, or51211_init()
484 if (i2c_readbytes(state,state->config->demod_address, or51211_init()
489 state->initialized = 1; or51211_init()
506 struct or51211_state* state = fe->demodulator_priv; or51211_release() local
507 state->config->sleep(fe); or51211_release()
508 kfree(state); or51211_release()
516 struct or51211_state* state = NULL; or51211_attach() local
518 /* Allocate memory for the internal state */ or51211_attach()
519 state = kzalloc(sizeof(struct or51211_state), GFP_KERNEL); or51211_attach()
520 if (state == NULL) or51211_attach()
523 /* Setup the state */ or51211_attach()
524 state->config = config; or51211_attach()
525 state->i2c = i2c; or51211_attach()
526 state->initialized = 0; or51211_attach()
527 state->current_frequency = 0; or51211_attach()
530 memcpy(&state->frontend.ops, &or51211_ops, sizeof(struct dvb_frontend_ops)); or51211_attach()
531 state->frontend.demodulator_priv = state; or51211_attach()
532 return &state->frontend; or51211_attach()
H A Dsp8870.c66 static int sp8870_writereg (struct sp8870_state* state, u16 reg, u16 data) sp8870_writereg() argument
69 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 4 }; sp8870_writereg()
72 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { sp8870_writereg()
80 static int sp8870_readreg (struct sp8870_state* state, u16 reg) sp8870_readreg() argument
85 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, sp8870_readreg()
86 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 2 } }; sp8870_readreg()
88 ret = i2c_transfer (state->i2c, msg, 2); sp8870_readreg()
98 static int sp8870_firmware_upload (struct sp8870_state* state, const struct firmware *fw) sp8870_firmware_upload() argument
113 sp8870_writereg(state, 0x0F00, 0x0000); sp8870_firmware_upload()
116 sp8870_writereg(state, 0x8F08, ((SP8870_FIRMWARE_SIZE / 2) & 0xFFFF)); sp8870_firmware_upload()
119 sp8870_writereg(state, 0x8F0A, ((SP8870_FIRMWARE_SIZE / 2) >> 16)); sp8870_firmware_upload()
129 msg.addr = state->config->demod_address; sp8870_firmware_upload()
133 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { sp8870_firmware_upload()
145 static void sp8870_microcontroller_stop (struct sp8870_state* state) sp8870_microcontroller_stop() argument
147 sp8870_writereg(state, 0x0F08, 0x000); sp8870_microcontroller_stop()
148 sp8870_writereg(state, 0x0F09, 0x000); sp8870_microcontroller_stop()
151 sp8870_writereg(state, 0x0F00, 0x000); sp8870_microcontroller_stop()
154 static void sp8870_microcontroller_start (struct sp8870_state* state) sp8870_microcontroller_start() argument
156 sp8870_writereg(state, 0x0F08, 0x000); sp8870_microcontroller_start()
157 sp8870_writereg(state, 0x0F09, 0x000); sp8870_microcontroller_start()
160 sp8870_writereg(state, 0x0F00, 0x001); sp8870_microcontroller_start()
163 sp8870_readreg(state, 0x0D01); sp8870_microcontroller_start()
166 static int sp8870_read_data_valid_signal(struct sp8870_state* state) sp8870_read_data_valid_signal() argument
168 return (sp8870_readreg(state, 0x0D02) > 0); sp8870_read_data_valid_signal()
242 static int sp8870_wake_up(struct sp8870_state* state) sp8870_wake_up() argument
245 return sp8870_writereg(state, 0xC18, 0x00D); sp8870_wake_up()
251 struct sp8870_state* state = fe->demodulator_priv; sp8870_set_frontend_parameters() local
259 sp8870_microcontroller_stop(state); sp8870_set_frontend_parameters()
268 sp8870_writereg(state, 0x0319, 0x000A); sp8870_set_frontend_parameters()
271 sp8870_writereg(state, 0x031A, 0x0AAB); sp8870_set_frontend_parameters()
274 sp8870_writereg(state, 0x0309, 0x0400); sp8870_set_frontend_parameters()
277 sp8870_writereg(state, 0x030A, 0x0000); sp8870_set_frontend_parameters()
281 sp8870_writereg(state, 0x0311, 0x0002); sp8870_set_frontend_parameters()
283 sp8870_writereg(state, 0x0311, 0x0001); sp8870_set_frontend_parameters()
285 sp8870_writereg(state, 0x0311, 0x0000); sp8870_set_frontend_parameters()
289 sp8870_writereg(state, 0x0338, 0x0000); sp8870_set_frontend_parameters()
291 sp8870_writereg(state, 0x0338, 0x0001); sp8870_set_frontend_parameters()
293 sp8870_writereg(state, 0xc05, reg0xc05); sp8870_set_frontend_parameters()
296 sp8870_readreg(state, 0x200); sp8870_set_frontend_parameters()
299 sp8870_microcontroller_start(state); sp8870_set_frontend_parameters()
306 struct sp8870_state* state = fe->demodulator_priv; sp8870_init() local
309 sp8870_wake_up(state); sp8870_init()
310 if (state->initialised) return 0; sp8870_init()
311 state->initialised = 1; sp8870_init()
318 if (state->config->request_firmware(fe, &fw, SP8870_DEFAULT_FIRMWARE)) { sp8870_init()
323 if (sp8870_firmware_upload(state, fw)) { sp8870_init()
332 sp8870_writereg(state, 0xc18, 0x00d); sp8870_init()
335 sp8870_microcontroller_stop(state); sp8870_init()
338 sp8870_writereg(state, 0x0301, 0x0003); sp8870_init()
341 sp8870_writereg(state, 0x0C13, 0x0001); sp8870_init()
344 sp8870_writereg(state, 0x0C14, 0x0001); sp8870_init()
347 sp8870_writereg(state, 0x0D00, 0x010); sp8870_init()
348 sp8870_writereg(state, 0x0D01, 0x000); sp8870_init()
355 struct sp8870_state* state = fe->demodulator_priv; sp8870_read_status() local
361 status = sp8870_readreg (state, 0x0200); sp8870_read_status()
365 signal = sp8870_readreg (state, 0x0303); sp8870_read_status()
381 struct sp8870_state* state = fe->demodulator_priv; sp8870_read_ber() local
387 ret = sp8870_readreg(state, 0xC08); sp8870_read_ber()
393 ret = sp8870_readreg(state, 0xC07); sp8870_read_ber()
408 struct sp8870_state* state = fe->demodulator_priv; sp8870_read_signal_strength() local
414 ret = sp8870_readreg (state, 0x306); sp8870_read_signal_strength()
420 ret = sp8870_readreg (state, 0x303); sp8870_read_signal_strength()
434 struct sp8870_state* state = fe->demodulator_priv; sp8870_read_uncorrected_blocks() local
439 ret = sp8870_readreg(state, 0xC0C); sp8870_read_uncorrected_blocks()
464 struct sp8870_state* state = fe->demodulator_priv; sp8870_set_frontend() local
488 valid = sp8870_read_data_valid_signal(state); sp8870_set_frontend()
522 struct sp8870_state* state = fe->demodulator_priv; sp8870_sleep() local
525 return sp8870_writereg(state, 0xC18, 0x000); sp8870_sleep()
538 struct sp8870_state* state = fe->demodulator_priv; sp8870_i2c_gate_ctrl() local
541 return sp8870_writereg(state, 0x206, 0x001); sp8870_i2c_gate_ctrl()
543 return sp8870_writereg(state, 0x206, 0x000); sp8870_i2c_gate_ctrl()
549 struct sp8870_state* state = fe->demodulator_priv; sp8870_release() local
550 kfree(state); sp8870_release()
558 struct sp8870_state* state = NULL; sp8870_attach() local
560 /* allocate memory for the internal state */ sp8870_attach()
561 state = kzalloc(sizeof(struct sp8870_state), GFP_KERNEL); sp8870_attach()
562 if (state == NULL) goto error; sp8870_attach()
564 /* setup the state */ sp8870_attach()
565 state->config = config; sp8870_attach()
566 state->i2c = i2c; sp8870_attach()
567 state->initialised = 0; sp8870_attach()
570 if (sp8870_readreg(state, 0x0200) < 0) goto error; sp8870_attach()
573 memcpy(&state->frontend.ops, &sp8870_ops, sizeof(struct dvb_frontend_ops)); sp8870_attach()
574 state->frontend.demodulator_priv = state; sp8870_attach()
575 return &state->frontend; sp8870_attach()
578 kfree(state); sp8870_attach()
H A Dcx22702.c85 static int cx22702_writereg(struct cx22702_state *state, u8 reg, u8 data) cx22702_writereg() argument
90 .addr = state->config->demod_address, .flags = 0, cx22702_writereg()
93 ret = i2c_transfer(state->i2c, &msg, 1); cx22702_writereg()
105 static u8 cx22702_readreg(struct cx22702_state *state, u8 reg) cx22702_readreg() argument
111 { .addr = state->config->demod_address, .flags = 0, cx22702_readreg()
113 { .addr = state->config->demod_address, .flags = I2C_M_RD, cx22702_readreg()
116 ret = i2c_transfer(state->i2c, msg, 2); cx22702_readreg()
127 static int cx22702_set_inversion(struct cx22702_state *state, int inversion) cx22702_set_inversion() argument
131 val = cx22702_readreg(state, 0x0C); cx22702_set_inversion()
144 return cx22702_writereg(state, 0x0C, val); cx22702_set_inversion()
148 static int cx22702_get_tps(struct cx22702_state *state, cx22702_get_tps() argument
154 if (!(cx22702_readreg(state, 0x0A) & 0x20)) cx22702_get_tps()
157 val = cx22702_readreg(state, 0x01); cx22702_get_tps()
185 val = cx22702_readreg(state, 0x02); cx22702_get_tps()
221 val = cx22702_readreg(state, 0x03); cx22702_get_tps()
250 struct cx22702_state *state = fe->demodulator_priv; cx22702_i2c_gate_ctrl() local
254 val = cx22702_readreg(state, 0x0D); cx22702_i2c_gate_ctrl()
259 return cx22702_writereg(state, 0x0D, val); cx22702_i2c_gate_ctrl()
267 struct cx22702_state *state = fe->demodulator_priv; cx22702_set_tps() local
276 cx22702_set_inversion(state, p->inversion); cx22702_set_tps()
279 val = cx22702_readreg(state, 0x0C) & 0xcf; cx22702_set_tps()
293 cx22702_writereg(state, 0x0C, val); cx22702_set_tps()
306 cx22702_writereg(state, 0x06, 0x10); cx22702_set_tps()
307 cx22702_writereg(state, 0x07, 0x9); cx22702_set_tps()
308 cx22702_writereg(state, 0x08, 0xC1); cx22702_set_tps()
309 cx22702_writereg(state, 0x0B, cx22702_readreg(state, 0x0B) cx22702_set_tps()
311 cx22702_writereg(state, 0x0C, cx22702_set_tps()
312 (cx22702_readreg(state, 0x0C) & 0xBF) | 0x40); cx22702_set_tps()
313 cx22702_writereg(state, 0x00, 0x01); /* Begin acquisition */ cx22702_set_tps()
349 cx22702_writereg(state, 0x06, val); cx22702_set_tps()
392 cx22702_writereg(state, 0x07, val); cx22702_set_tps()
421 cx22702_writereg(state, 0x08, val); cx22702_set_tps()
422 cx22702_writereg(state, 0x0B, cx22702_set_tps()
423 (cx22702_readreg(state, 0x0B) & 0xfc) | 0x02); cx22702_set_tps()
424 cx22702_writereg(state, 0x0C, cx22702_set_tps()
425 (cx22702_readreg(state, 0x0C) & 0xBF) | 0x40); cx22702_set_tps()
428 cx22702_writereg(state, 0x00, 0x01); cx22702_set_tps()
434 to a default state. */ cx22702_init()
438 struct cx22702_state *state = fe->demodulator_priv; cx22702_init() local
440 cx22702_writereg(state, 0x00, 0x02); cx22702_init()
445 cx22702_writereg(state, init_tab[i], init_tab[i + 1]); cx22702_init()
447 cx22702_writereg(state, 0xf8, (state->config->output_mode << 1) cx22702_init()
457 struct cx22702_state *state = fe->demodulator_priv; cx22702_read_status() local
463 reg0A = cx22702_readreg(state, 0x0A); cx22702_read_status()
464 reg23 = cx22702_readreg(state, 0x23); cx22702_read_status()
486 struct cx22702_state *state = fe->demodulator_priv; cx22702_read_ber() local
488 if (cx22702_readreg(state, 0xE4) & 0x02) { cx22702_read_ber()
490 *ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7 cx22702_read_ber()
491 | (cx22702_readreg(state, 0xDF) & 0x7F); cx22702_read_ber()
494 *ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7 cx22702_read_ber()
495 | cx22702_readreg(state, 0xDF); cx22702_read_ber()
504 struct cx22702_state *state = fe->demodulator_priv; cx22702_read_signal_strength() local
517 reg23 = cx22702_readreg(state, 0x23); cx22702_read_signal_strength()
531 struct cx22702_state *state = fe->demodulator_priv; cx22702_read_snr() local
534 if (cx22702_readreg(state, 0xE4) & 0x02) { cx22702_read_snr()
536 rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7 cx22702_read_snr()
537 | (cx22702_readreg(state, 0xDF) & 0x7F); cx22702_read_snr()
540 rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 8 cx22702_read_snr()
541 | cx22702_readreg(state, 0xDF); cx22702_read_snr()
550 struct cx22702_state *state = fe->demodulator_priv; cx22702_read_ucblocks() local
555 _ucblocks = cx22702_readreg(state, 0xE3); cx22702_read_ucblocks()
556 if (state->prevUCBlocks < _ucblocks) cx22702_read_ucblocks()
557 *ucblocks = (_ucblocks - state->prevUCBlocks); cx22702_read_ucblocks()
559 *ucblocks = state->prevUCBlocks - _ucblocks; cx22702_read_ucblocks()
560 state->prevUCBlocks = _ucblocks; cx22702_read_ucblocks()
568 struct cx22702_state *state = fe->demodulator_priv; cx22702_get_frontend() local
570 u8 reg0C = cx22702_readreg(state, 0x0C); cx22702_get_frontend()
573 return cx22702_get_tps(state, c); cx22702_get_frontend()
585 struct cx22702_state *state = fe->demodulator_priv; cx22702_release() local
586 kfree(state); cx22702_release()
594 struct cx22702_state *state = NULL; cx22702_attach() local
596 /* allocate memory for the internal state */ cx22702_attach()
597 state = kzalloc(sizeof(struct cx22702_state), GFP_KERNEL); cx22702_attach()
598 if (state == NULL) cx22702_attach()
601 /* setup the state */ cx22702_attach()
602 state->config = config; cx22702_attach()
603 state->i2c = i2c; cx22702_attach()
606 if (cx22702_readreg(state, 0x1f) != 0x3) cx22702_attach()
610 memcpy(&state->frontend.ops, &cx22702_ops, cx22702_attach()
612 state->frontend.demodulator_priv = state; cx22702_attach()
613 return &state->frontend; cx22702_attach()
616 kfree(state); cx22702_attach()
H A Dmt312.c63 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, mt312_read() argument
70 msg[0].addr = state->config->demod_address; mt312_read()
74 msg[1].addr = state->config->demod_address; mt312_read()
79 ret = i2c_transfer(state->i2c, msg, 2); mt312_read()
97 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, mt312_write() argument
121 msg.addr = state->config->demod_address; mt312_write()
126 ret = i2c_transfer(state->i2c, &msg, 1); mt312_write()
136 static inline int mt312_readreg(struct mt312_state *state, mt312_readreg() argument
139 return mt312_read(state, reg, val, 1); mt312_readreg()
142 static inline int mt312_writereg(struct mt312_state *state, mt312_writereg() argument
145 return mt312_write(state, reg, &val, 1); mt312_writereg()
153 static int mt312_reset(struct mt312_state *state, const u8 full) mt312_reset() argument
155 return mt312_writereg(state, RESET, full ? 0x80 : 0x40); mt312_reset()
158 static int mt312_get_inversion(struct mt312_state *state, mt312_get_inversion() argument
164 ret = mt312_readreg(state, VIT_MODE, &vit_mode); mt312_get_inversion()
174 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr) mt312_get_symbol_rate() argument
183 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); mt312_get_symbol_rate()
189 ret = mt312_writereg(state, MON_CTRL, 0x03); mt312_get_symbol_rate()
193 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); mt312_get_symbol_rate()
202 ret = mt312_writereg(state, MON_CTRL, 0x05); mt312_get_symbol_rate()
206 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); mt312_get_symbol_rate()
212 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); mt312_get_symbol_rate()
221 (((state->xtal * 8192) / (sym_rat_op + 8192)) * mt312_get_symbol_rate()
228 static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr) mt312_get_code_rate() argument
237 ret = mt312_readreg(state, FEC_STATUS, &fec_status); mt312_get_code_rate()
248 struct mt312_state *state = fe->demodulator_priv; mt312_initfe() local
253 ret = mt312_writereg(state, CONFIG, mt312_initfe()
254 (state->freq_mult == 6 ? 0x88 : 0x8c)); mt312_initfe()
262 ret = mt312_reset(state, 1); mt312_initfe()
272 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); mt312_initfe()
277 switch (state->id) { mt312_initfe()
280 ret = mt312_writereg(state, GPP_CTRL, 0x80); mt312_initfe()
287 ret = mt312_write(state, HW_CTRL, buf, 2); mt312_initfe()
292 ret = mt312_writereg(state, HW_CTRL, 0x00); mt312_initfe()
296 ret = mt312_writereg(state, MPEG_CTRL, 0x00); mt312_initfe()
304 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000); mt312_initfe()
307 buf[1] = mt312_div(state->xtal, 22000 * 4); mt312_initfe()
309 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); mt312_initfe()
313 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); mt312_initfe()
318 switch (state->id) { mt312_initfe()
327 ret = mt312_writereg(state, OP_CTRL, buf[0]); mt312_initfe()
335 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); mt312_initfe()
339 ret = mt312_writereg(state, CS_SW_LIM, 0x69); mt312_initfe()
349 struct mt312_state *state = fe->demodulator_priv; mt312_send_master_cmd() local
356 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); mt312_send_master_cmd()
360 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); mt312_send_master_cmd()
364 ret = mt312_writereg(state, DISEQC_MODE, mt312_send_master_cmd()
375 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); mt312_send_master_cmd()
385 struct mt312_state *state = fe->demodulator_priv; mt312_send_burst() local
394 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); mt312_send_burst()
398 ret = mt312_writereg(state, DISEQC_MODE, mt312_send_burst()
408 struct mt312_state *state = fe->demodulator_priv; mt312_set_tone() local
417 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); mt312_set_tone()
421 ret = mt312_writereg(state, DISEQC_MODE, mt312_set_tone()
431 struct mt312_state *state = fe->demodulator_priv; mt312_set_voltage() local
439 if (state->config->voltage_inverted) mt312_set_voltage()
442 return mt312_writereg(state, DISEQC_MODE, val); mt312_set_voltage()
447 struct mt312_state *state = fe->demodulator_priv; mt312_read_status() local
453 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); mt312_read_status()
476 struct mt312_state *state = fe->demodulator_priv; mt312_read_ber() local
480 ret = mt312_read(state, RS_BERCNT_H, buf, 3); mt312_read_ber()
492 struct mt312_state *state = fe->demodulator_priv; mt312_read_signal_strength() local
498 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); mt312_read_signal_strength()
514 struct mt312_state *state = fe->demodulator_priv; mt312_read_snr() local
518 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); mt312_read_snr()
529 struct mt312_state *state = fe->demodulator_priv; mt312_read_ucblocks() local
533 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); mt312_read_ucblocks()
545 struct mt312_state *state = fe->demodulator_priv; mt312_set_frontend() local
576 switch (state->id) { mt312_set_frontend()
582 ret = mt312_readreg(state, CONFIG, &config_val); mt312_set_frontend()
587 if (state->freq_mult == 6) { mt312_set_frontend()
589 state->freq_mult = 9; mt312_set_frontend()
595 if (state->freq_mult == 9) { mt312_set_frontend()
597 state->freq_mult = 6; mt312_set_frontend()
638 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); mt312_set_frontend()
642 mt312_reset(state, 0); mt312_set_frontend()
650 struct mt312_state *state = fe->demodulator_priv; mt312_get_frontend() local
653 ret = mt312_get_inversion(state, &p->inversion); mt312_get_frontend()
657 ret = mt312_get_symbol_rate(state, &p->symbol_rate); mt312_get_frontend()
661 ret = mt312_get_code_rate(state, &p->fec_inner); mt312_get_frontend()
670 struct mt312_state *state = fe->demodulator_priv; mt312_i2c_gate_ctrl() local
675 switch (state->id) { mt312_i2c_gate_ctrl()
677 ret = mt312_readreg(state, GPP_CTRL, &val); mt312_i2c_gate_ctrl()
691 ret = mt312_writereg(state, GPP_CTRL, val); mt312_i2c_gate_ctrl()
699 struct mt312_state *state = fe->demodulator_priv; mt312_sleep() local
704 ret = mt312_reset(state, 1); mt312_sleep()
708 if (state->id == ID_ZL10313) { mt312_sleep()
710 ret = mt312_writereg(state, GPP_CTRL, 0x00); mt312_sleep()
715 ret = mt312_writereg(state, HW_CTRL, 0x0d); mt312_sleep()
720 ret = mt312_readreg(state, CONFIG, &config); mt312_sleep()
725 ret = mt312_writereg(state, CONFIG, config & 0x7f); mt312_sleep()
743 struct mt312_state *state = fe->demodulator_priv; mt312_release() local
744 kfree(state); mt312_release()
790 struct mt312_state *state = NULL; mt312_attach() local
792 /* allocate memory for the internal state */ mt312_attach()
793 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL); mt312_attach()
794 if (state == NULL) mt312_attach()
797 /* setup the state */ mt312_attach()
798 state->config = config; mt312_attach()
799 state->i2c = i2c; mt312_attach()
802 if (mt312_readreg(state, ID, &state->id) < 0) mt312_attach()
806 memcpy(&state->frontend.ops, &mt312_ops, mt312_attach()
808 state->frontend.demodulator_priv = state; mt312_attach()
810 switch (state->id) { mt312_attach()
812 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S"); mt312_attach()
813 state->xtal = MT312_PLL_CLK; mt312_attach()
814 state->freq_mult = 9; mt312_attach()
817 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S"); mt312_attach()
818 state->xtal = MT312_PLL_CLK; mt312_attach()
819 state->freq_mult = 6; mt312_attach()
822 strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S"); mt312_attach()
823 state->xtal = MT312_PLL_CLK_10_111; mt312_attach()
824 state->freq_mult = 9; mt312_attach()
832 return &state->frontend; mt312_attach()
835 kfree(state); mt312_attach()
H A Dau8522_common.c42 int au8522_writereg(struct au8522_state *state, u16 reg, u8 data) au8522_writereg() argument
47 struct i2c_msg msg = { .addr = state->config->demod_address, au8522_writereg()
50 ret = i2c_transfer(state->i2c, &msg, 1); au8522_writereg()
60 u8 au8522_readreg(struct au8522_state *state, u16 reg) au8522_readreg() argument
67 { .addr = state->config->demod_address, .flags = 0, au8522_readreg()
69 { .addr = state->config->demod_address, .flags = I2C_M_RD, au8522_readreg()
72 ret = i2c_transfer(state->i2c, msg, 2); au8522_readreg()
83 struct au8522_state *state = fe->demodulator_priv; au8522_i2c_gate_ctrl() local
87 if (state->operational_mode == AU8522_ANALOG_MODE) { au8522_i2c_gate_ctrl()
96 return au8522_writereg(state, 0x106, 1); au8522_i2c_gate_ctrl()
98 return au8522_writereg(state, 0x106, 0); au8522_i2c_gate_ctrl()
104 struct au8522_state *state = fe->demodulator_priv; au8522_analog_i2c_gate_ctrl() local
109 return au8522_writereg(state, 0x106, 1); au8522_analog_i2c_gate_ctrl()
111 return au8522_writereg(state, 0x106, 0); au8522_analog_i2c_gate_ctrl()
116 to a default state. */ au8522_get_state()
117 int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c, au8522_get_state() argument
123 ret = hybrid_tuner_request_state(struct au8522_state, (*state), au8522_get_state()
132 void au8522_release_state(struct au8522_state *state) au8522_release_state() argument
135 if (state != NULL) au8522_release_state()
136 hybrid_tuner_release_state(state); au8522_release_state()
141 static int au8522_led_gpio_enable(struct au8522_state *state, int onoff) au8522_led_gpio_enable() argument
143 struct au8522_led_config *led_config = state->config->led_cfg; au8522_led_gpio_enable()
151 val = au8522_readreg(state, 0x4000 | au8522_led_gpio_enable()
162 return au8522_writereg(state, 0x8000 | au8522_led_gpio_enable()
171 int au8522_led_ctrl(struct au8522_state *state, int led) au8522_led_ctrl() argument
173 struct au8522_led_config *led_config = state->config->led_cfg; au8522_led_ctrl()
183 if (state->led_state) au8522_led_ctrl()
189 /* toggle LED if changing state */ au8522_led_ctrl()
190 if (state->led_state != led) { au8522_led_ctrl()
195 au8522_led_gpio_enable(state, 1); au8522_led_ctrl()
197 val = au8522_readreg(state, 0x4000 | au8522_led_ctrl()
204 /* set selected LED state */ au8522_led_ctrl()
211 ret = au8522_writereg(state, 0x8000 | au8522_led_ctrl()
216 state->led_state = led; au8522_led_ctrl()
219 au8522_led_gpio_enable(state, 0); au8522_led_ctrl()
228 struct au8522_state *state = fe->demodulator_priv; au8522_init() local
231 state->operational_mode = AU8522_DIGITAL_MODE; au8522_init()
233 /* Clear out any state associated with the digital side of the au8522_init()
236 state->current_frequency = 0; au8522_init()
238 au8522_writereg(state, 0xa4, 1 << 5); au8522_init()
248 struct au8522_state *state = fe->demodulator_priv; au8522_sleep() local
252 if (state->operational_mode == AU8522_ANALOG_MODE) { au8522_sleep()
261 au8522_led_ctrl(state, 0); au8522_sleep()
264 au8522_writereg(state, 0xa4, 1 << 5); au8522_sleep()
266 state->current_frequency = 0; au8522_sleep()
H A Dlgdt3305.c115 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val) lgdt3305_write_reg() argument
120 .addr = state->cfg->i2c_addr, .flags = 0, lgdt3305_write_reg()
126 ret = i2c_transfer(state->i2c_adap, &msg, 1); lgdt3305_write_reg()
139 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val) lgdt3305_read_reg() argument
144 { .addr = state->cfg->i2c_addr, lgdt3305_read_reg()
146 { .addr = state->cfg->i2c_addr, lgdt3305_read_reg()
152 ret = i2c_transfer(state->i2c_adap, msg, 2); lgdt3305_read_reg()
156 state->cfg->i2c_addr, reg, ret); lgdt3305_read_reg()
165 #define read_reg(state, reg) \
168 int ret = lgdt3305_read_reg(state, reg, &__val); \
174 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state, lgdt3305_set_reg_bit() argument
182 ret = lgdt3305_read_reg(state, reg, &val); lgdt3305_set_reg_bit()
189 ret = lgdt3305_write_reg(state, reg, val); lgdt3305_set_reg_bit()
199 static int lgdt3305_write_regs(struct lgdt3305_state *state, lgdt3305_write_regs() argument
207 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val); lgdt3305_write_regs()
216 static int lgdt3305_soft_reset(struct lgdt3305_state *state) lgdt3305_soft_reset() argument
222 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0); lgdt3305_soft_reset()
227 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1); lgdt3305_soft_reset()
232 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state, lgdt3305_mpeg_mode() argument
236 return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode); lgdt3305_mpeg_mode()
239 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state) lgdt3305_mpeg_mode_polarity() argument
243 enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge; lgdt3305_mpeg_mode_polarity()
244 enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode; lgdt3305_mpeg_mode_polarity()
245 enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity; lgdt3305_mpeg_mode_polarity()
249 ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val); lgdt3305_mpeg_mode_polarity()
262 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val); lgdt3305_mpeg_mode_polarity()
266 ret = lgdt3305_soft_reset(state); lgdt3305_mpeg_mode_polarity()
271 static int lgdt3305_set_modulation(struct lgdt3305_state *state, lgdt3305_set_modulation() argument
279 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode); lgdt3305_set_modulation()
298 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode); lgdt3305_set_modulation()
303 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state, lgdt3305_set_filter_extension() argument
321 return lgdt3305_set_reg_bit(state, 0x043f, 2, val); lgdt3305_set_filter_extension()
326 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state, lgdt3305_passband_digital_agc() argument
347 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8); lgdt3305_passband_digital_agc()
348 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff); lgdt3305_passband_digital_agc()
353 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state, lgdt3305_rfagc_loop() argument
370 if (state->cfg->demod_chip == LGDT3304) lgdt3305_rfagc_loop()
372 else /* (state->cfg->demod_chip == LGDT3305) */ lgdt3305_rfagc_loop()
379 if (state->cfg->rf_agc_loop) { lgdt3305_rfagc_loop()
383 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1, lgdt3305_rfagc_loop()
385 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2, lgdt3305_rfagc_loop()
388 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1, lgdt3305_rfagc_loop()
390 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2, lgdt3305_rfagc_loop()
396 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8); lgdt3305_rfagc_loop()
397 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff); lgdt3305_rfagc_loop()
403 static int lgdt3305_agc_setup(struct lgdt3305_state *state, lgdt3305_agc_setup() argument
425 switch (state->cfg->demod_chip) { lgdt3305_agc_setup()
427 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1); lgdt3305_agc_setup()
428 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen); lgdt3305_agc_setup()
431 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1); lgdt3305_agc_setup()
432 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen); lgdt3305_agc_setup()
438 return lgdt3305_rfagc_loop(state, p); lgdt3305_agc_setup()
441 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state, lgdt3305_set_agc_power_ref() argument
448 if (state->cfg->usref_8vsb) lgdt3305_set_agc_power_ref()
449 usref = state->cfg->usref_8vsb; lgdt3305_set_agc_power_ref()
452 if (state->cfg->usref_qam64) lgdt3305_set_agc_power_ref()
453 usref = state->cfg->usref_qam64; lgdt3305_set_agc_power_ref()
456 if (state->cfg->usref_qam256) lgdt3305_set_agc_power_ref()
457 usref = state->cfg->usref_qam256; lgdt3305_set_agc_power_ref()
466 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1); lgdt3305_set_agc_power_ref()
468 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1, lgdt3305_set_agc_power_ref()
470 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2, lgdt3305_set_agc_power_ref()
478 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state, lgdt3305_spectral_inversion() argument
488 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7, lgdt3305_spectral_inversion()
493 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL, lgdt3305_spectral_inversion()
502 static int lgdt3305_set_if(struct lgdt3305_state *state, lgdt3305_set_if() argument
511 if_freq_khz = state->cfg->vsb_if_khz; lgdt3305_set_if()
515 if_freq_khz = state->cfg->qam_if_khz; lgdt3305_set_if()
543 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1); lgdt3305_set_if()
544 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2); lgdt3305_set_if()
545 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3); lgdt3305_set_if()
546 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4); lgdt3305_set_if()
558 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_i2c_gate_ctrl() local
560 if (state->cfg->deny_i2c_rptr) lgdt3305_i2c_gate_ctrl()
565 return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5, lgdt3305_i2c_gate_ctrl()
571 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_sleep() local
576 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3); lgdt3305_sleep()
577 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4); lgdt3305_sleep()
591 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3); lgdt3305_sleep()
592 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4); lgdt3305_sleep()
599 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_init() local
663 switch (state->cfg->demod_chip) { lgdt3305_init()
665 ret = lgdt3305_write_regs(state, lgdt3304_init_data, lgdt3305_init()
669 ret = lgdt3305_write_regs(state, lgdt3305_init_data, lgdt3305_init()
678 ret = lgdt3305_soft_reset(state); lgdt3305_init()
686 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3304_set_parameters() local
697 state->current_frequency = p->frequency; lgdt3304_set_parameters()
700 ret = lgdt3305_set_modulation(state, p); lgdt3304_set_parameters()
704 ret = lgdt3305_passband_digital_agc(state, p); lgdt3304_set_parameters()
708 ret = lgdt3305_agc_setup(state, p); lgdt3304_set_parameters()
715 lgdt3305_write_reg(state, 0x030d, 0x00); lgdt3304_set_parameters()
716 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f); lgdt3304_set_parameters()
717 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c); lgdt3304_set_parameters()
718 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac); lgdt3304_set_parameters()
719 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba); lgdt3304_set_parameters()
723 lgdt3305_write_reg(state, 0x030d, 0x14); lgdt3304_set_parameters()
724 ret = lgdt3305_set_if(state, p); lgdt3304_set_parameters()
733 ret = lgdt3305_spectral_inversion(state, p, lgdt3304_set_parameters()
734 state->cfg->spectral_inversion lgdt3304_set_parameters()
739 state->current_modulation = p->modulation; lgdt3304_set_parameters()
741 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); lgdt3304_set_parameters()
746 ret = lgdt3305_mpeg_mode_polarity(state); lgdt3304_set_parameters()
754 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_set_parameters() local
765 state->current_frequency = p->frequency; lgdt3305_set_parameters()
768 ret = lgdt3305_set_modulation(state, p); lgdt3305_set_parameters()
772 ret = lgdt3305_passband_digital_agc(state, p); lgdt3305_set_parameters()
775 ret = lgdt3305_set_agc_power_ref(state, p); lgdt3305_set_parameters()
778 ret = lgdt3305_agc_setup(state, p); lgdt3305_set_parameters()
783 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f); lgdt3305_set_parameters()
786 ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1); lgdt3305_set_parameters()
790 ret = lgdt3305_set_if(state, p); lgdt3305_set_parameters()
793 ret = lgdt3305_spectral_inversion(state, p, lgdt3305_set_parameters()
794 state->cfg->spectral_inversion lgdt3305_set_parameters()
799 ret = lgdt3305_set_filter_extension(state, p); lgdt3305_set_parameters()
803 state->current_modulation = p->modulation; lgdt3305_set_parameters()
805 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode); lgdt3305_set_parameters()
810 ret = lgdt3305_mpeg_mode_polarity(state); lgdt3305_set_parameters()
818 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_get_frontend() local
822 p->modulation = state->current_modulation; lgdt3305_get_frontend()
823 p->frequency = state->current_frequency; lgdt3305_get_frontend()
829 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state, lgdt3305_read_cr_lock_status() argument
838 ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val); lgdt3305_read_cr_lock_status()
842 switch (state->current_modulation) { lgdt3305_read_cr_lock_status()
880 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state, lgdt3305_read_fec_lock_status() argument
888 switch (state->current_modulation) { lgdt3305_read_fec_lock_status()
891 ret = lgdt3305_read_reg(state, lgdt3305_read_fec_lock_status()
917 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_read_status() local
924 ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val); lgdt3305_read_status()
941 ret = lgdt3305_read_cr_lock_status(state, &cr_lock); lgdt3305_read_status()
954 switch (state->current_modulation) { lgdt3305_read_status()
958 if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock)) lgdt3305_read_status()
961 ret = lgdt3305_read_fec_lock_status(state, &fec_lock); lgdt3305_read_status()
999 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_read_snr() local
1003 switch (state->current_modulation) { lgdt3305_read_snr()
1008 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) | lgdt3305_read_snr()
1009 (read_reg(state, LGDT3305_PT_MSE_2) << 8) | lgdt3305_read_snr()
1010 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff); lgdt3305_read_snr()
1015 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) | lgdt3305_read_snr()
1016 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) | lgdt3305_read_snr()
1017 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff); lgdt3305_read_snr()
1023 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) | lgdt3305_read_snr()
1024 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff); lgdt3305_read_snr()
1026 c = (state->current_modulation == QAM_64) ? lgdt3305_read_snr()
1033 state->snr = calculate_snr(noise, c); lgdt3305_read_snr()
1035 *snr = (state->snr / ((1 << 24) / 10)); lgdt3305_read_snr()
1037 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16); lgdt3305_read_snr()
1052 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_read_signal_strength() local
1061 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ lgdt3305_read_signal_strength()
1063 if (state->snr >= 8960 * 0x10000) lgdt3305_read_signal_strength()
1066 *strength = state->snr / 8960; lgdt3305_read_signal_strength()
1081 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_read_ucblocks() local
1084 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) | lgdt3305_read_ucblocks()
1085 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff); lgdt3305_read_ucblocks()
1101 struct lgdt3305_state *state = fe->demodulator_priv; lgdt3305_release() local
1103 kfree(state); lgdt3305_release()
1112 struct lgdt3305_state *state = NULL; lgdt3305_attach() local
1120 state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL); lgdt3305_attach()
1121 if (state == NULL) lgdt3305_attach()
1124 state->cfg = config; lgdt3305_attach()
1125 state->i2c_adap = i2c_adap; lgdt3305_attach()
1129 memcpy(&state->frontend.ops, &lgdt3304_ops, lgdt3305_attach()
1133 memcpy(&state->frontend.ops, &lgdt3305_ops, lgdt3305_attach()
1139 state->frontend.demodulator_priv = state; lgdt3305_attach()
1142 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val); lgdt3305_attach()
1145 ret = lgdt3305_write_reg(state, 0x0808, 0x80); lgdt3305_attach()
1148 ret = lgdt3305_read_reg(state, 0x0808, &val); lgdt3305_attach()
1151 ret = lgdt3305_write_reg(state, 0x0808, 0x00); lgdt3305_attach()
1155 state->current_frequency = -1; lgdt3305_attach()
1156 state->current_modulation = -1; lgdt3305_attach()
1158 return &state->frontend; lgdt3305_attach()
1162 kfree(state); lgdt3305_attach()
H A Dstb6100.c133 static int stb6100_read_regs(struct stb6100_state *state, u8 regs[]) stb6100_read_regs() argument
137 .addr = state->config->tuner_address, stb6100_read_regs()
143 rc = i2c_transfer(state->i2c, &msg, 1); stb6100_read_regs()
146 state->config->tuner_address, rc); stb6100_read_regs()
153 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); stb6100_read_regs()
160 static int stb6100_read_reg(struct stb6100_state *state, u8 reg) stb6100_read_reg() argument
165 .addr = state->config->tuner_address + reg, stb6100_read_reg()
171 i2c_transfer(state->i2c, &msg, 1); stb6100_read_reg()
178 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); stb6100_read_reg()
185 static int stb6100_write_reg_range(struct stb6100_state *state, u8 buf[], int start, int len) stb6100_write_reg_range() argument
190 .addr = state->config->tuner_address, stb6100_write_reg_range()
214 dprintk(verbose, FE_DEBUG, 1, " Write @ 0x%02x: [%d:%d]", state->config->tuner_address, start, len); stb6100_write_reg_range()
218 rc = i2c_transfer(state->i2c, &msg, 1); stb6100_write_reg_range()
221 (unsigned int)state->config->tuner_address, start, len, rc); stb6100_write_reg_range()
227 static int stb6100_write_reg(struct stb6100_state *state, u8 reg, u8 data) stb6100_write_reg() argument
234 return stb6100_write_reg_range(state, &data, reg, 1); stb6100_write_reg()
241 struct stb6100_state *state = fe->tuner_priv; stb6100_get_status() local
243 rc = stb6100_read_reg(state, STB6100_LD); stb6100_get_status()
255 struct stb6100_state *state = fe->tuner_priv; stb6100_get_bandwidth() local
257 rc = stb6100_read_reg(state, STB6100_F); stb6100_get_bandwidth()
262 state->status.bandwidth = (f + 5) * 2000; /* x2 for ZIF */ stb6100_get_bandwidth()
264 *bandwidth = state->bandwidth = state->status.bandwidth * 1000; stb6100_get_bandwidth()
265 dprintk(verbose, FE_DEBUG, 1, "bandwidth = %u Hz", state->bandwidth); stb6100_get_bandwidth()
273 struct stb6100_state *state = fe->tuner_priv; stb6100_set_bandwidth() local
289 rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d | STB6100_FCCK_FCCK); stb6100_set_bandwidth()
292 rc = stb6100_write_reg(state, STB6100_F, 0xc0 | tmp); stb6100_set_bandwidth()
298 rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d); stb6100_set_bandwidth()
312 struct stb6100_state *state = fe->tuner_priv; stb6100_get_frequency() local
315 rc = stb6100_read_regs(state, regs); stb6100_get_frequency()
323 fvco = (nfrac * state->reference >> (9 - psd2)) + (nint * state->reference << psd2); stb6100_get_frequency()
324 *frequency = state->frequency = fvco >> (odiv + 1); stb6100_get_frequency()
328 state->frequency, odiv, psd2, state->reference, fvco, nint, nfrac); stb6100_get_frequency()
337 struct stb6100_state *state = fe->tuner_priv; stb6100_set_frequency() local
353 rc = stb6100_write_reg(state, STB6100_FCCK, 0x4d | STB6100_FCCK_FCCK); stb6100_set_frequency()
359 rc = stb6100_write_reg(state, STB6100_LPEN, regs[STB6100_LPEN]); stb6100_set_frequency()
384 rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO]); stb6100_set_frequency()
395 nint = fvco / (state->reference << psd2); stb6100_set_frequency()
397 nfrac = DIV_ROUND_CLOSEST((fvco - (nint * state->reference << psd2)) stb6100_set_frequency()
398 << (9 - psd2), state->reference); stb6100_set_frequency()
402 rc = stb6100_write_reg(state, STB6100_NI, regs[STB6100_NI]); stb6100_set_frequency()
408 rc = stb6100_write_reg(state, STB6100_NF_LSB, regs[STB6100_NF_LSB]); stb6100_set_frequency()
415 rc = stb6100_write_reg(state, STB6100_K, regs[STB6100_K]); stb6100_set_frequency()
430 rc = stb6100_write_reg(state, STB6100_G, regs[STB6100_G]); stb6100_set_frequency()
438 rc = stb6100_write_reg(state, STB6100_DLB, regs[STB6100_DLB]); stb6100_set_frequency()
445 (unsigned int)psd2, state->reference, stb6100_set_frequency()
450 rc = stb6100_write_reg(state, STB6100_TEST1, regs[STB6100_TEST1]); stb6100_set_frequency()
454 rc = stb6100_write_reg(state, STB6100_TEST3, regs[STB6100_TEST3]); stb6100_set_frequency()
460 rc = stb6100_write_reg(state, STB6100_LPEN, regs[STB6100_LPEN]); stb6100_set_frequency()
468 rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO]); stb6100_set_frequency()
476 rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO]); stb6100_set_frequency()
480 rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d); stb6100_set_frequency()
497 struct stb6100_state *state = fe->tuner_priv; stb6100_init() local
498 struct tuner_state *status = &state->status; stb6100_init()
505 state->bandwidth = status->bandwidth * 1000; /* Hz */ stb6100_init()
506 state->reference = status->refclock / 1000; /* kHz */ stb6100_init()
514 struct tuner_state *state) stb6100_get_state()
518 stb6100_get_frequency(fe, &state->frequency); stb6100_get_state()
525 stb6100_get_bandwidth(fe, &state->bandwidth); stb6100_get_state()
538 struct tuner_state *state) stb6100_set_state()
544 stb6100_set_frequency(fe, state->frequency); stb6100_set_state()
545 tstate->frequency = state->frequency; stb6100_set_state()
552 stb6100_set_bandwidth(fe, state->bandwidth); stb6100_set_state()
553 tstate->bandwidth = state->bandwidth; stb6100_set_state()
584 struct stb6100_state *state = NULL; stb6100_attach() local
586 state = kzalloc(sizeof (struct stb6100_state), GFP_KERNEL); stb6100_attach()
587 if (!state) stb6100_attach()
590 state->config = config; stb6100_attach()
591 state->i2c = i2c; stb6100_attach()
592 state->frontend = fe; stb6100_attach()
593 state->reference = config->refclock / 1000; /* kHz */ stb6100_attach()
594 fe->tuner_priv = state; stb6100_attach()
603 struct stb6100_state *state = fe->tuner_priv; stb6100_release() local
606 kfree(state); stb6100_release()
512 stb6100_get_state(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state) stb6100_get_state() argument
536 stb6100_set_state(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state) stb6100_set_state() argument
H A Das102_fe.c65 struct as102_state *state = fe->demodulator_priv; as102_fe_set_frontend() local
190 return state->ops->set_tune(state->priv, &tune_args); as102_fe_set_frontend()
195 struct as102_state *state = fe->demodulator_priv; as102_fe_get_frontend() local
201 ret = state->ops->get_tps(state->priv, &tps); as102_fe_get_frontend()
312 struct as102_state *state = fe->demodulator_priv; as102_fe_read_status() local
316 ret = state->ops->get_status(state->priv, &tstate); as102_fe_read_status()
320 state->signal_strength = tstate.signal_strength; as102_fe_read_status()
321 state->ber = tstate.BER; as102_fe_read_status()
344 memset(&state->demod_stats, 0, sizeof(state->demod_stats)); as102_fe_read_status()
348 ret = state->ops->get_stats(state->priv, &state->demod_stats); as102_fe_read_status()
350 memset(&state->demod_stats, 0, sizeof(state->demod_stats)); as102_fe_read_status()
364 struct as102_state *state = fe->demodulator_priv; as102_fe_read_snr() local
366 *snr = state->demod_stats.mer; as102_fe_read_snr()
373 struct as102_state *state = fe->demodulator_priv; as102_fe_read_ber() local
375 *ber = state->ber; as102_fe_read_ber()
383 struct as102_state *state = fe->demodulator_priv; as102_fe_read_signal_strength() local
385 *strength = (((0xffff * 400) * state->signal_strength + 41000) * 2); as102_fe_read_signal_strength()
392 struct as102_state *state = fe->demodulator_priv; as102_fe_read_ucblocks() local
394 if (state->demod_stats.has_started) as102_fe_read_ucblocks()
395 *ucblocks = state->demod_stats.bad_frame_count; as102_fe_read_ucblocks()
404 struct as102_state *state = fe->demodulator_priv; as102_fe_ts_bus_ctrl() local
406 return state->ops->stream_ctrl(state->priv, acquire, as102_fe_ts_bus_ctrl()
407 state->elna_cfg); as102_fe_ts_bus_ctrl()
412 struct as102_state *state = fe->demodulator_priv; as102_fe_release() local
414 kfree(state); as102_fe_release()
455 struct as102_state *state; as102_attach() local
458 state = kzalloc(sizeof(struct as102_state), GFP_KERNEL); as102_attach()
459 if (state == NULL) { as102_attach()
460 pr_err("%s: unable to allocate memory for state\n", __func__); as102_attach()
463 fe = &state->frontend; as102_attach()
464 fe->demodulator_priv = state; as102_attach()
465 state->ops = ops; as102_attach()
466 state->priv = priv; as102_attach()
467 state->elna_cfg = elna_cfg; as102_attach()
H A Dds3000.c240 static int ds3000_writereg(struct ds3000_state *state, int reg, int data) ds3000_writereg() argument
243 struct i2c_msg msg = { .addr = state->config->demod_address, ds3000_writereg()
249 err = i2c_transfer(state->i2c, &msg, 1); ds3000_writereg()
261 struct ds3000_state *state = fe->demodulator_priv; ds3000_i2c_gate_ctrl() local
264 ds3000_writereg(state, 0x03, 0x12); ds3000_i2c_gate_ctrl()
266 ds3000_writereg(state, 0x03, 0x02); ds3000_i2c_gate_ctrl()
272 static int ds3000_writeFW(struct ds3000_state *state, int reg, ds3000_writeFW() argument
287 msg.addr = state->config->demod_address; ds3000_writeFW()
297 ret = i2c_transfer(state->i2c, &msg, 1); ds3000_writeFW()
313 static int ds3000_readreg(struct ds3000_state *state, u8 reg) ds3000_readreg() argument
320 .addr = state->config->demod_address, ds3000_readreg()
325 .addr = state->config->demod_address, ds3000_readreg()
332 ret = i2c_transfer(state->i2c, msg, 2); ds3000_readreg()
349 struct ds3000_state *state = fe->demodulator_priv; ds3000_firmware_ondemand() local
355 ret = ds3000_readreg(state, 0xb2); ds3000_firmware_ondemand()
364 state->i2c->dev.parent); ds3000_firmware_ondemand()
387 struct ds3000_state *state = fe->demodulator_priv; ds3000_load_firmware() local
399 ds3000_writereg(state, 0xb2, 0x01); ds3000_load_firmware()
401 ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size); ds3000_load_firmware()
402 ds3000_writereg(state, 0xb2, 0x00); ds3000_load_firmware()
409 struct ds3000_state *state = fe->demodulator_priv; ds3000_set_voltage() local
414 data = ds3000_readreg(state, 0xa2); ds3000_set_voltage()
429 ds3000_writereg(state, 0xa2, data); ds3000_set_voltage()
436 struct ds3000_state *state = fe->demodulator_priv; ds3000_read_status() local
444 lock = ds3000_readreg(state, 0xd1); ds3000_read_status()
452 lock = ds3000_readreg(state, 0x0d); ds3000_read_status()
463 if (state->config->set_lock_led) ds3000_read_status()
464 state->config->set_lock_led(fe, *status == 0 ? 0 : 1); ds3000_read_status()
474 struct ds3000_state *state = fe->demodulator_priv; ds3000_read_ber() local
485 ds3000_writereg(state, 0xf9, 0x04); ds3000_read_ber()
487 data = ds3000_readreg(state, 0xf8); ds3000_read_ber()
493 *ber = (ds3000_readreg(state, 0xf7) << 8) | ds3000_read_ber()
494 ds3000_readreg(state, 0xf6); ds3000_read_ber()
499 ds3000_writereg(state, 0xf8, data); ds3000_read_ber()
500 ds3000_writereg(state, 0xf8, data); ds3000_read_ber()
508 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) | ds3000_read_ber()
509 (ds3000_readreg(state, 0xd6) << 8) | ds3000_read_ber()
510 ds3000_readreg(state, 0xd5); ds3000_read_ber()
512 ber_reading = (ds3000_readreg(state, 0xf8) << 8) | ds3000_read_ber()
513 ds3000_readreg(state, 0xf7); ds3000_read_ber()
516 ds3000_writereg(state, 0xd1, 0x01); ds3000_read_ber()
518 ds3000_writereg(state, 0xf9, 0x01); ds3000_read_ber()
520 ds3000_writereg(state, 0xf9, 0x00); ds3000_read_ber()
522 ds3000_writereg(state, 0xd1, 0x00); ds3000_read_ber()
548 struct ds3000_state *state = fe->demodulator_priv; ds3000_read_snr() local
576 snr_reading = ds3000_readreg(state, 0xff); ds3000_read_snr()
592 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) + ds3000_read_snr()
593 (ds3000_readreg(state, 0x8d) << 4); ds3000_read_snr()
594 dvbs2_signal_reading = ds3000_readreg(state, 0x8e); ds3000_read_snr()
634 struct ds3000_state *state = fe->demodulator_priv; ds3000_read_ucblocks() local
643 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) | ds3000_read_ucblocks()
644 ds3000_readreg(state, 0xf4); ds3000_read_ucblocks()
645 data = ds3000_readreg(state, 0xf8); ds3000_read_ucblocks()
648 ds3000_writereg(state, 0xf8, data); ds3000_read_ucblocks()
651 ds3000_writereg(state, 0xf8, data); ds3000_read_ucblocks()
654 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) | ds3000_read_ucblocks()
655 ds3000_readreg(state, 0xe1); ds3000_read_ucblocks()
656 if (_ucblocks > state->prevUCBS2) ds3000_read_ucblocks()
657 *ucblocks = _ucblocks - state->prevUCBS2; ds3000_read_ucblocks()
659 *ucblocks = state->prevUCBS2 - _ucblocks; ds3000_read_ucblocks()
660 state->prevUCBS2 = _ucblocks; ds3000_read_ucblocks()
671 struct ds3000_state *state = fe->demodulator_priv; ds3000_set_tone() local
680 data = ds3000_readreg(state, 0xa2); ds3000_set_tone()
682 ds3000_writereg(state, 0xa2, data); ds3000_set_tone()
687 data = ds3000_readreg(state, 0xa1); ds3000_set_tone()
690 ds3000_writereg(state, 0xa1, data); ds3000_set_tone()
694 data = ds3000_readreg(state, 0xa2); ds3000_set_tone()
696 ds3000_writereg(state, 0xa2, data); ds3000_set_tone()
706 struct ds3000_state *state = fe->demodulator_priv; ds3000_send_diseqc_msg() local
719 data = ds3000_readreg(state, 0xa2); ds3000_send_diseqc_msg()
721 ds3000_writereg(state, 0xa2, data); ds3000_send_diseqc_msg()
725 ds3000_writereg(state, 0xa3 + i, d->msg[i]); ds3000_send_diseqc_msg()
727 data = ds3000_readreg(state, 0xa1); ds3000_send_diseqc_msg()
734 ds3000_writereg(state, 0xa1, data); ds3000_send_diseqc_msg()
738 data = ds3000_readreg(state, 0xa1); ds3000_send_diseqc_msg()
746 data = ds3000_readreg(state, 0xa1); ds3000_send_diseqc_msg()
749 ds3000_writereg(state, 0xa1, data); ds3000_send_diseqc_msg()
751 data = ds3000_readreg(state, 0xa2); ds3000_send_diseqc_msg()
754 ds3000_writereg(state, 0xa2, data); ds3000_send_diseqc_msg()
759 data = ds3000_readreg(state, 0xa2); ds3000_send_diseqc_msg()
762 ds3000_writereg(state, 0xa2, data); ds3000_send_diseqc_msg()
771 struct ds3000_state *state = fe->demodulator_priv; ds3000_diseqc_send_burst() local
777 data = ds3000_readreg(state, 0xa2); ds3000_diseqc_send_burst()
779 ds3000_writereg(state, 0xa2, data); ds3000_diseqc_send_burst()
784 ds3000_writereg(state, 0xa1, 0x02); ds3000_diseqc_send_burst()
787 ds3000_writereg(state, 0xa1, 0x01); ds3000_diseqc_send_burst()
793 data = ds3000_readreg(state, 0xa1); ds3000_diseqc_send_burst()
800 data = ds3000_readreg(state, 0xa1); ds3000_diseqc_send_burst()
803 ds3000_writereg(state, 0xa1, data); ds3000_diseqc_send_burst()
805 data = ds3000_readreg(state, 0xa2); ds3000_diseqc_send_burst()
808 ds3000_writereg(state, 0xa2, data); ds3000_diseqc_send_burst()
813 data = ds3000_readreg(state, 0xa2); ds3000_diseqc_send_burst()
816 ds3000_writereg(state, 0xa2, data); ds3000_diseqc_send_burst()
823 struct ds3000_state *state = fe->demodulator_priv; ds3000_release() local
825 if (state->config->set_lock_led) ds3000_release()
826 state->config->set_lock_led(fe, 0); ds3000_release()
829 kfree(state); ds3000_release()
837 struct ds3000_state *state = NULL; ds3000_attach() local
842 /* allocate memory for the internal state */ ds3000_attach()
843 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL); ds3000_attach()
844 if (state == NULL) { ds3000_attach()
849 state->config = config; ds3000_attach()
850 state->i2c = i2c; ds3000_attach()
851 state->prevUCBS2 = 0; ds3000_attach()
854 ret = ds3000_readreg(state, 0x00) & 0xfe; ds3000_attach()
861 ds3000_readreg(state, 0x02), ds3000_attach()
862 ds3000_readreg(state, 0x01)); ds3000_attach()
864 memcpy(&state->frontend.ops, &ds3000_ops, ds3000_attach()
866 state->frontend.demodulator_priv = state; ds3000_attach()
873 ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF); ds3000_attach()
874 return &state->frontend; ds3000_attach()
877 kfree(state); ds3000_attach()
886 struct ds3000_state *state = fe->demodulator_priv; ds3000_set_carrier_offset() local
896 ds3000_writereg(state, 0x5f, tmp >> 8); ds3000_set_carrier_offset()
897 ds3000_writereg(state, 0x5e, tmp & 0xff); ds3000_set_carrier_offset()
904 struct ds3000_state *state = fe->demodulator_priv; ds3000_set_frontend() local
915 if (state->config->set_ts_params) ds3000_set_frontend()
916 state->config->set_ts_params(fe, 0); ds3000_set_frontend()
922 ds3000_writereg(state, 0x07, 0x80); ds3000_set_frontend()
923 ds3000_writereg(state, 0x07, 0x00); ds3000_set_frontend()
925 ds3000_writereg(state, 0xb2, 0x01); ds3000_set_frontend()
927 ds3000_writereg(state, 0x00, 0x01); ds3000_set_frontend()
933 ds3000_writereg(state, ds3000_set_frontend()
936 value = ds3000_readreg(state, 0xfe); ds3000_set_frontend()
939 ds3000_writereg(state, 0xfe, value); ds3000_set_frontend()
944 ds3000_writereg(state, ds3000_set_frontend()
948 ds3000_writereg(state, 0xfe, 0x54); ds3000_set_frontend()
950 ds3000_writereg(state, 0xfe, 0x98); ds3000_set_frontend()
957 ds3000_writereg(state, 0x29, 0x80); ds3000_set_frontend()
959 ds3000_writereg(state, 0x25, 0x8a); ds3000_set_frontend()
966 ds3000_writereg(state, 0xc3, 0x0d); ds3000_set_frontend()
967 ds3000_writereg(state, 0xc8, value); ds3000_set_frontend()
968 ds3000_writereg(state, 0xc4, 0x10); ds3000_set_frontend()
969 ds3000_writereg(state, 0xc7, 0x0e); ds3000_set_frontend()
974 ds3000_writereg(state, 0xc3, 0x07); ds3000_set_frontend()
975 ds3000_writereg(state, 0xc8, value); ds3000_set_frontend()
976 ds3000_writereg(state, 0xc4, 0x09); ds3000_set_frontend()
977 ds3000_writereg(state, 0xc7, 0x12); ds3000_set_frontend()
980 ds3000_writereg(state, 0xc3, value); ds3000_set_frontend()
981 ds3000_writereg(state, 0xc8, 0x0e); ds3000_set_frontend()
982 ds3000_writereg(state, 0xc4, 0x07); ds3000_set_frontend()
983 ds3000_writereg(state, 0xc7, 0x18); ds3000_set_frontend()
986 ds3000_writereg(state, 0xc3, value); ds3000_set_frontend()
987 ds3000_writereg(state, 0xc8, 0x0a); ds3000_set_frontend()
988 ds3000_writereg(state, 0xc4, 0x05); ds3000_set_frontend()
989 ds3000_writereg(state, 0xc7, 0x24); ds3000_set_frontend()
995 ds3000_writereg(state, 0x61, value & 0x00ff); ds3000_set_frontend()
996 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8); ds3000_set_frontend()
999 ds3000_writereg(state, 0x56, 0x00); ds3000_set_frontend()
1002 ds3000_writereg(state, 0x76, 0x00); ds3000_set_frontend()
1004 /*ds3000_writereg(state, 0x08, 0x03); ds3000_set_frontend()
1005 ds3000_writereg(state, 0xfd, 0x22); ds3000_set_frontend()
1006 ds3000_writereg(state, 0x08, 0x07); ds3000_set_frontend()
1007 ds3000_writereg(state, 0xfd, 0x42); ds3000_set_frontend()
1008 ds3000_writereg(state, 0x08, 0x07);*/ ds3000_set_frontend()
1010 if (state->config->ci_mode) { ds3000_set_frontend()
1014 ds3000_writereg(state, 0xfd, 0x80); ds3000_set_frontend()
1017 ds3000_writereg(state, 0xfd, 0x01); ds3000_set_frontend()
1023 ds3000_writereg(state, 0x00, 0x00); ds3000_set_frontend()
1025 ds3000_writereg(state, 0xb2, 0x00); ds3000_set_frontend()
1063 struct ds3000_state *state = fe->demodulator_priv; ds3000_get_algo() local
1065 if (state->config->set_lock_led) ds3000_get_algo()
1066 state->config->set_lock_led(fe, 0); ds3000_get_algo()
1079 struct ds3000_state *state = fe->demodulator_priv; ds3000_initfe() local
1084 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08)); ds3000_initfe()
H A Ds5h1411.c342 static int s5h1411_writereg(struct s5h1411_state *state, s5h1411_writereg() argument
350 ret = i2c_transfer(state->i2c, &msg, 1); s5h1411_writereg()
359 static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg) s5h1411_readreg() argument
369 ret = i2c_transfer(state->i2c, msg, 2); s5h1411_readreg()
379 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_softreset() local
383 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0); s5h1411_softreset()
384 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1); s5h1411_softreset()
390 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_set_if_freq() local
396 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5); s5h1411_set_if_freq()
397 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342); s5h1411_set_if_freq()
398 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9); s5h1411_set_if_freq()
401 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225); s5h1411_set_if_freq()
402 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96); s5h1411_set_if_freq()
403 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225); s5h1411_set_if_freq()
406 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc); s5h1411_set_if_freq()
407 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e); s5h1411_set_if_freq()
408 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd); s5h1411_set_if_freq()
416 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4); s5h1411_set_if_freq()
417 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655); s5h1411_set_if_freq()
418 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4); s5h1411_set_if_freq()
422 state->if_freq = KHz; s5h1411_set_if_freq()
429 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_set_mpeg_timing() local
434 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff; s5h1411_set_mpeg_timing()
454 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val); s5h1411_set_mpeg_timing()
459 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_set_spectralinversion() local
463 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000; s5h1411_set_spectralinversion()
468 state->inversion = inversion; s5h1411_set_spectralinversion()
469 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val); s5h1411_set_spectralinversion()
474 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_set_serialmode() local
478 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100; s5h1411_set_serialmode()
483 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val); s5h1411_set_serialmode()
489 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_enable_modulation() local
493 if ((state->first_tune == 0) && (m == state->current_modulation)) { s5h1411_enable_modulation()
502 s5h1411_set_if_freq(fe, state->config->vsb_if); s5h1411_enable_modulation()
503 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71); s5h1411_enable_modulation()
504 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00); s5h1411_enable_modulation()
505 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1); s5h1411_enable_modulation()
511 s5h1411_set_if_freq(fe, state->config->qam_if); s5h1411_enable_modulation()
512 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171); s5h1411_enable_modulation()
513 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001); s5h1411_enable_modulation()
514 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101); s5h1411_enable_modulation()
515 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0); s5h1411_enable_modulation()
522 state->current_modulation = m; s5h1411_enable_modulation()
523 state->first_tune = 0; s5h1411_enable_modulation()
531 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_i2c_gate_ctrl() local
536 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); s5h1411_i2c_gate_ctrl()
538 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0); s5h1411_i2c_gate_ctrl()
543 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_set_gpio() local
548 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02; s5h1411_set_gpio()
551 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, s5h1411_set_gpio()
554 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val); s5h1411_set_gpio()
559 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_set_powerstate() local
564 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1); s5h1411_set_powerstate()
566 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0); s5h1411_set_powerstate()
580 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_register_reset() local
584 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0); s5h1411_register_reset()
591 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_set_frontend() local
597 state->current_frequency = p->frequency; s5h1411_set_frontend()
619 to a default state. */ s5h1411_init()
622 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_init() local
631 s5h1411_writereg(state, init_tab[i].addr, s5h1411_init()
636 state->current_modulation = VSB_8; s5h1411_init()
641 state->first_tune = 1; s5h1411_init()
643 if (state->config->output_mode == S5H1411_SERIAL_OUTPUT) s5h1411_init()
650 s5h1411_set_spectralinversion(fe, state->config->inversion); s5h1411_init()
651 s5h1411_set_if_freq(fe, state->config->vsb_if); s5h1411_init()
652 s5h1411_set_gpio(fe, state->config->gpio); s5h1411_init()
653 s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing); s5h1411_init()
664 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_read_status() local
672 switch (state->current_modulation) { s5h1411_read_status()
675 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0); s5h1411_read_status()
683 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2); s5h1411_read_status()
689 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53); s5h1411_read_status()
698 switch (state->config->status_mode) { s5h1411_read_status()
772 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_read_snr() local
776 switch (state->current_modulation) { s5h1411_read_snr()
778 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); s5h1411_read_snr()
781 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); s5h1411_read_snr()
784 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, s5h1411_read_snr()
831 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_read_ucblocks() local
833 *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9); s5h1411_read_ucblocks()
846 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_get_frontend() local
848 p->frequency = state->current_frequency; s5h1411_get_frontend()
849 p->modulation = state->current_modulation; s5h1411_get_frontend()
863 struct s5h1411_state *state = fe->demodulator_priv; s5h1411_release() local
864 kfree(state); s5h1411_release()
872 struct s5h1411_state *state = NULL; s5h1411_attach() local
875 /* allocate memory for the internal state */ s5h1411_attach()
876 state = kzalloc(sizeof(struct s5h1411_state), GFP_KERNEL); s5h1411_attach()
877 if (state == NULL) s5h1411_attach()
880 /* setup the state */ s5h1411_attach()
881 state->config = config; s5h1411_attach()
882 state->i2c = i2c; s5h1411_attach()
883 state->current_modulation = VSB_8; s5h1411_attach()
884 state->inversion = state->config->inversion; s5h1411_attach()
887 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05); s5h1411_attach()
892 memcpy(&state->frontend.ops, &s5h1411_ops, s5h1411_attach()
895 state->frontend.demodulator_priv = state; s5h1411_attach()
897 if (s5h1411_init(&state->frontend) != 0) { s5h1411_attach()
904 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); s5h1411_attach()
907 s5h1411_set_powerstate(&state->frontend, 1); s5h1411_attach()
909 return &state->frontend; s5h1411_attach()
912 kfree(state); s5h1411_attach()
H A Ddvb_dummy_fe.c112 struct dvb_dummy_fe_state* state = fe->demodulator_priv; dvb_dummy_fe_release() local
113 kfree(state); dvb_dummy_fe_release()
120 struct dvb_dummy_fe_state* state = NULL; dvb_dummy_fe_ofdm_attach() local
122 /* allocate memory for the internal state */ dvb_dummy_fe_ofdm_attach()
123 state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL); dvb_dummy_fe_ofdm_attach()
124 if (!state) dvb_dummy_fe_ofdm_attach()
128 memcpy(&state->frontend.ops, &dvb_dummy_fe_ofdm_ops, sizeof(struct dvb_frontend_ops)); dvb_dummy_fe_ofdm_attach()
129 state->frontend.demodulator_priv = state; dvb_dummy_fe_ofdm_attach()
130 return &state->frontend; dvb_dummy_fe_ofdm_attach()
137 struct dvb_dummy_fe_state* state = NULL; dvb_dummy_fe_qpsk_attach() local
139 /* allocate memory for the internal state */ dvb_dummy_fe_qpsk_attach()
140 state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL); dvb_dummy_fe_qpsk_attach()
141 if (!state) dvb_dummy_fe_qpsk_attach()
145 memcpy(&state->frontend.ops, &dvb_dummy_fe_qpsk_ops, sizeof(struct dvb_frontend_ops)); dvb_dummy_fe_qpsk_attach()
146 state->frontend.demodulator_priv = state; dvb_dummy_fe_qpsk_attach()
147 return &state->frontend; dvb_dummy_fe_qpsk_attach()
154 struct dvb_dummy_fe_state* state = NULL; dvb_dummy_fe_qam_attach() local
156 /* allocate memory for the internal state */ dvb_dummy_fe_qam_attach()
157 state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL); dvb_dummy_fe_qam_attach()
158 if (!state) dvb_dummy_fe_qam_attach()
162 memcpy(&state->frontend.ops, &dvb_dummy_fe_qam_ops, sizeof(struct dvb_frontend_ops)); dvb_dummy_fe_qam_attach()
163 state->frontend.demodulator_priv = state; dvb_dummy_fe_qam_attach()
164 return &state->frontend; dvb_dummy_fe_qam_attach()
H A Dlgdt330x.c77 static int i2c_write_demod_bytes (struct lgdt330x_state* state, i2c_write_demod_bytes() argument
82 { .addr = state->config->demod_address, i2c_write_demod_bytes()
90 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { i2c_write_demod_bytes()
107 static int i2c_read_demod_bytes(struct lgdt330x_state *state, i2c_read_demod_bytes() argument
112 { .addr = state->config->demod_address, i2c_read_demod_bytes()
114 { .addr = state->config->demod_address, i2c_read_demod_bytes()
118 ret = i2c_transfer(state->i2c, msg, 2); i2c_read_demod_bytes()
120 printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __func__, state->config->demod_address, reg, ret); i2c_read_demod_bytes()
130 static int lgdt3302_SwReset(struct lgdt330x_state* state) lgdt3302_SwReset() argument
139 ret = i2c_write_demod_bytes(state, lgdt3302_SwReset()
145 ret = i2c_write_demod_bytes(state, lgdt3302_SwReset()
151 static int lgdt3303_SwReset(struct lgdt330x_state* state) lgdt3303_SwReset() argument
159 ret = i2c_write_demod_bytes(state, lgdt3303_SwReset()
165 ret = i2c_write_demod_bytes(state, lgdt3303_SwReset()
171 static int lgdt330x_SwReset(struct lgdt330x_state* state) lgdt330x_SwReset() argument
173 switch (state->config->demod_chip) { lgdt330x_SwReset()
175 return lgdt3302_SwReset(state); lgdt330x_SwReset()
177 return lgdt3303_SwReset(state); lgdt330x_SwReset()
241 struct lgdt330x_state* state = fe->demodulator_priv; lgdt330x_init() local
245 switch (state->config->demod_chip) { lgdt330x_init()
248 err = i2c_write_demod_bytes(state, lgdt3302_init_data, lgdt330x_init()
253 switch (state->config->clock_polarity_flip) { lgdt330x_init()
255 err = i2c_write_demod_bytes(state, lgdt330x_init()
260 err = i2c_write_demod_bytes(state, lgdt330x_init()
266 err = i2c_write_demod_bytes(state, lgdt3303_init_data, lgdt330x_init()
278 return lgdt330x_SwReset(state); lgdt330x_init()
289 struct lgdt330x_state* state = fe->demodulator_priv; lgdt330x_read_ucblocks() local
295 switch (state->config->demod_chip) { lgdt330x_read_ucblocks()
297 err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1, lgdt330x_read_ucblocks()
301 err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1, lgdt330x_read_ucblocks()
348 struct lgdt330x_state* state = fe->demodulator_priv; lgdt330x_set_parameters() local
354 if (state->current_modulation != p->modulation) { lgdt330x_set_parameters()
363 if (state->config->pll_rf_set) lgdt330x_set_parameters()
364 state->config->pll_rf_set(fe, 1); lgdt330x_set_parameters()
366 if (state->config->demod_chip == LGDT3303) { lgdt330x_set_parameters()
367 err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data, lgdt330x_set_parameters()
379 if (state->config->pll_rf_set) lgdt330x_set_parameters()
380 state->config->pll_rf_set(fe, 0); lgdt330x_set_parameters()
382 if (state->config->demod_chip == LGDT3303) { lgdt330x_set_parameters()
383 err = i2c_write_demod_bytes(state, lgdt3303_qam_data, lgdt330x_set_parameters()
395 if (state->config->pll_rf_set) lgdt330x_set_parameters()
396 state->config->pll_rf_set(fe, 0); lgdt330x_set_parameters()
398 if (state->config->demod_chip == LGDT3303) { lgdt330x_set_parameters()
399 err = i2c_write_demod_bytes(state, lgdt3303_qam_data, lgdt330x_set_parameters()
417 top_ctrl_cfg[1] |= state->config->serial_mpeg; lgdt330x_set_parameters()
420 i2c_write_demod_bytes(state, top_ctrl_cfg, lgdt330x_set_parameters()
422 if (state->config->set_ts_params) lgdt330x_set_parameters()
423 state->config->set_ts_params(fe, 0); lgdt330x_set_parameters()
424 state->current_modulation = p->modulation; lgdt330x_set_parameters()
436 state->current_frequency = p->frequency; lgdt330x_set_parameters()
438 lgdt330x_SwReset(state); lgdt330x_set_parameters()
445 struct lgdt330x_state *state = fe->demodulator_priv; lgdt330x_get_frontend() local
446 p->frequency = state->current_frequency; lgdt330x_get_frontend()
452 struct lgdt330x_state* state = fe->demodulator_priv; lgdt3302_read_status() local
458 i2c_read_demod_bytes(state, AGC_STATUS, buf, 1); lgdt3302_read_status()
472 i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf)); lgdt3302_read_status()
488 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); lgdt3302_read_status()
490 switch (state->current_modulation) { lgdt3302_read_status()
510 struct lgdt330x_state* state = fe->demodulator_priv; lgdt3303_read_status() local
517 err = i2c_read_demod_bytes(state, 0x58, buf, 1); lgdt3303_read_status()
529 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); lgdt3303_read_status()
531 switch (state->current_modulation) { lgdt3303_read_status()
539 i2c_read_demod_bytes(state, 0x8a, buf, 1); lgdt3303_read_status()
552 i2c_read_demod_bytes(state, 0x38, buf, 1); lgdt3303_read_status()
606 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; lgdt3302_read_snr() local
611 switch(state->current_modulation) { lgdt3302_read_snr()
613 i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5); lgdt3302_read_snr()
628 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2); lgdt3302_read_snr()
630 c = state->current_modulation == QAM_64 ? 97939837 : 98026066; lgdt3302_read_snr()
639 state->snr = calculate_snr(noise, c); lgdt3302_read_snr()
640 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */ lgdt3302_read_snr()
643 state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16); lgdt3302_read_snr()
650 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; lgdt3303_read_snr() local
655 switch(state->current_modulation) { lgdt3303_read_snr()
657 i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5); lgdt3303_read_snr()
672 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2); lgdt3303_read_snr()
674 c = state->current_modulation == QAM_64 ? 97939837 : 98026066; lgdt3303_read_snr()
683 state->snr = calculate_snr(noise, c); lgdt3303_read_snr()
684 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */ lgdt3303_read_snr()
687 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16); lgdt3303_read_snr()
697 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; lgdt330x_read_signal_strength() local
704 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ lgdt330x_read_signal_strength()
706 if (state->snr >= 8960 * 0x10000) lgdt330x_read_signal_strength()
709 *strength = state->snr / 8960; lgdt330x_read_signal_strength()
725 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; lgdt330x_release() local
726 kfree(state); lgdt330x_release()
735 struct lgdt330x_state* state = NULL; lgdt330x_attach() local
738 /* Allocate memory for the internal state */ lgdt330x_attach()
739 state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL); lgdt330x_attach()
740 if (state == NULL) lgdt330x_attach()
743 /* Setup the state */ lgdt330x_attach()
744 state->config = config; lgdt330x_attach()
745 state->i2c = i2c; lgdt330x_attach()
750 memcpy(&state->frontend.ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops)); lgdt330x_attach()
753 memcpy(&state->frontend.ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops)); lgdt330x_attach()
758 state->frontend.demodulator_priv = state; lgdt330x_attach()
761 if (i2c_read_demod_bytes(state, 2, buf, 1)) lgdt330x_attach()
764 state->current_frequency = -1; lgdt330x_attach()
765 state->current_modulation = -1; lgdt330x_attach()
767 return &state->frontend; lgdt330x_attach()
770 kfree(state); lgdt330x_attach()
H A Dzl10353.c55 struct zl10353_state *state = fe->demodulator_priv; zl10353_single_write() local
57 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, zl10353_single_write()
59 int err = i2c_transfer(state->i2c, &msg, 1); zl10353_single_write()
77 static int zl10353_read_register(struct zl10353_state *state, u8 reg) zl10353_read_register() argument
82 struct i2c_msg msg[2] = { { .addr = state->config.demod_address, zl10353_read_register()
85 { .addr = state->config.demod_address, zl10353_read_register()
89 ret = i2c_transfer(state->i2c, msg, 2); zl10353_read_register()
102 struct zl10353_state *state = fe->demodulator_priv; zl10353_dump_regs() local
113 ret = zl10353_read_register(state, reg); zl10353_dump_regs()
128 struct zl10353_state *state = fe->demodulator_priv; zl10353_calc_nominal_rate() local
133 if (state->config.adc_clock) zl10353_calc_nominal_rate()
134 adc_clock = state->config.adc_clock; zl10353_calc_nominal_rate()
148 struct zl10353_state *state = fe->demodulator_priv; zl10353_calc_input_freq() local
154 if (state->config.adc_clock) zl10353_calc_input_freq()
155 adc_clock = state->config.adc_clock; zl10353_calc_input_freq()
156 if (state->config.if2) zl10353_calc_input_freq()
157 if2 = state->config.if2; zl10353_calc_input_freq()
185 struct zl10353_state *state = fe->demodulator_priv; zl10353_set_parameters() local
190 state->frequency = c->frequency; zl10353_set_parameters()
230 state->bandwidth = c->bandwidth_hz; zl10353_set_parameters()
351 if (state->config.no_tuner) { zl10353_set_parameters()
366 if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL) zl10353_set_parameters()
377 struct zl10353_state *state = fe->demodulator_priv; zl10353_get_parameters() local
391 s6 = zl10353_read_register(state, STATUS_6); zl10353_get_parameters()
392 s9 = zl10353_read_register(state, STATUS_9); zl10353_get_parameters()
398 tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 | zl10353_get_parameters()
399 zl10353_read_register(state, TPS_RECEIVED_0); zl10353_get_parameters()
458 c->frequency = state->frequency; zl10353_get_parameters()
459 c->bandwidth_hz = state->bandwidth; zl10353_get_parameters()
467 struct zl10353_state *state = fe->demodulator_priv; zl10353_read_status() local
470 if ((s6 = zl10353_read_register(state, STATUS_6)) < 0) zl10353_read_status()
472 if ((s7 = zl10353_read_register(state, STATUS_7)) < 0) zl10353_read_status()
474 if ((s8 = zl10353_read_register(state, STATUS_8)) < 0) zl10353_read_status()
498 struct zl10353_state *state = fe->demodulator_priv; zl10353_read_ber() local
500 *ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 | zl10353_read_ber()
501 zl10353_read_register(state, RS_ERR_CNT_1) << 8 | zl10353_read_ber()
502 zl10353_read_register(state, RS_ERR_CNT_0); zl10353_read_ber()
509 struct zl10353_state *state = fe->demodulator_priv; zl10353_read_signal_strength() local
511 u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 | zl10353_read_signal_strength()
512 zl10353_read_register(state, AGC_GAIN_0) << 2 | 3; zl10353_read_signal_strength()
521 struct zl10353_state *state = fe->demodulator_priv; zl10353_read_snr() local
527 _snr = zl10353_read_register(state, SNR); zl10353_read_snr()
535 struct zl10353_state *state = fe->demodulator_priv; zl10353_read_ucblocks() local
538 ubl = zl10353_read_register(state, RS_UBC_1) << 8 | zl10353_read_ucblocks()
539 zl10353_read_register(state, RS_UBC_0); zl10353_read_ucblocks()
541 state->ucblocks += ubl; zl10353_read_ucblocks()
542 *ucblocks = state->ucblocks; zl10353_read_ucblocks()
560 struct zl10353_state *state = fe->demodulator_priv; zl10353_init() local
565 if (state->config.parallel_ts) zl10353_init()
567 if (state->config.clock_ctl_1) zl10353_init()
568 zl10353_reset_attach[3] = state->config.clock_ctl_1; zl10353_init()
569 if (state->config.pll_0) zl10353_init()
570 zl10353_reset_attach[4] = state->config.pll_0; zl10353_init()
573 if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] || zl10353_init()
574 zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) { zl10353_init()
586 struct zl10353_state *state = fe->demodulator_priv; zl10353_i2c_gate_ctrl() local
589 if (state->config.disable_i2c_gate_ctrl) { zl10353_i2c_gate_ctrl()
603 struct zl10353_state *state = fe->demodulator_priv; zl10353_release() local
604 kfree(state); zl10353_release()
612 struct zl10353_state *state = NULL; zl10353_attach() local
615 /* allocate memory for the internal state */ zl10353_attach()
616 state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL); zl10353_attach()
617 if (state == NULL) zl10353_attach()
620 /* setup the state */ zl10353_attach()
621 state->i2c = i2c; zl10353_attach()
622 memcpy(&state->config, config, sizeof(struct zl10353_config)); zl10353_attach()
625 id = zl10353_read_register(state, CHIP_ID); zl10353_attach()
630 memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops)); zl10353_attach()
631 state->frontend.demodulator_priv = state; zl10353_attach()
633 return &state->frontend; zl10353_attach()
635 kfree(state); zl10353_attach()
H A Ds921.c206 static int s921_i2c_writereg(struct s921_state *state, s921_i2c_writereg() argument
215 rc = i2c_transfer(state->i2c, &msg, 1); s921_i2c_writereg()
225 static int s921_i2c_writeregdata(struct s921_state *state, u8 i2c_addr, s921_i2c_writeregdata() argument
231 rc = s921_i2c_writereg(state, i2c_addr, rd[i].reg, rd[i].data); s921_i2c_writeregdata()
238 static int s921_i2c_readreg(struct s921_state *state, u8 i2c_addr, u8 reg) s921_i2c_readreg() argument
247 rc = i2c_transfer(state->i2c, msg, 2); s921_i2c_readreg()
257 #define s921_readreg(state, reg) \
258 s921_i2c_readreg(state, state->config->demod_address, reg)
259 #define s921_writereg(state, reg, val) \
260 s921_i2c_writereg(state, state->config->demod_address, reg, val)
261 #define s921_writeregdata(state, regdata) \
262 s921_i2c_writeregdata(state, state->config->demod_address, \
268 struct s921_state *state = fe->demodulator_priv; s921_pll_tune() local
292 rc = s921_writeregdata(state, s921_prefreq); s921_pll_tune()
296 rc = s921_writereg(state, 0xf2, (f_offset >> 8) & 0xff); s921_pll_tune()
300 rc = s921_writereg(state, 0xf3, f_offset & 0xff); s921_pll_tune()
304 rc = s921_writereg(state, 0xf4, f_switch); s921_pll_tune()
308 rc = s921_writeregdata(state, s921_postfreq); s921_pll_tune()
313 rc = s921_readreg(state, 0x80); s921_pll_tune()
316 rc = s921_writereg(state, 0x01, 0x40); s921_pll_tune()
320 rc = s921_readreg(state, 0x01); s921_pll_tune()
323 rc = s921_readreg(state, 0x80); s921_pll_tune()
326 rc = s921_readreg(state, 0x80); s921_pll_tune()
329 rc = s921_readreg(state, 0x32); s921_pll_tune()
339 struct s921_state *state = fe->demodulator_priv; s921_initfe() local
344 rc = s921_writeregdata(state, s921_init); s921_initfe()
353 struct s921_state *state = fe->demodulator_priv; s921_read_status() local
358 rc = s921_readreg(state, 0x81); s921_read_status()
364 rc = s921_readreg(state, 0x82); s921_read_status()
393 struct s921_state *state = fe->demodulator_priv; s921_read_signal_strength() local
405 rc = s921_readreg(state, 0x01); s921_read_signal_strength()
408 rc = s921_readreg(state, 0x80); s921_read_signal_strength()
411 rc = s921_readreg(state, 0x32); s921_read_signal_strength()
420 struct s921_state *state = fe->demodulator_priv; s921_set_frontend() local
431 state->currentfreq = p->frequency; s921_set_frontend()
439 struct s921_state *state = fe->demodulator_priv; s921_get_frontend() local
442 p->frequency = state->currentfreq; s921_get_frontend()
474 struct s921_state *state = fe->demodulator_priv; s921_release() local
477 kfree(state); s921_release()
485 /* allocate memory for the internal state */ s921_attach()
486 struct s921_state *state = s921_attach() local
490 if (!state) { s921_attach()
495 /* setup the state */ s921_attach()
496 state->config = config; s921_attach()
497 state->i2c = i2c; s921_attach()
500 memcpy(&state->frontend.ops, &s921_ops, s921_attach()
502 state->frontend.demodulator_priv = state; s921_attach()
504 return &state->frontend; s921_attach()
H A Dmb86a20s.c228 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, mb86a20s_i2c_writereg() argument
237 rc = i2c_transfer(state->i2c, &msg, 1); mb86a20s_i2c_writereg()
239 dev_err(&state->i2c->dev, mb86a20s_i2c_writereg()
248 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, mb86a20s_i2c_writeregdata() argument
254 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, mb86a20s_i2c_writeregdata()
262 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, mb86a20s_i2c_readreg() argument
272 rc = i2c_transfer(state->i2c, msg, 2); mb86a20s_i2c_readreg()
275 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", mb86a20s_i2c_readreg()
283 #define mb86a20s_readreg(state, reg) \
284 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
285 #define mb86a20s_writereg(state, reg, val) \
286 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
287 #define mb86a20s_writeregdata(state, regdata) \
288 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
299 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_read_status() local
304 val = mb86a20s_readreg(state, 0x0a) & 0xf; mb86a20s_read_status()
323 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", mb86a20s_read_status()
331 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_read_signal_strength() local
336 if (state->get_strength_time && mb86a20s_read_signal_strength()
337 (!time_after(jiffies, state->get_strength_time))) mb86a20s_read_signal_strength()
348 rc = mb86a20s_writereg(state, 0x04, 0x1f); mb86a20s_read_signal_strength()
351 rc = mb86a20s_writereg(state, 0x05, rf >> 8); mb86a20s_read_signal_strength()
354 rc = mb86a20s_writereg(state, 0x04, 0x20); mb86a20s_read_signal_strength()
357 rc = mb86a20s_writereg(state, 0x05, rf); mb86a20s_read_signal_strength()
361 rc = mb86a20s_readreg(state, 0x02); mb86a20s_read_signal_strength()
376 dev_dbg(&state->i2c->dev, mb86a20s_read_signal_strength()
380 state->get_strength_time = jiffies + mb86a20s_read_signal_strength()
387 static int mb86a20s_get_modulation(struct mb86a20s_state *state, mb86a20s_get_modulation() argument
399 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); mb86a20s_get_modulation()
402 rc = mb86a20s_readreg(state, 0x6e); mb86a20s_get_modulation()
419 static int mb86a20s_get_fec(struct mb86a20s_state *state, mb86a20s_get_fec() argument
432 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); mb86a20s_get_fec()
435 rc = mb86a20s_readreg(state, 0x6e); mb86a20s_get_fec()
454 static int mb86a20s_get_interleaving(struct mb86a20s_state *state, mb86a20s_get_interleaving() argument
470 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); mb86a20s_get_interleaving()
473 rc = mb86a20s_readreg(state, 0x6e); mb86a20s_get_interleaving()
480 static int mb86a20s_get_segment_count(struct mb86a20s_state *state, mb86a20s_get_segment_count() argument
490 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_get_segment_count()
495 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); mb86a20s_get_segment_count()
498 rc = mb86a20s_readreg(state, 0x6e); mb86a20s_get_segment_count()
503 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); mb86a20s_get_segment_count()
510 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_reset_frontend_cache() local
513 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_reset_frontend_cache()
558 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_layer_bitrate() local
626 dev_dbg(&state->i2c->dev, mb86a20s_layer_bitrate()
632 state->estimated_rate[layer] = rate; mb86a20s_layer_bitrate()
637 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_get_frontend() local
641 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_get_frontend()
647 rc = mb86a20s_writereg(state, 0x6d, 0x85); mb86a20s_get_frontend()
650 rc = mb86a20s_readreg(state, 0x6e); mb86a20s_get_frontend()
658 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", mb86a20s_get_frontend()
661 rc = mb86a20s_get_segment_count(state, layer); mb86a20s_get_frontend()
668 state->estimated_rate[layer] = 0; mb86a20s_get_frontend()
672 rc = mb86a20s_get_modulation(state, layer); mb86a20s_get_frontend()
675 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", mb86a20s_get_frontend()
678 rc = mb86a20s_get_fec(state, layer); mb86a20s_get_frontend()
681 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", mb86a20s_get_frontend()
684 rc = mb86a20s_get_interleaving(state, layer); mb86a20s_get_frontend()
687 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", mb86a20s_get_frontend()
696 rc = mb86a20s_writereg(state, 0x6d, 0x84); mb86a20s_get_frontend()
707 rc = mb86a20s_readreg(state, 0x07); mb86a20s_get_frontend()
749 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_reset_counters() local
753 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_reset_counters()
756 if (state->last_frequency != c->frequency) { mb86a20s_reset_counters()
765 state->last_frequency = c->frequency; mb86a20s_reset_counters()
771 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); mb86a20s_reset_counters()
776 rc = mb86a20s_readreg(state, 0x45); mb86a20s_reset_counters()
780 rc = mb86a20s_writereg(state, 0x45, val | 0x10); mb86a20s_reset_counters()
783 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); mb86a20s_reset_counters()
788 rc = mb86a20s_writereg(state, 0x50, 0x50); mb86a20s_reset_counters()
791 rc = mb86a20s_readreg(state, 0x51); mb86a20s_reset_counters()
795 rc = mb86a20s_writereg(state, 0x51, val | 0x01); mb86a20s_reset_counters()
798 rc = mb86a20s_writereg(state, 0x51, val & 0x06); mb86a20s_reset_counters()
804 dev_err(&state->i2c->dev, mb86a20s_reset_counters()
815 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_get_pre_ber() local
818 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_get_pre_ber()
824 rc = mb86a20s_readreg(state, 0x54); mb86a20s_get_pre_ber()
830 dev_dbg(&state->i2c->dev, mb86a20s_get_pre_ber()
837 rc = mb86a20s_readreg(state, 0x55 + layer * 3); mb86a20s_get_pre_ber()
841 rc = mb86a20s_readreg(state, 0x56 + layer * 3); mb86a20s_get_pre_ber()
845 rc = mb86a20s_readreg(state, 0x57 + layer * 3); mb86a20s_get_pre_ber()
850 dev_dbg(&state->i2c->dev, mb86a20s_get_pre_ber()
855 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); mb86a20s_get_pre_ber()
858 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_pre_ber()
862 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); mb86a20s_get_pre_ber()
865 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_pre_ber()
869 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); mb86a20s_get_pre_ber()
872 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_pre_ber()
877 dev_dbg(&state->i2c->dev, mb86a20s_get_pre_ber()
889 if (state->estimated_rate[layer] mb86a20s_get_pre_ber()
890 && state->estimated_rate[layer] != *count) { mb86a20s_get_pre_ber()
891 dev_dbg(&state->i2c->dev, mb86a20s_get_pre_ber()
893 __func__, 'A' + layer, state->estimated_rate[layer]); mb86a20s_get_pre_ber()
896 rc = mb86a20s_writereg(state, 0x52, 0x00); mb86a20s_get_pre_ber()
899 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); mb86a20s_get_pre_ber()
902 rc = mb86a20s_writereg(state, 0x51, mb86a20s_get_pre_ber()
903 state->estimated_rate[layer] >> 16); mb86a20s_get_pre_ber()
906 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); mb86a20s_get_pre_ber()
909 rc = mb86a20s_writereg(state, 0x51, mb86a20s_get_pre_ber()
910 state->estimated_rate[layer] >> 8); mb86a20s_get_pre_ber()
913 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); mb86a20s_get_pre_ber()
916 rc = mb86a20s_writereg(state, 0x51, mb86a20s_get_pre_ber()
917 state->estimated_rate[layer]); mb86a20s_get_pre_ber()
922 rc = mb86a20s_writereg(state, 0x52, 0x01); mb86a20s_get_pre_ber()
925 rc = mb86a20s_writereg(state, 0x53, 0x00); mb86a20s_get_pre_ber()
928 rc = mb86a20s_writereg(state, 0x53, 0x07); mb86a20s_get_pre_ber()
931 rc = mb86a20s_readreg(state, 0x53); mb86a20s_get_pre_ber()
935 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); mb86a20s_get_pre_ber()
938 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); mb86a20s_get_pre_ber()
948 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_get_post_ber() local
952 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_get_post_ber()
958 rc = mb86a20s_readreg(state, 0x60); mb86a20s_get_post_ber()
964 dev_dbg(&state->i2c->dev, mb86a20s_get_post_ber()
971 rc = mb86a20s_readreg(state, 0x64 + layer * 3); mb86a20s_get_post_ber()
975 rc = mb86a20s_readreg(state, 0x65 + layer * 3); mb86a20s_get_post_ber()
979 rc = mb86a20s_readreg(state, 0x66 + layer * 3); mb86a20s_get_post_ber()
984 dev_dbg(&state->i2c->dev, mb86a20s_get_post_ber()
989 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); mb86a20s_get_post_ber()
992 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_post_ber()
996 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); mb86a20s_get_post_ber()
999 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_post_ber()
1005 dev_dbg(&state->i2c->dev, mb86a20s_get_post_ber()
1016 if (!state->estimated_rate[layer]) mb86a20s_get_post_ber()
1019 collect_rate = state->estimated_rate[layer] / 204 / 8; mb86a20s_get_post_ber()
1025 dev_dbg(&state->i2c->dev, mb86a20s_get_post_ber()
1030 rc = mb86a20s_writereg(state, 0x5e, 0x00); mb86a20s_get_post_ber()
1033 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); mb86a20s_get_post_ber()
1036 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); mb86a20s_get_post_ber()
1039 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); mb86a20s_get_post_ber()
1042 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); mb86a20s_get_post_ber()
1047 rc = mb86a20s_writereg(state, 0x5e, 0x07); mb86a20s_get_post_ber()
1050 rc = mb86a20s_writereg(state, 0x5f, 0x00); mb86a20s_get_post_ber()
1053 rc = mb86a20s_writereg(state, 0x5f, 0x07); mb86a20s_get_post_ber()
1060 rc = mb86a20s_readreg(state, 0x5f); mb86a20s_get_post_ber()
1064 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); mb86a20s_get_post_ber()
1067 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); mb86a20s_get_post_ber()
1076 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_get_blk_error() local
1079 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_get_blk_error()
1085 rc = mb86a20s_writereg(state, 0x50, 0xb8); mb86a20s_get_blk_error()
1088 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error()
1095 dev_dbg(&state->i2c->dev, mb86a20s_get_blk_error()
1102 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); mb86a20s_get_blk_error()
1105 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error()
1109 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); mb86a20s_get_blk_error()
1112 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error()
1116 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n", mb86a20s_get_blk_error()
1120 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); mb86a20s_get_blk_error()
1123 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error()
1127 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); mb86a20s_get_blk_error()
1130 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error()
1135 dev_dbg(&state->i2c->dev, mb86a20s_get_blk_error()
1146 if (!state->estimated_rate[layer]) mb86a20s_get_blk_error()
1149 collect_rate = state->estimated_rate[layer] / 204 / 8; mb86a20s_get_blk_error()
1156 dev_dbg(&state->i2c->dev, mb86a20s_get_blk_error()
1161 rc = mb86a20s_writereg(state, 0x50, 0xb0); mb86a20s_get_blk_error()
1164 rc = mb86a20s_writereg(state, 0x51, 0x00); mb86a20s_get_blk_error()
1169 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); mb86a20s_get_blk_error()
1172 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); mb86a20s_get_blk_error()
1175 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); mb86a20s_get_blk_error()
1178 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); mb86a20s_get_blk_error()
1183 rc = mb86a20s_writereg(state, 0x50, 0xb0); mb86a20s_get_blk_error()
1186 rc = mb86a20s_writereg(state, 0x51, 0x07); mb86a20s_get_blk_error()
1191 rc = mb86a20s_writereg(state, 0x50, 0xb1); mb86a20s_get_blk_error()
1194 rc = mb86a20s_writereg(state, 0x51, 0x07); mb86a20s_get_blk_error()
1197 rc = mb86a20s_writereg(state, 0x51, 0x00); mb86a20s_get_blk_error()
1204 rc = mb86a20s_writereg(state, 0x50, 0xb1); mb86a20s_get_blk_error()
1207 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error()
1211 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); mb86a20s_get_blk_error()
1214 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); mb86a20s_get_blk_error()
1396 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_get_main_CNR() local
1402 rc = mb86a20s_readreg(state, 0x45); mb86a20s_get_main_CNR()
1407 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n", mb86a20s_get_main_CNR()
1413 rc = mb86a20s_readreg(state, 0x46); mb86a20s_get_main_CNR()
1418 rc = mb86a20s_readreg(state, 0x46); mb86a20s_get_main_CNR()
1429 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", mb86a20s_get_main_CNR()
1433 rc = mb86a20s_writereg(state, 0x45, val | 0x10); mb86a20s_get_main_CNR()
1436 rc = mb86a20s_writereg(state, 0x45, val & 0x6f); mb86a20s_get_main_CNR()
1443 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_get_blk_error_layer_CNR() local
1450 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_get_blk_error_layer_CNR()
1453 rc = mb86a20s_writereg(state, 0x50, 0x5b); mb86a20s_get_blk_error_layer_CNR()
1456 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error_layer_CNR()
1462 dev_dbg(&state->i2c->dev, mb86a20s_get_blk_error_layer_CNR()
1474 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3); mb86a20s_get_blk_error_layer_CNR()
1477 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error_layer_CNR()
1481 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3); mb86a20s_get_blk_error_layer_CNR()
1484 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error_layer_CNR()
1488 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3); mb86a20s_get_blk_error_layer_CNR()
1491 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error_layer_CNR()
1517 dev_dbg(&state->i2c->dev, mb86a20s_get_blk_error_layer_CNR()
1525 rc = mb86a20s_writereg(state, 0x50, 0x50); mb86a20s_get_blk_error_layer_CNR()
1528 rc = mb86a20s_readreg(state, 0x51); mb86a20s_get_blk_error_layer_CNR()
1533 rc = mb86a20s_writereg(state, 0x51, val | 0x01); mb86a20s_get_blk_error_layer_CNR()
1536 rc = mb86a20s_writereg(state, 0x51, val & 0x06); mb86a20s_get_blk_error_layer_CNR()
1545 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_stats_not_ready() local
1549 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_stats_not_ready()
1583 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_get_stats() local
1594 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_get_stats()
1602 * At state 7, only CNR is available mb86a20s_get_stats()
1603 * For BER measures, state=9 is required mb86a20s_get_stats()
1604 * FIXME: we may get MER measures with state=8 mb86a20s_get_stats()
1629 dev_err(&state->i2c->dev, mb86a20s_get_stats()
1651 dev_err(&state->i2c->dev, mb86a20s_get_stats()
1674 dev_err(&state->i2c->dev, mb86a20s_get_stats()
1765 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_initfe() local
1771 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_initfe()
1777 rc = mb86a20s_writeregdata(state, mb86a20s_init1); mb86a20s_initfe()
1781 if (!state->inversion) mb86a20s_initfe()
1783 rc = mb86a20s_writereg(state, 0x09, reg09); mb86a20s_initfe()
1786 if (!state->bw) mb86a20s_initfe()
1790 rc = mb86a20s_writereg(state, 0x39, reg71); mb86a20s_initfe()
1793 rc = mb86a20s_writereg(state, 0x71, state->bw); mb86a20s_initfe()
1796 if (state->subchannel) { mb86a20s_initfe()
1797 rc = mb86a20s_writereg(state, 0x44, state->subchannel); mb86a20s_initfe()
1802 fclk = state->config->fclk; mb86a20s_initfe()
1808 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq); mb86a20s_initfe()
1810 if (!state->if_freq) mb86a20s_initfe()
1811 state->if_freq = 3300000; mb86a20s_initfe()
1813 pll = (((u64)1) << 34) * state->if_freq; mb86a20s_initfe()
1816 rc = mb86a20s_writereg(state, 0x28, 0x2a); mb86a20s_initfe()
1819 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); mb86a20s_initfe()
1822 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); mb86a20s_initfe()
1825 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); mb86a20s_initfe()
1828 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n", mb86a20s_initfe()
1829 __func__, fclk, state->if_freq, (long long)pll); mb86a20s_initfe()
1832 pll = state->if_freq * 1677721600L; mb86a20s_initfe()
1834 rc = mb86a20s_writereg(state, 0x28, 0x20); mb86a20s_initfe()
1837 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); mb86a20s_initfe()
1840 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); mb86a20s_initfe()
1843 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); mb86a20s_initfe()
1846 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n", mb86a20s_initfe()
1847 __func__, state->if_freq, (long long)pll); mb86a20s_initfe()
1849 if (!state->config->is_serial) mb86a20s_initfe()
1852 rc = mb86a20s_writereg(state, 0x50, 0xd5); mb86a20s_initfe()
1855 rc = mb86a20s_writereg(state, 0x51, regD5); mb86a20s_initfe()
1859 rc = mb86a20s_writeregdata(state, mb86a20s_init2); mb86a20s_initfe()
1869 state->need_init = true; mb86a20s_initfe()
1870 dev_info(&state->i2c->dev, mb86a20s_initfe()
1873 state->need_init = false; mb86a20s_initfe()
1874 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); mb86a20s_initfe()
1881 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_set_frontend() local
1884 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_set_frontend()
1890 state->bw = MB86A20S_1SEG; mb86a20s_set_frontend()
1892 state->bw = MB86A20S_13SEG_PARTIAL; mb86a20s_set_frontend()
1894 state->bw = MB86A20S_13SEG; mb86a20s_set_frontend()
1897 state->inversion = true; mb86a20s_set_frontend()
1899 state->inversion = false; mb86a20s_set_frontend()
1902 state->subchannel = 0; mb86a20s_set_frontend()
1907 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel]; mb86a20s_set_frontend()
1943 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); mb86a20s_set_frontend()
1956 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_read_status_and_stats() local
1959 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_read_status_and_stats()
1971 dev_err(&state->i2c->dev, mb86a20s_read_status_and_stats()
1979 dev_err(&state->i2c->dev, mb86a20s_read_status_and_stats()
1992 dev_err(&state->i2c->dev, mb86a20s_read_status_and_stats()
2001 dev_err(&state->i2c->dev, mb86a20s_read_status_and_stats()
2047 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_tune() local
2050 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_tune()
2063 struct mb86a20s_state *state = fe->demodulator_priv; mb86a20s_release() local
2065 dev_dbg(&state->i2c->dev, "%s called.\n", __func__); mb86a20s_release()
2067 kfree(state); mb86a20s_release()
2075 struct mb86a20s_state *state; mb86a20s_attach() local
2080 /* allocate memory for the internal state */ mb86a20s_attach()
2081 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); mb86a20s_attach()
2082 if (state == NULL) { mb86a20s_attach()
2084 "%s: unable to allocate memory for state\n", __func__); mb86a20s_attach()
2088 /* setup the state */ mb86a20s_attach()
2089 state->config = config; mb86a20s_attach()
2090 state->i2c = i2c; mb86a20s_attach()
2093 memcpy(&state->frontend.ops, &mb86a20s_ops, mb86a20s_attach()
2095 state->frontend.demodulator_priv = state; mb86a20s_attach()
2098 rev = mb86a20s_readreg(state, 0); mb86a20s_attach()
2110 return &state->frontend; mb86a20s_attach()
2113 kfree(state); mb86a20s_attach()
H A Dtda8261.c34 /* state cache */
39 static int tda8261_read(struct tda8261_state *state, u8 *buf) tda8261_read() argument
41 const struct tda8261_config *config = state->config; tda8261_read()
45 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) tda8261_read()
51 static int tda8261_write(struct tda8261_state *state, u8 *buf) tda8261_write() argument
53 const struct tda8261_config *config = state->config; tda8261_write()
57 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) tda8261_write()
65 struct tda8261_state *state = fe->tuner_priv; tda8261_get_status() local
71 if ((err = tda8261_read(state, &result)) < 0) { tda8261_get_status()
90 struct tda8261_state *state = fe->tuner_priv; tda8261_get_state() local
95 tstate->frequency = state->frequency; tda8261_get_state()
113 struct tda8261_state *state = fe->tuner_priv; tda8261_set_state() local
114 const struct tda8261_config *config = state->config; tda8261_set_state()
146 if ((err = tda8261_write(state, buf)) < 0) { tda8261_set_state()
160 state->frequency = frequency; /* cache successful state */ tda8261_set_state()
174 struct tda8261_state *state = fe->tuner_priv; tda8261_release() local
177 kfree(state); tda8261_release()
201 struct tda8261_state *state = NULL; tda8261_attach() local
203 if ((state = kzalloc(sizeof (struct tda8261_state), GFP_KERNEL)) == NULL) tda8261_attach()
206 state->config = config; tda8261_attach()
207 state->i2c = i2c; tda8261_attach()
208 state->fe = fe; tda8261_attach()
209 fe->tuner_priv = state; tda8261_attach()
222 kfree(state); tda8261_attach()
H A Dau8522_dig.c246 struct au8522_state *state = fe->demodulator_priv; au8522_set_if() local
274 au8522_writereg(state, 0x80b5, r0b5); au8522_set_if()
275 au8522_writereg(state, 0x80b6, r0b6); au8522_set_if()
276 au8522_writereg(state, 0x80b7, r0b7); au8522_set_if()
557 struct au8522_state *state = fe->demodulator_priv; au8522_enable_modulation() local
566 au8522_writereg(state, au8522_enable_modulation()
569 au8522_set_if(fe, state->config->vsb_if); au8522_enable_modulation()
574 au8522_writereg(state, au8522_enable_modulation()
577 au8522_set_if(fe, state->config->qam_if); au8522_enable_modulation()
583 au8522_writereg(state, au8522_enable_modulation()
586 au8522_set_if(fe, state->config->qam_if); au8522_enable_modulation()
588 au8522_writereg(state, 0x821a, 0x00); au8522_enable_modulation()
592 au8522_writereg(state, au8522_enable_modulation()
595 au8522_set_if(fe, state->config->qam_if); au8522_enable_modulation()
603 state->current_modulation = m; au8522_enable_modulation()
612 struct au8522_state *state = fe->demodulator_priv; au8522_set_frontend() local
617 if ((state->current_frequency == c->frequency) && au8522_set_frontend()
618 (state->current_modulation == c->modulation)) au8522_set_frontend()
642 state->current_frequency = c->frequency; au8522_set_frontend()
649 struct au8522_state *state = fe->demodulator_priv; au8522_read_status() local
655 if (state->current_modulation == VSB_8) { au8522_read_status()
657 reg = au8522_readreg(state, 0x4088); au8522_read_status()
662 reg = au8522_readreg(state, 0x4541); au8522_read_status()
669 switch (state->config->status_mode) { au8522_read_status()
691 state->fe_status = *status; au8522_read_status()
695 au8522_led_ctrl(state, -1); au8522_read_status()
698 au8522_led_ctrl(state, 0); au8522_read_status()
705 static int au8522_led_status(struct au8522_state *state, const u16 *snr) au8522_led_status() argument
707 struct au8522_led_config *led_config = state->config->led_cfg; au8522_led_status()
715 if (0 == (state->fe_status & FE_HAS_LOCK)) au8522_led_status()
716 return au8522_led_ctrl(state, 0); au8522_led_status()
717 else if (state->current_modulation == QAM_256) au8522_led_status()
719 else if (state->current_modulation == QAM_64) au8522_led_status()
721 else /* (state->current_modulation == VSB_8) */ au8522_led_status()
729 if ((state->led_state) && au8522_led_status()
735 return au8522_led_ctrl(state, led); au8522_led_status()
740 struct au8522_state *state = fe->demodulator_priv; au8522_read_snr() local
745 if (state->current_modulation == QAM_256) au8522_read_snr()
748 au8522_readreg(state, 0x4522), au8522_read_snr()
750 else if (state->current_modulation == QAM_64) au8522_read_snr()
753 au8522_readreg(state, 0x4522), au8522_read_snr()
758 au8522_readreg(state, 0x4311), au8522_read_snr()
761 if (state->config->led_cfg) au8522_read_snr()
762 au8522_led_status(state, snr); au8522_read_snr()
804 struct au8522_state *state = fe->demodulator_priv; au8522_read_ucblocks() local
806 if (state->current_modulation == VSB_8) au8522_read_ucblocks()
807 *ucblocks = au8522_readreg(state, 0x4087); au8522_read_ucblocks()
809 *ucblocks = au8522_readreg(state, 0x4543); au8522_read_ucblocks()
822 struct au8522_state *state = fe->demodulator_priv; au8522_get_frontend() local
824 c->frequency = state->current_frequency; au8522_get_frontend()
825 c->modulation = state->current_modulation; au8522_get_frontend()
842 struct au8522_state *state = fe->demodulator_priv; au8522_release() local
843 au8522_release_state(state); au8522_release()
849 struct au8522_state *state = NULL; au8522_attach() local
852 /* allocate memory for the internal state */ au8522_attach()
853 instance = au8522_get_state(&state, i2c, config->demod_address); au8522_attach()
856 dprintk("%s state allocation failed\n", __func__); au8522_attach()
868 /* setup the state */ au8522_attach()
869 state->config = config; au8522_attach()
870 state->i2c = i2c; au8522_attach()
871 state->operational_mode = AU8522_DIGITAL_MODE; au8522_attach()
874 memcpy(&state->frontend.ops, &au8522_ops, au8522_attach()
876 state->frontend.demodulator_priv = state; au8522_attach()
878 state->frontend.ops.analog_ops.i2c_gate_ctrl = au8522_analog_i2c_gate_ctrl; au8522_attach()
880 if (au8522_init(&state->frontend) != 0) { au8522_attach()
887 au8522_i2c_gate_ctrl(&state->frontend, 1); au8522_attach()
889 return &state->frontend; au8522_attach()
892 au8522_release_state(state); au8522_attach()
H A Dsi21xx.c227 static int si21_writeregs(struct si21xx_state *state, u8 reg1, si21_writeregs() argument
233 .addr = state->config->demod_address, si21_writeregs()
245 ret = i2c_transfer(state->i2c, &msg, 1); si21_writeregs()
254 static int si21_writereg(struct si21xx_state *state, u8 reg, u8 data) si21_writereg() argument
259 .addr = state->config->demod_address, si21_writereg()
265 ret = i2c_transfer(state->i2c, &msg, 1); si21_writereg()
276 struct si21xx_state *state = fe->demodulator_priv; si21_write() local
281 return si21_writereg(state, buf[0], buf[1]); si21_write()
284 static u8 si21_readreg(struct si21xx_state *state, u8 reg) si21_readreg() argument
291 .addr = state->config->demod_address, si21_readreg()
296 .addr = state->config->demod_address, si21_readreg()
303 ret = i2c_transfer(state->i2c, msg, 2); si21_readreg()
312 static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len) si21_readregs() argument
317 .addr = state->config->demod_address, si21_readregs()
322 .addr = state->config->demod_address, si21_readregs()
329 ret = i2c_transfer(state->i2c, msg, 2); si21_readregs()
337 static int si21xx_wait_diseqc_idle(struct si21xx_state *state, int timeout) si21xx_wait_diseqc_idle() argument
343 while ((si21_readreg(state, LNB_CTRL_REG_1) & 0x8) == 8) { si21xx_wait_diseqc_idle()
356 struct si21xx_state *state = fe->demodulator_priv; si21xx_set_symbolrate() local
372 state->fs; si21xx_set_symbolrate()
378 si21_writeregs(state, SYM_RATE_REG_L, sym_rate_bytes, 0x03); si21xx_set_symbolrate()
386 struct si21xx_state *state = fe->demodulator_priv; si21xx_send_diseqc_msg() local
396 status |= si21_readregs(state, LNB_CTRL_STATUS_REG, &lnb_status, 0x01); si21xx_send_diseqc_msg()
397 status |= si21_readregs(state, LNB_CTRL_REG_1, &lnb_status, 0x01); si21xx_send_diseqc_msg()
400 status |= si21_writeregs(state, LNB_FIFO_REGS_0, m->msg, m->msg_len); si21xx_send_diseqc_msg()
407 status |= si21_writeregs(state, LNB_CTRL_REG_1, &LNB_CTRL_1, 0x01); si21xx_send_diseqc_msg()
415 struct si21xx_state *state = fe->demodulator_priv; si21xx_send_diseqc_burst() local
420 if (si21xx_wait_diseqc_idle(state, 100) < 0) si21xx_send_diseqc_burst()
423 val = (0x80 | si21_readreg(state, 0xc1)); si21xx_send_diseqc_burst()
424 if (si21_writereg(state, LNB_CTRL_REG_1, si21xx_send_diseqc_burst()
428 if (si21xx_wait_diseqc_idle(state, 100) < 0) si21xx_send_diseqc_burst()
431 if (si21_writereg(state, LNB_CTRL_REG_1, val)) si21xx_send_diseqc_burst()
439 struct si21xx_state *state = fe->demodulator_priv; si21xx_set_tone() local
443 val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1)); si21xx_set_tone()
447 return si21_writereg(state, LNB_CTRL_REG_1, val | 0x20); si21xx_set_tone()
450 return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x20)); si21xx_set_tone()
459 struct si21xx_state *state = fe->demodulator_priv; si21xx_set_voltage() local
467 val = (0x80 | si21_readreg(state, LNB_CTRL_REG_1)); si21xx_set_voltage()
471 return si21_writereg(state, LNB_CTRL_REG_1, val | 0x40); si21xx_set_voltage()
474 return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x40)); si21xx_set_voltage()
483 struct si21xx_state *state = fe->demodulator_priv; si21xx_init() local
497 si21_writeregs(state, reg1, &val, 1); si21xx_init()
502 si21_writeregs(state, SYSTEM_MODE_REG, &reg1, 0x01); si21xx_init()
531 status |= si21_writeregs(state, TS_CTRL_REG_1, reg2, 0x02); si21xx_init()
541 struct si21xx_state *state = fe->demodulator_priv; si21_read_status() local
546 u8 signal = si21_readreg(state, ANALOG_AGC_POWER_LEVEL_REG); si21_read_status()
548 si21_readregs(state, LOCK_STATUS_REG_1, regs_read, 0x02); si21_read_status()
579 struct si21xx_state *state = fe->demodulator_priv; si21_read_signal_strength() local
581 /*status = si21_readreg(state, ANALOG_AGC_POWER_LEVEL_REG, si21_read_signal_strength()
584 u16 signal = (3 * si21_readreg(state, 0x27) * si21_read_signal_strength()
585 si21_readreg(state, 0x28)); si21_read_signal_strength()
588 si21_readreg(state, 0x27), si21_read_signal_strength()
589 si21_readreg(state, 0x28), (int) signal); si21_read_signal_strength()
599 struct si21xx_state *state = fe->demodulator_priv; si21_read_ber() local
603 if (state->errmode != STATUS_BER) si21_read_ber()
606 *ber = (si21_readreg(state, 0x1d) << 8) | si21_read_ber()
607 si21_readreg(state, 0x1e); si21_read_ber()
614 struct si21xx_state *state = fe->demodulator_priv; si21_read_snr() local
616 s32 xsnr = 0xffff - ((si21_readreg(state, 0x24) << 8) | si21_read_snr()
617 si21_readreg(state, 0x25)); si21_read_snr()
628 struct si21xx_state *state = fe->demodulator_priv; si21_read_ucblocks() local
632 if (state->errmode != STATUS_UCBLOCKS) si21_read_ucblocks()
635 *ucblocks = (si21_readreg(state, 0x1d) << 8) | si21_read_ucblocks()
636 si21_readreg(state, 0x1e); si21_read_ucblocks()
647 struct si21xx_state *state = fe->demodulator_priv; si21xx_setacquire() local
666 status |= si21_writeregs(state, si21xx_setacquire()
671 status |= si21_readregs(state, ACQ_CTRL_REG_2, &reg, 0x01); si21xx_setacquire()
673 status |= si21_writeregs(state, ACQ_CTRL_REG_2, &reg, 0x01); si21xx_setacquire()
680 status |= si21_writeregs(state, si21xx_setacquire()
684 status |= si21_writeregs(state, si21xx_setacquire()
687 status |= si21_writeregs(state, si21xx_setacquire()
690 status |= si21_writeregs(state, si21xx_setacquire()
698 struct si21xx_state *state = fe->demodulator_priv; si21xx_set_frontend() local
837 status |= si21_writeregs(state, PLL_DIVISOR_REG, &regs[0], 0x04); si21xx_set_frontend()
839 state->fs = sample_rate;/*ADC MHz*/ si21xx_set_frontend()
847 struct si21xx_state *state = fe->demodulator_priv; si21xx_sleep() local
852 si21_readregs(state, SYSTEM_MODE_REG, &regdata, 0x01); si21xx_sleep()
854 si21_writeregs(state, SYSTEM_MODE_REG, &regdata, 0x01); si21xx_sleep()
855 state->initialised = 0; si21xx_sleep()
862 struct si21xx_state *state = fe->demodulator_priv; si21xx_release() local
866 kfree(state); si21xx_release()
906 struct si21xx_state *state = NULL; si21xx_attach() local
911 /* allocate memory for the internal state */ si21xx_attach()
912 state = kzalloc(sizeof(struct si21xx_state), GFP_KERNEL); si21xx_attach()
913 if (state == NULL) si21xx_attach()
916 /* setup the state */ si21xx_attach()
917 state->config = config; si21xx_attach()
918 state->i2c = i2c; si21xx_attach()
919 state->initialised = 0; si21xx_attach()
920 state->errmode = STATUS_BER; si21xx_attach()
923 id = si21_readreg(state, SYSTEM_MODE_REG); si21xx_attach()
924 si21_writereg(state, SYSTEM_MODE_REG, id | 0x40); /* standby off */ si21xx_attach()
926 id = si21_readreg(state, 0x00); si21xx_attach()
938 memcpy(&state->frontend.ops, &si21xx_ops, si21xx_attach()
940 state->frontend.demodulator_priv = state; si21xx_attach()
941 return &state->frontend; si21xx_attach()
944 kfree(state); si21xx_attach()
H A Dcx24116.c199 static int cx24116_writereg(struct cx24116_state *state, int reg, int data) cx24116_writereg() argument
202 struct i2c_msg msg = { .addr = state->config->demod_address, cx24116_writereg()
210 err = i2c_transfer(state->i2c, &msg, 1); cx24116_writereg()
221 static int cx24116_writeregN(struct cx24116_state *state, int reg, cx24116_writeregN() argument
238 msg.addr = state->config->demod_address; cx24116_writeregN()
247 ret = i2c_transfer(state->i2c, &msg, 1); cx24116_writeregN()
260 static int cx24116_readreg(struct cx24116_state *state, u8 reg) cx24116_readreg() argument
266 { .addr = state->config->demod_address, .flags = 0, cx24116_readreg()
268 { .addr = state->config->demod_address, .flags = I2C_M_RD, cx24116_readreg()
272 ret = i2c_transfer(state->i2c, msg, 2); cx24116_readreg()
287 static int cx24116_set_inversion(struct cx24116_state *state, cx24116_set_inversion() argument
294 state->dnxt.inversion_val = 0x00; cx24116_set_inversion()
297 state->dnxt.inversion_val = 0x04; cx24116_set_inversion()
300 state->dnxt.inversion_val = 0x0C; cx24116_set_inversion()
306 state->dnxt.inversion = inversion; cx24116_set_inversion()
417 static int cx24116_lookup_fecmod(struct cx24116_state *state, cx24116_lookup_fecmod() argument
436 static int cx24116_set_fec(struct cx24116_state *state, cx24116_set_fec() argument
443 ret = cx24116_lookup_fecmod(state, delsys, mod, fec); cx24116_set_fec()
448 state->dnxt.fec = fec; cx24116_set_fec()
449 state->dnxt.fec_val = CX24116_MODFEC_MODES[ret].val; cx24116_set_fec()
450 state->dnxt.fec_mask = CX24116_MODFEC_MODES[ret].mask; cx24116_set_fec()
452 state->dnxt.fec_mask, state->dnxt.fec_val); cx24116_set_fec()
457 static int cx24116_set_symbolrate(struct cx24116_state *state, u32 rate) cx24116_set_symbolrate() argument
462 if ((rate > state->frontend.ops.info.symbol_rate_max) || cx24116_set_symbolrate()
463 (rate < state->frontend.ops.info.symbol_rate_min)) { cx24116_set_symbolrate()
468 state->dnxt.symbol_rate = rate; cx24116_set_symbolrate()
479 struct cx24116_state *state = fe->demodulator_priv; cx24116_firmware_ondemand() local
485 if (cx24116_readreg(state, 0x20) > 0) { cx24116_firmware_ondemand()
487 if (state->skip_fw_load) cx24116_firmware_ondemand()
495 state->i2c->dev.parent); cx24116_firmware_ondemand()
506 state->skip_fw_load = 1; cx24116_firmware_ondemand()
519 state->skip_fw_load = 0; cx24116_firmware_ondemand()
530 struct cx24116_state *state = fe->demodulator_priv; cx24116_cmd_execute() local
546 cx24116_writereg(state, i, cmd->args[i]); cx24116_cmd_execute()
550 cx24116_writereg(state, CX24116_REG_EXECUTE, 0x01); cx24116_cmd_execute()
551 while (cx24116_readreg(state, CX24116_REG_EXECUTE)) { cx24116_cmd_execute()
567 struct cx24116_state *state = fe->demodulator_priv; cx24116_load_firmware() local
581 if (state->config->reset_device) cx24116_load_firmware()
582 state->config->reset_device(fe); cx24116_load_firmware()
588 cx24116_writereg(state, 0xE5, 0x00); cx24116_load_firmware()
589 cx24116_writereg(state, 0xF1, 0x08); cx24116_load_firmware()
590 cx24116_writereg(state, 0xF2, 0x13); cx24116_load_firmware()
593 cx24116_writereg(state, 0xe0, 0x03); cx24116_load_firmware()
594 cx24116_writereg(state, 0xe0, 0x00); cx24116_load_firmware()
597 cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46); cx24116_load_firmware()
598 cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00); cx24116_load_firmware()
601 cx24116_writereg(state, 0xF0, 0x03); cx24116_load_firmware()
602 cx24116_writereg(state, 0xF4, 0x81); cx24116_load_firmware()
603 cx24116_writereg(state, 0xF5, 0x00); cx24116_load_firmware()
604 cx24116_writereg(state, 0xF6, 0x00); cx24116_load_firmware()
608 if (state->config->i2c_wr_max) cx24116_load_firmware()
609 max = state->config->i2c_wr_max; cx24116_load_firmware()
618 cx24116_writeregN(state, 0xF7, &fw->data[fw->size - remaining], cx24116_load_firmware()
622 cx24116_writereg(state, 0xF4, 0x10); cx24116_load_firmware()
623 cx24116_writereg(state, 0xF0, 0x00); cx24116_load_firmware()
624 cx24116_writereg(state, 0xF8, 0x06); cx24116_load_firmware()
642 cx24116_writereg(state, CX24116_REG_SSTATUS, 0x00); cx24116_load_firmware()
653 cx24116_writereg(state, 0xe5, 0x00); cx24116_load_firmware()
660 if (state->config->mpg_clk_pos_pol) cx24116_load_firmware()
661 cmd.args[0x04] = state->config->mpg_clk_pos_pol; cx24116_load_firmware()
678 vers[i] = cx24116_readreg(state, CX24116_REG_MAILBOX); cx24116_load_firmware()
688 struct cx24116_state *state = fe->demodulator_priv; cx24116_read_status() local
690 int lock = cx24116_readreg(state, CX24116_REG_SSTATUS) & cx24116_read_status()
711 struct cx24116_state *state = fe->demodulator_priv; cx24116_read_ber() local
715 *ber = (cx24116_readreg(state, CX24116_REG_BER24) << 24) | cx24116_read_ber()
716 (cx24116_readreg(state, CX24116_REG_BER16) << 16) | cx24116_read_ber()
717 (cx24116_readreg(state, CX24116_REG_BER8) << 8) | cx24116_read_ber()
718 cx24116_readreg(state, CX24116_REG_BER0); cx24116_read_ber()
727 struct cx24116_state *state = fe->demodulator_priv; cx24116_read_signal_strength() local
742 (cx24116_readreg(state, cx24116_read_signal_strength()
744 (cx24116_readreg(state, CX24116_REG_SIGNAL) << 6); cx24116_read_signal_strength()
756 struct cx24116_state *state = fe->demodulator_priv; cx24116_read_snr_pct() local
766 snr_reading = cx24116_readreg(state, CX24116_REG_QUALITY0); cx24116_read_snr_pct()
786 struct cx24116_state *state = fe->demodulator_priv; cx24116_read_snr_esno() local
790 *snr = cx24116_readreg(state, CX24116_REG_QUALITY8) << 8 | cx24116_read_snr_esno()
791 cx24116_readreg(state, CX24116_REG_QUALITY0); cx24116_read_snr_esno()
808 struct cx24116_state *state = fe->demodulator_priv; cx24116_read_ucblocks() local
812 *ucblocks = (cx24116_readreg(state, CX24116_REG_UCB8) << 8) | cx24116_read_ucblocks()
813 cx24116_readreg(state, CX24116_REG_UCB0); cx24116_read_ucblocks()
821 struct cx24116_state *state = fe->demodulator_priv; cx24116_clone_params() local
822 state->dcur = state->dnxt; cx24116_clone_params()
828 struct cx24116_state *state = fe->demodulator_priv; cx24116_wait_for_lnb() local
832 cx24116_readreg(state, CX24116_REG_QSTATUS)); cx24116_wait_for_lnb()
836 if (cx24116_readreg(state, CX24116_REG_QSTATUS) & 0x20) cx24116_wait_for_lnb()
920 struct cx24116_state *state = fe->demodulator_priv; cx24116_diseqc_init() local
939 state->dsec_cmd.args[0x00] = CMD_LNBSEND; cx24116_diseqc_init()
942 state->dsec_cmd.args[CX24116_DISEQC_BURST] = CX24116_DISEQC_MINI_A; cx24116_diseqc_init()
945 state->dsec_cmd.args[CX24116_DISEQC_ARG2_2] = 0x02; cx24116_diseqc_init()
946 state->dsec_cmd.args[CX24116_DISEQC_ARG3_0] = 0x00; cx24116_diseqc_init()
948 state->dsec_cmd.args[CX24116_DISEQC_ARG4_0] = 0x00; cx24116_diseqc_init()
951 state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = 0x00; cx24116_diseqc_init()
954 state->dsec_cmd.len = CX24116_DISEQC_MSGOFS; cx24116_diseqc_init()
963 struct cx24116_state *state = fe->demodulator_priv; cx24116_send_diseqc_msg() local
983 state->dsec_cmd.args[CX24116_DISEQC_MSGOFS + i] = d->msg[i]; cx24116_send_diseqc_msg()
986 state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] = d->msg_len; cx24116_send_diseqc_msg()
989 state->dsec_cmd.len = CX24116_DISEQC_MSGOFS + cx24116_send_diseqc_msg()
990 state->dsec_cmd.args[CX24116_DISEQC_MSGLEN]; cx24116_send_diseqc_msg()
999 state->dsec_cmd.args[CX24116_DISEQC_BURST] = 0; cx24116_send_diseqc_msg()
1021 state->dsec_cmd.args[CX24116_DISEQC_BURST] = cx24116_send_diseqc_msg()
1025 state->dsec_cmd.args[CX24116_DISEQC_BURST]); cx24116_send_diseqc_msg()
1037 ret = cx24116_cmd_execute(fe, &state->dsec_cmd); cx24116_send_diseqc_msg()
1050 msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) + cx24116_send_diseqc_msg()
1060 struct cx24116_state *state = fe->demodulator_priv; cx24116_diseqc_send_burst() local
1067 state->dsec_cmd.args[CX24116_DISEQC_BURST] = cx24116_diseqc_send_burst()
1070 state->dsec_cmd.args[CX24116_DISEQC_BURST] = cx24116_diseqc_send_burst()
1091 ret = cx24116_cmd_execute(fe, &state->dsec_cmd); cx24116_diseqc_send_burst()
1105 msleep((state->dsec_cmd.args[CX24116_DISEQC_MSGLEN] << 4) + 60); cx24116_diseqc_send_burst()
1112 struct cx24116_state *state = fe->demodulator_priv; cx24116_release() local
1114 kfree(state); cx24116_release()
1122 struct cx24116_state *state = NULL; cx24116_attach() local
1127 /* allocate memory for the internal state */ cx24116_attach()
1128 state = kzalloc(sizeof(struct cx24116_state), GFP_KERNEL); cx24116_attach()
1129 if (state == NULL) cx24116_attach()
1132 state->config = config; cx24116_attach()
1133 state->i2c = i2c; cx24116_attach()
1136 ret = (cx24116_readreg(state, 0xFF) << 8) | cx24116_attach()
1137 cx24116_readreg(state, 0xFE); cx24116_attach()
1144 memcpy(&state->frontend.ops, &cx24116_ops, cx24116_attach()
1146 state->frontend.demodulator_priv = state; cx24116_attach()
1147 return &state->frontend; cx24116_attach()
1149 error2: kfree(state); cx24116_attach()
1161 struct cx24116_state *state = fe->demodulator_priv; cx24116_initfe() local
1168 cx24116_writereg(state, 0xe0, 0); cx24116_initfe()
1169 cx24116_writereg(state, 0xe1, 0); cx24116_initfe()
1170 cx24116_writereg(state, 0xea, 0); cx24116_initfe()
1193 struct cx24116_state *state = fe->demodulator_priv; cx24116_sleep() local
1208 cx24116_writereg(state, 0xea, 0xff); cx24116_sleep()
1209 cx24116_writereg(state, 0xe1, 1); cx24116_sleep()
1210 cx24116_writereg(state, 0xe0, 1); cx24116_sleep()
1220 struct cx24116_state *state = fe->demodulator_priv; cx24116_set_frontend() local
1240 state->dnxt.pilot_val = CX24116_PILOT_OFF; cx24116_set_frontend()
1248 state->dnxt.rolloff_val = CX24116_ROLLOFF_035; cx24116_set_frontend()
1266 state->dnxt.pilot_val = (c->modulation == QPSK) cx24116_set_frontend()
1271 state->dnxt.pilot_val = CX24116_PILOT_OFF; cx24116_set_frontend()
1274 state->dnxt.pilot_val = CX24116_PILOT_ON; cx24116_set_frontend()
1284 state->dnxt.rolloff_val = CX24116_ROLLOFF_020; cx24116_set_frontend()
1287 state->dnxt.rolloff_val = CX24116_ROLLOFF_025; cx24116_set_frontend()
1290 state->dnxt.rolloff_val = CX24116_ROLLOFF_035; cx24116_set_frontend()
1305 state->dnxt.delsys = c->delivery_system; cx24116_set_frontend()
1306 state->dnxt.modulation = c->modulation; cx24116_set_frontend()
1307 state->dnxt.frequency = c->frequency; cx24116_set_frontend()
1308 state->dnxt.pilot = c->pilot; cx24116_set_frontend()
1309 state->dnxt.rolloff = c->rolloff; cx24116_set_frontend()
1311 ret = cx24116_set_inversion(state, c->inversion); cx24116_set_frontend()
1316 ret = cx24116_set_fec(state, c->delivery_system, c->modulation, c->fec_inner); cx24116_set_frontend()
1320 ret = cx24116_set_symbolrate(state, c->symbol_rate); cx24116_set_frontend()
1327 dprintk("%s: delsys = %d\n", __func__, state->dcur.delsys); cx24116_set_frontend()
1328 dprintk("%s: modulation = %d\n", __func__, state->dcur.modulation); cx24116_set_frontend()
1329 dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency); cx24116_set_frontend()
1331 state->dcur.pilot, state->dcur.pilot_val); cx24116_set_frontend()
1334 state->dcur.rolloff, state->dcur.rolloff_val); cx24116_set_frontend()
1335 dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate); cx24116_set_frontend()
1337 state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val); cx24116_set_frontend()
1339 state->dcur.inversion, state->dcur.inversion_val); cx24116_set_frontend()
1342 if (state->config->set_ts_params) cx24116_set_frontend()
1343 state->config->set_ts_params(fe, 0); cx24116_set_frontend()
1357 cmd.args[0x01] = (state->dcur.frequency & 0xff0000) >> 16; cx24116_set_frontend()
1358 cmd.args[0x02] = (state->dcur.frequency & 0x00ff00) >> 8; cx24116_set_frontend()
1359 cmd.args[0x03] = (state->dcur.frequency & 0x0000ff); cx24116_set_frontend()
1362 cmd.args[0x04] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8; cx24116_set_frontend()
1363 cmd.args[0x05] = ((state->dcur.symbol_rate / 1000) & 0x00ff); cx24116_set_frontend()
1366 cmd.args[0x06] = state->dcur.inversion_val; cx24116_set_frontend()
1369 cmd.args[0x07] = state->dcur.fec_val | state->dcur.pilot_val; cx24116_set_frontend()
1375 cmd.args[0x0c] = state->dcur.rolloff_val; cx24116_set_frontend()
1376 cmd.args[0x0d] = state->dcur.fec_mask; cx24116_set_frontend()
1378 if (state->dcur.symbol_rate > 30000000) { cx24116_set_frontend()
1384 cx24116_writereg(state, CX24116_REG_CLKDIV, 0x44); cx24116_set_frontend()
1385 cx24116_writereg(state, CX24116_REG_RATEDIV, 0x01); cx24116_set_frontend()
1392 cx24116_writereg(state, CX24116_REG_CLKDIV, 0x46); cx24116_set_frontend()
1393 cx24116_writereg(state, CX24116_REG_RATEDIV, 0x00); cx24116_set_frontend()
1404 status = cx24116_readreg(state, CX24116_REG_SSTATUS) cx24116_set_frontend()
1406 cx24116_writereg(state, CX24116_REG_SSTATUS, status); cx24116_set_frontend()
1432 if (state->dcur.pilot == PILOT_AUTO) cx24116_set_frontend()
1450 * that re-tuning is needed, e. g. (fepriv->state & FESTATE_RETUNE) is cx24116_tune()
H A Dzl10039.c71 static int zl10039_read(const struct zl10039_state *state, zl10039_read() argument
78 .addr = state->i2c_addr, zl10039_read()
83 .addr = state->i2c_addr, zl10039_read()
92 if (i2c_transfer(state->i2c, msg, 2) != 2) { zl10039_read()
100 static int zl10039_write(struct zl10039_state *state, zl10039_write() argument
106 .addr = state->i2c_addr, zl10039_write()
123 if (i2c_transfer(state->i2c, &msg, 1) != 1) { zl10039_write()
131 static inline int zl10039_readreg(struct zl10039_state *state, zl10039_readreg() argument
134 return zl10039_read(state, reg, val, 1); zl10039_readreg()
137 static inline int zl10039_writereg(struct zl10039_state *state, zl10039_writereg() argument
141 return zl10039_write(state, reg, &val, 1); zl10039_writereg()
146 struct zl10039_state *state = fe->tuner_priv; zl10039_init() local
153 ret = zl10039_writereg(state, GENERAL, 0x40); zl10039_init()
159 ret = zl10039_writereg(state, GENERAL, 0x01); zl10039_init()
172 struct zl10039_state *state = fe->tuner_priv; zl10039_sleep() local
178 ret = zl10039_writereg(state, GENERAL, 0x80); zl10039_sleep()
192 struct zl10039_state *state = fe->tuner_priv; zl10039_set_params() local
227 ret = zl10039_writereg(state, BASE1, 0x0A); zl10039_set_params()
231 ret = zl10039_write(state, PLL0, buf, sizeof(buf)); zl10039_set_params()
235 ret = zl10039_writereg(state, BASE1, 0x6A); zl10039_set_params()
250 struct zl10039_state *state = fe->tuner_priv; zl10039_release() local
253 kfree(state); zl10039_release()
268 struct zl10039_state *state = NULL; zl10039_attach() local
271 state = kmalloc(sizeof(struct zl10039_state), GFP_KERNEL); zl10039_attach()
272 if (state == NULL) zl10039_attach()
275 state->i2c = i2c; zl10039_attach()
276 state->i2c_addr = i2c_addr; zl10039_attach()
282 if (zl10039_readreg(state, GENERAL, &state->id) < 0) { zl10039_attach()
292 state->id = state->id & 0x0f; zl10039_attach()
293 switch (state->id) { zl10039_attach()
299 dprintk("Chip ID=%x does not match a known type\n", state->id); zl10039_attach()
304 fe->tuner_priv = state; zl10039_attach()
308 kfree(state); zl10039_attach()
H A Dmt352.c60 struct mt352_state* state = fe->demodulator_priv; mt352_single_write() local
62 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, mt352_single_write()
64 int err = i2c_transfer(state->i2c, &msg, 1); mt352_single_write()
82 static int mt352_read_register(struct mt352_state* state, u8 reg) mt352_read_register() argument
87 struct i2c_msg msg [] = { { .addr = state->config.demod_address, mt352_read_register()
90 { .addr = state->config.demod_address, mt352_read_register()
94 ret = i2c_transfer(state->i2c, msg, 2); mt352_read_register()
113 static void mt352_calc_nominal_rate(struct mt352_state* state, mt352_calc_nominal_rate() argument
132 if (state->config.adc_clock) mt352_calc_nominal_rate()
133 adc_clock = state->config.adc_clock; mt352_calc_nominal_rate()
143 static void mt352_calc_input_freq(struct mt352_state* state, mt352_calc_input_freq() argument
150 if (state->config.adc_clock) mt352_calc_input_freq()
151 adc_clock = state->config.adc_clock; mt352_calc_input_freq()
152 if (state->config.if2) mt352_calc_input_freq()
153 if2 = state->config.if2; mt352_calc_input_freq()
172 struct mt352_state* state = fe->demodulator_priv; mt352_set_parameters() local
290 mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4); mt352_set_parameters()
291 mt352_calc_input_freq(state, buf+6); mt352_set_parameters()
293 if (state->config.no_tuner) { mt352_set_parameters()
317 struct mt352_state* state = fe->demodulator_priv; mt352_get_parameters() local
333 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 ) mt352_get_parameters()
339 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0); mt352_get_parameters()
340 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0); mt352_get_parameters()
341 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1); mt352_get_parameters()
412 if (mt352_read_register(state, STATUS_2) & 0x02) mt352_get_parameters()
422 struct mt352_state* state = fe->demodulator_priv; mt352_read_status() local
437 if ((s0 = mt352_read_register(state, STATUS_0)) < 0) mt352_read_status()
439 if ((s1 = mt352_read_register(state, STATUS_1)) < 0) mt352_read_status()
441 if ((s3 = mt352_read_register(state, STATUS_3)) < 0) mt352_read_status()
465 struct mt352_state* state = fe->demodulator_priv; mt352_read_ber() local
467 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) | mt352_read_ber()
468 (mt352_read_register (state, RS_ERR_CNT_1) << 8) | mt352_read_ber()
469 (mt352_read_register (state, RS_ERR_CNT_0)); mt352_read_ber()
476 struct mt352_state* state = fe->demodulator_priv; mt352_read_signal_strength() local
479 u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) | mt352_read_signal_strength()
480 (mt352_read_register(state, AGC_GAIN_0) << 4); mt352_read_signal_strength()
489 struct mt352_state* state = fe->demodulator_priv; mt352_read_snr() local
491 u8 _snr = mt352_read_register (state, SNR); mt352_read_snr()
499 struct mt352_state* state = fe->demodulator_priv; mt352_read_ucblocks() local
501 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) | mt352_read_ucblocks()
502 (mt352_read_register (state, RS_UBC_0)); mt352_read_ucblocks()
518 struct mt352_state* state = fe->demodulator_priv; mt352_init() local
524 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 || mt352_init()
525 (mt352_read_register(state, CONFIG) & 0x20) == 0) { mt352_init()
529 return state->config.demod_init(fe); mt352_init()
537 struct mt352_state* state = fe->demodulator_priv; mt352_release() local
538 kfree(state); mt352_release()
546 struct mt352_state* state = NULL; mt352_attach() local
548 /* allocate memory for the internal state */ mt352_attach()
549 state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL); mt352_attach()
550 if (state == NULL) goto error; mt352_attach()
552 /* setup the state */ mt352_attach()
553 state->i2c = i2c; mt352_attach()
554 memcpy(&state->config,config,sizeof(struct mt352_config)); mt352_attach()
557 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error; mt352_attach()
560 memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops)); mt352_attach()
561 state->frontend.demodulator_priv = state; mt352_attach()
562 return &state->frontend; mt352_attach()
565 kfree(state); mt352_attach()
/linux-4.1.27/drivers/mtd/maps/
H A Dbfin-async-flash.c46 static void switch_to_flash(struct async_state *state) switch_to_flash() argument
48 local_irq_save(state->irq_flags); switch_to_flash()
50 gpio_set_value(state->enet_flash_pin, 0); switch_to_flash()
52 state->save_ambctl0 = bfin_read_EBIU_AMBCTL0(); switch_to_flash()
53 state->save_ambctl1 = bfin_read_EBIU_AMBCTL1(); switch_to_flash()
54 bfin_write_EBIU_AMBCTL0(state->flash_ambctl0); switch_to_flash()
55 bfin_write_EBIU_AMBCTL1(state->flash_ambctl1); switch_to_flash()
59 static void switch_back(struct async_state *state) switch_back() argument
61 bfin_write_EBIU_AMBCTL0(state->save_ambctl0); switch_back()
62 bfin_write_EBIU_AMBCTL1(state->save_ambctl1); switch_back()
65 gpio_set_value(state->enet_flash_pin, 1); switch_back()
67 local_irq_restore(state->irq_flags); switch_back()
72 struct async_state *state = (struct async_state *)map->map_priv_1; bfin_flash_read() local
76 switch_to_flash(state); bfin_flash_read()
80 switch_back(state); bfin_flash_read()
88 struct async_state *state = (struct async_state *)map->map_priv_1; bfin_flash_copy_from() local
90 switch_to_flash(state); bfin_flash_copy_from()
94 switch_back(state); bfin_flash_copy_from()
99 struct async_state *state = (struct async_state *)map->map_priv_1; bfin_flash_write() local
104 switch_to_flash(state); bfin_flash_write()
109 switch_back(state); bfin_flash_write()
114 struct async_state *state = (struct async_state *)map->map_priv_1; bfin_flash_copy_to() local
116 switch_to_flash(state); bfin_flash_copy_to()
121 switch_back(state); bfin_flash_copy_to()
132 struct async_state *state; bfin_flash_probe() local
134 state = kzalloc(sizeof(*state), GFP_KERNEL); bfin_flash_probe()
135 if (!state) bfin_flash_probe()
138 state->map.name = DRIVER_NAME; bfin_flash_probe()
139 state->map.read = bfin_flash_read; bfin_flash_probe()
140 state->map.copy_from = bfin_flash_copy_from; bfin_flash_probe()
141 state->map.write = bfin_flash_write; bfin_flash_probe()
142 state->map.copy_to = bfin_flash_copy_to; bfin_flash_probe()
143 state->map.bankwidth = pdata->width; bfin_flash_probe()
144 state->map.size = resource_size(memory); bfin_flash_probe()
145 state->map.virt = (void __iomem *)memory->start; bfin_flash_probe()
146 state->map.phys = memory->start; bfin_flash_probe()
147 state->map.map_priv_1 = (unsigned long)state; bfin_flash_probe()
148 state->enet_flash_pin = platform_get_irq(pdev, 0); bfin_flash_probe()
149 state->flash_ambctl0 = flash_ambctl->start; bfin_flash_probe()
150 state->flash_ambctl1 = flash_ambctl->end; bfin_flash_probe()
152 if (gpio_request(state->enet_flash_pin, DRIVER_NAME)) { bfin_flash_probe()
153 pr_devinit(KERN_ERR DRIVER_NAME ": Failed to request gpio %d\n", state->enet_flash_pin); bfin_flash_probe()
154 kfree(state); bfin_flash_probe()
157 gpio_direction_output(state->enet_flash_pin, 1); bfin_flash_probe()
159 pr_devinit(KERN_NOTICE DRIVER_NAME ": probing %d-bit flash bus\n", state->map.bankwidth * 8); bfin_flash_probe()
160 state->mtd = do_map_probe(memory->name, &state->map); bfin_flash_probe()
161 if (!state->mtd) { bfin_flash_probe()
162 gpio_free(state->enet_flash_pin); bfin_flash_probe()
163 kfree(state); bfin_flash_probe()
167 mtd_device_parse_register(state->mtd, part_probe_types, NULL, bfin_flash_probe()
170 platform_set_drvdata(pdev, state); bfin_flash_probe()
177 struct async_state *state = platform_get_drvdata(pdev); bfin_flash_remove() local
178 gpio_free(state->enet_flash_pin); bfin_flash_remove()
179 mtd_device_unregister(state->mtd); bfin_flash_remove()
180 map_destroy(state->mtd); bfin_flash_remove()
181 kfree(state); bfin_flash_remove()
H A Dgpio-addr-flash.c35 * struct async_state - keep GPIO flash state
36 * @mtd: MTD state for this mapping
37 * @map: MTD map state for this flash
55 * @state: GPIO flash state
63 static void gf_set_gpios(struct async_state *state, unsigned long ofs) gf_set_gpios() argument
67 ofs /= state->win_size; gf_set_gpios()
70 if (state->gpio_values[i] != value) { gf_set_gpios()
71 gpio_set_value(state->gpio_addrs[i], value); gf_set_gpios()
72 state->gpio_values[i] = value; gf_set_gpios()
74 } while (++i < state->gpio_count); gf_set_gpios()
79 * @map: MTD map state
84 struct async_state *state = gf_map_info_to_state(map); gf_read() local
88 gf_set_gpios(state, ofs); gf_read()
90 word = readw(map->virt + (ofs % state->win_size)); gf_read()
97 * @map: MTD map state
107 struct async_state *state = gf_map_info_to_state(map); gf_copy_from() local
112 if ((from % state->win_size) + len > state->win_size) gf_copy_from()
113 this_len = state->win_size - (from % state->win_size); gf_copy_from()
117 gf_set_gpios(state, from); gf_copy_from()
118 memcpy_fromio(to, map->virt + (from % state->win_size), gf_copy_from()
128 * @map: MTD map state
133 struct async_state *state = gf_map_info_to_state(map); gf_write() local
136 gf_set_gpios(state, ofs); gf_write()
139 writew(d, map->virt + (ofs % state->win_size)); gf_write()
144 * @map: MTD map state
154 struct async_state *state = gf_map_info_to_state(map); gf_copy_to() local
159 if ((to % state->win_size) + len > state->win_size) gf_copy_to()
160 this_len = state->win_size - (to % state->win_size); gf_copy_to()
164 gf_set_gpios(state, to); gf_copy_to()
165 memcpy_toio(map->virt + (to % state->win_size), from, len); gf_copy_to()
210 struct async_state *state; gpio_flash_probe() local
220 state = kzalloc(sizeof(*state) + arr_size, GFP_KERNEL); gpio_flash_probe()
221 if (!state) gpio_flash_probe()
228 state->gpio_count = gpios->end; gpio_flash_probe()
229 state->gpio_addrs = (void *)(unsigned long)gpios->start; gpio_flash_probe()
230 state->gpio_values = (void *)(state + 1); gpio_flash_probe()
231 state->win_size = resource_size(memory); gpio_flash_probe()
232 memset(state->gpio_values, 0xff, arr_size); gpio_flash_probe()
234 state->map.name = DRIVER_NAME; gpio_flash_probe()
235 state->map.read = gf_read; gpio_flash_probe()
236 state->map.copy_from = gf_copy_from; gpio_flash_probe()
237 state->map.write = gf_write; gpio_flash_probe()
238 state->map.copy_to = gf_copy_to; gpio_flash_probe()
239 state->map.bankwidth = pdata->width; gpio_flash_probe()
240 state->map.size = state->win_size * (1 << state->gpio_count); gpio_flash_probe()
241 state->map.virt = ioremap_nocache(memory->start, state->map.size); gpio_flash_probe()
242 state->map.phys = NO_XIP; gpio_flash_probe()
243 state->map.map_priv_1 = (unsigned long)state; gpio_flash_probe()
245 platform_set_drvdata(pdev, state); gpio_flash_probe()
249 if (gpio_request(state->gpio_addrs[i], DRIVER_NAME)) { gpio_flash_probe()
251 state->gpio_addrs[i]); gpio_flash_probe()
253 gpio_free(state->gpio_addrs[i]); gpio_flash_probe()
254 kfree(state); gpio_flash_probe()
257 gpio_direction_output(state->gpio_addrs[i], 0); gpio_flash_probe()
258 } while (++i < state->gpio_count); gpio_flash_probe()
261 state->map.bankwidth * 8); gpio_flash_probe()
262 state->mtd = do_map_probe(memory->name, &state->map); gpio_flash_probe()
263 if (!state->mtd) { gpio_flash_probe()
264 for (i = 0; i < state->gpio_count; ++i) gpio_flash_probe()
265 gpio_free(state->gpio_addrs[i]); gpio_flash_probe()
266 kfree(state); gpio_flash_probe()
271 mtd_device_parse_register(state->mtd, part_probe_types, NULL, gpio_flash_probe()
279 struct async_state *state = platform_get_drvdata(pdev); gpio_flash_remove() local
282 gpio_free(state->gpio_addrs[i]); gpio_flash_remove()
283 } while (++i < state->gpio_count); gpio_flash_remove()
284 mtd_device_unregister(state->mtd); gpio_flash_remove()
285 map_destroy(state->mtd); gpio_flash_remove()
286 kfree(state); gpio_flash_remove()
/linux-4.1.27/drivers/media/pci/bt8xx/
H A Ddst.c58 state->bt->nr, __func__ , ##arg); \
61 state->bt->nr, __func__ , ##arg); \
64 state->bt->nr, __func__ , ##arg); \
67 state->bt->nr, __func__ , ##arg); \
74 static int dst_command(struct dst_state *state, u8 *data, u8 len);
76 static void dst_packsize(struct dst_state *state, int psize) dst_packsize() argument
81 bt878_device_control(state->bt, DST_IG_TS, &bits); dst_packsize()
84 static int dst_gpio_outb(struct dst_state *state, u32 mask, u32 enbb, dst_gpio_outb() argument
95 if ((err = bt878_device_control(state->bt, DST_IG_ENABLE, &enb)) < 0) { dst_gpio_outb()
107 if ((err = bt878_device_control(state->bt, DST_IG_WRITE, &bits)) < 0) { dst_gpio_outb()
115 static int dst_gpio_inb(struct dst_state *state, u8 *result) dst_gpio_inb() argument
121 if ((err = bt878_device_control(state->bt, DST_IG_READ, &rd_packet)) < 0) { dst_gpio_inb()
130 int rdc_reset_state(struct dst_state *state) rdc_reset_state() argument
132 dprintk(verbose, DST_INFO, 1, "Resetting state machine"); rdc_reset_state()
133 if (dst_gpio_outb(state, RDC_8820_INT, RDC_8820_INT, 0, NO_DELAY) < 0) { rdc_reset_state()
138 if (dst_gpio_outb(state, RDC_8820_INT, RDC_8820_INT, RDC_8820_INT, NO_DELAY) < 0) { rdc_reset_state()
148 static int rdc_8820_reset(struct dst_state *state) rdc_8820_reset() argument
151 if (dst_gpio_outb(state, RDC_8820_RESET, RDC_8820_RESET, 0, NO_DELAY) < 0) { rdc_8820_reset()
156 if (dst_gpio_outb(state, RDC_8820_RESET, RDC_8820_RESET, RDC_8820_RESET, DELAY) < 0) { rdc_8820_reset()
164 static int dst_pio_enable(struct dst_state *state) dst_pio_enable() argument
166 if (dst_gpio_outb(state, ~0, RDC_8820_PIO_0_ENABLE, 0, NO_DELAY) < 0) { dst_pio_enable()
175 int dst_pio_disable(struct dst_state *state) dst_pio_disable() argument
177 if (dst_gpio_outb(state, ~0, RDC_8820_PIO_0_DISABLE, RDC_8820_PIO_0_DISABLE, NO_DELAY) < 0) { dst_pio_disable()
181 if (state->type_flags & DST_TYPE_HAS_FW_1) dst_pio_disable()
188 int dst_wait_dst_ready(struct dst_state *state, u8 delay_mode) dst_wait_dst_ready() argument
194 if (dst_gpio_inb(state, &reply) < 0) { dst_wait_dst_ready()
210 int dst_error_recovery(struct dst_state *state) dst_error_recovery() argument
213 dst_pio_disable(state); dst_error_recovery()
215 dst_pio_enable(state); dst_error_recovery()
222 int dst_error_bailout(struct dst_state *state) dst_error_bailout() argument
225 rdc_8820_reset(state); dst_error_bailout()
226 dst_pio_disable(state); dst_error_bailout()
233 int dst_comm_init(struct dst_state *state) dst_comm_init() argument
236 if ((dst_pio_enable(state)) < 0) { dst_comm_init()
240 if ((rdc_reset_state(state)) < 0) { dst_comm_init()
244 if (state->type_flags & DST_TYPE_HAS_FW_1) dst_comm_init()
253 int write_dst(struct dst_state *state, u8 *data, u8 len) write_dst() argument
256 .addr = state->config->demod_address, write_dst()
271 if ((err = i2c_transfer(state->i2c, &msg, 1)) < 0) { write_dst()
273 dst_error_recovery(state); write_dst()
280 dst_error_bailout(state); write_dst()
289 int read_dst(struct dst_state *state, u8 *ret, u8 len) read_dst() argument
292 .addr = state->config->demod_address, read_dst()
302 if ((err = i2c_transfer(state->i2c, &msg, 1)) < 0) { read_dst()
304 dst_error_recovery(state); read_dst()
311 dst_error_bailout(state); read_dst()
325 static int dst_set_polarization(struct dst_state *state) dst_set_polarization() argument
327 switch (state->voltage) { dst_set_polarization()
330 state->tx_tuna[8] &= ~0x40; dst_set_polarization()
334 state->tx_tuna[8] |= 0x40; dst_set_polarization()
343 static int dst_set_freq(struct dst_state *state, u32 freq) dst_set_freq() argument
345 state->frequency = freq; dst_set_freq()
348 if (state->dst_type == DST_TYPE_IS_SAT) { dst_set_freq()
352 state->tx_tuna[2] = (freq >> 8); dst_set_freq()
353 state->tx_tuna[3] = (u8) freq; dst_set_freq()
354 state->tx_tuna[4] = 0x01; dst_set_freq()
355 state->tx_tuna[8] &= ~0x04; dst_set_freq()
356 if (state->type_flags & DST_TYPE_HAS_OBS_REGS) { dst_set_freq()
358 state->tx_tuna[8] |= 0x04; dst_set_freq()
360 } else if (state->dst_type == DST_TYPE_IS_TERR) { dst_set_freq()
364 state->tx_tuna[2] = (freq >> 16) & 0xff; dst_set_freq()
365 state->tx_tuna[3] = (freq >> 8) & 0xff; dst_set_freq()
366 state->tx_tuna[4] = (u8) freq; dst_set_freq()
367 } else if (state->dst_type == DST_TYPE_IS_CABLE) { dst_set_freq()
369 state->tx_tuna[2] = (freq >> 16) & 0xff; dst_set_freq()
370 state->tx_tuna[3] = (freq >> 8) & 0xff; dst_set_freq()
371 state->tx_tuna[4] = (u8) freq; dst_set_freq()
372 } else if (state->dst_type == DST_TYPE_IS_ATSC) { dst_set_freq()
376 state->tx_tuna[2] = (freq >> 16) & 0xff; dst_set_freq()
377 state->tx_tuna[3] = (freq >> 8) & 0xff; dst_set_freq()
378 state->tx_tuna[4] = (u8) freq; dst_set_freq()
379 state->tx_tuna[5] = 0x00; /* ATSC */ dst_set_freq()
380 state->tx_tuna[6] = 0x00; dst_set_freq()
381 if (state->dst_hw_cap & DST_TYPE_HAS_ANALOG) dst_set_freq()
382 state->tx_tuna[7] = 0x00; /* Digital */ dst_set_freq()
389 static int dst_set_bandwidth(struct dst_state *state, u32 bandwidth) dst_set_bandwidth() argument
391 state->bandwidth = bandwidth; dst_set_bandwidth()
393 if (state->dst_type != DST_TYPE_IS_TERR) dst_set_bandwidth()
398 if (state->dst_hw_cap & DST_TYPE_HAS_CA) dst_set_bandwidth()
399 state->tx_tuna[7] = 0x06; dst_set_bandwidth()
401 state->tx_tuna[6] = 0x06; dst_set_bandwidth()
402 state->tx_tuna[7] = 0x00; dst_set_bandwidth()
406 if (state->dst_hw_cap & DST_TYPE_HAS_CA) dst_set_bandwidth()
407 state->tx_tuna[7] = 0x07; dst_set_bandwidth()
409 state->tx_tuna[6] = 0x07; dst_set_bandwidth()
410 state->tx_tuna[7] = 0x00; dst_set_bandwidth()
414 if (state->dst_hw_cap & DST_TYPE_HAS_CA) dst_set_bandwidth()
415 state->tx_tuna[7] = 0x08; dst_set_bandwidth()
417 state->tx_tuna[6] = 0x08; dst_set_bandwidth()
418 state->tx_tuna[7] = 0x00; dst_set_bandwidth()
428 static int dst_set_inversion(struct dst_state *state, fe_spectral_inversion_t inversion) dst_set_inversion() argument
430 state->inversion = inversion; dst_set_inversion()
433 state->tx_tuna[8] &= ~0x80; dst_set_inversion()
436 state->tx_tuna[8] |= 0x80; dst_set_inversion()
445 static int dst_set_fec(struct dst_state *state, fe_code_rate_t fec) dst_set_fec() argument
447 state->fec = fec; dst_set_fec()
451 static fe_code_rate_t dst_get_fec(struct dst_state *state) dst_get_fec() argument
453 return state->fec; dst_get_fec()
456 static int dst_set_symbolrate(struct dst_state *state, u32 srate) dst_set_symbolrate() argument
461 state->symbol_rate = srate; dst_set_symbolrate()
462 if (state->dst_type == DST_TYPE_IS_TERR) { dst_set_symbolrate()
467 if (state->dst_type == DST_TYPE_IS_SAT) { dst_set_symbolrate()
468 if (state->type_flags & DST_TYPE_HAS_SYMDIV) { dst_set_symbolrate()
474 state->tx_tuna[5] = (u8) (symcalc >> 12); dst_set_symbolrate()
475 state->tx_tuna[6] = (u8) (symcalc >> 4); dst_set_symbolrate()
476 state->tx_tuna[7] = (u8) (symcalc << 4); dst_set_symbolrate()
478 state->tx_tuna[5] = (u8) (srate >> 16) & 0x7f; dst_set_symbolrate()
479 state->tx_tuna[6] = (u8) (srate >> 8); dst_set_symbolrate()
480 state->tx_tuna[7] = (u8) srate; dst_set_symbolrate()
482 state->tx_tuna[8] &= ~0x20; dst_set_symbolrate()
483 if (state->type_flags & DST_TYPE_HAS_OBS_REGS) { dst_set_symbolrate()
485 state->tx_tuna[8] |= 0x20; dst_set_symbolrate()
487 } else if (state->dst_type == DST_TYPE_IS_CABLE) { dst_set_symbolrate()
488 dprintk(verbose, DST_DEBUG, 1, "%s", state->fw_name); dst_set_symbolrate()
489 if (!strncmp(state->fw_name, "DCTNEW", 6)) { dst_set_symbolrate()
490 state->tx_tuna[5] = (u8) (srate >> 8); dst_set_symbolrate()
491 state->tx_tuna[6] = (u8) srate; dst_set_symbolrate()
492 state->tx_tuna[7] = 0x00; dst_set_symbolrate()
493 } else if (!strncmp(state->fw_name, "DCT-CI", 6)) { dst_set_symbolrate()
494 state->tx_tuna[5] = 0x00; dst_set_symbolrate()
495 state->tx_tuna[6] = (u8) (srate >> 8); dst_set_symbolrate()
496 state->tx_tuna[7] = (u8) srate; dst_set_symbolrate()
502 static int dst_set_modulation(struct dst_state *state, fe_modulation_t modulation) dst_set_modulation() argument
504 if (state->dst_type != DST_TYPE_IS_CABLE) dst_set_modulation()
507 state->modulation = modulation; dst_set_modulation()
510 state->tx_tuna[8] = 0x10; dst_set_modulation()
513 state->tx_tuna[8] = 0x20; dst_set_modulation()
516 state->tx_tuna[8] = 0x40; dst_set_modulation()
519 state->tx_tuna[8] = 0x80; dst_set_modulation()
522 if (!strncmp(state->fw_name, "DCTNEW", 6)) dst_set_modulation()
523 state->tx_tuna[8] = 0xff; dst_set_modulation()
524 else if (!strncmp(state->fw_name, "DCT-CI", 6)) dst_set_modulation()
525 state->tx_tuna[8] = 0x00; dst_set_modulation()
539 static fe_modulation_t dst_get_modulation(struct dst_state *state) dst_get_modulation() argument
541 return state->modulation; dst_get_modulation()
558 static void dst_type_flags_print(struct dst_state *state) dst_type_flags_print() argument
560 u32 type_flags = state->type_flags; dst_type_flags_print()
583 static int dst_type_print(struct dst_state *state, u8 type) dst_type_print() argument
910 static int dst_get_mac(struct dst_state *state) dst_get_mac() argument
914 if (dst_command(state, get_mac, 8) < 0) { dst_get_mac()
918 memset(&state->mac_address, '\0', 8); dst_get_mac()
919 memcpy(&state->mac_address, &state->rxbuffer, 6); dst_get_mac()
920 dprintk(verbose, DST_ERROR, 1, "MAC Address=[%pM]", state->mac_address); dst_get_mac()
925 static int dst_fw_ver(struct dst_state *state) dst_fw_ver() argument
929 if (dst_command(state, get_ver, 8) < 0) { dst_fw_ver()
933 memcpy(&state->fw_version, &state->rxbuffer, 8); dst_fw_ver()
935 state->fw_version[0] >> 4, state->fw_version[0] & 0x0f, dst_fw_ver()
936 state->fw_version[1], dst_fw_ver()
937 state->fw_version[5], state->fw_version[6], dst_fw_ver()
938 state->fw_version[4], state->fw_version[3], state->fw_version[2]); dst_fw_ver()
943 static int dst_card_type(struct dst_state *state) dst_card_type() argument
950 if (dst_command(state, get_type, 8) < 0) { dst_card_type()
954 memset(&state->card_info, '\0', 8); dst_card_type()
955 memcpy(&state->card_info, &state->rxbuffer, 7); dst_card_type()
956 dprintk(verbose, DST_ERROR, 1, "Device Model=[%s]", &state->card_info[0]); dst_card_type()
959 if (!strcmp(&state->card_info[0], p_tuner_list->board_name)) { dst_card_type()
960 state->tuner_type = p_tuner_list->tuner_type; dst_card_type()
969 static int dst_get_vendor(struct dst_state *state) dst_get_vendor() argument
973 if (dst_command(state, get_vendor, 8) < 0) { dst_get_vendor()
977 memset(&state->vendor, '\0', 8); dst_get_vendor()
978 memcpy(&state->vendor, &state->rxbuffer, 7); dst_get_vendor()
979 dprintk(verbose, DST_ERROR, 1, "Vendor=[%s]", &state->vendor[0]); dst_get_vendor()
984 static void debug_dst_buffer(struct dst_state *state) debug_dst_buffer() argument
991 printk(" %02x", state->rxbuffer[i]); debug_dst_buffer()
996 static int dst_check_stv0299(struct dst_state *state) dst_check_stv0299() argument
1001 if (dst_command(state, check_stv0299, 8) < 0) { dst_check_stv0299()
1005 debug_dst_buffer(state); dst_check_stv0299()
1007 if (memcmp(&check_stv0299, &state->rxbuffer, 8)) { dst_check_stv0299()
1009 state->tuner_type = TUNER_TYPE_STV0299; dst_check_stv0299()
1016 static int dst_check_mb86a15(struct dst_state *state) dst_check_mb86a15() argument
1021 if (dst_command(state, check_mb86a15, 8) < 0) { dst_check_mb86a15()
1025 debug_dst_buffer(state); dst_check_mb86a15()
1027 if (memcmp(&check_mb86a15, &state->rxbuffer, 8) < 0) { dst_check_mb86a15()
1029 state->tuner_type = TUNER_TYPE_MB86A15; dst_check_mb86a15()
1036 static int dst_get_tuner_info(struct dst_state *state) dst_get_tuner_info() argument
1044 if (state->type_flags & DST_TYPE_HAS_MULTI_FE) { dst_get_tuner_info()
1045 if (dst_command(state, get_tuner_1, 8) < 0) { dst_get_tuner_info()
1050 if (dst_command(state, get_tuner_2, 8) < 0) { dst_get_tuner_info()
1055 memcpy(&state->board_info, &state->rxbuffer, 8); dst_get_tuner_info()
1056 if (state->type_flags & DST_TYPE_HAS_MULTI_FE) { dst_get_tuner_info()
1059 if (state->board_info[0] == 0xbc) { dst_get_tuner_info()
1060 if (state->dst_type != DST_TYPE_IS_ATSC) dst_get_tuner_info()
1061 state->type_flags |= DST_TYPE_HAS_TS188; dst_get_tuner_info()
1063 state->type_flags |= DST_TYPE_HAS_NEWTUNE_2; dst_get_tuner_info()
1065 if (state->board_info[1] == 0x01) { dst_get_tuner_info()
1066 state->dst_hw_cap |= DST_TYPE_HAS_DBOARD; dst_get_tuner_info()
1073 if (!strncmp(state->fw_name, "DCT-CI", 6)) { dst_get_tuner_info()
1074 state->type_flags |= DST_TYPE_HAS_TS204; dst_get_tuner_info()
1075 dprintk(verbose, DST_ERROR, 1, "Forcing [%s] to TS188", state->fw_name); dst_get_tuner_info()
1081 static int dst_get_device_id(struct dst_state *state) dst_get_device_id() argument
1094 state->tuner_type = 0; dst_get_device_id()
1097 if (write_dst(state, device_type, FIXED_COMM)) dst_get_device_id()
1099 if ((dst_pio_disable(state)) < 0) dst_get_device_id()
1101 if (read_dst(state, &reply, GET_ACK)) dst_get_device_id()
1107 if (!dst_wait_dst_ready(state, DEVICE_INIT)) dst_get_device_id()
1109 if (read_dst(state, state->rxbuffer, FIXED_COMM)) dst_get_device_id()
1112 dst_pio_disable(state); dst_get_device_id()
1113 if (state->rxbuffer[7] != dst_check_sum(state->rxbuffer, 7)) { dst_get_device_id()
1117 state->rxbuffer[7] = '\0'; dst_get_device_id()
1120 if (!strncmp (&state->rxbuffer[p_dst_type->offset], p_dst_type->device_id, strlen (p_dst_type->device_id))) { dst_get_device_id()
1125 state->dst_hw_cap = p_dst_type->dst_feature; dst_get_device_id()
1127 strncpy(&state->fw_name[0], p_dst_type->device_id, 6); dst_get_device_id()
1133 if (dst_check_stv0299(state) < 0) { dst_get_device_id()
1135 state->tuner_type = TUNER_TYPE_MB86A15; dst_get_device_id()
1141 if (dst_check_mb86a15(state) < 0) dst_get_device_id()
1145 state->tuner_type = p_dst_type->tuner_type; dst_get_device_id()
1149 p_tuner_list->tuner_type == state->tuner_type) { dst_get_device_id()
1159 dprintk(verbose, DST_ERROR, 1, "Unable to recognize %s or %s", &state->rxbuffer[0], &state->rxbuffer[1]); dst_get_device_id()
1164 dst_type_print(state, use_dst_type); dst_get_device_id()
1165 state->type_flags = use_type_flags; dst_get_device_id()
1166 state->dst_type = use_dst_type; dst_get_device_id()
1167 dst_type_flags_print(state); dst_get_device_id()
1172 static int dst_probe(struct dst_state *state) dst_probe() argument
1174 mutex_init(&state->dst_mutex); dst_probe()
1176 if ((rdc_8820_reset(state)) < 0) { dst_probe()
1184 if ((dst_comm_init(state)) < 0) { dst_probe()
1189 if (dst_get_device_id(state) < 0) { dst_probe()
1193 if (dst_get_mac(state) < 0) { dst_probe()
1196 if ((state->type_flags & DST_TYPE_HAS_MULTI_FE) || (state->type_flags & DST_TYPE_HAS_FW_BUILD)) { dst_probe()
1197 if (dst_get_tuner_info(state) < 0) dst_probe()
1200 if (state->type_flags & DST_TYPE_HAS_TS204) { dst_probe()
1201 dst_packsize(state, 204); dst_probe()
1203 if (state->type_flags & DST_TYPE_HAS_FW_BUILD) { dst_probe()
1204 if (dst_fw_ver(state) < 0) { dst_probe()
1208 if (dst_card_type(state) < 0) { dst_probe()
1212 if (dst_get_vendor(state) < 0) { dst_probe()
1221 static int dst_command(struct dst_state *state, u8 *data, u8 len) dst_command() argument
1225 mutex_lock(&state->dst_mutex); dst_command()
1226 if ((dst_comm_init(state)) < 0) { dst_command()
1230 if (write_dst(state, data, len)) { dst_command()
1232 if ((dst_error_recovery(state)) < 0) { dst_command()
1238 if ((dst_pio_disable(state)) < 0) { dst_command()
1242 if (state->type_flags & DST_TYPE_HAS_FW_1) dst_command()
1244 if (read_dst(state, &reply, GET_ACK)) { dst_command()
1246 if ((dst_error_recovery(state)) < 0) { dst_command()
1258 if (state->type_flags & DST_TYPE_HAS_FW_1) dst_command()
1262 if (!dst_wait_dst_ready(state, NO_DELAY)) dst_command()
1264 if (read_dst(state, state->rxbuffer, FIXED_COMM)) { dst_command()
1266 if ((dst_error_recovery(state)) < 0) { dst_command()
1272 if (state->rxbuffer[7] != dst_check_sum(state->rxbuffer, 7)) { dst_command()
1276 mutex_unlock(&state->dst_mutex); dst_command()
1280 mutex_unlock(&state->dst_mutex); dst_command()
1285 static int dst_get_signal(struct dst_state *state) dst_get_signal() argument
1290 if ((state->diseq_flags & ATTEMPT_TUNE) == 0) { dst_get_signal()
1291 state->decode_lock = state->decode_strength = state->decode_snr = 0; dst_get_signal()
1294 if (0 == (state->diseq_flags & HAS_LOCK)) { dst_get_signal()
1295 state->decode_lock = state->decode_strength = state->decode_snr = 0; dst_get_signal()
1298 if (time_after_eq(jiffies, state->cur_jiff + (HZ / 5))) { dst_get_signal()
1299 retval = dst_command(state, get_signal, 8); dst_get_signal()
1302 if (state->dst_type == DST_TYPE_IS_SAT) { dst_get_signal()
1303 state->decode_lock = ((state->rxbuffer[6] & 0x10) == 0) ? 1 : 0; dst_get_signal()
1304 state->decode_strength = state->rxbuffer[5] << 8; dst_get_signal()
1305 state->decode_snr = state->rxbuffer[2] << 8 | state->rxbuffer[3]; dst_get_signal()
1306 } else if ((state->dst_type == DST_TYPE_IS_TERR) || (state->dst_type == DST_TYPE_IS_CABLE)) { dst_get_signal()
1307 state->decode_lock = (state->rxbuffer[1]) ? 1 : 0; dst_get_signal()
1308 state->decode_strength = state->rxbuffer[4] << 8; dst_get_signal()
1309 state->decode_snr = state->rxbuffer[3] << 8; dst_get_signal()
1310 } else if (state->dst_type == DST_TYPE_IS_ATSC) { dst_get_signal()
1311 state->decode_lock = (state->rxbuffer[6] == 0x00) ? 1 : 0; dst_get_signal()
1312 state->decode_strength = state->rxbuffer[4] << 8; dst_get_signal()
1313 state->decode_snr = state->rxbuffer[2] << 8 | state->rxbuffer[3]; dst_get_signal()
1315 state->cur_jiff = jiffies; dst_get_signal()
1320 static int dst_tone_power_cmd(struct dst_state *state) dst_tone_power_cmd() argument
1324 if (state->dst_type != DST_TYPE_IS_SAT) dst_tone_power_cmd()
1326 paket[4] = state->tx_tuna[4]; dst_tone_power_cmd()
1327 paket[2] = state->tx_tuna[2]; dst_tone_power_cmd()
1328 paket[3] = state->tx_tuna[3]; dst_tone_power_cmd()
1330 return dst_command(state, paket, 8); dst_tone_power_cmd()
1333 static int dst_get_tuna(struct dst_state *state) dst_get_tuna() argument
1337 if ((state->diseq_flags & ATTEMPT_TUNE) == 0) dst_get_tuna()
1339 state->diseq_flags &= ~(HAS_LOCK); dst_get_tuna()
1340 if (!dst_wait_dst_ready(state, NO_DELAY)) dst_get_tuna()
1342 if ((state->type_flags & DST_TYPE_HAS_VLF) && dst_get_tuna()
1343 !(state->dst_type == DST_TYPE_IS_ATSC)) dst_get_tuna()
1345 retval = read_dst(state, state->rx_tuna, 10); dst_get_tuna()
1347 retval = read_dst(state, &state->rx_tuna[2], FIXED_COMM); dst_get_tuna()
1352 if ((state->type_flags & DST_TYPE_HAS_VLF) && dst_get_tuna()
1353 !(state->dst_type == DST_TYPE_IS_ATSC)) { dst_get_tuna()
1355 if (state->rx_tuna[9] != dst_check_sum(&state->rx_tuna[0], 9)) { dst_get_tuna()
1360 if (state->rx_tuna[9] != dst_check_sum(&state->rx_tuna[2], 7)) { dst_get_tuna()
1365 if (state->rx_tuna[2] == 0 && state->rx_tuna[3] == 0) dst_get_tuna()
1367 if (state->dst_type == DST_TYPE_IS_SAT) { dst_get_tuna()
1368 state->decode_freq = ((state->rx_tuna[2] & 0x7f) << 8) + state->rx_tuna[3]; dst_get_tuna()
1370 state->decode_freq = ((state->rx_tuna[2] & 0x7f) << 16) + (state->rx_tuna[3] << 8) + state->rx_tuna[4]; dst_get_tuna()
1372 state->decode_freq = state->decode_freq * 1000; dst_get_tuna()
1373 state->decode_lock = 1; dst_get_tuna()
1374 state->diseq_flags |= HAS_LOCK; dst_get_tuna()
1383 struct dst_state *state = fe->demodulator_priv; dst_write_tuna() local
1387 dprintk(verbose, DST_INFO, 1, "type_flags 0x%x ", state->type_flags); dst_write_tuna()
1388 state->decode_freq = 0; dst_write_tuna()
1389 state->decode_lock = state->decode_strength = state->decode_snr = 0; dst_write_tuna()
1390 if (state->dst_type == DST_TYPE_IS_SAT) { dst_write_tuna()
1391 if (!(state->diseq_flags & HAS_POWER)) dst_write_tuna()
1394 state->diseq_flags &= ~(HAS_LOCK | ATTEMPT_TUNE); dst_write_tuna()
1395 mutex_lock(&state->dst_mutex); dst_write_tuna()
1396 if ((dst_comm_init(state)) < 0) { dst_write_tuna()
1400 // if (state->type_flags & DST_TYPE_HAS_NEWTUNE) { dst_write_tuna()
1401 if ((state->type_flags & DST_TYPE_HAS_VLF) && dst_write_tuna()
1402 (!(state->dst_type == DST_TYPE_IS_ATSC))) { dst_write_tuna()
1404 state->tx_tuna[9] = dst_check_sum(&state->tx_tuna[0], 9); dst_write_tuna()
1405 retval = write_dst(state, &state->tx_tuna[0], 10); dst_write_tuna()
1407 state->tx_tuna[9] = dst_check_sum(&state->tx_tuna[2], 7); dst_write_tuna()
1408 retval = write_dst(state, &state->tx_tuna[2], FIXED_COMM); dst_write_tuna()
1411 dst_pio_disable(state); dst_write_tuna()
1415 if ((dst_pio_disable(state)) < 0) { dst_write_tuna()
1419 if ((read_dst(state, &reply, GET_ACK) < 0)) { dst_write_tuna()
1427 state->diseq_flags |= ATTEMPT_TUNE; dst_write_tuna()
1428 retval = dst_get_tuna(state); dst_write_tuna()
1430 mutex_unlock(&state->dst_mutex); dst_write_tuna()
1434 mutex_unlock(&state->dst_mutex); dst_write_tuna()
1454 struct dst_state *state = fe->demodulator_priv; dst_set_diseqc() local
1457 if (state->dst_type != DST_TYPE_IS_SAT) dst_set_diseqc()
1461 else if (cmd->msg_len == 5 && state->dst_hw_cap & DST_TYPE_HAS_DISEQC5) dst_set_diseqc()
1466 return dst_command(state, paket, 8); dst_set_diseqc()
1472 struct dst_state *state = fe->demodulator_priv; dst_set_voltage() local
1474 state->voltage = voltage; dst_set_voltage()
1475 if (state->dst_type != DST_TYPE_IS_SAT) dst_set_voltage()
1483 if ((state->diseq_flags & HAS_POWER) == 0) dst_set_voltage()
1485 state->diseq_flags |= HAS_POWER; dst_set_voltage()
1486 state->tx_tuna[4] = 0x01; dst_set_voltage()
1490 state->diseq_flags &= ~(HAS_POWER | HAS_LOCK | ATTEMPT_TUNE); dst_set_voltage()
1491 state->tx_tuna[4] = 0x00; dst_set_voltage()
1498 retval = dst_tone_power_cmd(state); dst_set_voltage()
1505 struct dst_state *state = fe->demodulator_priv; dst_set_tone() local
1507 state->tone = tone; dst_set_tone()
1508 if (state->dst_type != DST_TYPE_IS_SAT) dst_set_tone()
1513 if (state->type_flags & DST_TYPE_HAS_OBS_REGS) dst_set_tone()
1514 state->tx_tuna[2] = 0x00; dst_set_tone()
1516 state->tx_tuna[2] = 0xff; dst_set_tone()
1520 state->tx_tuna[2] = 0x02; dst_set_tone()
1525 return dst_tone_power_cmd(state); dst_set_tone()
1530 struct dst_state *state = fe->demodulator_priv; dst_send_burst() local
1532 if (state->dst_type != DST_TYPE_IS_SAT) dst_send_burst()
1534 state->minicmd = minicmd; dst_send_burst()
1537 state->tx_tuna[3] = 0x02; dst_send_burst()
1540 state->tx_tuna[3] = 0xff; dst_send_burst()
1543 return dst_tone_power_cmd(state); dst_send_burst()
1549 struct dst_state *state = fe->demodulator_priv; bt8xx_dst_init() local
1559 state->inversion = INVERSION_OFF; bt8xx_dst_init()
1560 state->voltage = SEC_VOLTAGE_13; bt8xx_dst_init()
1561 state->tone = SEC_TONE_OFF; bt8xx_dst_init()
1562 state->diseq_flags = 0; bt8xx_dst_init()
1563 state->k22 = 0x02; bt8xx_dst_init()
1564 state->bandwidth = 7000000; bt8xx_dst_init()
1565 state->cur_jiff = jiffies; bt8xx_dst_init()
1566 if (state->dst_type == DST_TYPE_IS_SAT) bt8xx_dst_init()
1567 memcpy(state->tx_tuna, ((state->type_flags & DST_TYPE_HAS_VLF) ? sat_tuna_188 : sat_tuna_204), sizeof (sat_tuna_204)); bt8xx_dst_init()
1568 else if (state->dst_type == DST_TYPE_IS_TERR) bt8xx_dst_init()
1569 memcpy(state->tx_tuna, ((state->type_flags & DST_TYPE_HAS_VLF) ? ter_tuna_188 : ter_tuna_204), sizeof (ter_tuna_204)); bt8xx_dst_init()
1570 else if (state->dst_type == DST_TYPE_IS_CABLE) bt8xx_dst_init()
1571 memcpy(state->tx_tuna, ((state->type_flags & DST_TYPE_HAS_VLF) ? cab_tuna_188 : cab_tuna_204), sizeof (cab_tuna_204)); bt8xx_dst_init()
1572 else if (state->dst_type == DST_TYPE_IS_ATSC) bt8xx_dst_init()
1573 memcpy(state->tx_tuna, atsc_tuner, sizeof (atsc_tuner)); bt8xx_dst_init()
1580 struct dst_state *state = fe->demodulator_priv; dst_read_status() local
1583 if (state->diseq_flags & HAS_LOCK) { dst_read_status()
1584 // dst_get_signal(state); // don't require(?) to ask MCU dst_read_status()
1585 if (state->decode_lock) dst_read_status()
1594 struct dst_state *state = fe->demodulator_priv; dst_read_signal_strength() local
1596 int retval = dst_get_signal(state); dst_read_signal_strength()
1597 *strength = state->decode_strength; dst_read_signal_strength()
1604 struct dst_state *state = fe->demodulator_priv; dst_read_snr() local
1606 int retval = dst_get_signal(state); dst_read_snr()
1607 *snr = state->decode_snr; dst_read_snr()
1616 struct dst_state *state = fe->demodulator_priv; dst_set_frontend() local
1619 retval = dst_set_freq(state, p->frequency); dst_set_frontend()
1624 if (state->dst_type == DST_TYPE_IS_SAT) { dst_set_frontend()
1625 if (state->type_flags & DST_TYPE_HAS_OBS_REGS) dst_set_frontend()
1626 dst_set_inversion(state, p->inversion); dst_set_frontend()
1627 dst_set_fec(state, p->fec_inner); dst_set_frontend()
1628 dst_set_symbolrate(state, p->symbol_rate); dst_set_frontend()
1629 dst_set_polarization(state); dst_set_frontend()
1632 } else if (state->dst_type == DST_TYPE_IS_TERR) dst_set_frontend()
1633 dst_set_bandwidth(state, p->bandwidth_hz); dst_set_frontend()
1634 else if (state->dst_type == DST_TYPE_IS_CABLE) { dst_set_frontend()
1635 dst_set_fec(state, p->fec_inner); dst_set_frontend()
1636 dst_set_symbolrate(state, p->symbol_rate); dst_set_frontend()
1637 dst_set_modulation(state, p->modulation); dst_set_frontend()
1651 struct dst_state *state = fe->demodulator_priv; dst_tune_frontend() local
1655 dst_set_freq(state, p->frequency); dst_tune_frontend()
1658 if (state->dst_type == DST_TYPE_IS_SAT) { dst_tune_frontend()
1659 if (state->type_flags & DST_TYPE_HAS_OBS_REGS) dst_tune_frontend()
1660 dst_set_inversion(state, p->inversion); dst_tune_frontend()
1661 dst_set_fec(state, p->fec_inner); dst_tune_frontend()
1662 dst_set_symbolrate(state, p->symbol_rate); dst_tune_frontend()
1663 dst_set_polarization(state); dst_tune_frontend()
1666 } else if (state->dst_type == DST_TYPE_IS_TERR) dst_tune_frontend()
1667 dst_set_bandwidth(state, p->bandwidth_hz); dst_tune_frontend()
1668 else if (state->dst_type == DST_TYPE_IS_CABLE) { dst_tune_frontend()
1669 dst_set_fec(state, p->fec_inner); dst_tune_frontend()
1670 dst_set_symbolrate(state, p->symbol_rate); dst_tune_frontend()
1671 dst_set_modulation(state, p->modulation); dst_tune_frontend()
1691 struct dst_state *state = fe->demodulator_priv; dst_get_frontend() local
1693 p->frequency = state->decode_freq; dst_get_frontend()
1694 if (state->dst_type == DST_TYPE_IS_SAT) { dst_get_frontend()
1695 if (state->type_flags & DST_TYPE_HAS_OBS_REGS) dst_get_frontend()
1696 p->inversion = state->inversion; dst_get_frontend()
1697 p->symbol_rate = state->symbol_rate; dst_get_frontend()
1698 p->fec_inner = dst_get_fec(state); dst_get_frontend()
1699 } else if (state->dst_type == DST_TYPE_IS_TERR) { dst_get_frontend()
1700 p->bandwidth_hz = state->bandwidth; dst_get_frontend()
1701 } else if (state->dst_type == DST_TYPE_IS_CABLE) { dst_get_frontend()
1702 p->symbol_rate = state->symbol_rate; dst_get_frontend()
1703 p->fec_inner = dst_get_fec(state); dst_get_frontend()
1704 p->modulation = dst_get_modulation(state); dst_get_frontend()
1712 struct dst_state *state = fe->demodulator_priv; bt8xx_dst_release() local
1713 if (state->dst_ca) { bt8xx_dst_release()
1714 dvb_unregister_device(state->dst_ca); bt8xx_dst_release()
1719 kfree(state); bt8xx_dst_release()
1727 struct dst_state *dst_attach(struct dst_state *state, struct dvb_adapter *dvb_adapter) dst_attach() argument
1730 if (dst_probe(state) < 0) { dst_attach()
1731 kfree(state); dst_attach()
1736 switch (state->dst_type) { dst_attach()
1738 memcpy(&state->frontend.ops, &dst_dvbt_ops, sizeof(struct dvb_frontend_ops)); dst_attach()
1741 memcpy(&state->frontend.ops, &dst_dvbc_ops, sizeof(struct dvb_frontend_ops)); dst_attach()
1744 memcpy(&state->frontend.ops, &dst_dvbs_ops, sizeof(struct dvb_frontend_ops)); dst_attach()
1747 memcpy(&state->frontend.ops, &dst_atsc_ops, sizeof(struct dvb_frontend_ops)); dst_attach()
1751 kfree(state); dst_attach()
1754 state->frontend.demodulator_priv = state; dst_attach()
1756 return state; /* Manu (DST is a card not a frontend) */ dst_attach()
/linux-4.1.27/drivers/acpi/acpica/
H A Dutstate.c3 * Module Name: utstate - state object support procedures
54 * PARAMETERS: list_head - Head of the state stack
55 * state - State object to push
59 * DESCRIPTION: Push a state object onto a state stack
64 union acpi_generic_state *state) acpi_ut_push_generic_state()
68 /* Push the state object onto the front of the list (stack) */ acpi_ut_push_generic_state()
70 state->common.next = *list_head; acpi_ut_push_generic_state()
71 *list_head = state; acpi_ut_push_generic_state()
79 * PARAMETERS: list_head - Head of the state stack
81 * RETURN: The popped state object
83 * DESCRIPTION: Pop a state object from a state stack
90 union acpi_generic_state *state; acpi_ut_pop_generic_state() local
94 /* Remove the state object at the head of the list (stack) */ acpi_ut_pop_generic_state()
96 state = *list_head; acpi_ut_pop_generic_state()
97 if (state) { acpi_ut_pop_generic_state()
101 *list_head = state->common.next; acpi_ut_pop_generic_state()
104 return (state); acpi_ut_pop_generic_state()
113 * RETURN: The new state object. NULL on failure.
115 * DESCRIPTION: Create a generic state object. Attempt to obtain one from
116 * the global state cache; If none available, create a new one.
122 union acpi_generic_state *state; acpi_ut_create_generic_state() local
126 state = acpi_os_acquire_object(acpi_gbl_state_cache); acpi_ut_create_generic_state()
127 if (state) { acpi_ut_create_generic_state()
130 state->common.descriptor_type = ACPI_DESC_TYPE_STATE; acpi_ut_create_generic_state()
133 return (state); acpi_ut_create_generic_state()
144 * DESCRIPTION: Create a "Thread State" - a flavor of the generic state used
151 union acpi_generic_state *state; acpi_ut_create_thread_state() local
155 /* Create the generic state object */ acpi_ut_create_thread_state()
157 state = acpi_ut_create_generic_state(); acpi_ut_create_thread_state()
158 if (!state) { acpi_ut_create_thread_state()
164 state->common.descriptor_type = ACPI_DESC_TYPE_STATE_THREAD; acpi_ut_create_thread_state()
165 state->thread.thread_id = acpi_os_get_thread_id(); acpi_ut_create_thread_state()
169 if (!state->thread.thread_id) { acpi_ut_create_thread_state()
171 state->thread.thread_id = (acpi_thread_id) 1; acpi_ut_create_thread_state()
174 return ((struct acpi_thread_state *)state); acpi_ut_create_thread_state()
181 * PARAMETERS: object - Initial Object to be installed in the state
184 * RETURN: New state object, null on failure
186 * DESCRIPTION: Create an "Update State" - a flavor of the generic state used
195 union acpi_generic_state *state; acpi_ut_create_update_state() local
199 /* Create the generic state object */ acpi_ut_create_update_state()
201 state = acpi_ut_create_generic_state(); acpi_ut_create_update_state()
202 if (!state) { acpi_ut_create_update_state()
208 state->common.descriptor_type = ACPI_DESC_TYPE_STATE_UPDATE; acpi_ut_create_update_state()
209 state->update.object = object; acpi_ut_create_update_state()
210 state->update.value = action; acpi_ut_create_update_state()
211 return (state); acpi_ut_create_update_state()
218 * PARAMETERS: object - Initial Object to be installed in the state
221 * RETURN: New state object, null on failure
231 union acpi_generic_state *state; acpi_ut_create_pkg_state() local
235 /* Create the generic state object */ acpi_ut_create_pkg_state()
237 state = acpi_ut_create_generic_state(); acpi_ut_create_pkg_state()
238 if (!state) { acpi_ut_create_pkg_state()
244 state->common.descriptor_type = ACPI_DESC_TYPE_STATE_PACKAGE; acpi_ut_create_pkg_state()
245 state->pkg.source_object = (union acpi_operand_object *)internal_object; acpi_ut_create_pkg_state()
246 state->pkg.dest_object = external_object; acpi_ut_create_pkg_state()
247 state->pkg.index = index; acpi_ut_create_pkg_state()
248 state->pkg.num_packages = 1; acpi_ut_create_pkg_state()
249 return (state); acpi_ut_create_pkg_state()
258 * RETURN: New state object, null on failure
260 * DESCRIPTION: Create a "Control State" - a flavor of the generic state used
267 union acpi_generic_state *state; acpi_ut_create_control_state() local
271 /* Create the generic state object */ acpi_ut_create_control_state()
273 state = acpi_ut_create_generic_state(); acpi_ut_create_control_state()
274 if (!state) { acpi_ut_create_control_state()
280 state->common.descriptor_type = ACPI_DESC_TYPE_STATE_CONTROL; acpi_ut_create_control_state()
281 state->common.state = ACPI_CONTROL_CONDITIONAL_EXECUTING; acpi_ut_create_control_state()
282 return (state); acpi_ut_create_control_state()
289 * PARAMETERS: state - The state object to be deleted
293 * DESCRIPTION: Release a state object to the state cache. NULL state objects
298 void acpi_ut_delete_generic_state(union acpi_generic_state *state) acpi_ut_delete_generic_state() argument
302 /* Ignore null state */ acpi_ut_delete_generic_state()
304 if (state) { acpi_ut_delete_generic_state()
305 (void)acpi_os_release_object(acpi_gbl_state_cache, state); acpi_ut_delete_generic_state()
63 acpi_ut_push_generic_state(union acpi_generic_state **list_head, union acpi_generic_state *state) acpi_ut_push_generic_state() argument
H A Ddswstate.c63 * walk_state - Current Walk state
76 union acpi_generic_state *state; acpi_ds_result_pop() local
81 state = walk_state->results; acpi_ds_result_pop()
83 /* Incorrect state of result stack */ acpi_ds_result_pop()
85 if (state && !walk_state->result_count) { acpi_ds_result_pop()
90 if (!state && walk_state->result_count) { acpi_ds_result_pop()
91 ACPI_ERROR((AE_INFO, "No result state for result stack")); acpi_ds_result_pop()
97 if (!state) { acpi_ds_result_pop()
108 *object = state->results.obj_desc[index]; acpi_ds_result_pop()
116 state->results.obj_desc[index] = NULL; acpi_ds_result_pop()
137 * walk_state - Current Walk state
149 union acpi_generic_state *state; acpi_ds_result_push() local
175 state = walk_state->results; acpi_ds_result_push()
176 if (!state) { acpi_ds_result_push()
191 state->results.obj_desc[index] = object; acpi_ds_result_push()
209 * PARAMETERS: walk_state - Current Walk state
219 union acpi_generic_state *state; acpi_ds_result_stack_push() local
232 state = acpi_ut_create_generic_state(); acpi_ds_result_stack_push()
233 if (!state) { acpi_ds_result_stack_push()
237 state->common.descriptor_type = ACPI_DESC_TYPE_STATE_RESULT; acpi_ds_result_stack_push()
238 acpi_ut_push_generic_state(&walk_state->results, state); acpi_ds_result_stack_push()
245 state, walk_state)); acpi_ds_result_stack_push()
254 * PARAMETERS: walk_state - Current Walk state
264 union acpi_generic_state *state; acpi_ds_result_stack_pop() local
282 state = acpi_ut_pop_generic_state(&walk_state->results); acpi_ds_result_stack_pop()
283 acpi_ut_delete_generic_state(state); acpi_ds_result_stack_pop()
291 state, walk_state->result_count, walk_state)); acpi_ds_result_stack_pop()
301 * walk_state - Current Walk state
347 * walk_state - Current Walk state
392 * walk_state - Current Walk state
437 * PARAMETERS: thread - Get current active state for this Thread
439 * RETURN: Pointer to the current walk state
441 * DESCRIPTION: Get the walk state that is at the head of the list (the "current"
442 * walk state.)
466 * thread - Thread state object
470 * DESCRIPTION: Place the Thread state at the head of the state list
490 * PARAMETERS: thread - Current thread state
510 /* Next walk state becomes the current walk state */ acpi_ds_pop_walk_state()
531 * thread - Current thread state
533 * RETURN: Pointer to the new walk state.
535 * DESCRIPTION: Allocate and initialize a new walk state. The current walk
536 * state is set to this new state.
571 /* Put the new state at the head of the walk list */ acpi_ds_create_walk_state()
584 * PARAMETERS: walk_state - New state to be initialized
594 * DESCRIPTION: Initialize a walk state for a pass 1 or 2 parse tree walk
700 * DESCRIPTION: Delete a walk state including all internal data structures
706 union acpi_generic_state *state; acpi_ds_delete_walk_state() local
715 ACPI_ERROR((AE_INFO, "%p is not a valid walk state", acpi_ds_delete_walk_state()
731 state = walk_state->control_state; acpi_ds_delete_walk_state()
732 walk_state->control_state = state->common.next; acpi_ds_delete_walk_state()
734 acpi_ut_delete_generic_state(state); acpi_ds_delete_walk_state()
740 state = walk_state->scope_info; acpi_ds_delete_walk_state()
741 walk_state->scope_info = state->common.next; acpi_ds_delete_walk_state()
743 acpi_ut_delete_generic_state(state); acpi_ds_delete_walk_state()
749 state = walk_state->results; acpi_ds_delete_walk_state()
750 walk_state->results = state->common.next; acpi_ds_delete_walk_state()
752 acpi_ut_delete_generic_state(state); acpi_ds_delete_walk_state()
/linux-4.1.27/drivers/media/i2c/
H A Ds5k5baf.c422 static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr) s5k5baf_i2c_read() argument
424 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); s5k5baf_i2c_read()
435 if (state->error) s5k5baf_i2c_read()
446 state->error = ret; s5k5baf_i2c_read()
451 static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val) s5k5baf_i2c_write() argument
454 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); s5k5baf_i2c_write()
457 if (state->error) s5k5baf_i2c_write()
465 state->error = ret; s5k5baf_i2c_write()
469 static u16 s5k5baf_read(struct s5k5baf *state, u16 addr) s5k5baf_read() argument
471 s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr); s5k5baf_read()
472 return s5k5baf_i2c_read(state, REG_CMD_BUF); s5k5baf_read()
475 static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val) s5k5baf_write() argument
477 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr); s5k5baf_write()
478 s5k5baf_i2c_write(state, REG_CMD_BUF, val); s5k5baf_write()
481 static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr, s5k5baf_write_arr_seq() argument
484 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); s5k5baf_write_arr_seq()
487 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr); s5k5baf_write_arr_seq()
488 if (state->error) s5k5baf_write_arr_seq()
507 state->error = ret; s5k5baf_write_arr_seq()
515 #define s5k5baf_write_seq(state, addr, seq...) \
516 s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \
530 static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq) s5k5baf_write_nseq() argument
538 s5k5baf_write_arr_seq(state, addr, count, nseq); s5k5baf_write_nseq()
543 static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr) s5k5baf_synchronize() argument
548 s5k5baf_write(state, addr, 1); s5k5baf_synchronize()
550 reg = s5k5baf_read(state, addr); s5k5baf_synchronize()
551 if (state->error || !reg) s5k5baf_synchronize()
556 v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr); s5k5baf_synchronize()
557 state->error = -ETIMEDOUT; s5k5baf_synchronize()
560 static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id) s5k5baf_fw_get_seq() argument
562 struct s5k5baf_fw *fw = state->fw; s5k5baf_fw_get_seq()
579 static void s5k5baf_hw_patch(struct s5k5baf *state) s5k5baf_hw_patch() argument
581 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH); s5k5baf_hw_patch()
584 s5k5baf_write_nseq(state, seq); s5k5baf_hw_patch()
587 static void s5k5baf_hw_set_clocks(struct s5k5baf *state) s5k5baf_hw_set_clocks() argument
589 unsigned long mclk = state->mclk_frequency / 1000; s5k5baf_hw_set_clocks()
600 s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16); s5k5baf_hw_set_clocks()
601 s5k5baf_write_nseq(state, nseq_clk_cfg); s5k5baf_hw_set_clocks()
603 s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED); s5k5baf_hw_set_clocks()
604 status = s5k5baf_read(state, REG_I_ERROR_INFO); s5k5baf_hw_set_clocks()
605 if (!state->error && status) { s5k5baf_hw_set_clocks()
606 v4l2_err(&state->sd, "error configuring PLL (%d)\n", status); s5k5baf_hw_set_clocks()
607 state->error = -EINVAL; s5k5baf_hw_set_clocks()
612 static void s5k5baf_hw_set_ccm(struct s5k5baf *state) s5k5baf_hw_set_ccm() argument
614 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM); s5k5baf_hw_set_ccm()
617 s5k5baf_write_nseq(state, seq); s5k5baf_hw_set_ccm()
621 static void s5k5baf_hw_set_cis(struct s5k5baf *state) s5k5baf_hw_set_cis() argument
623 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS); s5k5baf_hw_set_cis()
628 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW); s5k5baf_hw_set_cis()
629 s5k5baf_write_nseq(state, seq); s5k5baf_hw_set_cis()
630 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW); s5k5baf_hw_set_cis()
633 static void s5k5baf_hw_sync_cfg(struct s5k5baf *state) s5k5baf_hw_sync_cfg() argument
635 s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1); s5k5baf_hw_sync_cfg()
636 if (state->apply_crop) { s5k5baf_hw_sync_cfg()
637 s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1); s5k5baf_hw_sync_cfg()
638 s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1); s5k5baf_hw_sync_cfg()
640 s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC); s5k5baf_hw_sync_cfg()
643 static void s5k5baf_hw_set_mirror(struct s5k5baf *state) s5k5baf_hw_set_mirror() argument
645 u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1); s5k5baf_hw_set_mirror()
647 s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip); s5k5baf_hw_set_mirror()
648 if (state->streaming) s5k5baf_hw_set_mirror()
649 s5k5baf_hw_sync_cfg(state); s5k5baf_hw_set_mirror()
652 static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable) s5k5baf_hw_set_alg() argument
656 if (!state->valid_auto_alg) s5k5baf_hw_set_alg()
657 cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN); s5k5baf_hw_set_alg()
659 cur_alg = state->auto_alg; s5k5baf_hw_set_alg()
664 s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg); s5k5baf_hw_set_alg()
666 if (state->error) s5k5baf_hw_set_alg()
669 state->valid_auto_alg = 1; s5k5baf_hw_set_alg()
670 state->auto_alg = new_alg; s5k5baf_hw_set_alg()
674 static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb) s5k5baf_hw_set_awb() argument
676 struct s5k5baf_ctrls *ctrls = &state->ctrls; s5k5baf_hw_set_awb()
679 s5k5baf_write_seq(state, REG_SF_RGAIN, s5k5baf_hw_set_awb()
685 s5k5baf_hw_set_alg(state, AALG_WB_EN, awb); s5k5baf_hw_set_awb()
689 static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure) s5k5baf_hw_set_user_exposure() argument
693 s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L, s5k5baf_hw_set_user_exposure()
697 static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain) s5k5baf_hw_set_user_gain() argument
699 s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1); s5k5baf_hw_set_user_gain()
703 static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value) s5k5baf_hw_set_auto_exposure() argument
706 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true); s5k5baf_hw_set_auto_exposure()
708 unsigned int exp_time = state->ctrls.exposure->val; s5k5baf_hw_set_auto_exposure()
710 s5k5baf_hw_set_user_exposure(state, exp_time); s5k5baf_hw_set_auto_exposure()
711 s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val); s5k5baf_hw_set_auto_exposure()
712 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false); s5k5baf_hw_set_auto_exposure()
716 static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v) s5k5baf_hw_set_anti_flicker() argument
719 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true); s5k5baf_hw_set_anti_flicker()
723 s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1); s5k5baf_hw_set_anti_flicker()
724 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false); s5k5baf_hw_set_anti_flicker()
728 static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val) s5k5baf_hw_set_colorfx() argument
739 s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]); s5k5baf_hw_set_colorfx()
757 static int s5k5baf_clear_error(struct s5k5baf *state) s5k5baf_clear_error() argument
759 int ret = state->error; s5k5baf_clear_error()
761 state->error = 0; s5k5baf_clear_error()
765 static int s5k5baf_hw_set_video_bus(struct s5k5baf *state) s5k5baf_hw_set_video_bus() argument
769 if (state->bus_type == V4L2_MBUS_CSI2) s5k5baf_hw_set_video_bus()
774 s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES, s5k5baf_hw_set_video_bus()
775 state->nlanes, en_pkts, 1); s5k5baf_hw_set_video_bus()
777 return s5k5baf_clear_error(state); s5k5baf_hw_set_video_bus()
780 static u16 s5k5baf_get_cfg_error(struct s5k5baf *state) s5k5baf_get_cfg_error() argument
782 u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR); s5k5baf_get_cfg_error()
784 s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0); s5k5baf_get_cfg_error()
788 static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv) s5k5baf_hw_set_fiv() argument
790 s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv); s5k5baf_hw_set_fiv()
791 s5k5baf_hw_sync_cfg(state); s5k5baf_hw_set_fiv()
794 static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state) s5k5baf_hw_find_min_fiv() argument
799 fiv = s5k5baf_read(state, REG_G_ACTUAL_P_FR_TIME); s5k5baf_hw_find_min_fiv()
800 if (state->error) s5k5baf_hw_find_min_fiv()
804 s5k5baf_hw_set_fiv(state, fiv); s5k5baf_hw_find_min_fiv()
805 err = s5k5baf_get_cfg_error(state); s5k5baf_hw_find_min_fiv()
806 if (state->error) s5k5baf_hw_find_min_fiv()
813 state->fiv = fiv; s5k5baf_hw_find_min_fiv()
814 v4l2_info(&state->sd, s5k5baf_hw_find_min_fiv()
818 v4l2_err(&state->sd, s5k5baf_hw_find_min_fiv()
820 state->error = -EINVAL; s5k5baf_hw_find_min_fiv()
823 v4l2_err(&state->sd, "cannot find correct frame interval\n"); s5k5baf_hw_find_min_fiv()
824 state->error = -ERANGE; s5k5baf_hw_find_min_fiv()
827 static void s5k5baf_hw_validate_cfg(struct s5k5baf *state) s5k5baf_hw_validate_cfg() argument
831 err = s5k5baf_get_cfg_error(state); s5k5baf_hw_validate_cfg()
832 if (state->error) s5k5baf_hw_validate_cfg()
837 state->apply_cfg = 1; s5k5baf_hw_validate_cfg()
840 s5k5baf_hw_find_min_fiv(state); s5k5baf_hw_validate_cfg()
841 if (!state->error) s5k5baf_hw_validate_cfg()
842 state->apply_cfg = 1; s5k5baf_hw_validate_cfg()
845 v4l2_err(&state->sd, s5k5baf_hw_validate_cfg()
847 state->error = -EINVAL; s5k5baf_hw_validate_cfg()
861 static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state) s5k5baf_hw_set_crop_rects() argument
867 p = &state->crop_sink; s5k5baf_hw_set_crop_rects()
868 s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height, s5k5baf_hw_set_crop_rects()
871 s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink, s5k5baf_hw_set_crop_rects()
872 &state->compose); s5k5baf_hw_set_crop_rects()
873 s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height, s5k5baf_hw_set_crop_rects()
876 s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ); s5k5baf_hw_set_crop_rects()
877 s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED); s5k5baf_hw_set_crop_rects()
878 err = s5k5baf_get_cfg_error(state); s5k5baf_hw_set_crop_rects()
879 ret = s5k5baf_clear_error(state); s5k5baf_hw_set_crop_rects()
888 s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME); s5k5baf_hw_set_crop_rects()
889 err = s5k5baf_get_cfg_error(state); s5k5baf_hw_set_crop_rects()
890 ret = s5k5baf_clear_error(state); s5k5baf_hw_set_crop_rects()
894 v4l2_err(&state->sd, s5k5baf_hw_set_crop_rects()
896 state->error = -EINVAL; s5k5baf_hw_set_crop_rects()
898 s5k5baf_hw_set_fiv(state, state->req_fiv); s5k5baf_hw_set_crop_rects()
899 s5k5baf_hw_validate_cfg(state); s5k5baf_hw_set_crop_rects()
902 v4l2_err(&state->sd, "crop error: %d\n", err); s5k5baf_hw_set_crop_rects()
906 if (!state->apply_cfg) s5k5baf_hw_set_crop_rects()
909 p = &state->crop_source; s5k5baf_hw_set_crop_rects()
910 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height); s5k5baf_hw_set_crop_rects()
911 s5k5baf_hw_set_fiv(state, state->req_fiv); s5k5baf_hw_set_crop_rects()
912 s5k5baf_hw_validate_cfg(state); s5k5baf_hw_set_crop_rects()
914 return s5k5baf_clear_error(state); s5k5baf_hw_set_crop_rects()
917 static void s5k5baf_hw_set_config(struct s5k5baf *state) s5k5baf_hw_set_config() argument
919 u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt; s5k5baf_hw_set_config()
920 struct v4l2_rect *r = &state->crop_source; s5k5baf_hw_set_config()
922 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), s5k5baf_hw_set_config()
927 state->req_fiv, S5K5BAF_MIN_FR_TIME); s5k5baf_hw_set_config()
928 s5k5baf_hw_sync_cfg(state); s5k5baf_hw_set_config()
929 s5k5baf_hw_validate_cfg(state); s5k5baf_hw_set_config()
933 static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id) s5k5baf_hw_set_test_pattern() argument
935 s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800); s5k5baf_hw_set_test_pattern()
936 s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511); s5k5baf_hw_set_test_pattern()
937 s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0); s5k5baf_hw_set_test_pattern()
938 s5k5baf_i2c_write(state, REG_PATTERN_SET, id); s5k5baf_hw_set_test_pattern()
941 static void s5k5baf_gpio_assert(struct s5k5baf *state, int id) s5k5baf_gpio_assert() argument
943 struct s5k5baf_gpio *gpio = &state->gpios[id]; s5k5baf_gpio_assert()
948 static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id) s5k5baf_gpio_deassert() argument
950 struct s5k5baf_gpio *gpio = &state->gpios[id]; s5k5baf_gpio_deassert()
955 static int s5k5baf_power_on(struct s5k5baf *state) s5k5baf_power_on() argument
959 ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies); s5k5baf_power_on()
963 ret = clk_set_rate(state->clock, state->mclk_frequency); s5k5baf_power_on()
967 ret = clk_prepare_enable(state->clock); s5k5baf_power_on()
971 v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n", s5k5baf_power_on()
972 clk_get_rate(state->clock)); s5k5baf_power_on()
974 s5k5baf_gpio_deassert(state, STBY); s5k5baf_power_on()
976 s5k5baf_gpio_deassert(state, RST); s5k5baf_power_on()
980 regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies); s5k5baf_power_on()
982 v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret); s5k5baf_power_on()
986 static int s5k5baf_power_off(struct s5k5baf *state) s5k5baf_power_off() argument
990 state->streaming = 0; s5k5baf_power_off()
991 state->apply_cfg = 0; s5k5baf_power_off()
992 state->apply_crop = 0; s5k5baf_power_off()
994 s5k5baf_gpio_assert(state, RST); s5k5baf_power_off()
995 s5k5baf_gpio_assert(state, STBY); s5k5baf_power_off()
997 if (!IS_ERR(state->clock)) s5k5baf_power_off()
998 clk_disable_unprepare(state->clock); s5k5baf_power_off()
1001 state->supplies); s5k5baf_power_off()
1003 v4l2_err(&state->sd, "failed to disable regulators\n"); s5k5baf_power_off()
1008 static void s5k5baf_hw_init(struct s5k5baf *state) s5k5baf_hw_init() argument
1010 s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW); s5k5baf_hw_init()
1011 s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0); s5k5baf_hw_init()
1012 s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1); s5k5baf_hw_init()
1013 s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW); s5k5baf_hw_init()
1014 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW); s5k5baf_hw_init()
1021 static void s5k5baf_initialize_data(struct s5k5baf *state) s5k5baf_initialize_data() argument
1023 state->pixfmt = 0; s5k5baf_initialize_data()
1024 state->req_fiv = 10000 / 15; s5k5baf_initialize_data()
1025 state->fiv = state->req_fiv; s5k5baf_initialize_data()
1026 state->valid_auto_alg = 0; s5k5baf_initialize_data()
1029 static int s5k5baf_load_setfile(struct s5k5baf *state) s5k5baf_load_setfile() argument
1031 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); s5k5baf_load_setfile()
1042 ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2, s5k5baf_load_setfile()
1052 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_set_power() local
1055 mutex_lock(&state->lock); s5k5baf_set_power()
1057 if (!on != state->power) s5k5baf_set_power()
1061 if (state->fw == NULL) s5k5baf_set_power()
1062 s5k5baf_load_setfile(state); s5k5baf_set_power()
1064 s5k5baf_initialize_data(state); s5k5baf_set_power()
1065 ret = s5k5baf_power_on(state); s5k5baf_set_power()
1069 s5k5baf_hw_init(state); s5k5baf_set_power()
1070 s5k5baf_hw_patch(state); s5k5baf_set_power()
1071 s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1); s5k5baf_set_power()
1072 s5k5baf_hw_set_clocks(state); s5k5baf_set_power()
1074 ret = s5k5baf_hw_set_video_bus(state); s5k5baf_set_power()
1078 s5k5baf_hw_set_cis(state); s5k5baf_set_power()
1079 s5k5baf_hw_set_ccm(state); s5k5baf_set_power()
1081 ret = s5k5baf_clear_error(state); s5k5baf_set_power()
1083 state->power++; s5k5baf_set_power()
1085 s5k5baf_power_off(state); s5k5baf_set_power()
1086 state->power--; s5k5baf_set_power()
1090 mutex_unlock(&state->lock); s5k5baf_set_power()
1093 ret = v4l2_ctrl_handler_setup(&state->ctrls.handler); s5k5baf_set_power()
1098 static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable) s5k5baf_hw_set_stream() argument
1100 s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1); s5k5baf_hw_set_stream()
1105 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_s_stream() local
1108 mutex_lock(&state->lock); s5k5baf_s_stream()
1110 if (state->streaming == !!on) { s5k5baf_s_stream()
1116 s5k5baf_hw_set_config(state); s5k5baf_s_stream()
1117 ret = s5k5baf_hw_set_crop_rects(state); s5k5baf_s_stream()
1120 s5k5baf_hw_set_stream(state, 1); s5k5baf_s_stream()
1121 s5k5baf_i2c_write(state, 0xb0cc, 0x000b); s5k5baf_s_stream()
1123 s5k5baf_hw_set_stream(state, 0); s5k5baf_s_stream()
1125 ret = s5k5baf_clear_error(state); s5k5baf_s_stream()
1127 state->streaming = !state->streaming; s5k5baf_s_stream()
1130 mutex_unlock(&state->lock); s5k5baf_s_stream()
1138 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_g_frame_interval() local
1140 mutex_lock(&state->lock); s5k5baf_g_frame_interval()
1141 fi->interval.numerator = state->fiv; s5k5baf_g_frame_interval()
1143 mutex_unlock(&state->lock); s5k5baf_g_frame_interval()
1148 static void s5k5baf_set_frame_interval(struct s5k5baf *state, s5k5baf_set_frame_interval() argument
1154 state->req_fiv = S5K5BAF_MAX_FR_TIME; s5k5baf_set_frame_interval()
1156 state->req_fiv = clamp_t(u32, s5k5baf_set_frame_interval()
1161 state->fiv = state->req_fiv; s5k5baf_set_frame_interval()
1162 if (state->apply_cfg) { s5k5baf_set_frame_interval()
1163 s5k5baf_hw_set_fiv(state, state->req_fiv); s5k5baf_set_frame_interval()
1164 s5k5baf_hw_validate_cfg(state); s5k5baf_set_frame_interval()
1166 *i = (struct v4l2_fract){ state->fiv, 10000 }; s5k5baf_set_frame_interval()
1167 if (state->fiv == state->req_fiv) s5k5baf_set_frame_interval()
1168 v4l2_info(&state->sd, "frame interval changed to %d00us\n", s5k5baf_set_frame_interval()
1169 state->fiv); s5k5baf_set_frame_interval()
1175 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_s_frame_interval() local
1177 mutex_lock(&state->lock); s5k5baf_s_frame_interval()
1178 s5k5baf_set_frame_interval(state, fi); s5k5baf_s_frame_interval()
1179 mutex_unlock(&state->lock); s5k5baf_s_frame_interval()
1284 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_get_fmt() local
1300 mutex_lock(&state->lock); s5k5baf_get_fmt()
1301 pixfmt = &s5k5baf_formats[state->pixfmt]; s5k5baf_get_fmt()
1302 mf->width = state->crop_source.width; s5k5baf_get_fmt()
1303 mf->height = state->crop_source.height; s5k5baf_get_fmt()
1306 mutex_unlock(&state->lock); s5k5baf_get_fmt()
1315 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_set_fmt() local
1331 mutex_lock(&state->lock); s5k5baf_set_fmt()
1333 if (state->streaming) { s5k5baf_set_fmt()
1334 mutex_unlock(&state->lock); s5k5baf_set_fmt()
1338 state->pixfmt = s5k5baf_try_isp_format(mf); s5k5baf_set_fmt()
1339 pixfmt = &s5k5baf_formats[state->pixfmt]; s5k5baf_set_fmt()
1342 mf->width = state->crop_source.width; s5k5baf_set_fmt()
1343 mf->height = state->crop_source.height; s5k5baf_set_fmt()
1345 mutex_unlock(&state->lock); s5k5baf_set_fmt()
1378 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_get_selection() local
1400 mutex_lock(&state->lock); s5k5baf_get_selection()
1403 sel->r = state->crop_sink; s5k5baf_get_selection()
1406 sel->r = state->compose; s5k5baf_get_selection()
1409 sel->r = state->crop_source; s5k5baf_get_selection()
1418 mutex_unlock(&state->lock); s5k5baf_get_selection()
1469 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_set_selection() local
1496 &state->crop_sink, s5k5baf_set_selection()
1497 &state->compose, s5k5baf_set_selection()
1498 &state->crop_source s5k5baf_set_selection()
1500 mutex_lock(&state->lock); s5k5baf_set_selection()
1501 if (state->streaming) { s5k5baf_set_selection()
1504 if (sel->r.width < state->crop_source.width) s5k5baf_set_selection()
1505 sel->r.width = state->crop_source.width; s5k5baf_set_selection()
1506 if (sel->r.height < state->crop_source.height) s5k5baf_set_selection()
1507 sel->r.height = state->crop_source.height; s5k5baf_set_selection()
1509 sel->r.width = state->crop_source.width; s5k5baf_set_selection()
1510 sel->r.height = state->crop_source.height; s5k5baf_set_selection()
1514 if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) || s5k5baf_set_selection()
1515 !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect)) s5k5baf_set_selection()
1516 state->apply_crop = 1; s5k5baf_set_selection()
1517 if (state->streaming) s5k5baf_set_selection()
1518 ret = s5k5baf_hw_set_crop_rects(state); s5k5baf_set_selection()
1519 mutex_unlock(&state->lock); s5k5baf_set_selection()
1554 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_s_ctrl() local
1559 mutex_lock(&state->lock); s5k5baf_s_ctrl()
1561 if (state->power == 0) s5k5baf_s_ctrl()
1566 s5k5baf_hw_set_awb(state, ctrl->val); s5k5baf_s_ctrl()
1570 s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val); s5k5baf_s_ctrl()
1574 s5k5baf_hw_set_colorfx(state, ctrl->val); s5k5baf_s_ctrl()
1578 s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val); s5k5baf_s_ctrl()
1582 s5k5baf_hw_set_auto_exposure(state, ctrl->val); s5k5baf_s_ctrl()
1586 s5k5baf_hw_set_mirror(state); s5k5baf_s_ctrl()
1590 s5k5baf_hw_set_anti_flicker(state, ctrl->val); s5k5baf_s_ctrl()
1594 s5k5baf_write(state, REG_USER_SATURATION, ctrl->val); s5k5baf_s_ctrl()
1598 s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val); s5k5baf_s_ctrl()
1602 s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val); s5k5baf_s_ctrl()
1603 if (state->apply_cfg) s5k5baf_s_ctrl()
1604 s5k5baf_hw_sync_cfg(state); s5k5baf_s_ctrl()
1608 s5k5baf_hw_set_test_pattern(state, ctrl->val); s5k5baf_s_ctrl()
1612 ret = s5k5baf_clear_error(state); s5k5baf_s_ctrl()
1613 mutex_unlock(&state->lock); s5k5baf_s_ctrl()
1631 static int s5k5baf_initialize_ctrls(struct s5k5baf *state) s5k5baf_initialize_ctrls() argument
1634 struct s5k5baf_ctrls *ctrls = &state->ctrls; s5k5baf_initialize_ctrls()
1640 v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret); s5k5baf_initialize_ctrls()
1688 v4l2_err(&state->sd, "error creating controls (%d)\n", s5k5baf_initialize_ctrls()
1695 state->sd.ctrl_handler = hdl; s5k5baf_initialize_ctrls()
1726 static int s5k5baf_check_fw_revision(struct s5k5baf *state) s5k5baf_check_fw_revision() argument
1731 api_ver = s5k5baf_read(state, REG_FW_APIVER); s5k5baf_check_fw_revision()
1732 fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff; s5k5baf_check_fw_revision()
1733 s_id = s5k5baf_read(state, REG_FW_SENSOR_ID); s5k5baf_check_fw_revision()
1734 ret = s5k5baf_clear_error(state); s5k5baf_check_fw_revision()
1738 v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n", s5k5baf_check_fw_revision()
1742 v4l2_err(&state->sd, "FW API version not supported\n"); s5k5baf_check_fw_revision()
1751 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_registered() local
1754 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd); s5k5baf_registered()
1757 state->cis_sd.name); s5k5baf_registered()
1759 ret = media_entity_create_link(&state->cis_sd.entity, PAD_CIS, s5k5baf_registered()
1760 &state->sd.entity, PAD_CIS, s5k5baf_registered()
1768 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_unregistered() local
1769 v4l2_device_unregister_subdev(&state->cis_sd); s5k5baf_unregistered()
1797 static int s5k5baf_configure_gpios(struct s5k5baf *state) s5k5baf_configure_gpios() argument
1800 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); s5k5baf_configure_gpios()
1801 struct s5k5baf_gpio *g = state->gpios; s5k5baf_configure_gpios()
1840 static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev) s5k5baf_parse_device_node() argument
1853 &state->mclk_frequency); s5k5baf_parse_device_node()
1855 state->mclk_frequency = S5K5BAF_DEFAULT_MCLK_FREQ; s5k5baf_parse_device_node()
1857 state->mclk_frequency); s5k5baf_parse_device_node()
1860 ret = s5k5baf_parse_gpios(state->gpios, dev); s5k5baf_parse_device_node()
1873 state->bus_type = ep.bus_type; s5k5baf_parse_device_node()
1875 switch (state->bus_type) { s5k5baf_parse_device_node()
1877 state->nlanes = ep.bus.mipi_csi2.num_data_lanes; s5k5baf_parse_device_node()
1890 static int s5k5baf_configure_subdevs(struct s5k5baf *state, s5k5baf_configure_subdevs() argument
1896 sd = &state->cis_sd; s5k5baf_configure_subdevs()
1899 v4l2_set_subdevdata(sd, state); s5k5baf_configure_subdevs()
1906 state->cis_pad.flags = MEDIA_PAD_FL_SOURCE; s5k5baf_configure_subdevs()
1908 ret = media_entity_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad, 0); s5k5baf_configure_subdevs()
1912 sd = &state->sd; s5k5baf_configure_subdevs()
1920 state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK; s5k5baf_configure_subdevs()
1921 state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE; s5k5baf_configure_subdevs()
1923 ret = media_entity_init(&sd->entity, NUM_ISP_PADS, state->pads, 0); s5k5baf_configure_subdevs()
1928 media_entity_cleanup(&state->cis_sd.entity); s5k5baf_configure_subdevs()
1934 static int s5k5baf_configure_regulators(struct s5k5baf *state) s5k5baf_configure_regulators() argument
1936 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); s5k5baf_configure_regulators()
1941 state->supplies[i].supply = s5k5baf_supply_names[i]; s5k5baf_configure_regulators()
1944 state->supplies); s5k5baf_configure_regulators()
1953 struct s5k5baf *state; s5k5baf_probe() local
1956 state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL); s5k5baf_probe()
1957 if (!state) s5k5baf_probe()
1960 mutex_init(&state->lock); s5k5baf_probe()
1961 state->crop_sink = s5k5baf_cis_rect; s5k5baf_probe()
1962 state->compose = s5k5baf_cis_rect; s5k5baf_probe()
1963 state->crop_source = s5k5baf_cis_rect; s5k5baf_probe()
1965 ret = s5k5baf_parse_device_node(state, &c->dev); s5k5baf_probe()
1969 ret = s5k5baf_configure_subdevs(state, c); s5k5baf_probe()
1973 ret = s5k5baf_configure_gpios(state); s5k5baf_probe()
1977 ret = s5k5baf_configure_regulators(state); s5k5baf_probe()
1981 state->clock = devm_clk_get(state->sd.dev, S5K5BAF_CLK_NAME); s5k5baf_probe()
1982 if (IS_ERR(state->clock)) { s5k5baf_probe()
1987 ret = s5k5baf_power_on(state); s5k5baf_probe()
1992 s5k5baf_hw_init(state); s5k5baf_probe()
1993 ret = s5k5baf_check_fw_revision(state); s5k5baf_probe()
1995 s5k5baf_power_off(state); s5k5baf_probe()
1999 ret = s5k5baf_initialize_ctrls(state); s5k5baf_probe()
2003 ret = v4l2_async_register_subdev(&state->sd); s5k5baf_probe()
2010 v4l2_ctrl_handler_free(state->sd.ctrl_handler); s5k5baf_probe()
2012 media_entity_cleanup(&state->sd.entity); s5k5baf_probe()
2013 media_entity_cleanup(&state->cis_sd.entity); s5k5baf_probe()
2020 struct s5k5baf *state = to_s5k5baf(sd); s5k5baf_remove() local
2026 sd = &state->cis_sd; s5k5baf_remove()
H A Dadv7180.c184 int (*init)(struct adv7180_state *state);
209 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) adv7180_select_page() argument
211 if (state->register_page != page) { adv7180_select_page()
212 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, adv7180_select_page()
214 state->register_page = page; adv7180_select_page()
220 static int adv7180_write(struct adv7180_state *state, unsigned int reg, adv7180_write() argument
223 lockdep_assert_held(&state->mutex); adv7180_write()
224 adv7180_select_page(state, reg >> 8); adv7180_write()
225 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); adv7180_write()
228 static int adv7180_read(struct adv7180_state *state, unsigned int reg) adv7180_read() argument
230 lockdep_assert_held(&state->mutex); adv7180_read()
231 adv7180_select_page(state, reg >> 8); adv7180_read()
232 return i2c_smbus_read_byte_data(state->client, reg & 0xff); adv7180_read()
235 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, adv7180_csi_write() argument
238 return i2c_smbus_write_byte_data(state->csi_client, reg, value); adv7180_csi_write()
241 static int adv7180_set_video_standard(struct adv7180_state *state, adv7180_set_video_standard() argument
244 return state->chip_info->set_std(state, std); adv7180_set_video_standard()
247 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, adv7180_vpp_write() argument
250 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); adv7180_vpp_write()
312 static int __adv7180_status(struct adv7180_state *state, u32 *status, __adv7180_status() argument
315 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); __adv7180_status()
335 struct adv7180_state *state = to_state(sd); adv7180_querystd() local
336 int err = mutex_lock_interruptible(&state->mutex); adv7180_querystd()
340 /* when we are interrupt driven we know the state */ adv7180_querystd()
341 if (!state->autodetect || state->irq > 0) adv7180_querystd()
342 *std = state->curr_norm; adv7180_querystd()
344 err = __adv7180_status(state, NULL, std); adv7180_querystd()
346 mutex_unlock(&state->mutex); adv7180_querystd()
353 struct adv7180_state *state = to_state(sd); adv7180_s_routing() local
354 int ret = mutex_lock_interruptible(&state->mutex); adv7180_s_routing()
359 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { adv7180_s_routing()
364 ret = state->chip_info->select_input(state, input); adv7180_s_routing()
367 state->input = input; adv7180_s_routing()
369 mutex_unlock(&state->mutex); adv7180_s_routing()
375 struct adv7180_state *state = to_state(sd); adv7180_g_input_status() local
376 int ret = mutex_lock_interruptible(&state->mutex); adv7180_g_input_status()
380 ret = __adv7180_status(state, status, NULL); adv7180_g_input_status()
381 mutex_unlock(&state->mutex); adv7180_g_input_status()
385 static int adv7180_program_std(struct adv7180_state *state) adv7180_program_std() argument
389 if (state->autodetect) { adv7180_program_std()
390 ret = adv7180_set_video_standard(state, adv7180_program_std()
395 __adv7180_status(state, NULL, &state->curr_norm); adv7180_program_std()
397 ret = v4l2_std_to_adv7180(state->curr_norm); adv7180_program_std()
401 ret = adv7180_set_video_standard(state, ret); adv7180_program_std()
411 struct adv7180_state *state = to_state(sd); adv7180_s_std() local
412 int ret = mutex_lock_interruptible(&state->mutex); adv7180_s_std()
419 state->autodetect = true; adv7180_s_std()
426 state->curr_norm = std; adv7180_s_std()
427 state->autodetect = false; adv7180_s_std()
430 ret = adv7180_program_std(state); adv7180_s_std()
432 mutex_unlock(&state->mutex); adv7180_s_std()
436 static int adv7180_set_power(struct adv7180_state *state, bool on) adv7180_set_power() argument
446 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); adv7180_set_power()
450 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { adv7180_set_power()
452 adv7180_csi_write(state, 0xDE, 0x02); adv7180_set_power()
453 adv7180_csi_write(state, 0xD2, 0xF7); adv7180_set_power()
454 adv7180_csi_write(state, 0xD8, 0x65); adv7180_set_power()
455 adv7180_csi_write(state, 0xE0, 0x09); adv7180_set_power()
456 adv7180_csi_write(state, 0x2C, 0x00); adv7180_set_power()
457 if (state->field == V4L2_FIELD_NONE) adv7180_set_power()
458 adv7180_csi_write(state, 0x1D, 0x80); adv7180_set_power()
459 adv7180_csi_write(state, 0x00, 0x00); adv7180_set_power()
461 adv7180_csi_write(state, 0x00, 0x80); adv7180_set_power()
470 struct adv7180_state *state = to_state(sd); adv7180_s_power() local
473 ret = mutex_lock_interruptible(&state->mutex); adv7180_s_power()
477 ret = adv7180_set_power(state, on); adv7180_s_power()
479 state->powered = on; adv7180_s_power()
481 mutex_unlock(&state->mutex); adv7180_s_power()
488 struct adv7180_state *state = to_state(sd); adv7180_s_ctrl() local
489 int ret = mutex_lock_interruptible(&state->mutex); adv7180_s_ctrl()
497 ret = adv7180_write(state, ADV7180_REG_BRI, val); adv7180_s_ctrl()
501 ret = adv7180_write(state, ADV7180_REG_HUE, -val); adv7180_s_ctrl()
504 ret = adv7180_write(state, ADV7180_REG_CON, val); adv7180_s_ctrl()
511 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); adv7180_s_ctrl()
514 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); adv7180_s_ctrl()
519 adv7180_write(state, 0x80d9, 0x44); adv7180_s_ctrl()
520 adv7180_write(state, ADV7180_REG_FLCONTROL, adv7180_s_ctrl()
524 adv7180_write(state, 0x80d9, 0xc4); adv7180_s_ctrl()
525 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); adv7180_s_ctrl()
532 mutex_unlock(&state->mutex); adv7180_s_ctrl()
550 static int adv7180_init_controls(struct adv7180_state *state) adv7180_init_controls() argument
552 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); adv7180_init_controls()
554 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, adv7180_init_controls()
557 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, adv7180_init_controls()
560 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, adv7180_init_controls()
563 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, adv7180_init_controls()
566 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); adv7180_init_controls()
568 state->sd.ctrl_handler = &state->ctrl_hdl; adv7180_init_controls()
569 if (state->ctrl_hdl.error) { adv7180_init_controls()
570 int err = state->ctrl_hdl.error; adv7180_init_controls()
572 v4l2_ctrl_handler_free(&state->ctrl_hdl); adv7180_init_controls()
575 v4l2_ctrl_handler_setup(&state->ctrl_hdl); adv7180_init_controls()
579 static void adv7180_exit_controls(struct adv7180_state *state) adv7180_exit_controls() argument
581 v4l2_ctrl_handler_free(&state->ctrl_hdl); adv7180_exit_controls()
599 struct adv7180_state *state = to_state(sd); adv7180_mbus_fmt() local
604 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; adv7180_mbus_fmt()
609 static int adv7180_set_field_mode(struct adv7180_state *state) adv7180_set_field_mode() argument
611 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) adv7180_set_field_mode()
614 if (state->field == V4L2_FIELD_NONE) { adv7180_set_field_mode()
615 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { adv7180_set_field_mode()
616 adv7180_csi_write(state, 0x01, 0x20); adv7180_set_field_mode()
617 adv7180_csi_write(state, 0x02, 0x28); adv7180_set_field_mode()
618 adv7180_csi_write(state, 0x03, 0x38); adv7180_set_field_mode()
619 adv7180_csi_write(state, 0x04, 0x30); adv7180_set_field_mode()
620 adv7180_csi_write(state, 0x05, 0x30); adv7180_set_field_mode()
621 adv7180_csi_write(state, 0x06, 0x80); adv7180_set_field_mode()
622 adv7180_csi_write(state, 0x07, 0x70); adv7180_set_field_mode()
623 adv7180_csi_write(state, 0x08, 0x50); adv7180_set_field_mode()
625 adv7180_vpp_write(state, 0xa3, 0x00); adv7180_set_field_mode()
626 adv7180_vpp_write(state, 0x5b, 0x00); adv7180_set_field_mode()
627 adv7180_vpp_write(state, 0x55, 0x80); adv7180_set_field_mode()
629 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { adv7180_set_field_mode()
630 adv7180_csi_write(state, 0x01, 0x18); adv7180_set_field_mode()
631 adv7180_csi_write(state, 0x02, 0x18); adv7180_set_field_mode()
632 adv7180_csi_write(state, 0x03, 0x30); adv7180_set_field_mode()
633 adv7180_csi_write(state, 0x04, 0x20); adv7180_set_field_mode()
634 adv7180_csi_write(state, 0x05, 0x28); adv7180_set_field_mode()
635 adv7180_csi_write(state, 0x06, 0x40); adv7180_set_field_mode()
636 adv7180_csi_write(state, 0x07, 0x58); adv7180_set_field_mode()
637 adv7180_csi_write(state, 0x08, 0x30); adv7180_set_field_mode()
639 adv7180_vpp_write(state, 0xa3, 0x70); adv7180_set_field_mode()
640 adv7180_vpp_write(state, 0x5b, 0x80); adv7180_set_field_mode()
641 adv7180_vpp_write(state, 0x55, 0x00); adv7180_set_field_mode()
651 struct adv7180_state *state = to_state(sd); adv7180_get_pad_format() local
657 format->format.field = state->field; adv7180_get_pad_format()
667 struct adv7180_state *state = to_state(sd); adv7180_set_pad_format() local
672 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) adv7180_set_pad_format()
682 if (state->field != format->format.field) { adv7180_set_pad_format()
683 state->field = format->format.field; adv7180_set_pad_format()
684 adv7180_set_power(state, false); adv7180_set_pad_format()
685 adv7180_set_field_mode(state); adv7180_set_pad_format()
686 adv7180_set_power(state, true); adv7180_set_pad_format()
699 struct adv7180_state *state = to_state(sd); adv7180_g_mbus_config() local
701 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { adv7180_g_mbus_config()
746 struct adv7180_state *state = devid; adv7180_irq() local
749 mutex_lock(&state->mutex); adv7180_irq()
750 isr3 = adv7180_read(state, ADV7180_REG_ISR3); adv7180_irq()
752 adv7180_write(state, ADV7180_REG_ICR3, isr3); adv7180_irq()
754 if (isr3 & ADV7180_IRQ3_AD_CHANGE && state->autodetect) adv7180_irq()
755 __adv7180_status(state, NULL, &state->curr_norm); adv7180_irq()
756 mutex_unlock(&state->mutex); adv7180_irq()
761 static int adv7180_init(struct adv7180_state *state) adv7180_init() argument
766 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, adv7180_init()
772 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, adv7180_init()
776 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) adv7180_set_std() argument
778 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, adv7180_set_std()
779 (std << 4) | state->input); adv7180_set_std()
782 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) adv7180_select_input() argument
786 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); adv7180_select_input()
792 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); adv7180_select_input()
795 static int adv7182_init(struct adv7180_state *state) adv7182_init() argument
797 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) adv7182_init()
798 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, adv7182_init()
801 if (state->chip_info->flags & ADV7180_FLAG_I2P) adv7182_init()
802 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, adv7182_init()
805 if (state->chip_info->flags & ADV7180_FLAG_V2) { adv7182_init()
807 adv7180_write(state, 0x0080, 0x51); adv7182_init()
808 adv7180_write(state, 0x0081, 0x51); adv7182_init()
809 adv7180_write(state, 0x0082, 0x68); adv7182_init()
813 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { adv7182_init()
814 adv7180_write(state, 0x0003, 0x4e); adv7182_init()
815 adv7180_write(state, 0x0004, 0x57); adv7182_init()
816 adv7180_write(state, 0x001d, 0xc0); adv7182_init()
818 if (state->chip_info->flags & ADV7180_FLAG_V2) adv7182_init()
819 adv7180_write(state, 0x0004, 0x17); adv7182_init()
821 adv7180_write(state, 0x0004, 0x07); adv7182_init()
822 adv7180_write(state, 0x0003, 0x0c); adv7182_init()
823 adv7180_write(state, 0x001d, 0x40); adv7182_init()
826 adv7180_write(state, 0x0013, 0x00); adv7182_init()
831 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) adv7182_set_std() argument
833 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); adv7182_set_std()
888 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) adv7182_select_input() argument
895 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); adv7182_select_input()
900 adv7180_write(state, 0x809c, 0x00); adv7182_select_input()
901 adv7180_write(state, 0x809c, 0xff); adv7182_select_input()
909 adv7180_write(state, 0x0017, 0x41); adv7182_select_input()
912 adv7180_write(state, 0x0017, 0x01); adv7182_select_input()
916 if (state->chip_info->flags & ADV7180_FLAG_V2) adv7182_select_input()
922 adv7180_write(state, 0x0052 + i, lbias[i]); adv7182_select_input()
926 adv7180_write(state, 0x005f, 0xa8); adv7182_select_input()
927 adv7180_write(state, 0x005a, 0x90); adv7182_select_input()
928 adv7180_write(state, 0x0060, 0xb0); adv7182_select_input()
929 adv7180_write(state, 0x80b6, 0x08); adv7182_select_input()
930 adv7180_write(state, 0x80c0, 0xa0); adv7182_select_input()
932 adv7180_write(state, 0x005f, 0xf0); adv7182_select_input()
933 adv7180_write(state, 0x005a, 0xd0); adv7182_select_input()
934 adv7180_write(state, 0x0060, 0x10); adv7182_select_input()
935 adv7180_write(state, 0x80b6, 0x9c); adv7182_select_input()
936 adv7180_write(state, 0x80c0, 0x00); adv7182_select_input()
1107 static int init_device(struct adv7180_state *state) init_device() argument
1111 mutex_lock(&state->mutex); init_device()
1113 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); init_device()
1116 ret = state->chip_info->init(state); init_device()
1120 ret = adv7180_program_std(state); init_device()
1124 adv7180_set_field_mode(state); init_device()
1127 if (state->irq > 0) { init_device()
1129 ret = adv7180_write(state, ADV7180_REG_ICONF1, init_device()
1135 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); init_device()
1139 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); init_device()
1144 ret = adv7180_write(state, ADV7180_REG_IMR3, init_device()
1149 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); init_device()
1155 mutex_unlock(&state->mutex); init_device()
1163 struct adv7180_state *state; adv7180_probe() local
1174 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); adv7180_probe()
1175 if (state == NULL) adv7180_probe()
1178 state->client = client; adv7180_probe()
1179 state->field = V4L2_FIELD_INTERLACED; adv7180_probe()
1180 state->chip_info = (struct adv7180_chip_info *)id->driver_data; adv7180_probe()
1182 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { adv7180_probe()
1183 state->csi_client = i2c_new_dummy(client->adapter, adv7180_probe()
1185 if (!state->csi_client) adv7180_probe()
1189 if (state->chip_info->flags & ADV7180_FLAG_I2P) { adv7180_probe()
1190 state->vpp_client = i2c_new_dummy(client->adapter, adv7180_probe()
1192 if (!state->vpp_client) { adv7180_probe()
1198 state->irq = client->irq; adv7180_probe()
1199 mutex_init(&state->mutex); adv7180_probe()
1200 state->autodetect = true; adv7180_probe()
1201 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) adv7180_probe()
1202 state->powered = true; adv7180_probe()
1204 state->powered = false; adv7180_probe()
1205 state->input = 0; adv7180_probe()
1206 sd = &state->sd; adv7180_probe()
1210 ret = adv7180_init_controls(state); adv7180_probe()
1214 state->pad.flags = MEDIA_PAD_FL_SOURCE; adv7180_probe()
1216 ret = media_entity_init(&sd->entity, 1, &state->pad, 0); adv7180_probe()
1220 ret = init_device(state); adv7180_probe()
1224 if (state->irq) { adv7180_probe()
1227 KBUILD_MODNAME, state); adv7180_probe()
1239 if (state->irq > 0) adv7180_probe()
1240 free_irq(client->irq, state); adv7180_probe()
1244 adv7180_exit_controls(state); adv7180_probe()
1246 if (state->chip_info->flags & ADV7180_FLAG_I2P) adv7180_probe()
1247 i2c_unregister_device(state->vpp_client); adv7180_probe()
1249 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) adv7180_probe()
1250 i2c_unregister_device(state->csi_client); adv7180_probe()
1251 mutex_destroy(&state->mutex); adv7180_probe()
1258 struct adv7180_state *state = to_state(sd); adv7180_remove() local
1262 if (state->irq > 0) adv7180_remove()
1263 free_irq(client->irq, state); adv7180_remove()
1266 adv7180_exit_controls(state); adv7180_remove()
1268 if (state->chip_info->flags & ADV7180_FLAG_I2P) adv7180_remove()
1269 i2c_unregister_device(state->vpp_client); adv7180_remove()
1270 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) adv7180_remove()
1271 i2c_unregister_device(state->csi_client); adv7180_remove()
1273 mutex_destroy(&state->mutex); adv7180_remove()
1297 struct adv7180_state *state = to_state(sd); adv7180_suspend() local
1299 return adv7180_set_power(state, false); adv7180_suspend()
1306 struct adv7180_state *state = to_state(sd); adv7180_resume() local
1309 ret = init_device(state); adv7180_resume()
1313 ret = adv7180_set_power(state, state->powered); adv7180_resume()
H A Dmsp3400-driver.c291 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp_set_scart() local
293 state->in_scart = in; msp_set_scart()
299 state->acb &= ~scarts[out][0]; msp_set_scart()
300 state->acb |= scarts[out][in + 1]; msp_set_scart()
302 state->acb = 0xf60; /* Mute Input and SCART 1 Output */ msp_set_scart()
305 scart_names[in], out, state->acb); msp_set_scart()
306 msp_write_dsp(client, 0x13, state->acb); msp_set_scart()
309 if (state->has_i2s_conf) msp_set_scart()
310 msp_write_dem(client, 0x40, state->i2s_mode); msp_set_scart()
317 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp_wake_thread() local
319 if (NULL == state->kthread) msp_wake_thread()
321 state->watch_stereo = 0; msp_wake_thread()
322 state->restart = 1; msp_wake_thread()
323 wake_up_interruptible(&state->wq); msp_wake_thread()
326 int msp_sleep(struct msp_state *state, int timeout) msp_sleep() argument
330 add_wait_queue(&state->wq, &wait); msp_sleep()
341 remove_wait_queue(&state->wq, &wait); msp_sleep()
343 return state->restart; msp_sleep()
350 struct msp_state *state = ctrl_to_state(ctrl); msp_s_ctrl() local
351 struct i2c_client *client = v4l2_get_subdevdata(&state->sd); msp_s_ctrl()
357 int reallymuted = state->muted->val | state->scan_in_progress; msp_s_ctrl()
363 state->muted->val ? "on" : "off", msp_s_ctrl()
364 state->scan_in_progress ? "yes" : "no", msp_s_ctrl()
365 state->volume->val); msp_s_ctrl()
369 if (state->has_scart2_out_volume) msp_s_ctrl()
371 if (state->has_headphones) msp_s_ctrl()
379 if (state->has_headphones) msp_s_ctrl()
386 if (state->has_headphones) msp_s_ctrl()
393 if (state->has_headphones) msp_s_ctrl()
400 if (state->has_headphones) msp_s_ctrl()
410 void msp_update_volume(struct msp_state *state) msp_update_volume() argument
413 v4l2_ctrl_lock(state->volume); msp_update_volume()
414 state->volume->val = state->volume->cur.val; msp_update_volume()
415 state->muted->val = state->muted->cur.val; msp_update_volume()
416 msp_s_ctrl(state->volume); msp_update_volume()
417 v4l2_ctrl_unlock(state->volume); msp_update_volume()
423 struct msp_state *state = to_state(sd); msp_s_radio() local
426 if (state->radio) msp_s_radio()
428 state->radio = 1; msp_s_radio()
430 state->watch_stereo = 0; msp_s_radio()
431 switch (state->opmode) { msp_s_radio()
437 msp_update_volume(state); msp_s_radio()
459 struct msp_state *state = to_state(sd); msp_querystd() local
462 *id &= state->detected_std; msp_querystd()
466 msp_standard_std_name(state->std), state->detected_std); msp_querystd()
473 struct msp_state *state = to_state(sd); msp_s_std() local
475 int update = state->radio || state->v4l2_std != id; msp_s_std()
477 state->v4l2_std = id; msp_s_std()
478 state->radio = 0; msp_s_std()
487 struct msp_state *state = to_state(sd); msp_s_routing() local
497 if (state->route_in == input && state->route_out == output) msp_s_routing()
499 state->route_in = input; msp_s_routing()
500 state->route_out = output; msp_s_routing()
506 state->mode = extern_input ? MSP_MODE_EXTERN : MSP_MODE_AM_DETECT; msp_s_routing()
507 state->rxsubchans = V4L2_TUNER_SUB_STEREO; msp_s_routing()
512 reg = (state->opmode == OPMODE_AUTOSELECT) ? 0x30 : 0xbb; msp_s_routing()
522 struct msp_state *state = to_state(sd); msp_g_tuner() local
527 if (!state->radio) { msp_g_tuner()
528 if (state->opmode == OPMODE_AUTOSELECT) msp_g_tuner()
530 vt->rxsubchans = state->rxsubchans; msp_g_tuner()
532 vt->audmode = state->audmode; msp_g_tuner()
540 struct msp_state *state = to_state(sd); msp_s_tuner() local
543 if (state->radio) /* TODO: add mono/stereo support for radio */ msp_s_tuner()
545 if (state->audmode == vt->audmode) msp_s_tuner()
547 state->audmode = vt->audmode; msp_s_tuner()
555 struct msp_state *state = to_state(sd); msp_s_i2s_clock_freq() local
562 state->i2s_mode = 0; msp_s_i2s_clock_freq()
565 state->i2s_mode = 1; msp_s_i2s_clock_freq()
575 struct msp_state *state = to_state(sd); msp_log_status() local
580 if (state->opmode == OPMODE_AUTOSELECT) msp_log_status()
583 client->name, state->rev1, state->rev2); msp_log_status()
585 v4l2_ctrl_handler_log_status(&state->hdl, prefix); msp_log_status()
586 switch (state->mode) { msp_log_status()
598 if (state->mode == MSP_MODE_EXTERN) { msp_log_status()
600 } else if (state->opmode == OPMODE_MANUAL) { msp_log_status()
602 (state->rxsubchans & V4L2_TUNER_SUB_STEREO) ? "stereo" : "mono", msp_log_status()
603 (state->rxsubchans & V4L2_TUNER_SUB_LANG2) ? ", dual" : ""); msp_log_status()
605 if (state->opmode == OPMODE_AUTODETECT) msp_log_status()
608 msp_standard_std_name(state->std), msp_log_status()
609 (state->rxsubchans & V4L2_TUNER_SUB_STEREO) ? "stereo" : "mono", msp_log_status()
610 (state->rxsubchans & V4L2_TUNER_SUB_LANG2) ? ", dual" : ""); msp_log_status()
612 v4l_info(client, "Audmode: 0x%04x\n", state->audmode); msp_log_status()
614 state->route_in, state->route_out); msp_log_status()
615 v4l_info(client, "ACB: 0x%04x\n", state->acb); msp_log_status()
682 struct msp_state *state; msp_probe() local
700 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); msp_probe()
701 if (!state) msp_probe()
704 sd = &state->sd; msp_probe()
707 state->v4l2_std = V4L2_STD_NTSC; msp_probe()
708 state->detected_std = V4L2_STD_ALL; msp_probe()
709 state->audmode = V4L2_TUNER_MODE_STEREO; msp_probe()
710 state->input = -1; msp_probe()
711 state->i2s_mode = 0; msp_probe()
712 init_waitqueue_head(&state->wq); msp_probe()
714 state->route_in = MSP_INPUT_DEFAULT; msp_probe()
715 state->route_out = MSP_OUTPUT_DEFAULT; msp_probe()
717 state->rev1 = msp_read_dsp(client, 0x1e); msp_probe()
718 if (state->rev1 != -1) msp_probe()
719 state->rev2 = msp_read_dsp(client, 0x1f); msp_probe()
721 state->rev1, state->rev2); msp_probe()
722 if (state->rev1 == -1 || (state->rev1 == 0 && state->rev2 == 0)) { msp_probe()
728 msp_family = ((state->rev1 >> 4) & 0x0f) + 3; msp_probe()
729 msp_product = (state->rev2 >> 8) & 0xff; msp_probe()
732 msp_revision = (state->rev1 & 0x0f) + '@'; msp_probe()
733 msp_hard = ((state->rev1 >> 8) & 0xff) + '@'; msp_probe()
734 msp_rom = state->rev2 & 0x1f; msp_probe()
736 state->ident = msp_family * 10000 + 4000 + msp_product * 10 + msp_probe()
740 state->has_nicam = msp_probe()
743 state->has_radio = msp_probe()
746 state->has_headphones = msp_probe()
749 state->has_scart2 = msp_probe()
752 state->has_scart3 = msp_probe()
755 state->has_scart4 = msp_probe()
759 state->has_scart2_out = msp_probe()
762 state->has_scart2_out_volume = msp_probe()
763 msp_revision > 'C' && state->has_scart2_out; msp_probe()
765 state->has_i2s_conf = msp_probe()
769 state->has_subwoofer = msp_probe()
773 state->has_sound_processing = msp_probe()
776 state->has_virtual_dolby_surround = msp_probe()
779 state->has_dolby_pro_logic = msp_probe()
783 state->force_btsc = msp_probe()
786 state->opmode = opmode; msp_probe()
787 if (state->opmode == OPMODE_AUTO) { msp_probe()
790 state->opmode = OPMODE_AUTOSELECT; msp_probe()
793 state->opmode = OPMODE_AUTODETECT; msp_probe()
795 state->opmode = OPMODE_MANUAL; msp_probe()
798 hdl = &state->hdl; msp_probe()
800 if (state->has_sound_processing) { msp_probe()
808 state->volume = v4l2_ctrl_new_std(hdl, &msp_ctrl_ops, msp_probe()
812 state->muted = v4l2_ctrl_new_std(hdl, &msp_ctrl_ops, msp_probe()
822 v4l2_ctrl_cluster(2, &state->volume); msp_probe()
831 if (state->has_nicam && state->has_radio) msp_probe()
833 else if (state->has_nicam) msp_probe()
835 else if (state->has_radio) msp_probe()
840 switch (state->opmode) { msp_probe()
858 state->kthread = kthread_run(thread_func, client, "msp34xx"); msp_probe()
860 if (IS_ERR(state->kthread)) msp_probe()
869 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp_remove() local
871 v4l2_device_unregister_subdev(&state->sd); msp_remove()
873 if (state->kthread) { msp_remove()
874 state->restart = 1; msp_remove()
875 kthread_stop(state->kthread); msp_remove()
879 v4l2_ctrl_handler_free(&state->hdl); msp_remove()
H A Dadv7343.c134 struct adv7343_state *state = to_state(sd); adv7343_setstd() local
158 val = state->reg80 & (~(SD_STD_MASK)); adv7343_setstd()
164 state->reg80 = val; adv7343_setstd()
167 val = state->reg01 & (~((u8) INPUT_MODE_MASK)); adv7343_setstd()
173 state->reg01 = val; adv7343_setstd()
184 val = state->reg80; adv7343_setstd()
196 state->reg80 = val; adv7343_setstd()
207 struct adv7343_state *state = to_state(sd); adv7343_setoutput() local
219 val = state->reg00 & 0x03; adv7343_setoutput()
222 if (!state->pdata) adv7343_setoutput()
230 val = state->pdata->mode_config.sleep_mode << 0 | adv7343_setoutput()
231 state->pdata->mode_config.pll_control << 1 | adv7343_setoutput()
232 state->pdata->mode_config.dac[2] << 2 | adv7343_setoutput()
233 state->pdata->mode_config.dac[1] << 3 | adv7343_setoutput()
234 state->pdata->mode_config.dac[0] << 4 | adv7343_setoutput()
235 state->pdata->mode_config.dac[5] << 5 | adv7343_setoutput()
236 state->pdata->mode_config.dac[4] << 6 | adv7343_setoutput()
237 state->pdata->mode_config.dac[3] << 7; adv7343_setoutput()
243 state->reg00 = val; adv7343_setoutput()
246 val = state->reg02 | YUV_OUTPUT_SELECT; adv7343_setoutput()
251 state->reg02 = val; adv7343_setoutput()
254 val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI); adv7343_setoutput()
256 if (state->pdata && state->pdata->sd_config.sd_dac_out[0]) adv7343_setoutput()
257 val = val | (state->pdata->sd_config.sd_dac_out[0] << 1); adv7343_setoutput()
258 else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0]) adv7343_setoutput()
259 val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1); adv7343_setoutput()
261 if (state->pdata && state->pdata->sd_config.sd_dac_out[1]) adv7343_setoutput()
262 val = val | (state->pdata->sd_config.sd_dac_out[1] << 2); adv7343_setoutput()
263 else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1]) adv7343_setoutput()
264 val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2); adv7343_setoutput()
270 state->reg82 = val; adv7343_setoutput()
274 val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI); adv7343_setoutput()
279 state->reg35 = val; adv7343_setoutput()
290 struct adv7343_state *state = to_state(sd); adv7343_log_status() local
292 v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std); adv7343_log_status()
293 v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" : adv7343_log_status()
294 ((state->output == 1) ? "Component" : "S-Video")); adv7343_log_status()
333 struct adv7343_state *state = to_state(sd); adv7343_s_std_output() local
336 if (state->std == std) adv7343_s_std_output()
341 state->std = std; adv7343_s_std_output()
349 struct adv7343_state *state = to_state(sd); adv7343_s_routing() local
352 if (state->output == output) adv7343_s_routing()
357 state->output = output; adv7343_s_routing()
374 struct adv7343_state *state = to_state(sd); adv7343_initialize() local
389 err = adv7343_setoutput(sd, state->output); adv7343_initialize()
395 err = adv7343_setstd(sd, state->std); adv7343_initialize()
441 struct adv7343_state *state; adv7343_probe() local
450 state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state), adv7343_probe()
452 if (state == NULL) adv7343_probe()
456 state->pdata = adv7343_get_pdata(client); adv7343_probe()
458 state->reg00 = 0x80; adv7343_probe()
459 state->reg01 = 0x00; adv7343_probe()
460 state->reg02 = 0x20; adv7343_probe()
461 state->reg35 = 0x00; adv7343_probe()
462 state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT; adv7343_probe()
463 state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT; adv7343_probe()
465 state->output = ADV7343_COMPOSITE_ID; adv7343_probe()
466 state->std = V4L2_STD_NTSC; adv7343_probe()
468 v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops); adv7343_probe()
470 v4l2_ctrl_handler_init(&state->hdl, 2); adv7343_probe()
471 v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops, adv7343_probe()
475 v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops, adv7343_probe()
479 v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops, adv7343_probe()
483 state->sd.ctrl_handler = &state->hdl; adv7343_probe()
484 if (state->hdl.error) { adv7343_probe()
485 err = state->hdl.error; adv7343_probe()
488 v4l2_ctrl_handler_setup(&state->hdl); adv7343_probe()
490 err = adv7343_initialize(&state->sd); adv7343_probe()
494 err = v4l2_async_register_subdev(&state->sd); adv7343_probe()
498 v4l2_ctrl_handler_free(&state->hdl); adv7343_probe()
506 struct adv7343_state *state = to_state(sd); adv7343_remove() local
508 v4l2_async_unregister_subdev(&state->sd); adv7343_remove()
509 v4l2_ctrl_handler_free(&state->hdl); adv7343_remove()
H A Dmsp3400-kthreads.c191 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp_set_source() local
203 if (state->has_scart2_out) msp_set_source()
218 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp3400c_set_mode() local
220 int tuner = (state->route_in >> 3) & 1; msp3400c_set_mode()
224 state->mode = mode; msp3400c_set_mode()
225 state->rxsubchans = V4L2_TUNER_SUB_MONO; msp3400c_set_mode()
248 if (state->has_nicam) /* nicam prescale */ msp3400c_set_mode()
259 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp3400c_set_audmode() local
260 char *modestr = (state->audmode >= 0 && state->audmode < 5) ? msp3400c_set_audmode()
261 strmode[state->audmode] : "unknown"; msp3400c_set_audmode()
263 int audmode = state->audmode; msp3400c_set_audmode()
265 if (state->opmode == OPMODE_AUTOSELECT) { msp3400c_set_audmode()
271 state->audmode); msp3400c_set_audmode()
279 if (state->mode != MSP_MODE_EXTERN) { msp3400c_set_audmode()
281 if (state->rxsubchans == V4L2_TUNER_SUB_MONO) msp3400c_set_audmode()
284 else if (state->rxsubchans & V4L2_TUNER_SUB_LANG2) { msp3400c_set_audmode()
296 switch (state->mode) { msp3400c_set_audmode()
334 if (state->nicam_on) msp3400c_set_audmode()
363 if (state->mode == MSP_MODE_AM_NICAM) { msp3400c_set_audmode()
371 if (state->rxsubchans & V4L2_TUNER_SUB_STEREO) msp3400c_set_audmode()
388 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp3400c_print_mode() local
390 if (state->main == state->second) msp3400c_print_mode()
393 state->main / 910000, (state->main / 910) % 1000); msp3400c_print_mode()
397 state->main / 910000, (state->main / 910) % 1000); msp3400c_print_mode()
398 if (state->mode == MSP_MODE_FM_NICAM1 || state->mode == MSP_MODE_FM_NICAM2) msp3400c_print_mode()
401 state->second / 910000, (state->second/910) % 1000); msp3400c_print_mode()
402 if (state->mode == MSP_MODE_AM_NICAM) msp3400c_print_mode()
405 state->second / 910000, (state->second / 910) % 1000); msp3400c_print_mode()
406 if (state->mode == MSP_MODE_FM_TERRA && state->main != state->second) { msp3400c_print_mode()
409 state->second / 910000, (state->second / 910) % 1000); msp3400c_print_mode()
417 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp3400c_detect_stereo() local
419 int rxsubchans = state->rxsubchans; msp3400c_detect_stereo()
420 int newnicam = state->nicam_on; msp3400c_detect_stereo()
423 switch (state->mode) { msp3400c_detect_stereo()
472 if (rxsubchans != state->rxsubchans) { msp3400c_detect_stereo()
476 state->rxsubchans, rxsubchans); msp3400c_detect_stereo()
477 state->rxsubchans = rxsubchans; msp3400c_detect_stereo()
479 if (newnicam != state->nicam_on) { msp3400c_detect_stereo()
482 state->nicam_on, newnicam); msp3400c_detect_stereo()
483 state->nicam_on = newnicam; msp3400c_detect_stereo()
495 struct msp_state *state = to_state(i2c_get_clientdata(client)); watch_stereo() local
501 state->watch_stereo = 0; watch_stereo()
507 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp3400c_thread() local
512 state->detected_std = V4L2_STD_ALL; msp3400c_thread()
516 msp_sleep(state, -1); msp3400c_thread()
521 state->restart = 0; msp3400c_thread()
525 if (state->radio || MSP_MODE_EXTERN == state->mode) { msp3400c_thread()
529 state->scan_in_progress = 0; msp3400c_thread()
530 msp_update_volume(state); msp3400c_thread()
535 state->scan_in_progress = 1; msp3400c_thread()
536 msp_update_volume(state); msp3400c_thread()
541 state->watch_stereo = 0; msp3400c_thread()
542 state->nicam_on = 0; msp3400c_thread()
545 if (msp_sleep(state, 200)) msp3400c_thread()
552 if (msp_amsound && (state->v4l2_std & V4L2_STD_SECAM)) { msp3400c_thread()
561 if (msp_sleep(state, 100)) msp3400c_thread()
590 if (msp_amsound && (state->v4l2_std & V4L2_STD_SECAM)) { msp3400c_thread()
598 if (msp_sleep(state, 100)) msp3400c_thread()
610 state->main = msp3400c_carrier_detect_main[max1].cdo; msp3400c_thread()
613 state->detected_std = V4L2_STD_BG | V4L2_STD_PAL_H; msp3400c_thread()
616 state->second = msp3400c_carrier_detect_55[max2].cdo; msp3400c_thread()
618 state->watch_stereo = 1; msp3400c_thread()
619 } else if (max2 == 1 && state->has_nicam) { msp3400c_thread()
621 state->second = msp3400c_carrier_detect_55[max2].cdo; msp3400c_thread()
623 state->nicam_on = 1; msp3400c_thread()
624 state->watch_stereo = 1; msp3400c_thread()
631 state->detected_std = V4L2_STD_PAL_I; msp3400c_thread()
632 state->second = MSP_CARRIER(6.552); msp3400c_thread()
634 state->nicam_on = 1; msp3400c_thread()
635 state->watch_stereo = 1; msp3400c_thread()
640 state->second = msp3400c_carrier_detect_65[max2].cdo; msp3400c_thread()
642 state->watch_stereo = 1; msp3400c_thread()
643 state->detected_std = V4L2_STD_DK; msp3400c_thread()
644 } else if (max2 == 0 && (state->v4l2_std & V4L2_STD_SECAM)) { msp3400c_thread()
646 state->second = msp3400c_carrier_detect_65[max2].cdo; msp3400c_thread()
648 state->watch_stereo = 1; msp3400c_thread()
649 state->detected_std = V4L2_STD_L; msp3400c_thread()
650 } else if (max2 == 0 && state->has_nicam) { msp3400c_thread()
652 state->second = msp3400c_carrier_detect_65[max2].cdo; msp3400c_thread()
654 state->nicam_on = 1; msp3400c_thread()
655 state->watch_stereo = 1; msp3400c_thread()
656 state->detected_std = V4L2_STD_DK; msp3400c_thread()
662 state->detected_std = V4L2_STD_MN; msp3400c_thread()
665 state->second = msp3400c_carrier_detect_main[max1].cdo; msp3400c_thread()
669 msp3400c_set_carrier(client, state->second, state->main); msp3400c_thread()
672 state->scan_in_progress = 0; msp3400c_thread()
674 msp_update_volume(state); msp3400c_thread()
682 while (state->watch_stereo) { msp3400c_thread()
683 if (msp_sleep(state, count ? 1000 : 5000)) msp3400c_thread()
698 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp3410d_thread() local
702 state->detected_std = V4L2_STD_ALL; msp3410d_thread()
706 msp_sleep(state, -1); msp3410d_thread()
711 state->restart = 0; msp3410d_thread()
715 if (state->mode == MSP_MODE_EXTERN) { msp3410d_thread()
719 state->scan_in_progress = 0; msp3410d_thread()
720 msp_update_volume(state); msp3410d_thread()
725 state->scan_in_progress = 1; msp3410d_thread()
726 msp_update_volume(state); msp3410d_thread()
731 if (state->radio) msp3410d_thread()
734 std = (state->v4l2_std & V4L2_STD_NTSC) ? 0x20 : 1; msp3410d_thread()
735 state->watch_stereo = 0; msp3410d_thread()
736 state->nicam_on = 0; msp3410d_thread()
739 if (msp_sleep(state, 200)) msp3410d_thread()
754 if (msp_sleep(state, 100)) msp3410d_thread()
770 state->main = msp_stdlist[i].main; msp3410d_thread()
771 state->second = msp_stdlist[i].second; msp3410d_thread()
772 state->std = val; msp3410d_thread()
773 state->rxsubchans = V4L2_TUNER_SUB_MONO; msp3410d_thread()
775 if (msp_amsound && !state->radio && msp3410d_thread()
776 (state->v4l2_std & V4L2_STD_SECAM) && (val != 0x0009)) { msp3410d_thread()
782 state->std = val = 0x0009; msp3410d_thread()
785 state->detected_std = msp_standard_std(state->std); msp3410d_thread()
794 state->mode = MSP_MODE_FM_NICAM2; msp3410d_thread()
796 state->mode = MSP_MODE_FM_NICAM1; msp3410d_thread()
798 state->nicam_on = 1; msp3410d_thread()
799 state->watch_stereo = 1; msp3410d_thread()
802 state->mode = MSP_MODE_AM_NICAM; msp3410d_thread()
803 state->nicam_on = 1; msp3410d_thread()
804 state->watch_stereo = 1; msp3410d_thread()
808 state->mode = MSP_MODE_BTSC; msp3410d_thread()
811 state->mode = MSP_MODE_FM_RADIO; msp3410d_thread()
812 state->rxsubchans = V4L2_TUNER_SUB_STEREO; msp3410d_thread()
823 state->mode = MSP_MODE_FM_TERRA; msp3410d_thread()
824 state->watch_stereo = 1; msp3410d_thread()
831 if (state->has_nicam) msp3410d_thread()
834 if (state->has_i2s_conf) msp3410d_thread()
835 msp_write_dem(client, 0x40, state->i2s_mode); msp3410d_thread()
839 state->scan_in_progress = 0; msp3410d_thread()
840 msp_update_volume(state); msp3410d_thread()
845 while (state->watch_stereo) { msp3410d_thread()
846 if (msp_sleep(state, count ? 1000 : 5000)) msp3410d_thread()
867 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp34xxg_modus() local
869 if (state->radio) { msp34xxg_modus()
873 if (state->v4l2_std == V4L2_STD_NTSC_M_JP) { msp34xxg_modus()
877 if (state->v4l2_std == V4L2_STD_NTSC_M_KR) { msp34xxg_modus()
881 if (state->v4l2_std == V4L2_STD_SECAM_L) { msp34xxg_modus()
885 if (state->v4l2_std & V4L2_STD_MN) { msp34xxg_modus()
894 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp34xxg_set_source() local
897 switch (state->audmode) { msp34xxg_set_source()
925 else if (in >= MSP_DSP_IN_MAIN_AVC && state->has_dolby_pro_logic) msp34xxg_set_source()
937 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp34xxg_set_sources() local
938 u32 in = state->route_in; msp34xxg_set_sources()
945 if (state->has_scart2_out) msp34xxg_set_sources()
953 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp34xxg_reset() local
954 int tuner = (state->route_in >> 3) & 1; msp34xxg_reset()
959 state->std = 1; msp34xxg_reset()
963 if (state->has_i2s_conf) msp34xxg_reset()
964 msp_write_dem(client, 0x40, state->i2s_mode); msp34xxg_reset()
977 if (state->has_nicam) msp34xxg_reset()
996 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp34xxg_thread() local
1000 state->detected_std = V4L2_STD_ALL; msp34xxg_thread()
1004 msp_sleep(state, -1); msp34xxg_thread()
1009 state->restart = 0; msp34xxg_thread()
1013 if (state->mode == MSP_MODE_EXTERN) { msp34xxg_thread()
1017 state->scan_in_progress = 0; msp34xxg_thread()
1018 msp_update_volume(state); msp34xxg_thread()
1024 state->std = state->radio ? 0x40 : msp34xxg_thread()
1025 (state->force_btsc && msp_standard == 1) ? 32 : msp_standard; msp34xxg_thread()
1026 msp_write_dem(client, 0x20, state->std); msp34xxg_thread()
1028 if (state->std != 1) msp34xxg_thread()
1035 if (msp_sleep(state, 100)) msp34xxg_thread()
1041 state->std = val; msp34xxg_thread()
1047 if (state->std == 1) { msp34xxg_thread()
1056 msp_standard_std_name(state->std), state->std); msp34xxg_thread()
1057 state->detected_std = msp_standard_std(state->std); msp34xxg_thread()
1059 if (state->std == 9) { msp34xxg_thread()
1065 msp_update_volume(state); msp34xxg_thread()
1068 if (msp_write_dsp(client, 0x13, state->acb)) msp34xxg_thread()
1073 if (state->std != 0x20) msp34xxg_thread()
1076 state->watch_stereo = 1; msp34xxg_thread()
1081 while (state->watch_stereo) { msp34xxg_thread()
1083 if (msp_sleep(state, 5000)) msp34xxg_thread()
1093 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp34xxg_detect_stereo() local
1097 int oldrx = state->rxsubchans; msp34xxg_detect_stereo()
1099 if (state->mode == MSP_MODE_EXTERN) msp34xxg_detect_stereo()
1102 state->rxsubchans = 0; msp34xxg_detect_stereo()
1104 state->rxsubchans = V4L2_TUNER_SUB_STEREO; msp34xxg_detect_stereo()
1106 state->rxsubchans = V4L2_TUNER_SUB_MONO; msp34xxg_detect_stereo()
1108 if (state->std == 0x20) msp34xxg_detect_stereo()
1109 state->rxsubchans |= V4L2_TUNER_SUB_SAP; msp34xxg_detect_stereo()
1111 state->rxsubchans = msp34xxg_detect_stereo()
1116 status, is_stereo, is_bilingual, state->rxsubchans); msp34xxg_detect_stereo()
1117 return (oldrx != state->rxsubchans); msp34xxg_detect_stereo()
1122 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp34xxg_set_audmode() local
1124 if (state->std == 0x20) { msp34xxg_set_audmode()
1125 if ((state->rxsubchans & V4L2_TUNER_SUB_SAP) && msp34xxg_set_audmode()
1126 (state->audmode == V4L2_TUNER_MODE_LANG1_LANG2 || msp34xxg_set_audmode()
1127 state->audmode == V4L2_TUNER_MODE_LANG2)) { msp34xxg_set_audmode()
1139 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp_set_audmode() local
1141 switch (state->opmode) { msp_set_audmode()
1154 struct msp_state *state = to_state(i2c_get_clientdata(client)); msp_detect_stereo() local
1156 switch (state->opmode) { msp_detect_stereo()
H A Dadv7393.c137 struct adv7393_state *state = to_state(sd); adv7393_setstd() local
162 val = state->reg80 & ~SD_STD_MASK; adv7393_setstd()
168 state->reg80 = val; adv7393_setstd()
171 val = state->reg01 & ~INPUT_MODE_MASK; adv7393_setstd()
177 state->reg01 = val; adv7393_setstd()
188 val = state->reg82; adv7393_setstd()
200 state->reg82 = val; adv7393_setstd()
211 struct adv7393_state *state = to_state(sd); adv7393_setoutput() local
223 val = state->reg00 & 0x03; adv7393_setoutput()
236 state->reg00 = val; adv7393_setoutput()
239 val = state->reg02 | YUV_OUTPUT_SELECT; adv7393_setoutput()
244 state->reg02 = val; adv7393_setoutput()
247 val = state->reg82; adv7393_setoutput()
256 state->reg82 = val; adv7393_setoutput()
259 val = state->reg35 & HD_DAC_SWAP_DI; adv7393_setoutput()
264 state->reg35 = val; adv7393_setoutput()
275 struct adv7393_state *state = to_state(sd); adv7393_log_status() local
277 v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std); adv7393_log_status()
278 v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" : adv7393_log_status()
279 ((state->output == 1) ? "Component" : "S-Video")); adv7393_log_status()
320 struct adv7393_state *state = to_state(sd); adv7393_s_std_output() local
323 if (state->std == std) adv7393_s_std_output()
328 state->std = std; adv7393_s_std_output()
336 struct adv7393_state *state = to_state(sd); adv7393_s_routing() local
339 if (state->output == output) adv7393_s_routing()
344 state->output = output; adv7393_s_routing()
361 struct adv7393_state *state = to_state(sd); adv7393_initialize() local
376 err = adv7393_setoutput(sd, state->output); adv7393_initialize()
382 err = adv7393_setstd(sd, state->std); adv7393_initialize()
394 struct adv7393_state *state; adv7393_probe() local
403 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); adv7393_probe()
404 if (state == NULL) adv7393_probe()
407 state->reg00 = ADV7393_POWER_MODE_REG_DEFAULT; adv7393_probe()
408 state->reg01 = 0x00; adv7393_probe()
409 state->reg02 = 0x20; adv7393_probe()
410 state->reg35 = ADV7393_HD_MODE_REG6_DEFAULT; adv7393_probe()
411 state->reg80 = ADV7393_SD_MODE_REG1_DEFAULT; adv7393_probe()
412 state->reg82 = ADV7393_SD_MODE_REG2_DEFAULT; adv7393_probe()
414 state->output = ADV7393_COMPOSITE_ID; adv7393_probe()
415 state->std = V4L2_STD_NTSC; adv7393_probe()
417 v4l2_i2c_subdev_init(&state->sd, client, &adv7393_ops); adv7393_probe()
419 v4l2_ctrl_handler_init(&state->hdl, 3); adv7393_probe()
420 v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops, adv7393_probe()
424 v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops, adv7393_probe()
428 v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops, adv7393_probe()
432 state->sd.ctrl_handler = &state->hdl; adv7393_probe()
433 if (state->hdl.error) { adv7393_probe()
434 int err = state->hdl.error; adv7393_probe()
436 v4l2_ctrl_handler_free(&state->hdl); adv7393_probe()
439 v4l2_ctrl_handler_setup(&state->hdl); adv7393_probe()
441 err = adv7393_initialize(&state->sd); adv7393_probe()
443 v4l2_ctrl_handler_free(&state->hdl); adv7393_probe()
450 struct adv7393_state *state = to_state(sd); adv7393_remove() local
453 v4l2_ctrl_handler_free(&state->hdl); adv7393_remove()
H A Dm52790.c53 struct m52790_state *state = to_state(sd); m52790_write() local
56 u8 sw1 = (state->input | state->output) & 0xff; m52790_write()
57 u8 sw2 = (state->input | state->output) >> 8; m52790_write()
73 struct m52790_state *state = to_state(sd); m52790_s_routing() local
75 state->input = input; m52790_s_routing()
76 state->output = output; m52790_s_routing()
84 struct m52790_state *state = to_state(sd); m52790_g_register() local
89 reg->val = state->input | state->output; m52790_g_register()
95 struct m52790_state *state = to_state(sd); m52790_s_register() local
99 state->input = reg->val & 0x0303; m52790_s_register()
100 state->output = reg->val & ~0x0303; m52790_s_register()
108 struct m52790_state *state = to_state(sd); m52790_log_status() local
111 (state->input | state->output) & 0xff); m52790_log_status()
113 (state->input | state->output) >> 8); m52790_log_status()
148 struct m52790_state *state; m52790_probe() local
158 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); m52790_probe()
159 if (state == NULL) m52790_probe()
162 sd = &state->sd; m52790_probe()
164 state->input = M52790_IN_TUNER; m52790_probe()
165 state->output = M52790_OUT_STEREO; m52790_probe()
H A Dsaa7127.c248 * Encoder Struct, holds the configuration state of the encoder
353 struct saa7127_state *state = to_state(sd); saa7127_set_vps() local
358 if (state->vps_enable != enable) { saa7127_set_vps()
361 state->vps_enable = enable; saa7127_set_vps()
366 state->vps_data[0] = data->data[2]; saa7127_set_vps()
367 state->vps_data[1] = data->data[8]; saa7127_set_vps()
368 state->vps_data[2] = data->data[9]; saa7127_set_vps()
369 state->vps_data[3] = data->data[10]; saa7127_set_vps()
370 state->vps_data[4] = data->data[11]; saa7127_set_vps()
371 v4l2_dbg(1, debug, sd, "Set VPS data %*ph\n", 5, state->vps_data); saa7127_set_vps()
372 saa7127_write(sd, 0x55, state->vps_data[0]); saa7127_set_vps()
373 saa7127_write(sd, 0x56, state->vps_data[1]); saa7127_set_vps()
374 saa7127_write(sd, 0x57, state->vps_data[2]); saa7127_set_vps()
375 saa7127_write(sd, 0x58, state->vps_data[3]); saa7127_set_vps()
376 saa7127_write(sd, 0x59, state->vps_data[4]); saa7127_set_vps()
384 struct saa7127_state *state = to_state(sd); saa7127_set_cc() local
390 if (state->cc_enable != enable) { saa7127_set_cc()
394 (state->xds_enable << 7) | (enable << 6) | 0x11); saa7127_set_cc()
395 state->cc_enable = enable; saa7127_set_cc()
403 state->cc_data = cc; saa7127_set_cc()
411 struct saa7127_state *state = to_state(sd); saa7127_set_xds() local
417 if (state->xds_enable != enable) { saa7127_set_xds()
420 (enable << 7) | (state->cc_enable << 6) | 0x11); saa7127_set_xds()
421 state->xds_enable = enable; saa7127_set_xds()
429 state->xds_data = xds; saa7127_set_xds()
437 struct saa7127_state *state = to_state(sd); saa7127_set_wss() local
442 if (state->wss_enable != enable) { saa7127_set_wss()
445 state->wss_enable = enable; saa7127_set_wss()
454 state->wss_mode = (data->data[1] & 0x3f) << 8 | data->data[0]; saa7127_set_wss()
462 struct saa7127_state *state = to_state(sd); saa7127_set_video_enable() local
466 saa7127_write(sd, 0x2d, state->reg_2d); saa7127_set_video_enable()
467 saa7127_write(sd, 0x61, state->reg_61); saa7127_set_video_enable()
470 saa7127_write(sd, 0x2d, (state->reg_2d & 0xf0)); saa7127_set_video_enable()
471 saa7127_write(sd, 0x61, (state->reg_61 | 0xc0)); saa7127_set_video_enable()
473 state->video_enable = enable; saa7127_set_video_enable()
481 struct saa7127_state *state = to_state(sd); saa7127_set_std() local
487 state->reg_61 = SAA7127_60HZ_DAC_CONTROL; saa7127_set_std()
489 } else if (state->ident == SAA7129 && saa7127_set_std()
497 state->reg_61 = SAA7127_50HZ_SECAM_DAC_CONTROL; saa7127_set_std()
502 state->reg_61 = SAA7127_50HZ_PAL_DAC_CONTROL; saa7127_set_std()
507 state->std = std; saa7127_set_std()
515 struct saa7127_state *state = to_state(sd); saa7127_set_output_type() local
519 state->reg_2d = 0x0f; /* RGB + CVBS (for sync) */ saa7127_set_output_type()
520 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */ saa7127_set_output_type()
524 if (state->ident == SAA7129) saa7127_set_output_type()
525 state->reg_2d = 0x20; /* CVBS only */ saa7127_set_output_type()
527 state->reg_2d = 0x08; /* 00001000 CVBS only, RGB DAC's off (high impedance mode) */ saa7127_set_output_type()
528 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */ saa7127_set_output_type()
532 if (state->ident == SAA7129) saa7127_set_output_type()
533 state->reg_2d = 0x18; /* Y + C */ saa7127_set_output_type()
535 state->reg_2d = 0xff; /*11111111 croma -> R, luma -> CVBS + G + B */ saa7127_set_output_type()
536 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */ saa7127_set_output_type()
540 state->reg_2d = 0x4f; /* reg 2D = 01001111, all DAC's on, RGB + VBS */ saa7127_set_output_type()
541 state->reg_3a = 0x0b; /* reg 3A = 00001011, bypass RGB-matrix */ saa7127_set_output_type()
545 state->reg_2d = 0x0f; /* reg 2D = 00001111, all DAC's on, RGB + CVBS */ saa7127_set_output_type()
546 state->reg_3a = 0x0b; /* reg 3A = 00001011, bypass RGB-matrix */ saa7127_set_output_type()
550 if (state->ident == SAA7129) saa7127_set_output_type()
551 state->reg_2d = 0x38; saa7127_set_output_type()
553 state->reg_2d = 0xbf; saa7127_set_output_type()
554 state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */ saa7127_set_output_type()
564 saa7127_write(sd, 0x2d, state->reg_2d); saa7127_set_output_type()
565 saa7127_write(sd, 0x3a, state->reg_3a | state->reg_3a_cb); saa7127_set_output_type()
566 state->output_type = output; saa7127_set_output_type()
574 struct saa7127_state *state = to_state(sd); saa7127_set_input_type() local
579 state->reg_3a_cb = 0; saa7127_set_input_type()
584 state->reg_3a_cb = 0x80; saa7127_set_input_type()
590 saa7127_write(sd, 0x3a, state->reg_3a | state->reg_3a_cb); saa7127_set_input_type()
591 state->input_type = input; saa7127_set_input_type()
599 struct saa7127_state *state = to_state(sd); saa7127_s_std_output() local
601 if (state->std == std) saa7127_s_std_output()
609 struct saa7127_state *state = to_state(sd); saa7127_s_routing() local
612 if (state->input_type != input) saa7127_s_routing()
614 if (rc == 0 && state->output_type != output) saa7127_s_routing()
621 struct saa7127_state *state = to_state(sd); saa7127_s_stream() local
623 if (state->video_enable == enable) saa7127_s_stream()
630 struct saa7127_state *state = to_state(sd); saa7127_g_sliced_fmt() local
633 if (state->vps_enable) saa7127_g_sliced_fmt()
635 if (state->wss_enable) saa7127_g_sliced_fmt()
637 if (state->cc_enable) { saa7127_g_sliced_fmt()
642 (state->vps_enable ? V4L2_SLICED_VPS : 0) | saa7127_g_sliced_fmt()
643 (state->wss_enable ? V4L2_SLICED_WSS_625 : 0) | saa7127_g_sliced_fmt()
644 (state->cc_enable ? V4L2_SLICED_CAPTION_525 : 0); saa7127_g_sliced_fmt()
682 struct saa7127_state *state = to_state(sd); saa7127_log_status() local
684 v4l2_info(sd, "Standard: %s\n", (state->std & V4L2_STD_525_60) ? "60 Hz" : "50 Hz"); saa7127_log_status()
685 v4l2_info(sd, "Input: %s\n", state->input_type ? "color bars" : "normal"); saa7127_log_status()
686 v4l2_info(sd, "Output: %s\n", state->video_enable ? saa7127_log_status()
687 output_strs[state->output_type] : "disabled"); saa7127_log_status()
688 v4l2_info(sd, "WSS: %s\n", state->wss_enable ? saa7127_log_status()
689 wss_strs[state->wss_mode] : "disabled"); saa7127_log_status()
690 v4l2_info(sd, "VPS: %s\n", state->vps_enable ? "enabled" : "disabled"); saa7127_log_status()
691 v4l2_info(sd, "CC: %s\n", state->cc_enable ? "enabled" : "disabled"); saa7127_log_status()
727 struct saa7127_state *state; saa7127_probe() local
738 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); saa7127_probe()
739 if (state == NULL) saa7127_probe()
742 sd = &state->sd; saa7127_probe()
757 state->ident = id->driver_data; saa7127_probe()
767 state->ident = SAA7129; saa7127_probe()
770 state->ident = SAA7127; saa7127_probe()
794 if (state->ident == SAA7129) saa7127_probe()
H A Dwm8775.c96 struct wm8775_state *state = to_state(sd); wm8775_set_audio() local
98 int muted = 0 != state->mute->val; wm8775_set_audio()
99 u16 volume = (u16)state->vol->val; wm8775_set_audio()
100 u16 balance = (u16)state->bal->val; wm8775_set_audio()
108 wm8775_write(sd, R21, 0x0c0 | state->input); wm8775_set_audio()
115 wm8775_write(sd, R21, state->input); wm8775_set_audio()
121 struct wm8775_state *state = to_state(sd); wm8775_s_routing() local
132 state->input = input; wm8775_s_routing()
133 if (v4l2_ctrl_g_ctrl(state->mute)) wm8775_s_routing()
135 if (!v4l2_ctrl_g_ctrl(state->vol)) wm8775_s_routing()
160 struct wm8775_state *state = to_state(sd); wm8775_log_status() local
162 v4l2_info(sd, "Input: %d\n", state->input); wm8775_log_status()
163 v4l2_ctrl_handler_log_status(&state->hdl, sd->name); wm8775_log_status()
216 struct wm8775_state *state; wm8775_probe() local
233 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); wm8775_probe()
234 if (state == NULL) wm8775_probe()
236 sd = &state->sd; wm8775_probe()
238 state->input = 2; wm8775_probe()
240 v4l2_ctrl_handler_init(&state->hdl, 4); wm8775_probe()
241 state->mute = v4l2_ctrl_new_std(&state->hdl, &wm8775_ctrl_ops, wm8775_probe()
243 state->vol = v4l2_ctrl_new_std(&state->hdl, &wm8775_ctrl_ops, wm8775_probe()
245 state->bal = v4l2_ctrl_new_std(&state->hdl, &wm8775_ctrl_ops, wm8775_probe()
247 state->loud = v4l2_ctrl_new_std(&state->hdl, &wm8775_ctrl_ops, wm8775_probe()
249 sd->ctrl_handler = &state->hdl; wm8775_probe()
250 err = state->hdl.error; wm8775_probe()
252 v4l2_ctrl_handler_free(&state->hdl); wm8775_probe()
283 wm8775_write(sd, R17, (state->loud->val ? ALC_EN : 0) | ALC_HOLD); wm8775_probe()
306 struct wm8775_state *state = to_state(sd); wm8775_remove() local
309 v4l2_ctrl_handler_free(&state->hdl); wm8775_remove()
H A Dvp27smpx.c53 struct vp27smpx_state *state = to_state(sd); vp27smpx_set_audmode() local
73 state->audmode = audmode; vp27smpx_set_audmode()
78 struct vp27smpx_state *state = to_state(sd); vp27smpx_s_radio() local
80 state->radio = 1; vp27smpx_s_radio()
86 struct vp27smpx_state *state = to_state(sd); vp27smpx_s_std() local
88 state->radio = 0; vp27smpx_s_std()
94 struct vp27smpx_state *state = to_state(sd); vp27smpx_s_tuner() local
96 if (!state->radio) vp27smpx_s_tuner()
103 struct vp27smpx_state *state = to_state(sd); vp27smpx_g_tuner() local
105 if (state->radio) vp27smpx_g_tuner()
107 vt->audmode = state->audmode; vp27smpx_g_tuner()
116 struct vp27smpx_state *state = to_state(sd); vp27smpx_log_status() local
118 v4l2_info(sd, "Audio Mode: %u%s\n", state->audmode, vp27smpx_log_status()
119 state->radio ? " (Radio)" : ""); vp27smpx_log_status()
157 struct vp27smpx_state *state; vp27smpx_probe() local
167 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); vp27smpx_probe()
168 if (state == NULL) vp27smpx_probe()
170 sd = &state->sd; vp27smpx_probe()
172 state->audmode = V4L2_TUNER_MODE_STEREO; vp27smpx_probe()
175 vp27smpx_set_audmode(sd, state->audmode); vp27smpx_probe()
H A Dwm8739.c100 struct wm8739_state *state = to_state(sd); wm8739_s_ctrl() local
115 work_l = (min(65536 - state->balance->val, 32768) * state->volume->val) / 32768; wm8739_s_ctrl()
116 work_r = (min(state->balance->val, 32768) * state->volume->val) / 32768; wm8739_s_ctrl()
122 mute = state->mute->val ? 0x80 : 0; wm8739_s_ctrl()
136 struct wm8739_state *state = to_state(sd); wm8739_s_clock_freq() local
138 state->clock_freq = audiofreq; wm8739_s_clock_freq()
164 struct wm8739_state *state = to_state(sd); wm8739_log_status() local
166 v4l2_info(sd, "Frequency: %u Hz\n", state->clock_freq); wm8739_log_status()
167 v4l2_ctrl_handler_log_status(&state->hdl, sd->name); wm8739_log_status()
204 struct wm8739_state *state; wm8739_probe() local
214 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); wm8739_probe()
215 if (state == NULL) wm8739_probe()
217 sd = &state->sd; wm8739_probe()
219 v4l2_ctrl_handler_init(&state->hdl, 2); wm8739_probe()
220 state->volume = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops, wm8739_probe()
222 state->mute = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops, wm8739_probe()
224 state->balance = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops, wm8739_probe()
226 sd->ctrl_handler = &state->hdl; wm8739_probe()
227 if (state->hdl.error) { wm8739_probe()
228 int err = state->hdl.error; wm8739_probe()
230 v4l2_ctrl_handler_free(&state->hdl); wm8739_probe()
233 v4l2_ctrl_cluster(3, &state->volume); wm8739_probe()
235 state->clock_freq = 48000; wm8739_probe()
253 v4l2_ctrl_handler_setup(&state->hdl); wm8739_probe()
260 struct wm8739_state *state = to_state(sd); wm8739_remove() local
263 v4l2_ctrl_handler_free(&state->hdl); wm8739_remove()
/linux-4.1.27/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c23 * Atmel HLCDC Plane state structure.
25 * @base: DRM plane state
260 struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_pos_and_size()
269 (state->crtc_w - 1) | atmel_hlcdc_plane_update_pos_and_size()
270 ((state->crtc_h - 1) << 16)); atmel_hlcdc_plane_update_pos_and_size()
276 (state->src_w - 1) | atmel_hlcdc_plane_update_pos_and_size()
277 ((state->src_h - 1) << 16)); atmel_hlcdc_plane_update_pos_and_size()
283 state->crtc_x | atmel_hlcdc_plane_update_pos_and_size()
284 (state->crtc_y << 16)); atmel_hlcdc_plane_update_pos_and_size()
287 if (state->crtc_w != state->src_w || state->crtc_h != state->src_h) { atmel_hlcdc_plane_update_pos_and_size()
290 if (state->crtc_w != state->src_w) { atmel_hlcdc_plane_update_pos_and_size()
296 if (state->crtc_w < state->src_w) atmel_hlcdc_plane_update_pos_and_size()
303 factor = ((8 * 256 * state->src_w) - (256 * 4)) / atmel_hlcdc_plane_update_pos_and_size()
304 state->crtc_w; atmel_hlcdc_plane_update_pos_and_size()
306 max_memsize = ((factor * state->crtc_w) + (256 * 4)) / atmel_hlcdc_plane_update_pos_and_size()
308 if (max_memsize > state->src_w) atmel_hlcdc_plane_update_pos_and_size()
313 if (state->crtc_h != state->src_h) { atmel_hlcdc_plane_update_pos_and_size()
319 if (state->crtc_w < state->src_w) atmel_hlcdc_plane_update_pos_and_size()
326 factor = ((8 * 256 * state->src_w) - (256 * 4)) / atmel_hlcdc_plane_update_pos_and_size()
327 state->crtc_w; atmel_hlcdc_plane_update_pos_and_size()
329 max_memsize = ((factor * state->crtc_w) + (256 * 4)) / atmel_hlcdc_plane_update_pos_and_size()
331 if (max_memsize > state->src_w) atmel_hlcdc_plane_update_pos_and_size()
343 struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_general_settings()
353 if (atmel_hlcdc_format_embeds_alpha(state->base.fb->pixel_format)) atmel_hlcdc_plane_update_general_settings()
357 ATMEL_HLCDC_LAYER_GA(state->alpha); atmel_hlcdc_plane_update_general_settings()
376 struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_format()
381 ret = atmel_hlcdc_format_to_plane_mode(state->base.fb->pixel_format, atmel_hlcdc_plane_update_format()
386 if ((state->base.fb->pixel_format == DRM_FORMAT_YUV422 || atmel_hlcdc_plane_update_format()
387 state->base.fb->pixel_format == DRM_FORMAT_NV61) && atmel_hlcdc_plane_update_format()
388 (state->base.rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)))) atmel_hlcdc_plane_update_format()
400 if (state->base.fb->pixel_format == DRM_FORMAT_RGB888) atmel_hlcdc_plane_update_format()
411 struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_buffers()
418 atmel_hlcdc_layer_update_set_fb(&plane->layer, state->base.fb, atmel_hlcdc_plane_update_buffers()
419 state->offsets); atmel_hlcdc_plane_update_buffers()
421 for (i = 0; i < state->nplanes; i++) { atmel_hlcdc_plane_update_buffers()
426 state->xstride[i]); atmel_hlcdc_plane_update_buffers()
433 state->pstride[i]); atmel_hlcdc_plane_update_buffers()
453 primary_s = drm_atomic_get_plane_state(c_state->state, atmel_hlcdc_plane_prepare_disc_area()
467 ovl_s = drm_atomic_get_plane_state(c_state->state, ovl); drm_atomic_crtc_state_for_each_plane()
506 struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_disc_area()
512 if (!state->disc_updated) atmel_hlcdc_plane_update_disc_area()
515 disc_surface = state->disc_h * state->disc_w; atmel_hlcdc_plane_update_disc_area()
527 state->disc_x | (state->disc_y << 16)); atmel_hlcdc_plane_update_disc_area()
532 (state->disc_w - 1) | atmel_hlcdc_plane_update_disc_area()
533 ((state->disc_h - 1) << 16)); atmel_hlcdc_plane_update_disc_area()
540 struct atmel_hlcdc_plane_state *state = atmel_hlcdc_plane_atomic_check() local
544 struct drm_framebuffer *fb = state->base.fb; atmel_hlcdc_plane_atomic_check()
558 if (!state->base.crtc || !fb) atmel_hlcdc_plane_atomic_check()
561 crtc_state = s->state->crtc_states[drm_crtc_index(s->crtc)]; atmel_hlcdc_plane_atomic_check()
564 state->src_x = s->src_x; atmel_hlcdc_plane_atomic_check()
565 state->src_y = s->src_y; atmel_hlcdc_plane_atomic_check()
566 state->src_h = s->src_h; atmel_hlcdc_plane_atomic_check()
567 state->src_w = s->src_w; atmel_hlcdc_plane_atomic_check()
568 state->crtc_x = s->crtc_x; atmel_hlcdc_plane_atomic_check()
569 state->crtc_y = s->crtc_y; atmel_hlcdc_plane_atomic_check()
570 state->crtc_h = s->crtc_h; atmel_hlcdc_plane_atomic_check()
571 state->crtc_w = s->crtc_w; atmel_hlcdc_plane_atomic_check()
572 if ((state->src_x | state->src_y | state->src_w | state->src_h) & atmel_hlcdc_plane_atomic_check()
576 state->src_x >>= 16; atmel_hlcdc_plane_atomic_check()
577 state->src_y >>= 16; atmel_hlcdc_plane_atomic_check()
578 state->src_w >>= 16; atmel_hlcdc_plane_atomic_check()
579 state->src_h >>= 16; atmel_hlcdc_plane_atomic_check()
581 state->nplanes = drm_format_num_planes(fb->pixel_format); atmel_hlcdc_plane_atomic_check()
582 if (state->nplanes > ATMEL_HLCDC_MAX_PLANES) atmel_hlcdc_plane_atomic_check()
588 if (state->base.rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))) { atmel_hlcdc_plane_atomic_check()
589 tmp = state->crtc_w; atmel_hlcdc_plane_atomic_check()
590 state->crtc_w = state->crtc_h; atmel_hlcdc_plane_atomic_check()
591 state->crtc_h = tmp; atmel_hlcdc_plane_atomic_check()
592 tmp = state->src_w; atmel_hlcdc_plane_atomic_check()
593 state->src_w = state->src_h; atmel_hlcdc_plane_atomic_check()
594 state->src_h = tmp; atmel_hlcdc_plane_atomic_check()
597 if (state->crtc_x + state->crtc_w > mode->hdisplay) atmel_hlcdc_plane_atomic_check()
598 patched_crtc_w = mode->hdisplay - state->crtc_x; atmel_hlcdc_plane_atomic_check()
600 patched_crtc_w = state->crtc_w; atmel_hlcdc_plane_atomic_check()
602 if (state->crtc_x < 0) { atmel_hlcdc_plane_atomic_check()
603 patched_crtc_w += state->crtc_x; atmel_hlcdc_plane_atomic_check()
604 x_offset = -state->crtc_x; atmel_hlcdc_plane_atomic_check()
605 state->crtc_x = 0; atmel_hlcdc_plane_atomic_check()
608 if (state->crtc_y + state->crtc_h > mode->vdisplay) atmel_hlcdc_plane_atomic_check()
609 patched_crtc_h = mode->vdisplay - state->crtc_y; atmel_hlcdc_plane_atomic_check()
611 patched_crtc_h = state->crtc_h; atmel_hlcdc_plane_atomic_check()
613 if (state->crtc_y < 0) { atmel_hlcdc_plane_atomic_check()
614 patched_crtc_h += state->crtc_y; atmel_hlcdc_plane_atomic_check()
615 y_offset = -state->crtc_y; atmel_hlcdc_plane_atomic_check()
616 state->crtc_y = 0; atmel_hlcdc_plane_atomic_check()
619 patched_src_w = DIV_ROUND_CLOSEST(patched_crtc_w * state->src_w, atmel_hlcdc_plane_atomic_check()
620 state->crtc_w); atmel_hlcdc_plane_atomic_check()
621 patched_src_h = DIV_ROUND_CLOSEST(patched_crtc_h * state->src_h, atmel_hlcdc_plane_atomic_check()
622 state->crtc_h); atmel_hlcdc_plane_atomic_check()
627 for (i = 0; i < state->nplanes; i++) { atmel_hlcdc_plane_atomic_check()
632 state->bpp[i] = drm_format_plane_cpp(fb->pixel_format, i); atmel_hlcdc_plane_atomic_check()
633 if (!state->bpp[i]) atmel_hlcdc_plane_atomic_check()
636 switch (state->base.rotation & 0xf) { atmel_hlcdc_plane_atomic_check()
638 offset = ((y_offset + state->src_y + patched_src_w - 1) / atmel_hlcdc_plane_atomic_check()
640 offset += ((x_offset + state->src_x) / xdiv) * atmel_hlcdc_plane_atomic_check()
641 state->bpp[i]; atmel_hlcdc_plane_atomic_check()
642 state->xstride[i] = ((patched_src_w - 1) / ydiv) * atmel_hlcdc_plane_atomic_check()
644 state->pstride[i] = -fb->pitches[i] - state->bpp[i]; atmel_hlcdc_plane_atomic_check()
647 offset = ((y_offset + state->src_y + patched_src_h - 1) / atmel_hlcdc_plane_atomic_check()
649 offset += ((x_offset + state->src_x + patched_src_w - 1) / atmel_hlcdc_plane_atomic_check()
650 xdiv) * state->bpp[i]; atmel_hlcdc_plane_atomic_check()
651 state->xstride[i] = ((((patched_src_w - 1) / xdiv) - 1) * atmel_hlcdc_plane_atomic_check()
652 state->bpp[i]) - fb->pitches[i]; atmel_hlcdc_plane_atomic_check()
653 state->pstride[i] = -2 * state->bpp[i]; atmel_hlcdc_plane_atomic_check()
656 offset = ((y_offset + state->src_y) / ydiv) * atmel_hlcdc_plane_atomic_check()
658 offset += ((x_offset + state->src_x + patched_src_h - 1) / atmel_hlcdc_plane_atomic_check()
659 xdiv) * state->bpp[i]; atmel_hlcdc_plane_atomic_check()
660 state->xstride[i] = -(((patched_src_w - 1) / ydiv) * atmel_hlcdc_plane_atomic_check()
662 (2 * state->bpp[i]); atmel_hlcdc_plane_atomic_check()
663 state->pstride[i] = fb->pitches[i] - state->bpp[i]; atmel_hlcdc_plane_atomic_check()
667 offset = ((y_offset + state->src_y) / ydiv) * atmel_hlcdc_plane_atomic_check()
669 offset += ((x_offset + state->src_x) / xdiv) * atmel_hlcdc_plane_atomic_check()
670 state->bpp[i]; atmel_hlcdc_plane_atomic_check()
671 state->xstride[i] = fb->pitches[i] - atmel_hlcdc_plane_atomic_check()
673 state->bpp[i]); atmel_hlcdc_plane_atomic_check()
674 state->pstride[i] = 0; atmel_hlcdc_plane_atomic_check()
678 state->offsets[i] = offset + fb->offsets[i]; atmel_hlcdc_plane_atomic_check()
681 state->src_w = patched_src_w; atmel_hlcdc_plane_atomic_check()
682 state->src_h = patched_src_h; atmel_hlcdc_plane_atomic_check()
683 state->crtc_w = patched_crtc_w; atmel_hlcdc_plane_atomic_check()
684 state->crtc_h = patched_crtc_h; atmel_hlcdc_plane_atomic_check()
687 (mode->hdisplay != state->crtc_w || atmel_hlcdc_plane_atomic_check()
688 mode->vdisplay != state->crtc_h)) atmel_hlcdc_plane_atomic_check()
692 state->crtc_h > plane->layer.desc->max_height) atmel_hlcdc_plane_atomic_check()
696 state->crtc_w > plane->layer.desc->max_width) atmel_hlcdc_plane_atomic_check()
699 if ((state->crtc_h != state->src_h || state->crtc_w != state->src_w) && atmel_hlcdc_plane_atomic_check()
701 atmel_hlcdc_format_embeds_alpha(state->base.fb->pixel_format))) atmel_hlcdc_plane_atomic_check()
704 if (state->crtc_x < 0 || state->crtc_y < 0) atmel_hlcdc_plane_atomic_check()
707 if (state->crtc_w + state->crtc_x > mode->hdisplay || atmel_hlcdc_plane_atomic_check()
708 state->crtc_h + state->crtc_y > mode->vdisplay) atmel_hlcdc_plane_atomic_check()
727 struct atmel_hlcdc_plane_state *state = atmel_hlcdc_plane_atomic_update() local
728 drm_plane_state_to_atmel_hlcdc_plane_state(p->state); atmel_hlcdc_plane_atomic_update()
730 if (!p->state->crtc || !p->state->fb) atmel_hlcdc_plane_atomic_update()
733 atmel_hlcdc_plane_update_pos_and_size(plane, state); atmel_hlcdc_plane_atomic_update()
734 atmel_hlcdc_plane_update_general_settings(plane, state); atmel_hlcdc_plane_atomic_update()
735 atmel_hlcdc_plane_update_format(plane, state); atmel_hlcdc_plane_atomic_update()
736 atmel_hlcdc_plane_update_buffers(plane, state); atmel_hlcdc_plane_atomic_update()
737 atmel_hlcdc_plane_update_disc_area(plane, state); atmel_hlcdc_plane_atomic_update()
770 struct atmel_hlcdc_plane_state *state = atmel_hlcdc_plane_atomic_set_property() local
774 state->alpha = val; atmel_hlcdc_plane_atomic_set_property()
788 const struct atmel_hlcdc_plane_state *state = atmel_hlcdc_plane_atomic_get_property() local
792 *val = state->alpha; atmel_hlcdc_plane_atomic_get_property()
852 struct atmel_hlcdc_plane_state *state; atmel_hlcdc_plane_reset() local
854 if (p->state) { atmel_hlcdc_plane_reset()
855 state = drm_plane_state_to_atmel_hlcdc_plane_state(p->state); atmel_hlcdc_plane_reset()
857 if (state->base.fb) atmel_hlcdc_plane_reset()
858 drm_framebuffer_unreference(state->base.fb); atmel_hlcdc_plane_reset()
860 kfree(state); atmel_hlcdc_plane_reset()
861 p->state = NULL; atmel_hlcdc_plane_reset()
864 state = kzalloc(sizeof(*state), GFP_KERNEL); atmel_hlcdc_plane_reset()
865 if (state) { atmel_hlcdc_plane_reset()
866 state->alpha = 255; atmel_hlcdc_plane_reset()
867 p->state = &state->base; atmel_hlcdc_plane_reset()
868 p->state->plane = p; atmel_hlcdc_plane_reset()
875 struct atmel_hlcdc_plane_state *state = atmel_hlcdc_plane_atomic_duplicate_state() local
876 drm_plane_state_to_atmel_hlcdc_plane_state(p->state); atmel_hlcdc_plane_atomic_duplicate_state()
879 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); atmel_hlcdc_plane_atomic_duplicate_state()
894 struct atmel_hlcdc_plane_state *state = atmel_hlcdc_plane_atomic_destroy_state() local
900 kfree(state); atmel_hlcdc_plane_atomic_destroy_state()
259 atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_pos_and_size() argument
342 atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_general_settings() argument
375 atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_format() argument
410 atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_buffers() argument
505 atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) atmel_hlcdc_plane_update_disc_area() argument
/linux-4.1.27/drivers/gpu/drm/rcar-du/
H A Drcar_du_plane.c47 struct rcar_du_plane_state *state = rcar_du_plane_setup_fb() local
48 to_rcar_du_plane_state(plane->plane.state); rcar_du_plane_setup_fb()
49 struct drm_framebuffer *fb = plane->plane.state->fb; rcar_du_plane_setup_fb()
51 unsigned int src_x = state->state.src_x >> 16; rcar_du_plane_setup_fb()
52 unsigned int src_y = state->state.src_y >> 16; rcar_du_plane_setup_fb()
53 unsigned int index = state->hwindex; rcar_du_plane_setup_fb()
58 interlaced = state->state.crtc->state->adjusted_mode.flags rcar_du_plane_setup_fb()
64 if (state->format->planes == 2) rcar_du_plane_setup_fb()
67 mwr = fb->pitches[0] * 8 / state->format->bpp; rcar_du_plane_setup_fb()
69 if (interlaced && state->format->bpp == 32) rcar_du_plane_setup_fb()
88 (!interlaced && state->format->bpp == 32 ? 2 : 1)); rcar_du_plane_setup_fb()
93 if (state->format->planes == 2) { rcar_du_plane_setup_fb()
100 (state->format->bpp == 16 ? 2 : 1) / 2); rcar_du_plane_setup_fb()
111 struct rcar_du_plane_state *state = rcar_du_plane_setup_mode() local
112 to_rcar_du_plane_state(plane->plane.state); rcar_du_plane_setup_mode()
126 if (state->format->fourcc != DRM_FORMAT_XRGB1555) rcar_du_plane_setup_mode()
130 PnALPHAR_ABIT_X | state->alpha); rcar_du_plane_setup_mode()
132 pnmr = PnMR_BM_MD | state->format->pnmr; rcar_du_plane_setup_mode()
138 if ((state->colorkey & RCAR_DU_COLORKEY_MASK) == RCAR_DU_COLORKEY_NONE) rcar_du_plane_setup_mode()
142 if (state->format->fourcc == DRM_FORMAT_YUYV) rcar_du_plane_setup_mode()
147 switch (state->format->fourcc) { rcar_du_plane_setup_mode()
149 colorkey = ((state->colorkey & 0xf80000) >> 8) rcar_du_plane_setup_mode()
150 | ((state->colorkey & 0x00fc00) >> 5) rcar_du_plane_setup_mode()
151 | ((state->colorkey & 0x0000f8) >> 3); rcar_du_plane_setup_mode()
157 colorkey = ((state->colorkey & 0xf80000) >> 9) rcar_du_plane_setup_mode()
158 | ((state->colorkey & 0x00f800) >> 6) rcar_du_plane_setup_mode()
159 | ((state->colorkey & 0x0000f8) >> 3); rcar_du_plane_setup_mode()
166 PnTC3R_CODE | (state->colorkey & 0xffffff)); rcar_du_plane_setup_mode()
174 struct rcar_du_plane_state *state = __rcar_du_plane_setup() local
175 to_rcar_du_plane_state(plane->plane.state); __rcar_du_plane_setup()
187 ddcr4 |= state->format->edf | PnDDCR4_CODE; __rcar_du_plane_setup()
191 if (state->format->planes == 2) { __rcar_du_plane_setup()
192 if (state->hwindex != index) { __rcar_du_plane_setup()
193 if (state->format->fourcc == DRM_FORMAT_NV12 || __rcar_du_plane_setup()
194 state->format->fourcc == DRM_FORMAT_NV21) __rcar_du_plane_setup()
197 if (state->format->fourcc == DRM_FORMAT_NV21) __rcar_du_plane_setup()
210 rcar_du_plane_write(rgrp, index, PnDSXR, plane->plane.state->crtc_w); __rcar_du_plane_setup()
211 rcar_du_plane_write(rgrp, index, PnDSYR, plane->plane.state->crtc_h); __rcar_du_plane_setup()
212 rcar_du_plane_write(rgrp, index, PnDPXR, plane->plane.state->crtc_x); __rcar_du_plane_setup()
213 rcar_du_plane_write(rgrp, index, PnDPYR, plane->plane.state->crtc_y); __rcar_du_plane_setup()
224 struct rcar_du_plane_state *state = rcar_du_plane_setup() local
225 to_rcar_du_plane_state(plane->plane.state); rcar_du_plane_setup()
227 __rcar_du_plane_setup(plane, state->hwindex); rcar_du_plane_setup()
228 if (state->format->planes == 2) rcar_du_plane_setup()
229 __rcar_du_plane_setup(plane, (state->hwindex + 1) % 8); rcar_du_plane_setup()
235 struct drm_plane_state *state) rcar_du_plane_atomic_check()
237 struct rcar_du_plane_state *rstate = to_rcar_du_plane_state(state); rcar_du_plane_atomic_check()
241 if (!state->fb || !state->crtc) { rcar_du_plane_atomic_check()
246 if (state->src_w >> 16 != state->crtc_w || rcar_du_plane_atomic_check()
247 state->src_h >> 16 != state->crtc_h) { rcar_du_plane_atomic_check()
252 rstate->format = rcar_du_format_info(state->fb->pixel_format); rcar_du_plane_atomic_check()
255 state->fb->pixel_format); rcar_du_plane_atomic_check()
267 if (plane->state->crtc) rcar_du_plane_atomic_update()
278 struct rcar_du_plane_state *state; rcar_du_plane_reset() local
280 if (plane->state && plane->state->fb) rcar_du_plane_reset()
281 drm_framebuffer_unreference(plane->state->fb); rcar_du_plane_reset()
283 kfree(plane->state); rcar_du_plane_reset()
284 plane->state = NULL; rcar_du_plane_reset()
286 state = kzalloc(sizeof(*state), GFP_KERNEL); rcar_du_plane_reset()
287 if (state == NULL) rcar_du_plane_reset()
290 state->hwindex = -1; rcar_du_plane_reset()
291 state->alpha = 255; rcar_du_plane_reset()
292 state->colorkey = RCAR_DU_COLORKEY_NONE; rcar_du_plane_reset()
293 state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1; rcar_du_plane_reset()
295 plane->state = &state->state; rcar_du_plane_reset()
296 plane->state->plane = plane; rcar_du_plane_reset()
302 struct rcar_du_plane_state *state; rcar_du_plane_atomic_duplicate_state() local
305 state = to_rcar_du_plane_state(plane->state); rcar_du_plane_atomic_duplicate_state()
306 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); rcar_du_plane_atomic_duplicate_state()
310 if (copy->state.fb) rcar_du_plane_atomic_duplicate_state()
311 drm_framebuffer_reference(copy->state.fb); rcar_du_plane_atomic_duplicate_state()
313 return &copy->state; rcar_du_plane_atomic_duplicate_state()
317 struct drm_plane_state *state) rcar_du_plane_atomic_destroy_state()
319 if (state->fb) rcar_du_plane_atomic_destroy_state()
320 drm_framebuffer_unreference(state->fb); rcar_du_plane_atomic_destroy_state()
322 kfree(to_rcar_du_plane_state(state)); rcar_du_plane_atomic_destroy_state()
326 struct drm_plane_state *state, rcar_du_plane_atomic_set_property()
330 struct rcar_du_plane_state *rstate = to_rcar_du_plane_state(state); rcar_du_plane_atomic_set_property()
347 const struct drm_plane_state *state, struct drm_property *property, rcar_du_plane_atomic_get_property()
351 container_of(state, const struct rcar_du_plane_state, state); rcar_du_plane_atomic_get_property()
234 rcar_du_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) rcar_du_plane_atomic_check() argument
316 rcar_du_plane_atomic_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) rcar_du_plane_atomic_destroy_state() argument
325 rcar_du_plane_atomic_set_property(struct drm_plane *plane, struct drm_plane_state *state, struct drm_property *property, uint64_t val) rcar_du_plane_atomic_set_property() argument
346 rcar_du_plane_atomic_get_property(struct drm_plane *plane, const struct drm_plane_state *state, struct drm_property *property, uint64_t *val) rcar_du_plane_atomic_get_property() argument
/linux-4.1.27/lib/
H A Drandom32.c54 * @state: pointer to state structure holding seeded state.
59 u32 prandom_u32_state(struct rnd_state *state) prandom_u32_state() argument
62 state->s1 = TAUSWORTHE(state->s1, 6U, 13U, 4294967294U, 18U); prandom_u32_state()
63 state->s2 = TAUSWORTHE(state->s2, 2U, 27U, 4294967288U, 2U); prandom_u32_state()
64 state->s3 = TAUSWORTHE(state->s3, 13U, 21U, 4294967280U, 7U); prandom_u32_state()
65 state->s4 = TAUSWORTHE(state->s4, 3U, 12U, 4294967168U, 13U); prandom_u32_state()
67 return (state->s1 ^ state->s2 ^ state->s3 ^ state->s4); prandom_u32_state()
80 struct rnd_state *state = &get_cpu_var(net_rand_state); prandom_u32() local
83 res = prandom_u32_state(state); prandom_u32()
84 put_cpu_var(state); prandom_u32()
93 * @state: pointer to state structure holding seeded state.
100 void prandom_bytes_state(struct rnd_state *state, void *buf, size_t bytes) prandom_bytes_state() argument
105 put_unaligned(prandom_u32_state(state), (u32 *) ptr); prandom_bytes_state()
111 u32 rem = prandom_u32_state(state); prandom_bytes_state()
128 struct rnd_state *state = &get_cpu_var(net_rand_state); prandom_bytes() local
130 prandom_bytes_state(state, buf, bytes); prandom_bytes()
131 put_cpu_var(state); prandom_bytes()
135 static void prandom_warmup(struct rnd_state *state) prandom_warmup() argument
138 prandom_u32_state(state); prandom_warmup()
139 prandom_u32_state(state); prandom_warmup()
140 prandom_u32_state(state); prandom_warmup()
141 prandom_u32_state(state); prandom_warmup()
142 prandom_u32_state(state); prandom_warmup()
143 prandom_u32_state(state); prandom_warmup()
144 prandom_u32_state(state); prandom_warmup()
145 prandom_u32_state(state); prandom_warmup()
146 prandom_u32_state(state); prandom_warmup()
147 prandom_u32_state(state); prandom_warmup()
160 static void prandom_seed_early(struct rnd_state *state, u32 seed, prandom_seed_early() argument
165 state->s1 = __seed(HWSEED() ^ LCG(seed), 2U); prandom_seed_early()
166 state->s2 = __seed(HWSEED() ^ LCG(state->s1), 8U); prandom_seed_early()
167 state->s3 = __seed(HWSEED() ^ LCG(state->s2), 16U); prandom_seed_early()
168 state->s4 = __seed(HWSEED() ^ LCG(state->s3), 128U); prandom_seed_early()
185 struct rnd_state *state = &per_cpu(net_rand_state, i); for_each_possible_cpu() local
187 state->s1 = __seed(state->s1 ^ entropy, 2U); for_each_possible_cpu()
188 prandom_warmup(state); for_each_possible_cpu()
204 struct rnd_state *state = &per_cpu(net_rand_state,i); for_each_possible_cpu() local
207 prandom_seed_early(state, weak_seed, true); for_each_possible_cpu()
208 prandom_warmup(state); for_each_possible_cpu()
271 struct rnd_state *state = &per_cpu(net_rand_state,i); for_each_possible_cpu() local
275 state->s1 = __seed(seeds[0], 2U); for_each_possible_cpu()
276 state->s2 = __seed(seeds[1], 8U); for_each_possible_cpu()
277 state->s3 = __seed(seeds[2], 16U); for_each_possible_cpu()
278 state->s4 = __seed(seeds[3], 128U); for_each_possible_cpu()
280 prandom_warmup(state); for_each_possible_cpu()
424 struct rnd_state state; prandom_state_selftest() local
426 prandom_seed_early(&state, test1[i].seed, false); prandom_state_selftest()
427 prandom_warmup(&state); prandom_state_selftest()
429 if (test1[i].result != prandom_u32_state(&state)) prandom_state_selftest()
439 struct rnd_state state; prandom_state_selftest() local
441 prandom_seed_early(&state, test2[i].seed, false); prandom_state_selftest()
442 prandom_warmup(&state); prandom_state_selftest()
445 prandom_u32_state(&state); prandom_state_selftest()
447 if (test2[i].result != prandom_u32_state(&state)) prandom_state_selftest()
/linux-4.1.27/kernel/power/
H A Dsuspend.c100 static bool valid_state(suspend_state_t state) valid_state() argument
107 return suspend_ops && suspend_ops->valid && suspend_ops->valid(state); valid_state()
111 * If this is set, the "mem" label always corresponds to the deepest sleep state
112 * available, the "standby" label corresponds to the second deepest sleep state
114 * available sleep state (if there is one).
160 int suspend_valid_only_mem(suspend_state_t state) suspend_valid_only_mem() argument
162 return state == PM_SUSPEND_MEM; suspend_valid_only_mem()
166 static bool sleep_state_supported(suspend_state_t state) sleep_state_supported() argument
168 return state == PM_SUSPEND_FREEZE || (suspend_ops && suspend_ops->enter); sleep_state_supported()
171 static int platform_suspend_prepare(suspend_state_t state) platform_suspend_prepare() argument
173 return state != PM_SUSPEND_FREEZE && suspend_ops->prepare ? platform_suspend_prepare()
177 static int platform_suspend_prepare_late(suspend_state_t state) platform_suspend_prepare_late() argument
179 return state == PM_SUSPEND_FREEZE && freeze_ops && freeze_ops->prepare ? platform_suspend_prepare_late()
183 static int platform_suspend_prepare_noirq(suspend_state_t state) platform_suspend_prepare_noirq() argument
185 return state != PM_SUSPEND_FREEZE && suspend_ops->prepare_late ? platform_suspend_prepare_noirq()
189 static void platform_resume_noirq(suspend_state_t state) platform_resume_noirq() argument
191 if (state != PM_SUSPEND_FREEZE && suspend_ops->wake) platform_resume_noirq()
195 static void platform_resume_early(suspend_state_t state) platform_resume_early() argument
197 if (state == PM_SUSPEND_FREEZE && freeze_ops && freeze_ops->restore) platform_resume_early()
201 static void platform_resume_finish(suspend_state_t state) platform_resume_finish() argument
203 if (state != PM_SUSPEND_FREEZE && suspend_ops->finish) platform_resume_finish()
207 static int platform_suspend_begin(suspend_state_t state) platform_suspend_begin() argument
209 if (state == PM_SUSPEND_FREEZE && freeze_ops && freeze_ops->begin) platform_suspend_begin()
212 return suspend_ops->begin(state); platform_suspend_begin()
217 static void platform_resume_end(suspend_state_t state) platform_resume_end() argument
219 if (state == PM_SUSPEND_FREEZE && freeze_ops && freeze_ops->end) platform_resume_end()
225 static void platform_recover(suspend_state_t state) platform_recover() argument
227 if (state != PM_SUSPEND_FREEZE && suspend_ops->recover) platform_recover()
231 static bool platform_suspend_again(suspend_state_t state) platform_suspend_again() argument
233 return state != PM_SUSPEND_FREEZE && suspend_ops->suspend_again ? platform_suspend_again()
258 * suspend_prepare - Prepare for entering system sleep state.
260 * Common code run for every system sleep state that can be entered (except for
264 static int suspend_prepare(suspend_state_t state) suspend_prepare() argument
268 if (!sleep_state_supported(state)) suspend_prepare()
304 * suspend_enter - Make the system enter the given sleep state.
305 * @state: System sleep state to enter.
306 * @wakeup: Returns information that the sleep state should not be re-entered.
310 static int suspend_enter(suspend_state_t state, bool *wakeup) suspend_enter() argument
314 error = platform_suspend_prepare(state); suspend_enter()
323 error = platform_suspend_prepare_late(state); suspend_enter()
332 error = platform_suspend_prepare_noirq(state); suspend_enter()
345 if (state == PM_SUSPEND_FREEZE) { suspend_enter()
346 trace_suspend_resume(TPS("machine_suspend"), state, true); suspend_enter()
348 trace_suspend_resume(TPS("machine_suspend"), state, false); suspend_enter()
364 state, true); suspend_enter()
365 error = suspend_ops->enter(state); suspend_enter()
367 state, false); suspend_enter()
380 platform_resume_noirq(state); suspend_enter()
384 platform_resume_early(state); suspend_enter()
390 platform_resume_finish(state); suspend_enter()
395 * suspend_devices_and_enter - Suspend devices and enter system sleep state.
396 * @state: System sleep state to enter.
398 int suspend_devices_and_enter(suspend_state_t state) suspend_devices_and_enter() argument
403 if (!sleep_state_supported(state)) suspend_devices_and_enter()
406 error = platform_suspend_begin(state); suspend_devices_and_enter()
422 error = suspend_enter(state, &wakeup); suspend_devices_and_enter()
423 } while (!error && !wakeup && platform_suspend_again(state)); suspend_devices_and_enter()
429 trace_suspend_resume(TPS("resume_console"), state, true); suspend_devices_and_enter()
431 trace_suspend_resume(TPS("resume_console"), state, false); suspend_devices_and_enter()
434 platform_resume_end(state); suspend_devices_and_enter()
438 platform_recover(state); suspend_devices_and_enter()
456 * enter_state - Do common work needed to enter system sleep state.
457 * @state: System sleep state to enter.
459 * Make sure that no one else is trying to put the system into a sleep state.
461 * system enter the given sleep state and clean up after wakeup.
463 static int enter_state(suspend_state_t state) enter_state() argument
467 trace_suspend_resume(TPS("suspend_enter"), state, true); enter_state()
468 if (state == PM_SUSPEND_FREEZE) { enter_state()
471 pr_warning("PM: Unsupported test mode for freeze state," enter_state()
476 } else if (!valid_state(state)) { enter_state()
482 if (state == PM_SUSPEND_FREEZE) enter_state()
491 pr_debug("PM: Preparing system for %s sleep\n", pm_states[state]); enter_state()
492 error = suspend_prepare(state); enter_state()
499 trace_suspend_resume(TPS("suspend_enter"), state, false); enter_state()
500 pr_debug("PM: Entering %s sleep\n", pm_states[state]); enter_state()
502 error = suspend_devices_and_enter(state); enter_state()
515 * @state: System sleep state to enter.
517 * Check if the value of @state represents one of the supported states,
520 int pm_suspend(suspend_state_t state) pm_suspend() argument
524 if (state <= PM_SUSPEND_ON || state >= PM_SUSPEND_MAX) pm_suspend()
527 error = enter_state(state); pm_suspend()
/linux-4.1.27/lib/zlib_inflate/
H A Dinflate.c25 struct inflate_state *state; zlib_inflateReset() local
27 if (strm == NULL || strm->state == NULL) return Z_STREAM_ERROR; zlib_inflateReset()
28 state = (struct inflate_state *)strm->state; zlib_inflateReset()
29 strm->total_in = strm->total_out = state->total = 0; zlib_inflateReset()
32 state->mode = HEAD; zlib_inflateReset()
33 state->last = 0; zlib_inflateReset()
34 state->havedict = 0; zlib_inflateReset()
35 state->dmax = 32768U; zlib_inflateReset()
36 state->hold = 0; zlib_inflateReset()
37 state->bits = 0; zlib_inflateReset()
38 state->lencode = state->distcode = state->next = state->codes; zlib_inflateReset()
41 state->wsize = 1U << state->wbits; zlib_inflateReset()
42 state->write = 0; zlib_inflateReset()
43 state->whave = 0; zlib_inflateReset()
50 struct inflate_state *state; zlib_inflateInit2() local
55 state = &WS(strm)->inflate_state; zlib_inflateInit2()
56 strm->state = (struct internal_state *)state; zlib_inflateInit2()
59 state->wrap = 0; zlib_inflateInit2()
63 state->wrap = (windowBits >> 4) + 1; zlib_inflateInit2()
68 state->wbits = (unsigned)windowBits; zlib_inflateInit2()
69 state->window = &WS(strm)->working_window[0]; zlib_inflateInit2()
75 Return state with length and distance decoding tables and index sizes set to
78 static void zlib_fixedtables(struct inflate_state *state) zlib_fixedtables() argument
81 state->lencode = lenfix; zlib_fixedtables()
82 state->lenbits = 9; zlib_fixedtables()
83 state->distcode = distfix; zlib_fixedtables()
84 state->distbits = 5; zlib_fixedtables()
103 struct inflate_state *state; zlib_updatewindow() local
106 state = (struct inflate_state *)strm->state; zlib_updatewindow()
108 /* copy state->wsize or less output bytes into the circular window */ zlib_updatewindow()
110 if (copy >= state->wsize) { zlib_updatewindow()
111 memcpy(state->window, strm->next_out - state->wsize, state->wsize); zlib_updatewindow()
112 state->write = 0; zlib_updatewindow()
113 state->whave = state->wsize; zlib_updatewindow()
116 dist = state->wsize - state->write; zlib_updatewindow()
118 memcpy(state->window + state->write, strm->next_out - copy, dist); zlib_updatewindow()
121 memcpy(state->window, strm->next_out - copy, copy); zlib_updatewindow()
122 state->write = copy; zlib_updatewindow()
123 state->whave = state->wsize; zlib_updatewindow()
126 state->write += dist; zlib_updatewindow()
127 if (state->write == state->wsize) state->write = 0; zlib_updatewindow()
128 if (state->whave < state->wsize) state->whave += dist; zlib_updatewindow()
148 struct inflate_state *state; zlib_inflateSyncPacket() local
150 if (strm == NULL || strm->state == NULL) return Z_STREAM_ERROR; zlib_inflateSyncPacket()
151 state = (struct inflate_state *)strm->state; zlib_inflateSyncPacket()
153 if (state->mode == STORED && state->bits == 0) { zlib_inflateSyncPacket()
154 state->mode = TYPE; zlib_inflateSyncPacket()
165 /* Load registers with state in inflate() for speed */
172 hold = state->hold; \
173 bits = state->bits; \
176 /* Restore state from registers in inflate() */
183 state->hold = hold; \
184 state->bits = bits; \
236 inflate() uses a state machine to process as much input data and generate as
237 much output data as possible before returning. The state machine is
240 for (;;) switch (state) {
246 state = STATEm;
253 next state. The NEEDBITS() macro is usually the way the state evaluates
276 state information is maintained to continue the loop where it left off
278 would all have to actually be part of the saved state in case NEEDBITS()
287 state = STATEx;
290 As shown above, if the next state is also the next case, then the break
293 A state may also return if there is not enough output space available to
294 complete that state. Those states are copying stored data, writing a
319 struct inflate_state *state; zlib_inflate() local
338 if (strm == NULL || strm->state == NULL || zlib_inflate()
342 state = (struct inflate_state *)strm->state; zlib_inflate()
344 if (state->mode == TYPE) state->mode = TYPEDO; /* skip check */ zlib_inflate()
350 switch (state->mode) { zlib_inflate()
352 if (state->wrap == 0) { zlib_inflate()
353 state->mode = TYPEDO; zlib_inflate()
360 state->mode = BAD; zlib_inflate()
365 state->mode = BAD; zlib_inflate()
370 if (len > state->wbits) { zlib_inflate()
372 state->mode = BAD; zlib_inflate()
375 state->dmax = 1U << len; zlib_inflate()
376 strm->adler = state->check = zlib_adler32(0L, NULL, 0); zlib_inflate()
377 state->mode = hold & 0x200 ? DICTID : TYPE; zlib_inflate()
382 strm->adler = state->check = REVERSE(hold); zlib_inflate()
384 state->mode = DICT; zlib_inflate()
386 if (state->havedict == 0) { zlib_inflate()
390 strm->adler = state->check = zlib_adler32(0L, NULL, 0); zlib_inflate()
391 state->mode = TYPE; zlib_inflate()
395 if (state->last) { zlib_inflate()
397 state->mode = CHECK; zlib_inflate()
401 state->last = BITS(1); zlib_inflate()
405 state->mode = STORED; zlib_inflate()
408 zlib_fixedtables(state); zlib_inflate()
409 state->mode = LEN; /* decode codes */ zlib_inflate()
412 state->mode = TABLE; zlib_inflate()
416 state->mode = BAD; zlib_inflate()
425 state->mode = BAD; zlib_inflate()
428 state->length = (unsigned)hold & 0xffff; zlib_inflate()
430 state->mode = COPY; zlib_inflate()
432 copy = state->length; zlib_inflate()
442 state->length -= copy; zlib_inflate()
445 state->mode = TYPE; zlib_inflate()
449 state->nlen = BITS(5) + 257; zlib_inflate()
451 state->ndist = BITS(5) + 1; zlib_inflate()
453 state->ncode = BITS(4) + 4; zlib_inflate()
456 if (state->nlen > 286 || state->ndist > 30) { zlib_inflate()
458 state->mode = BAD; zlib_inflate()
462 state->have = 0; zlib_inflate()
463 state->mode = LENLENS; zlib_inflate()
465 while (state->have < state->ncode) { zlib_inflate()
467 state->lens[order[state->have++]] = (unsigned short)BITS(3); zlib_inflate()
470 while (state->have < 19) zlib_inflate()
471 state->lens[order[state->have++]] = 0; zlib_inflate()
472 state->next = state->codes; zlib_inflate()
473 state->lencode = (code const *)(state->next); zlib_inflate()
474 state->lenbits = 7; zlib_inflate()
475 ret = zlib_inflate_table(CODES, state->lens, 19, &(state->next), zlib_inflate()
476 &(state->lenbits), state->work); zlib_inflate()
479 state->mode = BAD; zlib_inflate()
482 state->have = 0; zlib_inflate()
483 state->mode = CODELENS; zlib_inflate()
485 while (state->have < state->nlen + state->ndist) { zlib_inflate()
487 this = state->lencode[BITS(state->lenbits)]; zlib_inflate()
494 state->lens[state->have++] = this.val; zlib_inflate()
500 if (state->have == 0) { zlib_inflate()
502 state->mode = BAD; zlib_inflate()
505 len = state->lens[state->have - 1]; zlib_inflate()
523 if (state->have + copy > state->nlen + state->ndist) { zlib_inflate()
525 state->mode = BAD; zlib_inflate()
529 state->lens[state->have++] = (unsigned short)len; zlib_inflate()
534 if (state->mode == BAD) break; zlib_inflate()
537 state->next = state->codes; zlib_inflate()
538 state->lencode = (code const *)(state->next); zlib_inflate()
539 state->lenbits = 9; zlib_inflate()
540 ret = zlib_inflate_table(LENS, state->lens, state->nlen, &(state->next), zlib_inflate()
541 &(state->lenbits), state->work); zlib_inflate()
544 state->mode = BAD; zlib_inflate()
547 state->distcode = (code const *)(state->next); zlib_inflate()
548 state->distbits = 6; zlib_inflate()
549 ret = zlib_inflate_table(DISTS, state->lens + state->nlen, state->ndist, zlib_inflate()
550 &(state->next), &(state->distbits), state->work); zlib_inflate()
553 state->mode = BAD; zlib_inflate()
556 state->mode = LEN; zlib_inflate()
565 this = state->lencode[BITS(state->lenbits)]; zlib_inflate()
572 this = state->lencode[last.val + zlib_inflate()
580 state->length = (unsigned)this.val; zlib_inflate()
582 state->mode = LIT; zlib_inflate()
586 state->mode = TYPE; zlib_inflate()
591 state->mode = BAD; zlib_inflate()
594 state->extra = (unsigned)(this.op) & 15; zlib_inflate()
595 state->mode = LENEXT; zlib_inflate()
597 if (state->extra) { zlib_inflate()
598 NEEDBITS(state->extra); zlib_inflate()
599 state->length += BITS(state->extra); zlib_inflate()
600 DROPBITS(state->extra); zlib_inflate()
602 state->mode = DIST; zlib_inflate()
605 this = state->distcode[BITS(state->distbits)]; zlib_inflate()
612 this = state->distcode[last.val + zlib_inflate()
622 state->mode = BAD; zlib_inflate()
625 state->offset = (unsigned)this.val; zlib_inflate()
626 state->extra = (unsigned)(this.op) & 15; zlib_inflate()
627 state->mode = DISTEXT; zlib_inflate()
629 if (state->extra) { zlib_inflate()
630 NEEDBITS(state->extra); zlib_inflate()
631 state->offset += BITS(state->extra); zlib_inflate()
632 DROPBITS(state->extra); zlib_inflate()
635 if (state->offset > state->dmax) { zlib_inflate()
637 state->mode = BAD; zlib_inflate()
641 if (state->offset > state->whave + out - left) { zlib_inflate()
643 state->mode = BAD; zlib_inflate()
646 state->mode = MATCH; zlib_inflate()
650 if (state->offset > copy) { /* copy from window */ zlib_inflate()
651 copy = state->offset - copy; zlib_inflate()
652 if (copy > state->write) { zlib_inflate()
653 copy -= state->write; zlib_inflate()
654 from = state->window + (state->wsize - copy); zlib_inflate()
657 from = state->window + (state->write - copy); zlib_inflate()
658 if (copy > state->length) copy = state->length; zlib_inflate()
661 from = put - state->offset; zlib_inflate()
662 copy = state->length; zlib_inflate()
666 state->length -= copy; zlib_inflate()
670 if (state->length == 0) state->mode = LEN; zlib_inflate()
674 *put++ = (unsigned char)(state->length); zlib_inflate()
676 state->mode = LEN; zlib_inflate()
679 if (state->wrap) { zlib_inflate()
683 state->total += out; zlib_inflate()
685 strm->adler = state->check = zlib_inflate()
686 UPDATE(state->check, put - out, out); zlib_inflate()
689 REVERSE(hold)) != state->check) { zlib_inflate()
691 state->mode = BAD; zlib_inflate()
696 state->mode = DONE; zlib_inflate()
713 error. Call zlib_updatewindow() to create and/or update the window state. zlib_inflate()
717 if (state->wsize || (state->mode < CHECK && out != strm->avail_out)) zlib_inflate()
724 state->total += out; zlib_inflate()
725 if (state->wrap && out) zlib_inflate()
726 strm->adler = state->check = zlib_inflate()
727 UPDATE(state->check, strm->next_out - out, out); zlib_inflate()
729 strm->data_type = state->bits + (state->last ? 64 : 0) + zlib_inflate()
730 (state->mode == TYPE ? 128 : 0); zlib_inflate()
744 if (strm == NULL || strm->state == NULL) zlib_inflateEnd()
752 * i.e. no pending output but this should always be the case. The state must
759 struct inflate_state *state = (struct inflate_state *)z->state; zlib_inflateIncomp() local
763 if (state->mode != TYPE && state->mode != HEAD) zlib_inflateIncomp()
776 z->adler = state->check = zlib_inflateIncomp()
777 UPDATE(state->check, z->next_in, z->avail_in); zlib_inflateIncomp()
782 state->total += z->avail_in; zlib_inflateIncomp()
/linux-4.1.27/block/partitions/
H A Dkarma.h7 int karma_partition(struct parsed_partitions *state);
H A Dmsdos.h7 int msdos_partition(struct parsed_partitions *state);
H A Dosf.h7 int osf_partition(struct parsed_partitions *state);
H A Dsgi.h5 extern int sgi_partition(struct parsed_partitions *state);
H A Dsun.h8 int sun_partition(struct parsed_partitions *state);
H A Dcheck.c116 struct parsed_partitions *state; allocate_partitions() local
119 state = kzalloc(sizeof(*state), GFP_KERNEL); allocate_partitions()
120 if (!state) allocate_partitions()
124 state->parts = vzalloc(nr * sizeof(state->parts[0])); allocate_partitions()
125 if (!state->parts) { allocate_partitions()
126 kfree(state); allocate_partitions()
130 state->limit = nr; allocate_partitions()
132 return state; allocate_partitions()
135 void free_partitions(struct parsed_partitions *state) free_partitions() argument
137 vfree(state->parts); free_partitions()
138 kfree(state); free_partitions()
144 struct parsed_partitions *state; check_partition() local
147 state = allocate_partitions(hd); check_partition()
148 if (!state) check_partition()
150 state->pp_buf = (char *)__get_free_page(GFP_KERNEL); check_partition()
151 if (!state->pp_buf) { check_partition()
152 free_partitions(state); check_partition()
155 state->pp_buf[0] = '\0'; check_partition()
157 state->bdev = bdev; check_partition()
158 disk_name(hd, 0, state->name); check_partition()
159 snprintf(state->pp_buf, PAGE_SIZE, " %s:", state->name); check_partition()
160 if (isdigit(state->name[strlen(state->name)-1])) check_partition()
161 sprintf(state->name, "p"); check_partition()
165 memset(state->parts, 0, state->limit * sizeof(state->parts[0])); check_partition()
166 res = check_part[i++](state); check_partition()
177 printk(KERN_INFO "%s", state->pp_buf); check_partition()
179 free_page((unsigned long)state->pp_buf); check_partition()
180 return state; check_partition()
182 if (state->access_beyond_eod) check_partition()
189 strlcat(state->pp_buf, check_partition()
191 printk(KERN_INFO "%s", state->pp_buf); check_partition()
194 free_page((unsigned long)state->pp_buf); check_partition()
195 free_partitions(state); check_partition()
H A Dmsdos.c68 static int aix_magic_present(struct parsed_partitions *state, unsigned char *p) aix_magic_present() argument
89 d = read_part_sector(state, 7, &sect); aix_magic_present()
98 static void set_info(struct parsed_partitions *state, int slot, set_info() argument
101 struct partition_meta_info *info = &state->parts[slot].info; set_info()
106 state->parts[slot].has_info = true; set_info()
120 static void parse_extended(struct parsed_partitions *state, parse_extended() argument
128 sector_t sector_size = bdev_logical_block_size(state->bdev) / 512; parse_extended()
139 if (state->next == state->limit) parse_extended()
141 data = read_part_sector(state, this_sector, &sect); parse_extended()
182 put_partition(state, state->next, next, size); parse_extended()
183 set_info(state, state->next, disksig); parse_extended()
185 state->parts[state->next].flags = ADDPART_FLAG_RAID; parse_extended()
187 if (++state->next == state->limit) parse_extended()
215 static void parse_solaris_x86(struct parsed_partitions *state, parse_solaris_x86() argument
224 v = read_part_sector(state, offset + 1, &sect); parse_solaris_x86()
234 snprintf(tmp, sizeof(tmp), " %s%d: <solaris:", state->name, origin); parse_solaris_x86()
235 strlcat(state->pp_buf, tmp, PAGE_SIZE); parse_solaris_x86()
242 strlcat(state->pp_buf, tmp, PAGE_SIZE); parse_solaris_x86()
248 for (i = 0; i < max_nparts && state->next < state->limit; i++) { parse_solaris_x86()
255 strlcat(state->pp_buf, tmp, PAGE_SIZE); parse_solaris_x86()
258 put_partition(state, state->next++, parse_solaris_x86()
263 strlcat(state->pp_buf, " >\n", PAGE_SIZE); parse_solaris_x86()
272 static void parse_bsd(struct parsed_partitions *state, parse_bsd() argument
281 l = read_part_sector(state, offset + 1, &sect); parse_bsd()
289 snprintf(tmp, sizeof(tmp), " %s%d: <%s:", state->name, origin, flavour); parse_bsd()
290 strlcat(state->pp_buf, tmp, PAGE_SIZE); parse_bsd()
297 if (state->next == state->limit) parse_bsd()
307 strlcat(state->pp_buf, "bad subpartition - ignored\n", PAGE_SIZE); parse_bsd()
310 put_partition(state, state->next++, bsd_start, bsd_size); parse_bsd()
316 strlcat(state->pp_buf, tmp, PAGE_SIZE); parse_bsd()
318 strlcat(state->pp_buf, " >\n", PAGE_SIZE); parse_bsd()
322 static void parse_freebsd(struct parsed_partitions *state, parse_freebsd() argument
326 parse_bsd(state, offset, size, origin, "bsd", BSD_MAXPARTITIONS); parse_freebsd()
330 static void parse_netbsd(struct parsed_partitions *state, parse_netbsd() argument
334 parse_bsd(state, offset, size, origin, "netbsd", BSD_MAXPARTITIONS); parse_netbsd()
338 static void parse_openbsd(struct parsed_partitions *state, parse_openbsd() argument
342 parse_bsd(state, offset, size, origin, "openbsd", parse_openbsd()
351 static void parse_unixware(struct parsed_partitions *state, parse_unixware() argument
359 l = read_part_sector(state, offset + 29, &sect); parse_unixware()
370 snprintf(tmp, sizeof(tmp), " %s%d: <unixware:", state->name, origin); parse_unixware()
371 strlcat(state->pp_buf, tmp, PAGE_SIZE); parse_unixware()
376 if (state->next == state->limit) parse_unixware()
380 put_partition(state, state->next++, parse_unixware()
386 strlcat(state->pp_buf, " >\n", PAGE_SIZE); parse_unixware()
395 static void parse_minix(struct parsed_partitions *state, parse_minix() argument
404 data = read_part_sector(state, offset, &sect); parse_minix()
417 snprintf(tmp, sizeof(tmp), " %s%d: <minix:", state->name, origin); parse_minix()
418 strlcat(state->pp_buf, tmp, PAGE_SIZE); parse_minix()
420 if (state->next == state->limit) parse_minix()
424 put_partition(state, state->next++, parse_minix()
427 strlcat(state->pp_buf, " >\n", PAGE_SIZE); parse_minix()
447 int msdos_partition(struct parsed_partitions *state) msdos_partition() argument
449 sector_t sector_size = bdev_logical_block_size(state->bdev) / 512; msdos_partition()
457 data = read_part_sector(state, 0, &sect); msdos_partition()
465 if (aix_magic_present(state, data)) { msdos_partition()
468 return aix_partition(state); msdos_partition()
470 strlcat(state->pp_buf, " [AIX]", PAGE_SIZE); msdos_partition()
497 strlcat(state->pp_buf, "\n", PAGE_SIZE); msdos_partition()
527 state->next = 5; msdos_partition()
544 put_partition(state, slot, start, n); msdos_partition()
546 strlcat(state->pp_buf, " <", PAGE_SIZE); msdos_partition()
547 parse_extended(state, start, size, disksig); msdos_partition()
548 strlcat(state->pp_buf, " >", PAGE_SIZE); msdos_partition()
551 put_partition(state, slot, start, size); msdos_partition()
552 set_info(state, slot, disksig); msdos_partition()
554 state->parts[slot].flags = ADDPART_FLAG_RAID; msdos_partition()
556 strlcat(state->pp_buf, "[DM]", PAGE_SIZE); msdos_partition()
558 strlcat(state->pp_buf, "[EZD]", PAGE_SIZE); msdos_partition()
561 strlcat(state->pp_buf, "\n", PAGE_SIZE); msdos_partition()
577 subtypes[n].parse(state, start_sect(p) * sector_size, msdos_partition()
H A Dkarma.c13 int karma_partition(struct parsed_partitions *state) karma_partition() argument
33 data = read_part_sector(state, 0, &sect); karma_partition()
45 if (slot == state->limit) karma_partition()
49 put_partition(state, slot, le32_to_cpu(p->p_offset), karma_partition()
54 strlcat(state->pp_buf, "\n", PAGE_SIZE); karma_partition()
H A Dcmdline.c30 struct parsed_partitions *state = (struct parsed_partitions *)param; add_part() local
32 if (slot >= state->limit) add_part()
35 put_partition(state, slot, subpart->from >> 9, add_part()
38 info = &state->parts[slot].info; add_part()
46 strlcat(state->pp_buf, tmp, PAGE_SIZE); add_part()
48 state->parts[slot].has_info = true; add_part()
67 int cmdline_partition(struct parsed_partitions *state) cmdline_partition() argument
87 bdevname(state->bdev, bdev); cmdline_partition()
92 disk_size = get_capacity(state->bdev->bd_disk) << 9; cmdline_partition()
94 cmdline_parts_set(parts, disk_size, 1, add_part, (void *)state); cmdline_partition()
96 strlcat(state->pp_buf, "\n", PAGE_SIZE); cmdline_partition()
H A Dacorn.c31 adfs_partition(struct parsed_partitions *state, char *name, char *data, adfs_partition() argument
49 strlcat(state->pp_buf, " [", PAGE_SIZE); adfs_partition()
50 strlcat(state->pp_buf, name, PAGE_SIZE); adfs_partition()
51 strlcat(state->pp_buf, "]", PAGE_SIZE); adfs_partition()
53 put_partition(state, slot, first_sector, nr_sects); adfs_partition()
76 static int riscix_partition(struct parsed_partitions *state, riscix_partition() argument
83 rr = read_part_sector(state, first_sect, &sect); riscix_partition()
87 strlcat(state->pp_buf, " [RISCiX]", PAGE_SIZE); riscix_partition()
94 strlcat(state->pp_buf, " <", PAGE_SIZE); riscix_partition()
96 put_partition(state, slot++, first_sect, size); riscix_partition()
100 put_partition(state, slot++, riscix_partition()
103 strlcat(state->pp_buf, "(", PAGE_SIZE); riscix_partition()
104 strlcat(state->pp_buf, rr->part[part].name, PAGE_SIZE); riscix_partition()
105 strlcat(state->pp_buf, ")", PAGE_SIZE); riscix_partition()
109 strlcat(state->pp_buf, " >\n", PAGE_SIZE); riscix_partition()
111 put_partition(state, slot++, first_sect, nr_sects); riscix_partition()
131 static int linux_partition(struct parsed_partitions *state, linux_partition() argument
139 strlcat(state->pp_buf, " [Linux]", PAGE_SIZE); linux_partition()
141 put_partition(state, slot++, first_sect, size); linux_partition()
143 linuxp = read_part_sector(state, first_sect, &sect); linux_partition()
147 strlcat(state->pp_buf, " <", PAGE_SIZE); linux_partition()
150 if (slot == state->limit) linux_partition()
152 put_partition(state, slot++, first_sect + linux_partition()
157 strlcat(state->pp_buf, " >", PAGE_SIZE); linux_partition()
165 int adfspart_check_CUMANA(struct parsed_partitions *state) adfspart_check_CUMANA() argument
192 data = read_part_sector(state, start_blk * 2 + 6, &sect); adfspart_check_CUMANA()
196 if (slot == state->limit) adfspart_check_CUMANA()
199 dr = adfs_partition(state, name, data, first_sector, slot++); adfspart_check_CUMANA()
224 slot = riscix_partition(state, first_sector, slot, adfspart_check_CUMANA()
230 slot = linux_partition(state, first_sector, slot, adfspart_check_CUMANA()
256 int adfspart_check_ADFS(struct parsed_partitions *state) adfspart_check_ADFS() argument
265 data = read_part_sector(state, 6, &sect); adfspart_check_ADFS()
269 dr = adfs_partition(state, "ADFS", data, 0, slot++); adfspart_check_ADFS()
284 nr_sects = (state->bdev->bd_inode->i_size >> 9) - start_sect; adfspart_check_ADFS()
291 slot = riscix_partition(state, start_sect, slot, adfspart_check_ADFS()
297 slot = linux_partition(state, start_sect, slot, adfspart_check_ADFS()
302 strlcat(state->pp_buf, "\n", PAGE_SIZE); adfspart_check_ADFS()
314 static int adfspart_check_ICSLinux(struct parsed_partitions *state, adfspart_check_ICSLinux() argument
318 unsigned char *data = read_part_sector(state, block, &sect); adfspart_check_ICSLinux()
356 int adfspart_check_ICS(struct parsed_partitions *state) adfspart_check_ICS() argument
366 data = read_part_sector(state, 0, &sect); adfspart_check_ICS()
375 strlcat(state->pp_buf, " [ICS]", PAGE_SIZE); adfspart_check_ICS()
381 if (slot == state->limit) adfspart_check_ICS()
398 if (size > 1 && adfspart_check_ICSLinux(state, start)) { adfspart_check_ICS()
405 put_partition(state, slot++, start, size); adfspart_check_ICS()
409 strlcat(state->pp_buf, "\n", PAGE_SIZE); adfspart_check_ICS()
452 int adfspart_check_POWERTEC(struct parsed_partitions *state) adfspart_check_POWERTEC() argument
460 data = read_part_sector(state, 0, &sect); adfspart_check_POWERTEC()
469 strlcat(state->pp_buf, " [POWERTEC]", PAGE_SIZE); adfspart_check_POWERTEC()
476 put_partition(state, slot++, start, size); adfspart_check_POWERTEC()
480 strlcat(state->pp_buf, "\n", PAGE_SIZE); adfspart_check_POWERTEC()
513 int adfspart_check_EESOX(struct parsed_partitions *state) adfspart_check_EESOX() argument
522 data = read_part_sector(state, 7, &sect); adfspart_check_EESOX()
542 put_partition(state, slot++, start, next - start); adfspart_check_EESOX()
549 size = get_capacity(state->bdev->bd_disk); adfspart_check_EESOX()
550 put_partition(state, slot++, start, size - start); adfspart_check_EESOX()
551 strlcat(state->pp_buf, "\n", PAGE_SIZE); adfspart_check_EESOX()
H A Datari.c33 int atari_partition(struct parsed_partitions *state) atari_partition() argument
45 rs = read_part_sector(state, 0, &sect); atari_partition()
50 hd_size = state->bdev->bd_inode->i_size >> 9; atari_partition()
65 strlcat(state->pp_buf, " AHDI", PAGE_SIZE); atari_partition()
66 for (slot = 1; pi < &rs->part[4] && slot < state->limit; slot++, pi++) { atari_partition()
76 put_partition (state, slot, be32_to_cpu(pi->st), atari_partition()
84 strlcat(state->pp_buf, " XGM<", PAGE_SIZE); atari_partition()
87 xrs = read_part_sector(state, partsect, &sect2); atari_partition()
101 put_partition(state, slot, atari_partition()
118 if (++slot == state->limit) { atari_partition()
123 strlcat(state->pp_buf, " >", PAGE_SIZE); atari_partition()
130 strlcat(state->pp_buf, " ICD<", PAGE_SIZE); atari_partition()
131 for (; pi < &rs->icdpart[8] && slot < state->limit; slot++, pi++) { atari_partition()
136 put_partition (state, slot, atari_partition()
140 strlcat(state->pp_buf, " >", PAGE_SIZE); atari_partition()
146 strlcat(state->pp_buf, "\n", PAGE_SIZE); atari_partition()
H A Dsysv68.c49 int sysv68_partition(struct parsed_partitions *state) sysv68_partition() argument
59 data = read_part_sector(state, 0, &sect); sysv68_partition()
72 data = read_part_sector(state, i, &sect); sysv68_partition()
77 snprintf(tmp, sizeof(tmp), "sysV68: %s(s%u)", state->name, slices); sysv68_partition()
78 strlcat(state->pp_buf, tmp, PAGE_SIZE); sysv68_partition()
81 if (slot == state->limit) sysv68_partition()
84 put_partition(state, slot, sysv68_partition()
88 strlcat(state->pp_buf, tmp, PAGE_SIZE); sysv68_partition()
92 strlcat(state->pp_buf, "\n", PAGE_SIZE); sysv68_partition()
H A Dmac.c30 int mac_partition(struct parsed_partitions *state) mac_partition() argument
44 md = read_part_sector(state, 0, &sect); mac_partition()
53 data = read_part_sector(state, secsize/512, &sect); mac_partition()
67 if (blocks_in_map >= state->limit) mac_partition()
68 blocks_in_map = state->limit - 1; mac_partition()
70 strlcat(state->pp_buf, " [mac]", PAGE_SIZE); mac_partition()
74 data = read_part_sector(state, pos/512, &sect); mac_partition()
80 put_partition(state, slot, mac_partition()
85 state->parts[slot].flags = ADDPART_FLAG_RAID; mac_partition()
131 note_bootable_part(state->bdev->bd_dev, found_root, mac_partition()
136 strlcat(state->pp_buf, "\n", PAGE_SIZE); mac_partition()
/linux-4.1.27/drivers/net/ppp/
H A Dppp_mppe.c136 static void get_new_key_from_sha(struct ppp_mppe_state * state) get_new_key_from_sha() argument
144 nbytes = setup_sg(&sg[0], state->master_key, state->keylen); get_new_key_from_sha()
147 nbytes += setup_sg(&sg[2], state->session_key, state->keylen); get_new_key_from_sha()
151 desc.tfm = state->sha1; get_new_key_from_sha()
154 crypto_hash_digest(&desc, sg, nbytes, state->sha1_digest); get_new_key_from_sha()
161 static void mppe_rekey(struct ppp_mppe_state * state, int initial_key) mppe_rekey() argument
164 struct blkcipher_desc desc = { .tfm = state->arc4 }; mppe_rekey()
166 get_new_key_from_sha(state); mppe_rekey()
168 crypto_blkcipher_setkey(state->arc4, state->sha1_digest, mppe_rekey()
169 state->keylen); mppe_rekey()
172 setup_sg(sg_in, state->sha1_digest, state->keylen); mppe_rekey()
173 setup_sg(sg_out, state->session_key, state->keylen); mppe_rekey()
175 state->keylen) != 0) { mppe_rekey()
179 memcpy(state->session_key, state->sha1_digest, state->keylen); mppe_rekey()
181 if (state->keylen == 8) { mppe_rekey()
183 state->session_key[0] = 0xd1; mppe_rekey()
184 state->session_key[1] = 0x26; mppe_rekey()
185 state->session_key[2] = 0x9e; mppe_rekey()
187 crypto_blkcipher_setkey(state->arc4, state->session_key, state->keylen); mppe_rekey()
195 struct ppp_mppe_state *state; mppe_alloc() local
198 if (optlen != CILEN_MPPE + sizeof(state->master_key) || mppe_alloc()
202 state = kzalloc(sizeof(*state), GFP_KERNEL); mppe_alloc()
203 if (state == NULL) mppe_alloc()
207 state->arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); mppe_alloc()
208 if (IS_ERR(state->arc4)) { mppe_alloc()
209 state->arc4 = NULL; mppe_alloc()
213 state->sha1 = crypto_alloc_hash("sha1", 0, CRYPTO_ALG_ASYNC); mppe_alloc()
214 if (IS_ERR(state->sha1)) { mppe_alloc()
215 state->sha1 = NULL; mppe_alloc()
219 digestsize = crypto_hash_digestsize(state->sha1); mppe_alloc()
223 state->sha1_digest = kmalloc(digestsize, GFP_KERNEL); mppe_alloc()
224 if (!state->sha1_digest) mppe_alloc()
228 memcpy(state->master_key, &options[CILEN_MPPE], mppe_alloc()
229 sizeof(state->master_key)); mppe_alloc()
230 memcpy(state->session_key, state->master_key, mppe_alloc()
231 sizeof(state->master_key)); mppe_alloc()
238 return (void *)state; mppe_alloc()
241 if (state->sha1_digest) mppe_alloc()
242 kfree(state->sha1_digest); mppe_alloc()
243 if (state->sha1) mppe_alloc()
244 crypto_free_hash(state->sha1); mppe_alloc()
245 if (state->arc4) mppe_alloc()
246 crypto_free_blkcipher(state->arc4); mppe_alloc()
247 kfree(state); mppe_alloc()
257 struct ppp_mppe_state *state = (struct ppp_mppe_state *) arg; mppe_free() local
258 if (state) { mppe_free()
259 if (state->sha1_digest) mppe_free()
260 kfree(state->sha1_digest); mppe_free()
261 if (state->sha1) mppe_free()
262 crypto_free_hash(state->sha1); mppe_free()
263 if (state->arc4) mppe_free()
264 crypto_free_blkcipher(state->arc4); mppe_free()
265 kfree(state); mppe_free()
270 * Initialize (de)compressor state.
276 struct ppp_mppe_state *state = (struct ppp_mppe_state *) arg; mppe_init() local
285 state->keylen = 16; mppe_init()
287 state->keylen = 8; mppe_init()
294 state->stateful = 1; mppe_init()
297 mppe_rekey(state, 1); mppe_init()
301 char mkey[sizeof(state->master_key) * 2 + 1]; mppe_init()
302 char skey[sizeof(state->session_key) * 2 + 1]; mppe_init()
305 debugstr, unit, (state->keylen == 16) ? 128 : 40, mppe_init()
306 (state->stateful) ? "stateful" : "stateless"); mppe_init()
308 for (i = 0; i < sizeof(state->master_key); i++) mppe_init()
309 sprintf(mkey + i * 2, "%02x", state->master_key[i]); mppe_init()
310 for (i = 0; i < sizeof(state->session_key); i++) mppe_init()
311 sprintf(skey + i * 2, "%02x", state->session_key[i]); mppe_init()
323 state->ccount = MPPE_CCOUNT_SPACE - 1; mppe_init()
329 state->bits = MPPE_BIT_ENCRYPTED; mppe_init()
331 state->unit = unit; mppe_init()
332 state->debug = debug; mppe_init()
356 struct ppp_mppe_state *state = (struct ppp_mppe_state *) arg; mppe_comp_reset() local
358 state->bits |= MPPE_BIT_FLUSHED; mppe_comp_reset()
370 struct ppp_mppe_state *state = (struct ppp_mppe_state *) arg; mppe_compress() local
371 struct blkcipher_desc desc = { .tfm = state->arc4 }; mppe_compress()
386 "(have: %d need: %d)\n", state->unit, mppe_compress()
401 state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE; mppe_compress()
402 if (state->debug >= 7) mppe_compress()
403 printk(KERN_DEBUG "mppe_compress[%d]: ccount %d\n", state->unit, mppe_compress()
404 state->ccount); mppe_compress()
405 put_unaligned_be16(state->ccount, obuf); mppe_compress()
407 if (!state->stateful || /* stateless mode */ mppe_compress()
408 ((state->ccount & 0xff) == 0xff) || /* "flag" packet */ mppe_compress()
409 (state->bits & MPPE_BIT_FLUSHED)) { /* CCP Reset-Request */ mppe_compress()
411 if (state->debug && state->stateful) mppe_compress()
413 state->unit); mppe_compress()
414 mppe_rekey(state, 0); mppe_compress()
415 state->bits |= MPPE_BIT_FLUSHED; mppe_compress()
417 obuf[0] |= state->bits; mppe_compress()
418 state->bits &= ~MPPE_BIT_FLUSHED; /* reset for next xmit */ mppe_compress()
434 state->stats.unc_bytes += isize; mppe_compress()
435 state->stats.unc_packets++; mppe_compress()
436 state->stats.comp_bytes += osize; mppe_compress()
437 state->stats.comp_packets++; mppe_compress()
448 struct ppp_mppe_state *state = (struct ppp_mppe_state *) arg; mppe_comp_stats() local
450 *stats = state->stats; mppe_comp_stats()
477 struct ppp_mppe_state *state = (struct ppp_mppe_state *) arg; mppe_decompress() local
478 struct blkcipher_desc desc = { .tfm = state->arc4 }; mppe_decompress()
484 if (state->debug) mppe_decompress()
487 state->unit, isize); mppe_decompress()
499 "(have: %d need: %d)\n", state->unit, mppe_decompress()
506 if (state->debug >= 7) mppe_decompress()
508 state->unit, ccount); mppe_decompress()
514 state->unit); mppe_decompress()
515 state->sanity_errors += 100; mppe_decompress()
518 if (!state->stateful && !flushed) { mppe_decompress()
520 "stateless mode!\n", state->unit); mppe_decompress()
521 state->sanity_errors += 100; mppe_decompress()
524 if (state->stateful && ((ccount & 0xff) == 0xff) && !flushed) { mppe_decompress()
526 "flag packet!\n", state->unit); mppe_decompress()
527 state->sanity_errors += 100; mppe_decompress()
535 if (!state->stateful) { mppe_decompress()
537 if ((ccount - state->ccount) % MPPE_CCOUNT_SPACE mppe_decompress()
539 state->sanity_errors++; mppe_decompress()
544 while (state->ccount != ccount) { mppe_decompress()
545 mppe_rekey(state, 0); mppe_decompress()
546 state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE; mppe_decompress()
550 if (!state->discard) { mppe_decompress()
551 /* normal state */ mppe_decompress()
552 state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE; mppe_decompress()
553 if (ccount != state->ccount) { mppe_decompress()
555 * (ccount > state->ccount) mppe_decompress()
556 * Packet loss detected, enter the discard state. mppe_decompress()
559 state->discard = 1; mppe_decompress()
563 /* discard state */ mppe_decompress()
570 (state->ccount & ~0xff)) { mppe_decompress()
571 mppe_rekey(state, 0); mppe_decompress()
572 state->ccount = mppe_decompress()
573 (state->ccount + mppe_decompress()
578 state->discard = 0; mppe_decompress()
579 state->ccount = ccount; mppe_decompress()
585 * required to reset CCP state. mppe_decompress()
590 mppe_rekey(state, 0); mppe_decompress()
637 state->stats.unc_bytes += osize; mppe_decompress()
638 state->stats.unc_packets++; mppe_decompress()
639 state->stats.comp_bytes += isize; mppe_decompress()
640 state->stats.comp_packets++; mppe_decompress()
643 state->sanity_errors >>= 1; mppe_decompress()
648 if (state->sanity_errors < SANITY_MAX) mppe_decompress()
666 struct ppp_mppe_state *state = (struct ppp_mppe_state *) arg; mppe_incomp() local
668 if (state->debug && mppe_incomp()
672 "(proto %04x)\n", state->unit, PPP_PROTOCOL(ibuf)); mppe_incomp()
674 state->stats.inc_bytes += icnt; mppe_incomp()
675 state->stats.inc_packets++; mppe_incomp()
676 state->stats.unc_bytes += icnt; mppe_incomp()
677 state->stats.unc_packets++; mppe_incomp()
H A Dppp_deflate.c41 static void z_comp_free(void *state);
42 static void z_decomp_free(void *state);
43 static int z_comp_init(void *state, unsigned char *options,
46 static int z_decomp_init(void *state, unsigned char *options,
49 static int z_compress(void *state, unsigned char *rptr,
52 static void z_incomp(void *state, unsigned char *ibuf, int icnt);
53 static int z_decompress(void *state, unsigned char *ibuf,
55 static void z_comp_reset(void *state);
56 static void z_decomp_reset(void *state);
57 static void z_comp_stats(void *state, struct compstat *stats);
61 * @arg: pointer to the private state for the compressor.
65 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_comp_free() local
67 if (state) { z_comp_free()
68 zlib_deflateEnd(&state->strm); z_comp_free()
69 vfree(state->strm.workspace); z_comp_free()
70 kfree(state); z_comp_free()
85 * Returns the pointer to the private state for the compressor,
90 struct ppp_deflate_state *state; z_comp_alloc() local
103 state = kzalloc(sizeof(*state), z_comp_alloc()
105 if (state == NULL) z_comp_alloc()
108 state->strm.next_in = NULL; z_comp_alloc()
109 state->w_size = w_size; z_comp_alloc()
110 state->strm.workspace = vmalloc(zlib_deflate_workspacesize(-w_size, 8)); z_comp_alloc()
111 if (state->strm.workspace == NULL) z_comp_alloc()
114 if (zlib_deflateInit2(&state->strm, Z_DEFAULT_COMPRESSION, z_comp_alloc()
118 return (void *) state; z_comp_alloc()
121 z_comp_free(state); z_comp_alloc()
127 * @arg: pointer to the private state for the compressor
143 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_comp_init() local
149 DEFLATE_SIZE(options[2]) != state->w_size || z_comp_init()
153 state->seqno = 0; z_comp_init()
154 state->unit = unit; z_comp_init()
155 state->debug = debug; z_comp_init()
157 zlib_deflateReset(&state->strm); z_comp_init()
164 * @arg: pointer to private state for the compressor.
171 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_comp_reset() local
173 state->seqno = 0; z_comp_reset()
174 zlib_deflateReset(&state->strm); z_comp_reset()
179 * @arg: pointer to private state for the compressor
191 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_compress() local
216 put_unaligned_be16(state->seqno, wptr); z_compress()
219 state->strm.next_out = wptr; z_compress()
220 state->strm.avail_out = oavail = osize - olen; z_compress()
221 ++state->seqno; z_compress()
225 state->strm.next_in = rptr; z_compress()
226 state->strm.avail_in = (isize - off); z_compress()
229 r = zlib_deflate(&state->strm, Z_PACKET_FLUSH); z_compress()
231 if (state->debug) z_compress()
236 if (state->strm.avail_out == 0) { z_compress()
238 state->strm.next_out = NULL; z_compress()
239 state->strm.avail_out = oavail = 1000000; z_compress()
244 olen += oavail - state->strm.avail_out; z_compress()
250 state->stats.comp_bytes += olen; z_compress()
251 state->stats.comp_packets++; z_compress()
253 state->stats.inc_bytes += isize; z_compress()
254 state->stats.inc_packets++; z_compress()
257 state->stats.unc_bytes += isize; z_compress()
258 state->stats.unc_packets++; z_compress()
271 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_comp_stats() local
273 *stats = state->stats; z_comp_stats()
282 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_decomp_free() local
284 if (state) { z_decomp_free()
285 zlib_inflateEnd(&state->strm); z_decomp_free()
286 vfree(state->strm.workspace); z_decomp_free()
287 kfree(state); z_decomp_free()
302 * Returns the pointer to the private state for the decompressor,
307 struct ppp_deflate_state *state; z_decomp_alloc() local
320 state = kzalloc(sizeof(*state), GFP_KERNEL); z_decomp_alloc()
321 if (state == NULL) z_decomp_alloc()
324 state->w_size = w_size; z_decomp_alloc()
325 state->strm.next_out = NULL; z_decomp_alloc()
326 state->strm.workspace = vmalloc(zlib_inflate_workspacesize()); z_decomp_alloc()
327 if (state->strm.workspace == NULL) z_decomp_alloc()
330 if (zlib_inflateInit2(&state->strm, -w_size) != Z_OK) z_decomp_alloc()
332 return (void *) state; z_decomp_alloc()
335 z_decomp_free(state); z_decomp_alloc()
341 * @arg: pointer to the private state for the decompressor
358 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_decomp_init() local
364 DEFLATE_SIZE(options[2]) != state->w_size || z_decomp_init()
368 state->seqno = 0; z_decomp_init()
369 state->unit = unit; z_decomp_init()
370 state->debug = debug; z_decomp_init()
371 state->mru = mru; z_decomp_init()
373 zlib_inflateReset(&state->strm); z_decomp_init()
380 * @arg: pointer to private state for the decompressor.
387 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_decomp_reset() local
389 state->seqno = 0; z_decomp_reset()
390 zlib_inflateReset(&state->strm); z_decomp_reset()
395 * @arg: pointer to private state for the decompressor
417 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_decompress() local
423 if (state->debug) z_decompress()
425 state->unit, isize); z_decompress()
431 if (seq != (state->seqno & 0xffff)) { z_decompress()
432 if (state->debug) z_decompress()
434 state->unit, seq, state->seqno & 0xffff); z_decompress()
437 ++state->seqno; z_decompress()
452 state->strm.next_in = ibuf + PPP_HDRLEN + DEFLATE_OVHD; z_decompress()
453 state->strm.avail_in = isize - (PPP_HDRLEN + DEFLATE_OVHD); z_decompress()
454 state->strm.next_out = obuf + 3; z_decompress()
455 state->strm.avail_out = 1; z_decompress()
463 r = zlib_inflate(&state->strm, Z_PACKET_FLUSH); z_decompress()
465 if (state->debug) z_decompress()
467 state->unit, r, (state->strm.msg? state->strm.msg: "")); z_decompress()
470 if (state->strm.avail_out != 0) z_decompress()
473 state->strm.avail_out = osize - PPP_HDRLEN; z_decompress()
477 --state->strm.next_out; z_decompress()
478 ++state->strm.avail_out; z_decompress()
487 state->strm.next_out = overflow_buf; z_decompress()
488 state->strm.avail_out = 1; z_decompress()
491 if (state->debug) z_decompress()
493 state->unit); z_decompress()
499 if (state->debug) z_decompress()
501 state->unit); z_decompress()
505 olen = osize + overflow - state->strm.avail_out; z_decompress()
506 state->stats.unc_bytes += olen; z_decompress()
507 state->stats.unc_packets++; z_decompress()
508 state->stats.comp_bytes += isize; z_decompress()
509 state->stats.comp_packets++; z_decompress()
516 * @arg: pointer to private state for the decompressor
522 struct ppp_deflate_state *state = (struct ppp_deflate_state *) arg; z_incomp() local
532 ++state->seqno; z_incomp()
538 state->strm.next_in = ibuf + 3; z_incomp()
539 state->strm.avail_in = icnt - 3; z_incomp()
541 --state->strm.next_in; z_incomp()
542 ++state->strm.avail_in; z_incomp()
545 r = zlib_inflateIncomp(&state->strm); z_incomp()
548 if (state->debug) { z_incomp()
550 state->unit, r, (state->strm.msg? state->strm.msg: "")); z_incomp()
558 state->stats.inc_bytes += icnt; z_incomp()
559 state->stats.inc_packets++; z_incomp()
560 state->stats.unc_bytes += icnt; z_incomp()
561 state->stats.unc_packets++; z_incomp()
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_atomic_helper.c40 * also provides convenience implementations for the atomic state handling
42 * add their own additional internal state.
57 drm_atomic_helper_plane_changed(struct drm_atomic_state *state, drm_atomic_helper_plane_changed() argument
63 if (plane->state->crtc) { drm_atomic_helper_plane_changed()
64 crtc_state = state->crtc_states[drm_crtc_index(plane->state->crtc)]; drm_atomic_helper_plane_changed()
74 state->crtc_states[drm_crtc_index(plane_state->crtc)]; drm_atomic_helper_plane_changed()
93 if (connector->state->best_encoder != encoder) get_current_crtc_for_encoder()
96 return connector->state->crtc; get_current_crtc_for_encoder()
103 steal_encoder(struct drm_atomic_state *state, steal_encoder() argument
107 struct drm_mode_config *config = &state->dev->mode_config; steal_encoder()
123 crtc_state = drm_atomic_get_crtc_state(state, encoder_crtc); steal_encoder()
130 if (connector->state->best_encoder != encoder) steal_encoder()
137 connector_state = drm_atomic_get_connector_state(state, steal_encoder()
152 update_connector_routing(struct drm_atomic_state *state, int conn_idx) update_connector_routing() argument
162 connector = state->connectors[conn_idx]; update_connector_routing()
163 connector_state = state->connector_states[conn_idx]; update_connector_routing()
172 if (connector->state->crtc != connector_state->crtc) { update_connector_routing()
173 if (connector->state->crtc) { update_connector_routing()
174 idx = drm_crtc_index(connector->state->crtc); update_connector_routing()
176 crtc_state = state->crtc_states[idx]; update_connector_routing()
183 crtc_state = state->crtc_states[idx]; update_connector_routing()
219 encoder_crtc = get_current_crtc_for_encoder(state->dev, update_connector_routing()
223 ret = steal_encoder(state, new_encoder, encoder_crtc); update_connector_routing()
235 crtc_state = state->crtc_states[idx]; update_connector_routing()
249 mode_fixup(struct drm_atomic_state *state) mode_fixup() argument
258 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
265 for_each_connector_in_state(state, connector, conn_state, i) { for_each_connector_in_state()
275 state->crtc_states[drm_crtc_index(conn_state->crtc)]; for_each_connector_in_state()
313 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
333 needs_modeset(struct drm_crtc_state *state) needs_modeset() argument
335 return state->mode_changed || state->active_changed; needs_modeset()
339 * drm_atomic_helper_check_modeset - validate state object for modeset changes
341 * @state: the driver state object
343 * Check the state object to see if the requested state is physically possible.
362 struct drm_atomic_state *state) drm_atomic_helper_check_modeset()
370 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
371 if (!drm_mode_equal(&crtc->state->mode, &crtc_state->mode)) { for_each_crtc_in_state()
377 if (crtc->state->enable != crtc_state->enable) { for_each_crtc_in_state()
384 for_each_connector_in_state(state, connector, connector_state, i) { for_each_connector_in_state()
390 ret = update_connector_routing(state, i); for_each_connector_in_state()
401 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
409 if (crtc->state->active != crtc_state->active) { for_each_crtc_in_state()
423 ret = drm_atomic_add_affected_connectors(state, crtc); for_each_crtc_in_state()
427 num_connectors = drm_atomic_connectors_for_crtc(state, for_each_crtc_in_state()
438 return mode_fixup(state);
443 * drm_atomic_helper_check_planes - validate state object for planes changes
445 * @state: the driver state object
447 * Check the state object to see if the requested state is physically possible.
456 struct drm_atomic_state *state) drm_atomic_helper_check_planes()
464 for_each_plane_in_state(state, plane, plane_state, i) { for_each_plane_in_state()
469 drm_atomic_helper_plane_changed(state, plane_state, plane); for_each_plane_in_state()
482 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
490 ret = funcs->atomic_check(crtc, state->crtc_states[i]); for_each_crtc_in_state()
503 * drm_atomic_helper_check - validate state object
505 * @state: the driver state object
507 * Check the state object to see if the requested state is physically possible.
513 * This just wraps the two parts of the state checking for planes and modeset
514 * state in the default order: First it calls drm_atomic_helper_check_modeset()
523 struct drm_atomic_state *state) drm_atomic_helper_check()
527 ret = drm_atomic_helper_check_modeset(dev, state); drm_atomic_helper_check()
531 ret = drm_atomic_helper_check_planes(dev, state); drm_atomic_helper_check()
554 * still on. So need to check the old, saved state. */ for_each_connector_in_state()
561 !needs_modeset(old_conn_state->crtc->state)) for_each_connector_in_state()
584 /* Right function depends upon target state. */ for_each_connector_in_state()
585 if (connector->state->crtc && funcs->prepare) for_each_connector_in_state()
600 if (!needs_modeset(crtc->state)) for_each_crtc_in_state()
612 /* Right function depends upon target state. */ for_each_crtc_in_state()
613 if (crtc->state->enable && funcs->prepare) for_each_crtc_in_state()
644 if (!connector->state->crtc) for_each_connector_in_state()
647 if (WARN_ON(!connector->state->best_encoder)) for_each_connector_in_state()
650 connector->encoder = connector->state->best_encoder; for_each_connector_in_state()
651 connector->encoder->crtc = connector->state->crtc; for_each_connector_in_state()
654 /* set legacy state in the crtc structure */ for_each_crtc_in_state()
656 crtc->mode = crtc->state->mode; for_each_crtc_in_state()
657 crtc->enabled = crtc->state->enable; for_each_crtc_in_state()
658 crtc->x = crtc->primary->state->src_x >> 16; for_each_crtc_in_state()
659 crtc->y = crtc->primary->state->src_y >> 16; for_each_crtc_in_state()
675 if (!crtc->state->mode_changed) for_each_crtc_in_state()
680 if (crtc->state->enable && funcs->mode_set_nofb) { for_each_crtc_in_state()
694 if (!connector->state->best_encoder) for_each_connector_in_state()
697 encoder = connector->state->best_encoder; for_each_connector_in_state()
699 new_crtc_state = connector->state->crtc->state; for_each_connector_in_state()
725 * @old_state: atomic state object with old state structures
748 * @old_state: atomic state object with old state structures
772 if (!needs_modeset(crtc->state)) for_each_crtc_in_state()
775 if (!crtc->state->active) for_each_crtc_in_state()
780 if (crtc->state->enable) { for_each_crtc_in_state()
795 if (!connector->state->best_encoder) for_each_connector_in_state()
798 if (!connector->state->crtc->state->active || for_each_connector_in_state()
799 !needs_modeset(connector->state->crtc->state)) for_each_connector_in_state()
802 encoder = connector->state->best_encoder; for_each_connector_in_state()
827 struct drm_atomic_state *state) wait_for_fences()
833 for_each_plane_in_state(state, plane, plane_state, i) { for_each_plane_in_state()
834 if (!plane->state->fence) for_each_plane_in_state()
837 WARN_ON(!plane->state->fb); for_each_plane_in_state()
839 fence_wait(plane->state->fence, false); for_each_plane_in_state()
840 fence_put(plane->state->fence); for_each_plane_in_state()
841 plane->state->fence = NULL; for_each_plane_in_state()
854 if (plane->state->crtc != crtc && for_each_plane_in_state()
858 if (plane->state->fb != old_plane_state->fb) for_each_plane_in_state()
868 * @old_state: atomic state object with old state structures
885 /* No one cares about the old state, so abuse it for tracking for_each_crtc_in_state()
890 if (!crtc->state->enable) for_each_crtc_in_state()
924 * drm_atomic_helper_commit - commit validated state object
926 * @state: the driver state object
929 * This function commits a with drm_atomic_helper_check() pre-validated state
937 struct drm_atomic_state *state, drm_atomic_helper_commit()
945 ret = drm_atomic_helper_prepare_planes(dev, state); drm_atomic_helper_commit()
951 * when the hw goes bonghits. Which means we can commit the new state on drm_atomic_helper_commit()
955 drm_atomic_helper_swap_state(dev, state); drm_atomic_helper_commit()
963 * before the new state gets committed on the software side with drm_atomic_helper_commit()
966 * This scheme allows new atomic state updates to be prepared and drm_atomic_helper_commit()
973 wait_for_fences(dev, state); drm_atomic_helper_commit()
975 drm_atomic_helper_commit_modeset_disables(dev, state); drm_atomic_helper_commit()
977 drm_atomic_helper_commit_planes(dev, state); drm_atomic_helper_commit()
979 drm_atomic_helper_commit_modeset_enables(dev, state); drm_atomic_helper_commit()
981 drm_atomic_helper_wait_for_vblanks(dev, state); drm_atomic_helper_commit()
983 drm_atomic_helper_cleanup_planes(dev, state); drm_atomic_helper_commit()
985 drm_atomic_state_free(state); drm_atomic_helper_commit()
1006 * might be affected the new state update. This can be done by either cancelling
1012 * (for updates which don't touch global state) and a global one. Then we only
1016 * 3. The software state is updated synchronously with
1018 * locks means concurrent callers never see inconsistent state. And doing this
1032 * @state: atomic state object with new state structures
1034 * This function prepares plane state, specifically framebuffers, for the new
1042 struct drm_atomic_state *state) drm_atomic_helper_prepare_planes()
1049 struct drm_plane *plane = state->planes[i]; drm_atomic_helper_prepare_planes()
1050 struct drm_plane_state *plane_state = state->plane_states[i]; drm_atomic_helper_prepare_planes()
1072 struct drm_plane *plane = state->planes[i]; drm_atomic_helper_prepare_planes()
1073 struct drm_plane_state *plane_state = state->plane_states[i]; drm_atomic_helper_prepare_planes()
1081 fb = state->plane_states[i]->fb; drm_atomic_helper_prepare_planes()
1093 * drm_atomic_helper_commit_planes - commit plane state
1095 * @old_state: atomic state object with old state structures
1097 * This function commits the new plane state using the plane and atomic helper
1098 * functions for planes and crtcs. It assumes that the atomic state has already
1099 * been pushed into the relevant object state pointers, since this step can no
1102 * It still requires the global state object @old_state to know which planes and
1161 * @old_state: atomic state object with old state structures
1163 * This function cleans up plane state, specifically framebuffers, from the old
1167 * This function must also be called on the new state when the atomic update
1192 * drm_atomic_helper_swap_state - store atomic state into current sw state
1194 * @state: atomic state
1196 * This function stores the atomic state into the current state pointers in all
1198 * and succeeded, but before the actual hardware state is committed.
1200 * For cleanup and error recovery the current state for all changed objects will
1201 * be swaped into @state.
1205 * 1. Call drm_atomic_helper_prepare_planes() with the staged atomic state.
1209 * 3. Put the staged state into the current state pointers with this function.
1211 * 4. Actually commit the hardware state.
1213 * 5. Call drm_atomic_helper_cleanup_planes with @state, which since step 3
1214 * contains the old state. Also do any other cleanup required with that state.
1217 struct drm_atomic_state *state) drm_atomic_helper_swap_state()
1222 struct drm_connector *connector = state->connectors[i]; drm_atomic_helper_swap_state()
1227 connector->state->state = state; drm_atomic_helper_swap_state()
1228 swap(state->connector_states[i], connector->state); drm_atomic_helper_swap_state()
1229 connector->state->state = NULL; drm_atomic_helper_swap_state()
1233 struct drm_crtc *crtc = state->crtcs[i]; drm_atomic_helper_swap_state()
1238 crtc->state->state = state; drm_atomic_helper_swap_state()
1239 swap(state->crtc_states[i], crtc->state); drm_atomic_helper_swap_state()
1240 crtc->state->state = NULL; drm_atomic_helper_swap_state()
1244 struct drm_plane *plane = state->planes[i]; drm_atomic_helper_swap_state()
1249 plane->state->state = state; drm_atomic_helper_swap_state()
1250 swap(state->plane_states[i], plane->state); drm_atomic_helper_swap_state()
1251 plane->state->state = NULL; drm_atomic_helper_swap_state()
1283 struct drm_atomic_state *state; drm_atomic_helper_update_plane() local
1287 state = drm_atomic_state_alloc(plane->dev); drm_atomic_helper_update_plane()
1288 if (!state) drm_atomic_helper_update_plane()
1291 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); drm_atomic_helper_update_plane()
1293 plane_state = drm_atomic_get_plane_state(state, plane); drm_atomic_helper_update_plane()
1312 ret = drm_atomic_commit(state); drm_atomic_helper_update_plane()
1317 state->legacy_cursor_update = true; drm_atomic_helper_update_plane()
1319 /* Driver takes ownership of state on successful commit. */ drm_atomic_helper_update_plane()
1325 drm_atomic_state_free(state); drm_atomic_helper_update_plane()
1329 drm_atomic_state_clear(state); drm_atomic_helper_update_plane()
1330 drm_atomic_legacy_backoff(state); drm_atomic_helper_update_plane()
1354 struct drm_atomic_state *state; drm_atomic_helper_disable_plane() local
1369 state = drm_atomic_state_alloc(plane->dev); drm_atomic_helper_disable_plane()
1370 if (!state) drm_atomic_helper_disable_plane()
1373 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(plane->crtc); drm_atomic_helper_disable_plane()
1375 plane_state = drm_atomic_get_plane_state(state, plane); drm_atomic_helper_disable_plane()
1395 state->legacy_cursor_update = true; drm_atomic_helper_disable_plane()
1397 ret = drm_atomic_commit(state); drm_atomic_helper_disable_plane()
1401 /* Driver takes ownership of state on successful commit. */ drm_atomic_helper_disable_plane()
1407 drm_atomic_state_free(state); drm_atomic_helper_disable_plane()
1411 drm_atomic_state_clear(state); drm_atomic_helper_disable_plane()
1412 drm_atomic_legacy_backoff(state); drm_atomic_helper_disable_plane()
1425 static int update_output_state(struct drm_atomic_state *state, update_output_state() argument
1436 state->acquire_ctx); update_output_state()
1442 conn_state = drm_atomic_get_connector_state(state, update_output_state()
1448 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
1449 ret = drm_atomic_add_affected_connectors(state, crtc); for_each_crtc_in_state()
1454 /* Then recompute connector->crtc links and crtc enabling state. */ for_each_connector_in_state()
1455 for_each_connector_in_state(state, connector, conn_state, i) { for_each_connector_in_state()
1474 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
1483 drm_atomic_connectors_for_crtc(state, crtc); for_each_crtc_in_state()
1500 struct drm_atomic_state *state; drm_atomic_helper_set_config() local
1506 state = drm_atomic_state_alloc(crtc->dev); drm_atomic_helper_set_config()
1507 if (!state) drm_atomic_helper_set_config()
1510 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); drm_atomic_helper_set_config()
1512 crtc_state = drm_atomic_get_crtc_state(state, crtc); drm_atomic_helper_set_config()
1518 primary_state = drm_atomic_get_plane_state(state, crtc->primary); drm_atomic_helper_set_config()
1561 ret = update_output_state(state, set); drm_atomic_helper_set_config()
1565 ret = drm_atomic_commit(state); drm_atomic_helper_set_config()
1569 /* Driver takes ownership of state on successful commit. */ drm_atomic_helper_set_config()
1575 drm_atomic_state_free(state); drm_atomic_helper_set_config()
1579 drm_atomic_state_clear(state); drm_atomic_helper_set_config()
1580 drm_atomic_legacy_backoff(state); drm_atomic_helper_set_config()
1610 struct drm_atomic_state *state; drm_atomic_helper_crtc_set_property() local
1614 state = drm_atomic_state_alloc(crtc->dev); drm_atomic_helper_crtc_set_property()
1615 if (!state) drm_atomic_helper_crtc_set_property()
1619 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; drm_atomic_helper_crtc_set_property()
1621 crtc_state = drm_atomic_get_crtc_state(state, crtc); drm_atomic_helper_crtc_set_property()
1632 ret = drm_atomic_commit(state); drm_atomic_helper_crtc_set_property()
1636 /* Driver takes ownership of state on successful commit. */ drm_atomic_helper_crtc_set_property()
1642 drm_atomic_state_free(state); drm_atomic_helper_crtc_set_property()
1646 drm_atomic_state_clear(state); drm_atomic_helper_crtc_set_property()
1647 drm_atomic_legacy_backoff(state); drm_atomic_helper_crtc_set_property()
1670 struct drm_atomic_state *state; drm_atomic_helper_plane_set_property() local
1674 state = drm_atomic_state_alloc(plane->dev); drm_atomic_helper_plane_set_property()
1675 if (!state) drm_atomic_helper_plane_set_property()
1679 state->acquire_ctx = plane->dev->mode_config.acquire_ctx; drm_atomic_helper_plane_set_property()
1681 plane_state = drm_atomic_get_plane_state(state, plane); drm_atomic_helper_plane_set_property()
1692 ret = drm_atomic_commit(state); drm_atomic_helper_plane_set_property()
1696 /* Driver takes ownership of state on successful commit. */ drm_atomic_helper_plane_set_property()
1702 drm_atomic_state_free(state); drm_atomic_helper_plane_set_property()
1706 drm_atomic_state_clear(state); drm_atomic_helper_plane_set_property()
1707 drm_atomic_legacy_backoff(state); drm_atomic_helper_plane_set_property()
1730 struct drm_atomic_state *state; drm_atomic_helper_connector_set_property() local
1734 state = drm_atomic_state_alloc(connector->dev); drm_atomic_helper_connector_set_property()
1735 if (!state) drm_atomic_helper_connector_set_property()
1739 state->acquire_ctx = connector->dev->mode_config.acquire_ctx; drm_atomic_helper_connector_set_property()
1741 connector_state = drm_atomic_get_connector_state(state, connector); drm_atomic_helper_connector_set_property()
1752 ret = drm_atomic_commit(state); drm_atomic_helper_connector_set_property()
1756 /* Driver takes ownership of state on successful commit. */ drm_atomic_helper_connector_set_property()
1762 drm_atomic_state_free(state); drm_atomic_helper_connector_set_property()
1766 drm_atomic_state_clear(state); drm_atomic_helper_connector_set_property()
1767 drm_atomic_legacy_backoff(state); drm_atomic_helper_connector_set_property()
1795 struct drm_atomic_state *state; drm_atomic_helper_page_flip() local
1803 state = drm_atomic_state_alloc(plane->dev); drm_atomic_helper_page_flip()
1804 if (!state) drm_atomic_helper_page_flip()
1807 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); drm_atomic_helper_page_flip()
1809 crtc_state = drm_atomic_get_crtc_state(state, crtc); drm_atomic_helper_page_flip()
1816 plane_state = drm_atomic_get_plane_state(state, plane); drm_atomic_helper_page_flip()
1827 ret = drm_atomic_async_commit(state); drm_atomic_helper_page_flip()
1833 plane->fb = plane->state->fb; drm_atomic_helper_page_flip()
1835 /* Driver takes ownership of state on successful async commit. */ drm_atomic_helper_page_flip()
1841 drm_atomic_state_free(state); drm_atomic_helper_page_flip()
1845 drm_atomic_state_clear(state); drm_atomic_helper_page_flip()
1846 drm_atomic_legacy_backoff(state); drm_atomic_helper_page_flip()
1866 * ->active state for the corresponding CRTC (if the connector is enabled) and
1873 struct drm_atomic_state *state; drm_atomic_helper_connector_dpms() local
1884 crtc = connector->state->crtc; drm_atomic_helper_connector_dpms()
1890 state = drm_atomic_state_alloc(connector->dev); drm_atomic_helper_connector_dpms()
1891 if (!state) drm_atomic_helper_connector_dpms()
1894 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); drm_atomic_helper_connector_dpms()
1896 crtc_state = drm_atomic_get_crtc_state(state, crtc); drm_atomic_helper_connector_dpms()
1903 if (tmp_connector->state->crtc != crtc) drm_atomic_helper_connector_dpms()
1913 ret = drm_atomic_commit(state); drm_atomic_helper_connector_dpms()
1917 /* Driver takes ownership of state on successful async commit. */ drm_atomic_helper_connector_dpms()
1923 drm_atomic_state_free(state); drm_atomic_helper_connector_dpms()
1929 drm_atomic_state_clear(state); drm_atomic_helper_connector_dpms()
1930 drm_atomic_legacy_backoff(state); drm_atomic_helper_connector_dpms()
1937 * DOC: atomic state reset and initialization
1940 * and correct atomic software state for all connectors, CRTCs and planes
1942 * suspend. One way to solve this is to have a hardware state read-out
1943 * infrastructure which reconstructs the full software state (e.g. the i915
1946 * The simpler solution is to just reset the software state to everything off,
1955 * Resets the atomic state for @crtc by freeing the state pointer (which might
1956 * be NULL, e.g. at driver load time) and allocating a new empty state object.
1960 kfree(crtc->state); drm_atomic_helper_crtc_reset()
1961 crtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL); drm_atomic_helper_crtc_reset()
1963 if (crtc->state) drm_atomic_helper_crtc_reset()
1964 crtc->state->crtc = crtc; drm_atomic_helper_crtc_reset()
1969 * __drm_atomic_helper_crtc_duplicate_state - copy atomic CRTC state
1971 * @state: atomic CRTC state
1973 * Copies atomic state from a CRTC's current state and resets inferred values.
1974 * This is useful for drivers that subclass the CRTC state.
1977 struct drm_crtc_state *state) __drm_atomic_helper_crtc_duplicate_state()
1979 memcpy(state, crtc->state, sizeof(*state)); __drm_atomic_helper_crtc_duplicate_state()
1981 state->mode_changed = false; __drm_atomic_helper_crtc_duplicate_state()
1982 state->active_changed = false; __drm_atomic_helper_crtc_duplicate_state()
1983 state->planes_changed = false; __drm_atomic_helper_crtc_duplicate_state()
1984 state->event = NULL; __drm_atomic_helper_crtc_duplicate_state()
1989 * drm_atomic_helper_crtc_duplicate_state - default state duplicate hook
1992 * Default CRTC state duplicate hook for drivers which don't have their own
1993 * subclassed CRTC state structure.
1998 struct drm_crtc_state *state; drm_atomic_helper_crtc_duplicate_state() local
2000 if (WARN_ON(!crtc->state)) drm_atomic_helper_crtc_duplicate_state()
2003 state = kmalloc(sizeof(*state), GFP_KERNEL); drm_atomic_helper_crtc_duplicate_state()
2004 if (state) drm_atomic_helper_crtc_duplicate_state()
2005 __drm_atomic_helper_crtc_duplicate_state(crtc, state); drm_atomic_helper_crtc_duplicate_state()
2007 return state; drm_atomic_helper_crtc_duplicate_state()
2012 * __drm_atomic_helper_crtc_destroy_state - release CRTC state
2014 * @state: CRTC state object to release
2016 * Releases all resources stored in the CRTC state without actually freeing
2017 * the memory of the CRTC state. This is useful for drivers that subclass the
2018 * CRTC state.
2021 struct drm_crtc_state *state) __drm_atomic_helper_crtc_destroy_state()
2025 * state will automatically do the right thing if code is ever added __drm_atomic_helper_crtc_destroy_state()
2032 * drm_atomic_helper_crtc_destroy_state - default state destroy hook
2034 * @state: CRTC state object to release
2036 * Default CRTC state destroy hook for drivers which don't have their own
2037 * subclassed CRTC state structure.
2040 struct drm_crtc_state *state) drm_atomic_helper_crtc_destroy_state()
2042 __drm_atomic_helper_crtc_destroy_state(crtc, state); drm_atomic_helper_crtc_destroy_state()
2043 kfree(state); drm_atomic_helper_crtc_destroy_state()
2051 * Resets the atomic state for @plane by freeing the state pointer (which might
2052 * be NULL, e.g. at driver load time) and allocating a new empty state object.
2056 if (plane->state && plane->state->fb) drm_atomic_helper_plane_reset()
2057 drm_framebuffer_unreference(plane->state->fb); drm_atomic_helper_plane_reset()
2059 kfree(plane->state); drm_atomic_helper_plane_reset()
2060 plane->state = kzalloc(sizeof(*plane->state), GFP_KERNEL); drm_atomic_helper_plane_reset()
2062 if (plane->state) drm_atomic_helper_plane_reset()
2063 plane->state->plane = plane; drm_atomic_helper_plane_reset()
2068 * __drm_atomic_helper_plane_duplicate_state - copy atomic plane state
2070 * @state: atomic plane state
2072 * Copies atomic state from a plane's current state. This is useful for
2073 * drivers that subclass the plane state.
2076 struct drm_plane_state *state) __drm_atomic_helper_plane_duplicate_state()
2078 memcpy(state, plane->state, sizeof(*state)); __drm_atomic_helper_plane_duplicate_state()
2080 if (state->fb) __drm_atomic_helper_plane_duplicate_state()
2081 drm_framebuffer_reference(state->fb); __drm_atomic_helper_plane_duplicate_state()
2086 * drm_atomic_helper_plane_duplicate_state - default state duplicate hook
2089 * Default plane state duplicate hook for drivers which don't have their own
2090 * subclassed plane state structure.
2095 struct drm_plane_state *state; drm_atomic_helper_plane_duplicate_state() local
2097 if (WARN_ON(!plane->state)) drm_atomic_helper_plane_duplicate_state()
2100 state = kmalloc(sizeof(*state), GFP_KERNEL); drm_atomic_helper_plane_duplicate_state()
2101 if (state) drm_atomic_helper_plane_duplicate_state()
2102 __drm_atomic_helper_plane_duplicate_state(plane, state); drm_atomic_helper_plane_duplicate_state()
2104 return state; drm_atomic_helper_plane_duplicate_state()
2109 * __drm_atomic_helper_plane_destroy_state - release plane state
2111 * @state: plane state object to release
2113 * Releases all resources stored in the plane state without actually freeing
2114 * the memory of the plane state. This is useful for drivers that subclass the
2115 * plane state.
2118 struct drm_plane_state *state) __drm_atomic_helper_plane_destroy_state()
2120 if (state->fb) __drm_atomic_helper_plane_destroy_state()
2121 drm_framebuffer_unreference(state->fb); __drm_atomic_helper_plane_destroy_state()
2126 * drm_atomic_helper_plane_destroy_state - default state destroy hook
2128 * @state: plane state object to release
2130 * Default plane state destroy hook for drivers which don't have their own
2131 * subclassed plane state structure.
2134 struct drm_plane_state *state) drm_atomic_helper_plane_destroy_state()
2136 __drm_atomic_helper_plane_destroy_state(plane, state); drm_atomic_helper_plane_destroy_state()
2137 kfree(state); drm_atomic_helper_plane_destroy_state()
2145 * Resets the atomic state for @connector by freeing the state pointer (which
2146 * might be NULL, e.g. at driver load time) and allocating a new empty state
2151 kfree(connector->state); drm_atomic_helper_connector_reset()
2152 connector->state = kzalloc(sizeof(*connector->state), GFP_KERNEL); drm_atomic_helper_connector_reset()
2154 if (connector->state) drm_atomic_helper_connector_reset()
2155 connector->state->connector = connector; drm_atomic_helper_connector_reset()
2160 * __drm_atomic_helper_connector_duplicate_state - copy atomic connector state
2162 * @state: atomic connector state
2164 * Copies atomic state from a connector's current state. This is useful for
2165 * drivers that subclass the connector state.
2169 struct drm_connector_state *state) __drm_atomic_helper_connector_duplicate_state()
2171 memcpy(state, connector->state, sizeof(*state)); __drm_atomic_helper_connector_duplicate_state()
2176 * drm_atomic_helper_connector_duplicate_state - default state duplicate hook
2179 * Default connector state duplicate hook for drivers which don't have their own
2180 * subclassed connector state structure.
2185 struct drm_connector_state *state; drm_atomic_helper_connector_duplicate_state() local
2187 if (WARN_ON(!connector->state)) drm_atomic_helper_connector_duplicate_state()
2190 state = kmalloc(sizeof(*state), GFP_KERNEL); drm_atomic_helper_connector_duplicate_state()
2191 if (state) drm_atomic_helper_connector_duplicate_state()
2192 __drm_atomic_helper_connector_duplicate_state(connector, state); drm_atomic_helper_connector_duplicate_state()
2194 return state; drm_atomic_helper_connector_duplicate_state()
2199 * __drm_atomic_helper_connector_destroy_state - release connector state
2201 * @state: connector state object to release
2203 * Releases all resources stored in the connector state without actually
2204 * freeing the memory of the connector state. This is useful for drivers that
2205 * subclass the connector state.
2209 struct drm_connector_state *state) __drm_atomic_helper_connector_destroy_state()
2213 * state will automatically do the right thing if code is ever added __drm_atomic_helper_connector_destroy_state()
2220 * drm_atomic_helper_connector_destroy_state - default state destroy hook
2222 * @state: connector state object to release
2224 * Default connector state destroy hook for drivers which don't have their own
2225 * subclassed connector state structure.
2228 struct drm_connector_state *state) drm_atomic_helper_connector_destroy_state()
2230 __drm_atomic_helper_connector_destroy_state(connector, state); drm_atomic_helper_connector_destroy_state()
2231 kfree(state); drm_atomic_helper_connector_destroy_state()
361 drm_atomic_helper_check_modeset(struct drm_device *dev, struct drm_atomic_state *state) drm_atomic_helper_check_modeset() argument
455 drm_atomic_helper_check_planes(struct drm_device *dev, struct drm_atomic_state *state) drm_atomic_helper_check_planes() argument
522 drm_atomic_helper_check(struct drm_device *dev, struct drm_atomic_state *state) drm_atomic_helper_check() argument
826 wait_for_fences(struct drm_device *dev, struct drm_atomic_state *state) wait_for_fences() argument
936 drm_atomic_helper_commit(struct drm_device *dev, struct drm_atomic_state *state, bool async) drm_atomic_helper_commit() argument
1041 drm_atomic_helper_prepare_planes(struct drm_device *dev, struct drm_atomic_state *state) drm_atomic_helper_prepare_planes() argument
1216 drm_atomic_helper_swap_state(struct drm_device *dev, struct drm_atomic_state *state) drm_atomic_helper_swap_state() argument
1976 __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, struct drm_crtc_state *state) __drm_atomic_helper_crtc_duplicate_state() argument
2020 __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) __drm_atomic_helper_crtc_destroy_state() argument
2039 drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) drm_atomic_helper_crtc_destroy_state() argument
2075 __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, struct drm_plane_state *state) __drm_atomic_helper_plane_duplicate_state() argument
2117 __drm_atomic_helper_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) __drm_atomic_helper_plane_destroy_state() argument
2133 drm_atomic_helper_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) drm_atomic_helper_plane_destroy_state() argument
2168 __drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector, struct drm_connector_state *state) __drm_atomic_helper_connector_duplicate_state() argument
2208 __drm_atomic_helper_connector_destroy_state(struct drm_connector *connector, struct drm_connector_state *state) __drm_atomic_helper_connector_destroy_state() argument
2227 drm_atomic_helper_connector_destroy_state(struct drm_connector *connector, struct drm_connector_state *state) drm_atomic_helper_connector_destroy_state() argument
H A Ddrm_atomic.c33 static void kfree_state(struct drm_atomic_state *state) kfree_state() argument
35 kfree(state->connectors); kfree_state()
36 kfree(state->connector_states); kfree_state()
37 kfree(state->crtcs); kfree_state()
38 kfree(state->crtc_states); kfree_state()
39 kfree(state->planes); kfree_state()
40 kfree(state->plane_states); kfree_state()
41 kfree(state); kfree_state()
45 * drm_atomic_state_alloc - allocate atomic state
48 * This allocates an empty atomic state to track updates.
53 struct drm_atomic_state *state; drm_atomic_state_alloc() local
55 state = kzalloc(sizeof(*state), GFP_KERNEL); drm_atomic_state_alloc()
56 if (!state) drm_atomic_state_alloc()
62 state->allow_modeset = true; drm_atomic_state_alloc()
64 state->num_connector = ACCESS_ONCE(dev->mode_config.num_connector); drm_atomic_state_alloc()
66 state->crtcs = kcalloc(dev->mode_config.num_crtc, drm_atomic_state_alloc()
67 sizeof(*state->crtcs), GFP_KERNEL); drm_atomic_state_alloc()
68 if (!state->crtcs) drm_atomic_state_alloc()
70 state->crtc_states = kcalloc(dev->mode_config.num_crtc, drm_atomic_state_alloc()
71 sizeof(*state->crtc_states), GFP_KERNEL); drm_atomic_state_alloc()
72 if (!state->crtc_states) drm_atomic_state_alloc()
74 state->planes = kcalloc(dev->mode_config.num_total_plane, drm_atomic_state_alloc()
75 sizeof(*state->planes), GFP_KERNEL); drm_atomic_state_alloc()
76 if (!state->planes) drm_atomic_state_alloc()
78 state->plane_states = kcalloc(dev->mode_config.num_total_plane, drm_atomic_state_alloc()
79 sizeof(*state->plane_states), GFP_KERNEL); drm_atomic_state_alloc()
80 if (!state->plane_states) drm_atomic_state_alloc()
82 state->connectors = kcalloc(state->num_connector, drm_atomic_state_alloc()
83 sizeof(*state->connectors), drm_atomic_state_alloc()
85 if (!state->connectors) drm_atomic_state_alloc()
87 state->connector_states = kcalloc(state->num_connector, drm_atomic_state_alloc()
88 sizeof(*state->connector_states), drm_atomic_state_alloc()
90 if (!state->connector_states) drm_atomic_state_alloc()
93 state->dev = dev; drm_atomic_state_alloc()
95 DRM_DEBUG_ATOMIC("Allocate atomic state %p\n", state); drm_atomic_state_alloc()
97 return state; drm_atomic_state_alloc()
99 kfree_state(state); drm_atomic_state_alloc()
106 * drm_atomic_state_clear - clear state object
107 * @state: atomic state
111 * configuration. Which means that all the state assembled in @state is no
112 * longer an atomic update to the current state, but to some arbitrary earlier
113 * state. Which could break assumptions the driver's ->atomic_check likely
116 * Hence we must clear all cached state and completely start over, using this
119 void drm_atomic_state_clear(struct drm_atomic_state *state) drm_atomic_state_clear() argument
121 struct drm_device *dev = state->dev; drm_atomic_state_clear()
125 DRM_DEBUG_ATOMIC("Clearing atomic state %p\n", state); drm_atomic_state_clear()
127 for (i = 0; i < state->num_connector; i++) { drm_atomic_state_clear()
128 struct drm_connector *connector = state->connectors[i]; drm_atomic_state_clear()
136 state->connector_states[i]); drm_atomic_state_clear()
137 state->connectors[i] = NULL; drm_atomic_state_clear()
138 state->connector_states[i] = NULL; drm_atomic_state_clear()
142 struct drm_crtc *crtc = state->crtcs[i]; drm_atomic_state_clear()
148 state->crtc_states[i]); drm_atomic_state_clear()
149 state->crtcs[i] = NULL; drm_atomic_state_clear()
150 state->crtc_states[i] = NULL; drm_atomic_state_clear()
154 struct drm_plane *plane = state->planes[i]; drm_atomic_state_clear()
160 state->plane_states[i]); drm_atomic_state_clear()
161 state->planes[i] = NULL; drm_atomic_state_clear()
162 state->plane_states[i] = NULL; drm_atomic_state_clear()
168 * drm_atomic_state_free - free all memory for an atomic state
169 * @state: atomic state to deallocate
171 * This frees all memory associated with an atomic state, including all the
172 * per-object state for planes, crtcs and connectors.
174 void drm_atomic_state_free(struct drm_atomic_state *state) drm_atomic_state_free() argument
176 if (!state) drm_atomic_state_free()
179 drm_atomic_state_clear(state); drm_atomic_state_free()
181 DRM_DEBUG_ATOMIC("Freeing atomic state %p\n", state); drm_atomic_state_free()
183 kfree_state(state); drm_atomic_state_free()
188 * drm_atomic_get_crtc_state - get crtc state
189 * @state: global atomic state object
190 * @crtc: crtc to get state object for
192 * This function returns the crtc state for the given crtc, allocating it if
193 * needed. It will also grab the relevant crtc lock to make sure that the state
198 * Either the allocated state or the error code encoded into the pointer. When
203 drm_atomic_get_crtc_state(struct drm_atomic_state *state, drm_atomic_get_crtc_state() argument
211 if (state->crtc_states[index]) drm_atomic_get_crtc_state()
212 return state->crtc_states[index]; drm_atomic_get_crtc_state()
214 ret = drm_modeset_lock(&crtc->mutex, state->acquire_ctx); drm_atomic_get_crtc_state()
222 state->crtc_states[index] = crtc_state; drm_atomic_get_crtc_state()
223 state->crtcs[index] = crtc; drm_atomic_get_crtc_state()
224 crtc_state->state = state; drm_atomic_get_crtc_state()
226 DRM_DEBUG_ATOMIC("Added [CRTC:%d] %p state to %p\n", drm_atomic_get_crtc_state()
227 crtc->base.id, crtc_state, state); drm_atomic_get_crtc_state()
236 * @state: the state object to update with the new property value
250 struct drm_crtc_state *state, struct drm_property *property, drm_atomic_crtc_set_property()
258 state->active = val; drm_atomic_crtc_set_property()
260 return crtc->funcs->atomic_set_property(crtc, state, property, val); drm_atomic_crtc_set_property()
275 const struct drm_crtc_state *state, drm_atomic_crtc_get_property()
282 *val = state->active; drm_atomic_crtc_get_property()
284 return crtc->funcs->atomic_get_property(crtc, state, property, val); drm_atomic_crtc_get_property()
292 * drm_atomic_crtc_check - check crtc state
294 * @state: crtc state to check
296 * Provides core sanity checks for crtc state.
302 struct drm_crtc_state *state) drm_atomic_crtc_check()
309 * TODO: Add generic modeset state checks once we support those. drm_atomic_crtc_check()
312 if (state->active && !state->enable) { drm_atomic_crtc_check()
322 * drm_atomic_get_plane_state - get plane state
323 * @state: global atomic state object
324 * @plane: plane to get state object for
326 * This function returns the plane state for the given plane, allocating it if
327 * needed. It will also grab the relevant plane lock to make sure that the state
332 * Either the allocated state or the error code encoded into the pointer. When
337 drm_atomic_get_plane_state(struct drm_atomic_state *state, drm_atomic_get_plane_state() argument
345 if (state->plane_states[index]) drm_atomic_get_plane_state()
346 return state->plane_states[index]; drm_atomic_get_plane_state()
348 ret = drm_modeset_lock(&plane->mutex, state->acquire_ctx); drm_atomic_get_plane_state()
356 state->plane_states[index] = plane_state; drm_atomic_get_plane_state()
357 state->planes[index] = plane; drm_atomic_get_plane_state()
358 plane_state->state = state; drm_atomic_get_plane_state()
360 DRM_DEBUG_ATOMIC("Added [PLANE:%d] %p state to %p\n", drm_atomic_get_plane_state()
361 plane->base.id, plane_state, state); drm_atomic_get_plane_state()
366 crtc_state = drm_atomic_get_crtc_state(state, drm_atomic_get_plane_state()
379 * @state: the state object to update with the new property value
393 struct drm_plane_state *state, struct drm_property *property, drm_atomic_plane_set_property()
401 drm_atomic_set_fb_for_plane(state, fb); drm_atomic_plane_set_property()
406 return drm_atomic_set_crtc_for_plane(state, crtc); drm_atomic_plane_set_property()
408 state->crtc_x = U642I64(val); drm_atomic_plane_set_property()
410 state->crtc_y = U642I64(val); drm_atomic_plane_set_property()
412 state->crtc_w = val; drm_atomic_plane_set_property()
414 state->crtc_h = val; drm_atomic_plane_set_property()
416 state->src_x = val; drm_atomic_plane_set_property()
418 state->src_y = val; drm_atomic_plane_set_property()
420 state->src_w = val; drm_atomic_plane_set_property()
422 state->src_h = val; drm_atomic_plane_set_property()
424 state->rotation = val; drm_atomic_plane_set_property()
426 return plane->funcs->atomic_set_property(plane, state, drm_atomic_plane_set_property()
444 const struct drm_plane_state *state, drm_atomic_plane_get_property()
451 *val = (state->fb) ? state->fb->base.id : 0; drm_atomic_plane_get_property()
453 *val = (state->crtc) ? state->crtc->base.id : 0; drm_atomic_plane_get_property()
455 *val = I642U64(state->crtc_x); drm_atomic_plane_get_property()
457 *val = I642U64(state->crtc_y); drm_atomic_plane_get_property()
459 *val = state->crtc_w; drm_atomic_plane_get_property()
461 *val = state->crtc_h; drm_atomic_plane_get_property()
463 *val = state->src_x; drm_atomic_plane_get_property()
465 *val = state->src_y; drm_atomic_plane_get_property()
467 *val = state->src_w; drm_atomic_plane_get_property()
469 *val = state->src_h; drm_atomic_plane_get_property()
471 *val = state->rotation; drm_atomic_plane_get_property()
473 return plane->funcs->atomic_get_property(plane, state, property, val); drm_atomic_plane_get_property()
482 * drm_atomic_plane_check - check plane state
484 * @state: plane state to check
486 * Provides core sanity checks for plane state.
492 struct drm_plane_state *state) drm_atomic_plane_check()
498 if (WARN_ON(state->crtc && !state->fb)) { drm_atomic_plane_check()
501 } else if (WARN_ON(state->fb && !state->crtc)) { drm_atomic_plane_check()
506 /* if disabled, we don't care about the rest of the state: */ drm_atomic_plane_check()
507 if (!state->crtc) drm_atomic_plane_check()
511 if (!(plane->possible_crtcs & drm_crtc_mask(state->crtc))) { drm_atomic_plane_check()
517 ret = drm_plane_check_pixel_format(plane, state->fb->pixel_format); drm_atomic_plane_check()
520 drm_get_format_name(state->fb->pixel_format)); drm_atomic_plane_check()
525 if (state->crtc_w > INT_MAX || drm_atomic_plane_check()
526 state->crtc_x > INT_MAX - (int32_t) state->crtc_w || drm_atomic_plane_check()
527 state->crtc_h > INT_MAX || drm_atomic_plane_check()
528 state->crtc_y > INT_MAX - (int32_t) state->crtc_h) { drm_atomic_plane_check()
530 state->crtc_w, state->crtc_h, drm_atomic_plane_check()
531 state->crtc_x, state->crtc_y); drm_atomic_plane_check()
535 fb_width = state->fb->width << 16; drm_atomic_plane_check()
536 fb_height = state->fb->height << 16; drm_atomic_plane_check()
539 if (state->src_w > fb_width || drm_atomic_plane_check()
540 state->src_x > fb_width - state->src_w || drm_atomic_plane_check()
541 state->src_h > fb_height || drm_atomic_plane_check()
542 state->src_y > fb_height - state->src_h) { drm_atomic_plane_check()
545 state->src_w >> 16, ((state->src_w & 0xffff) * 15625) >> 10, drm_atomic_plane_check()
546 state->src_h >> 16, ((state->src_h & 0xffff) * 15625) >> 10, drm_atomic_plane_check()
547 state->src_x >> 16, ((state->src_x & 0xffff) * 15625) >> 10, drm_atomic_plane_check()
548 state->src_y >> 16, ((state->src_y & 0xffff) * 15625) >> 10); drm_atomic_plane_check()
556 * drm_atomic_get_connector_state - get connector state
557 * @state: global atomic state object
558 * @connector: connector to get state object for
560 * This function returns the connector state for the given connector,
562 * make sure that the state is consistent.
566 * Either the allocated state or the error code encoded into the pointer. When
571 drm_atomic_get_connector_state(struct drm_atomic_state *state, drm_atomic_get_connector_state() argument
578 ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx); drm_atomic_get_connector_state()
585 * Construction of atomic state updates can race with a connector drm_atomic_get_connector_state()
594 if (index >= state->num_connector) { drm_atomic_get_connector_state()
595 DRM_DEBUG_ATOMIC("Hot-added connector would overflow state array, restarting\n"); drm_atomic_get_connector_state()
599 if (state->connector_states[index]) drm_atomic_get_connector_state()
600 return state->connector_states[index]; drm_atomic_get_connector_state()
606 state->connector_states[index] = connector_state; drm_atomic_get_connector_state()
607 state->connectors[index] = connector; drm_atomic_get_connector_state()
608 connector_state->state = state; drm_atomic_get_connector_state()
610 DRM_DEBUG_ATOMIC("Added [CONNECTOR:%d] %p state to %p\n", drm_atomic_get_connector_state()
611 connector->base.id, connector_state, state); drm_atomic_get_connector_state()
616 crtc_state = drm_atomic_get_crtc_state(state, drm_atomic_get_connector_state()
629 * @state: the state object to update with the new property value
643 struct drm_connector_state *state, struct drm_property *property, drm_atomic_connector_set_property()
651 return drm_atomic_set_crtc_for_connector(state, crtc); drm_atomic_connector_set_property()
660 state, property, val); drm_atomic_connector_set_property()
675 const struct drm_connector_state *state, drm_atomic_connector_get_property()
682 *val = (state->crtc) ? state->crtc->base.id : 0; drm_atomic_connector_get_property()
687 state, property, val); drm_atomic_connector_get_property()
706 connector->state, property, val); drm_atomic_get_property()
713 crtc->state, property, val); drm_atomic_get_property()
720 plane->state, property, val); drm_atomic_get_property()
733 * @plane_state: the plane whose incoming state to update
736 * Changing the assigned crtc for a plane requires us to grab the lock and state
738 * besides updating the pointer in the state object itself.
753 crtc_state = drm_atomic_get_crtc_state(plane_state->state, drm_atomic_set_crtc_for_plane()
764 crtc_state = drm_atomic_get_crtc_state(plane_state->state, drm_atomic_set_crtc_for_plane()
772 DRM_DEBUG_ATOMIC("Link plane state %p to [CRTC:%d]\n", drm_atomic_set_crtc_for_plane()
775 DRM_DEBUG_ATOMIC("Link plane state %p to [NOCRTC]\n", drm_atomic_set_crtc_for_plane()
784 * @plane_state: atomic state object for the plane
790 * state object itself.
803 DRM_DEBUG_ATOMIC("Set [FB:%d] for plane state %p\n", drm_atomic_set_fb_for_plane()
806 DRM_DEBUG_ATOMIC("Set [NOFB] for plane state %p\n", drm_atomic_set_fb_for_plane()
813 * @conn_state: atomic state object for the connector
817 * state for the new crtc, as needed. This function takes care of all these
818 * details besides updating the pointer in the state object itself.
832 crtc_state = drm_atomic_get_crtc_state(conn_state->state, crtc); drm_atomic_set_crtc_for_connector()
840 DRM_DEBUG_ATOMIC("Link connector state %p to [CRTC:%d]\n", drm_atomic_set_crtc_for_connector()
843 DRM_DEBUG_ATOMIC("Link connector state %p to [NOCRTC]\n", drm_atomic_set_crtc_for_connector()
852 * @state: atomic state
856 * currently using @crtc to the atomic configuration @state. Note that this
868 drm_atomic_add_affected_connectors(struct drm_atomic_state *state, drm_atomic_add_affected_connectors() argument
871 struct drm_mode_config *config = &state->dev->mode_config; drm_atomic_add_affected_connectors()
876 ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx); drm_atomic_add_affected_connectors()
881 crtc->base.id, state); drm_atomic_add_affected_connectors()
884 * Changed connectors are already in @state, so only need to look at the drm_atomic_add_affected_connectors()
888 if (connector->state->crtc != crtc) drm_atomic_add_affected_connectors()
891 conn_state = drm_atomic_get_connector_state(state, connector); drm_atomic_add_affected_connectors()
902 * @state: atomic state
906 * according to @state. Useful to recompute the enable state for @crtc.
909 drm_atomic_connectors_for_crtc(struct drm_atomic_state *state, drm_atomic_connectors_for_crtc() argument
917 for_each_connector_in_state(state, connector, conn_state, i) { for_each_connector_in_state()
923 state, num_connected_connectors, crtc->base.id);
931 * @state: atomic state
937 void drm_atomic_legacy_backoff(struct drm_atomic_state *state) drm_atomic_legacy_backoff() argument
942 drm_modeset_backoff(state->acquire_ctx); drm_atomic_legacy_backoff()
944 ret = drm_modeset_lock(&state->dev->mode_config.connection_mutex, drm_atomic_legacy_backoff()
945 state->acquire_ctx); drm_atomic_legacy_backoff()
948 ret = drm_modeset_lock_all_crtcs(state->dev, drm_atomic_legacy_backoff()
949 state->acquire_ctx); drm_atomic_legacy_backoff()
957 * @state: atomic configuration to check
966 int drm_atomic_check_only(struct drm_atomic_state *state) drm_atomic_check_only() argument
968 struct drm_device *dev = state->dev; drm_atomic_check_only()
976 DRM_DEBUG_ATOMIC("checking %p\n", state); drm_atomic_check_only()
978 for_each_plane_in_state(state, plane, plane_state, i) { for_each_plane_in_state()
987 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
997 ret = config->funcs->atomic_check(state->dev, state);
999 if (!state->allow_modeset) { for_each_crtc_in_state()
1000 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
1016 * @state: atomic configuration to check
1022 * Also note that on successful execution ownership of @state is transferred
1024 * free or in any other way access @state. If the function fails then the caller
1025 * must clean up @state itself.
1030 int drm_atomic_commit(struct drm_atomic_state *state) drm_atomic_commit() argument
1032 struct drm_mode_config *config = &state->dev->mode_config; drm_atomic_commit()
1035 ret = drm_atomic_check_only(state); drm_atomic_commit()
1039 DRM_DEBUG_ATOMIC("commiting %p\n", state); drm_atomic_commit()
1041 return config->funcs->atomic_commit(state->dev, state, false); drm_atomic_commit()
1047 * @state: atomic configuration to check
1053 * Also note that on successful execution ownership of @state is transferred
1055 * free or in any other way access @state. If the function fails then the caller
1056 * must clean up @state itself.
1061 int drm_atomic_async_commit(struct drm_atomic_state *state) drm_atomic_async_commit() argument
1063 struct drm_mode_config *config = &state->dev->mode_config; drm_atomic_async_commit()
1066 ret = drm_atomic_check_only(state); drm_atomic_async_commit()
1070 DRM_DEBUG_ATOMIC("commiting %p asynchronously\n", state); drm_atomic_async_commit()
1072 return config->funcs->atomic_commit(state->dev, state, true); drm_atomic_async_commit()
1124 static int atomic_set_prop(struct drm_atomic_state *state, atomic_set_prop() argument
1139 connector_state = drm_atomic_get_connector_state(state, connector); atomic_set_prop()
1153 crtc_state = drm_atomic_get_crtc_state(state, crtc); atomic_set_prop()
1167 plane_state = drm_atomic_get_plane_state(state, plane); atomic_set_prop()
1195 struct drm_atomic_state *state; drm_mode_atomic_ioctl() local
1232 state = drm_atomic_state_alloc(dev); drm_mode_atomic_ioctl()
1233 if (!state) drm_mode_atomic_ioctl()
1236 state->acquire_ctx = &ctx; drm_mode_atomic_ioctl()
1237 state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET); drm_mode_atomic_ioctl()
1294 ret = atomic_set_prop(state, obj, prop, prop_value); drm_mode_atomic_ioctl()
1303 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
1317 ret = drm_atomic_check_only(state);
1318 /* _check_only() does not free state, unlike _commit() */
1319 drm_atomic_state_free(state);
1321 ret = drm_atomic_async_commit(state);
1323 ret = drm_atomic_commit(state);
1327 * locks (ie. while it is still safe to deref plane->state). We
1333 struct drm_framebuffer *new_fb = plane->state->fb; drm_for_each_plane_mask()
1337 plane->crtc = plane->state->crtc; drm_for_each_plane_mask()
1357 for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state()
1363 drm_atomic_state_free(state);
1371 drm_atomic_state_clear(state);
249 drm_atomic_crtc_set_property(struct drm_crtc *crtc, struct drm_crtc_state *state, struct drm_property *property, uint64_t val) drm_atomic_crtc_set_property() argument
274 drm_atomic_crtc_get_property(struct drm_crtc *crtc, const struct drm_crtc_state *state, struct drm_property *property, uint64_t *val) drm_atomic_crtc_get_property() argument
301 drm_atomic_crtc_check(struct drm_crtc *crtc, struct drm_crtc_state *state) drm_atomic_crtc_check() argument
392 drm_atomic_plane_set_property(struct drm_plane *plane, struct drm_plane_state *state, struct drm_property *property, uint64_t val) drm_atomic_plane_set_property() argument
443 drm_atomic_plane_get_property(struct drm_plane *plane, const struct drm_plane_state *state, struct drm_property *property, uint64_t *val) drm_atomic_plane_get_property() argument
491 drm_atomic_plane_check(struct drm_plane *plane, struct drm_plane_state *state) drm_atomic_plane_check() argument
642 drm_atomic_connector_set_property(struct drm_connector *connector, struct drm_connector_state *state, struct drm_property *property, uint64_t val) drm_atomic_connector_set_property() argument
674 drm_atomic_connector_get_property(struct drm_connector *connector, const struct drm_connector_state *state, struct drm_property *property, uint64_t *val) drm_atomic_connector_get_property() argument
/linux-4.1.27/drivers/media/pci/cx23885/
H A Dcimax2.c180 struct netup_ci_state *state = en50221->data; netup_ci_op_cam() local
181 struct cx23885_tsport *port = state->priv; netup_ci_op_cam()
191 if (state->current_ci_flag != flag) { netup_ci_op_cam()
192 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_op_cam()
200 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_op_cam()
205 state->current_ci_flag = flag; netup_ci_op_cam()
225 (state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1); netup_ci_op_cam()
237 (read) ? "read" : "write", state->ci_i2c_addr, addr, netup_ci_op_cam()
274 struct netup_ci_state *state = en50221->data; netup_ci_slot_reset() local
282 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_slot_reset()
291 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_slot_reset()
295 dvb_ca_en50221_camready_irq(&state->ca, 0); netup_ci_slot_reset()
309 struct netup_ci_state *state = en50221->data; netup_ci_set_irq() local
312 if (irq_mode == state->current_irq_mode) netup_ci_set_irq()
316 __func__, state->ci_i2c_addr, irq_mode); netup_ci_set_irq()
317 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_set_irq()
323 state->current_irq_mode = irq_mode; netup_ci_set_irq()
330 struct netup_ci_state *state = en50221->data; netup_ci_slot_ts_ctl() local
336 netup_read_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_slot_ts_ctl()
340 return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_slot_ts_ctl()
347 struct netup_ci_state *state = netup_read_ci_status() local
353 dvb_ca_en50221_frda_irq(&state->ca, 0); netup_read_ci_status()
357 if (time_after(jiffies, state->next_status_checked_time) netup_read_ci_status()
358 || !state->status) { netup_read_ci_status()
359 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr, netup_read_ci_status()
362 state->next_status_checked_time = jiffies netup_read_ci_status()
371 state->ci_i2c_addr, 0, buf[0], netup_read_ci_status()
376 state->status = DVB_CA_EN50221_POLL_CAM_PRESENT | netup_read_ci_status()
379 state->status = 0; netup_read_ci_status()
387 struct netup_ci_state *state = NULL; netup_ci_slot_status() local
396 state = port->port_priv; netup_ci_slot_status()
397 schedule_work(&state->work); netup_ci_slot_status()
403 state = port->port_priv; netup_ci_slot_status()
404 schedule_work(&state->work); netup_ci_slot_status()
414 struct netup_ci_state *state = en50221->data; netup_poll_ci_slot_status() local
422 return state->status; netup_poll_ci_slot_status()
427 struct netup_ci_state *state; netup_ci_init() local
467 state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL); netup_ci_init()
468 if (!state) { netup_ci_init()
474 port->port_priv = state; netup_ci_init()
478 state->ci_i2c_addr = 0x40; netup_ci_init()
481 state->ci_i2c_addr = 0x41; netup_ci_init()
485 state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap; netup_ci_init()
486 state->ca.owner = THIS_MODULE; netup_ci_init()
487 state->ca.read_attribute_mem = netup_ci_read_attribute_mem; netup_ci_init()
488 state->ca.write_attribute_mem = netup_ci_write_attribute_mem; netup_ci_init()
489 state->ca.read_cam_control = netup_ci_read_cam_ctl; netup_ci_init()
490 state->ca.write_cam_control = netup_ci_write_cam_ctl; netup_ci_init()
491 state->ca.slot_reset = netup_ci_slot_reset; netup_ci_init()
492 state->ca.slot_shutdown = netup_ci_slot_shutdown; netup_ci_init()
493 state->ca.slot_ts_enable = netup_ci_slot_ts_ctl; netup_ci_init()
494 state->ca.poll_slot_status = netup_poll_ci_slot_status; netup_ci_init()
495 state->ca.data = state; netup_ci_init()
496 state->priv = port; netup_ci_init()
497 state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM; netup_ci_init()
499 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_init()
502 ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_init()
505 ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr, netup_ci_init()
512 &state->ca, netup_ci_init()
518 INIT_WORK(&state->work, netup_read_ci_status); netup_ci_init()
519 schedule_work(&state->work); netup_ci_init()
526 kfree(state); netup_ci_init()
532 struct netup_ci_state *state; netup_ci_exit() local
537 state = (struct netup_ci_state *)port->port_priv; netup_ci_exit()
538 if (NULL == state) netup_ci_exit()
541 if (NULL == state->ca.data) netup_ci_exit()
544 dvb_ca_en50221_release(&state->ca); netup_ci_exit()
545 kfree(state); netup_ci_exit()
/linux-4.1.27/include/net/
H A Dllc_c_st.h14 /* Connection component state management */
18 #define LLC_CONN_STATE_ADM 1 /* disc, initial state */
19 #define LLC_CONN_STATE_SETUP 2 /* disconnected state */
20 #define LLC_CONN_STATE_NORMAL 3 /* connected state */
21 #define LLC_CONN_STATE_BUSY 4 /* connected state */
22 #define LLC_CONN_STATE_REJ 5 /* connected state */
23 #define LLC_CONN_STATE_AWAIT 6 /* connected state */
24 #define LLC_CONN_STATE_AWAIT_BUSY 7 /* connected state */
25 #define LLC_CONN_STATE_AWAIT_REJ 8 /* connected state */
26 #define LLC_CONN_STATE_D_CONN 9 /* disconnected state */
27 #define LLC_CONN_STATE_RESET 10 /* disconnected state */
28 #define LLC_CONN_STATE_ERROR 11 /* disconnected state */
29 #define LLC_CONN_STATE_TEMP 12 /* disconnected state */
31 #define NBR_CONN_STATES 12 /* size of state table */
34 /* Connection state table structure */
/linux-4.1.27/drivers/media/i2c/s5c73m3/
H A Ds5c73m3-core.c182 int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data) s5c73m3_write() argument
184 struct i2c_client *client = state->i2c_client; s5c73m3_write()
187 if ((addr ^ state->i2c_write_address) & 0xffff0000) { s5c73m3_write()
190 state->i2c_write_address = 0; s5c73m3_write()
195 if ((addr ^ state->i2c_write_address) & 0xffff) { s5c73m3_write()
198 state->i2c_write_address = 0; s5c73m3_write()
203 state->i2c_write_address = addr; s5c73m3_write()
209 state->i2c_write_address += 2; s5c73m3_write()
214 int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data) s5c73m3_read() argument
216 struct i2c_client *client = state->i2c_client; s5c73m3_read()
219 if ((addr ^ state->i2c_read_address) & 0xffff0000) { s5c73m3_read()
222 state->i2c_read_address = 0; s5c73m3_read()
227 if ((addr ^ state->i2c_read_address) & 0xffff) { s5c73m3_read()
230 state->i2c_read_address = 0; s5c73m3_read()
235 state->i2c_read_address = addr; s5c73m3_read()
241 state->i2c_read_address += 2; s5c73m3_read()
246 static int s5c73m3_check_status(struct s5c73m3 *state, unsigned int value) s5c73m3_check_status() argument
255 ret = s5c73m3_read(state, REG_STATUS, &status); s5c73m3_check_status()
263 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, s5c73m3_check_status()
271 s5c73m3_read(state, REG_I2C_STATUS, &i2c_status); s5c73m3_check_status()
272 s5c73m3_read(state, REG_I2C_SEQ_STATUS, &i2c_seq_status); s5c73m3_check_status()
274 v4l2_err(&state->sensor_sd, s5c73m3_check_status()
284 int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data) s5c73m3_isp_command() argument
288 ret = s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED); s5c73m3_isp_command()
292 ret = s5c73m3_write(state, 0x00095000, command); s5c73m3_isp_command()
296 ret = s5c73m3_write(state, 0x00095002, data); s5c73m3_isp_command()
300 return s5c73m3_write(state, REG_STATUS, 0x0001); s5c73m3_isp_command()
303 static int s5c73m3_isp_comm_result(struct s5c73m3 *state, u16 command, s5c73m3_isp_comm_result() argument
306 return s5c73m3_read(state, COMM_RESULT_OFFSET + command, data); s5c73m3_isp_comm_result()
309 static int s5c73m3_set_af_softlanding(struct s5c73m3 *state) s5c73m3_set_af_softlanding() argument
317 ret = s5c73m3_isp_command(state, COMM_AF_SOFTLANDING, s5c73m3_set_af_softlanding()
320 v4l2_info(&state->sensor_sd, "AF soft-landing failed\n"); s5c73m3_set_af_softlanding()
325 ret = s5c73m3_isp_comm_result(state, COMM_AF_SOFTLANDING, s5c73m3_set_af_softlanding()
343 v4l2_info(&state->sensor_sd, "AF soft-landing %s after %dms\n", s5c73m3_set_af_softlanding()
351 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); s5c73m3_load_fw() local
352 struct i2c_client *client = state->i2c_client; s5c73m3_load_fw()
358 state->fw_file_version); s5c73m3_load_fw()
367 ret = s5c73m3_spi_write(state, fw->data, fw->size, 64); s5c73m3_load_fw()
370 state->isp_ready = 1; s5c73m3_load_fw()
379 static int s5c73m3_set_frame_size(struct s5c73m3 *state) s5c73m3_set_frame_size() argument
382 state->sensor_pix_size[RES_ISP]; s5c73m3_set_frame_size()
384 state->sensor_pix_size[RES_JPEG]; s5c73m3_set_frame_size()
387 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, s5c73m3_set_frame_size()
393 if (state->mbus_code == S5C73M3_JPEG_FMT) { s5c73m3_set_frame_size()
394 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, s5c73m3_set_frame_size()
400 return s5c73m3_isp_command(state, COMM_CHG_MODE, chg_mode); s5c73m3_set_frame_size()
403 static int s5c73m3_set_frame_rate(struct s5c73m3 *state) s5c73m3_set_frame_rate() argument
407 if (state->ctrls.stabilization->val) s5c73m3_set_frame_rate()
410 if (WARN_ON(state->fiv == NULL)) s5c73m3_set_frame_rate()
413 ret = s5c73m3_isp_command(state, COMM_FRAME_RATE, state->fiv->fps_reg); s5c73m3_set_frame_rate()
415 state->apply_fiv = 0; s5c73m3_set_frame_rate()
420 static int __s5c73m3_s_stream(struct s5c73m3 *state, struct v4l2_subdev *sd, __s5c73m3_s_stream() argument
426 if (on && state->apply_fmt) { __s5c73m3_s_stream()
427 if (state->mbus_code == S5C73M3_JPEG_FMT) __s5c73m3_s_stream()
432 ret = s5c73m3_isp_command(state, COMM_IMG_OUTPUT, mode); __s5c73m3_s_stream()
434 ret = s5c73m3_set_frame_size(state); __s5c73m3_s_stream()
437 state->apply_fmt = 0; __s5c73m3_s_stream()
440 ret = s5c73m3_isp_command(state, COMM_SENSOR_STREAMING, !!on); __s5c73m3_s_stream()
444 state->streaming = !!on; __s5c73m3_s_stream()
449 if (state->apply_fiv) { __s5c73m3_s_stream()
450 ret = s5c73m3_set_frame_rate(state); __s5c73m3_s_stream()
455 return s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED); __s5c73m3_s_stream()
460 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_s_stream() local
463 mutex_lock(&state->lock); s5c73m3_oif_s_stream()
464 ret = __s5c73m3_s_stream(state, sd, on); s5c73m3_oif_s_stream()
465 mutex_unlock(&state->lock); s5c73m3_oif_s_stream()
470 static int s5c73m3_system_status_wait(struct s5c73m3 *state, u32 value, s5c73m3_system_status_wait() argument
476 int ret = s5c73m3_read(state, 0x30100010, &reg); s5c73m3_system_status_wait()
486 static int s5c73m3_read_fw_version(struct s5c73m3 *state) s5c73m3_read_fw_version() argument
488 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_read_fw_version()
493 offset = state->isp_ready ? 0x60 : 0; s5c73m3_read_fw_version()
496 ret = s5c73m3_read(state, offset + i * 2, data); s5c73m3_read_fw_version()
499 state->sensor_fw[i * 2] = (char)(*data & 0xff); s5c73m3_read_fw_version()
500 state->sensor_fw[i * 2 + 1] = (char)(*data >> 8); s5c73m3_read_fw_version()
502 state->sensor_fw[S5C73M3_SENSOR_FW_LEN] = '\0'; s5c73m3_read_fw_version()
506 ret = s5c73m3_read(state, offset + 6 + i * 2, data); s5c73m3_read_fw_version()
509 state->sensor_type[i * 2] = (char)(*data & 0xff); s5c73m3_read_fw_version()
510 state->sensor_type[i * 2 + 1] = (char)(*data >> 8); s5c73m3_read_fw_version()
512 state->sensor_type[S5C73M3_SENSOR_TYPE_LEN] = '\0'; s5c73m3_read_fw_version()
514 ret = s5c73m3_read(state, offset + 0x14, data); s5c73m3_read_fw_version()
516 ret = s5c73m3_read(state, offset + 0x16, data + 1); s5c73m3_read_fw_version()
518 state->fw_size = data[0] + (data[1] << 16); s5c73m3_read_fw_version()
522 state->sensor_type, state->sensor_fw); s5c73m3_read_fw_version()
526 static int s5c73m3_fw_update_from(struct s5c73m3 *state) s5c73m3_fw_update_from() argument
528 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_fw_update_from()
536 ret = s5c73m3_isp_command(state, COMM_FW_UPDATE, 0); s5c73m3_fw_update_from()
541 ret = s5c73m3_read(state, 0x00095906, &status); s5c73m3_fw_update_from()
560 static int s5c73m3_spi_boot(struct s5c73m3 *state, bool load_fw) s5c73m3_spi_boot() argument
562 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_spi_boot()
566 ret = s5c73m3_write(state, 0x30000004, 0xffff); s5c73m3_spi_boot()
573 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3); s5c73m3_spi_boot()
580 ret = s5c73m3_write(state, 0x30100014, 0x2146); s5c73m3_spi_boot()
584 ret = s5c73m3_write(state, 0x30100010, 0x210c); s5c73m3_spi_boot()
591 ret = s5c73m3_system_status_wait(state, 0x210d, 100, 300); s5c73m3_spi_boot()
600 ret = s5c73m3_write(state, 0x30000004, 0xfffd); s5c73m3_spi_boot()
605 ret = s5c73m3_write(state, 0x301000a4, 0x0183); s5c73m3_spi_boot()
610 ret = s5c73m3_write(state, 0x30000004, 0xffff); s5c73m3_spi_boot()
614 ret = s5c73m3_read_fw_version(state); s5c73m3_spi_boot()
619 ret = s5c73m3_fw_update_from(state); s5c73m3_spi_boot()
626 static int s5c73m3_set_timing_register_for_vdd(struct s5c73m3 *state) s5c73m3_set_timing_register_for_vdd() argument
637 ret = s5c73m3_write(state, regs[i][0], regs[i][1]); s5c73m3_set_timing_register_for_vdd()
645 static void s5c73m3_set_fw_file_version(struct s5c73m3 *state) s5c73m3_set_fw_file_version() argument
647 switch (state->sensor_fw[0]) { s5c73m3_set_fw_file_version()
650 state->fw_file_version[0] = 'G'; s5c73m3_set_fw_file_version()
654 state->fw_file_version[0] = 'Z'; s5c73m3_set_fw_file_version()
658 switch (state->sensor_fw[1]) { s5c73m3_set_fw_file_version()
660 state->fw_file_version[1] = state->sensor_fw[1]; s5c73m3_set_fw_file_version()
665 static int s5c73m3_get_fw_version(struct s5c73m3 *state) s5c73m3_get_fw_version() argument
667 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_get_fw_version()
671 ret = s5c73m3_write(state, 0x30000004, 0xffff); s5c73m3_get_fw_version()
677 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3); s5c73m3_get_fw_version()
685 ret = s5c73m3_write(state, 0x30100120, 0x0820); s5c73m3_get_fw_version()
686 ret = s5c73m3_write(state, 0x30100124, 0x0820); s5c73m3_get_fw_version()
689 ret = s5c73m3_write(state, 0x00010418, 0x0008); s5c73m3_get_fw_version()
692 ret = s5c73m3_write(state, 0x30100014, 0x2146); s5c73m3_get_fw_version()
695 ret = s5c73m3_write(state, 0x30100010, 0x230c); s5c73m3_get_fw_version()
702 ret = s5c73m3_system_status_wait(state, 0x230e, 100, 300); s5c73m3_get_fw_version()
707 ret = s5c73m3_write(state, 0x30000004, 0xfffd); s5c73m3_get_fw_version()
712 ret = s5c73m3_write(state, 0x301000a4, 0x0183); s5c73m3_get_fw_version()
716 s5c73m3_set_timing_register_for_vdd(state); s5c73m3_get_fw_version()
718 ret = s5c73m3_read_fw_version(state); s5c73m3_get_fw_version()
720 s5c73m3_set_fw_file_version(state); s5c73m3_get_fw_version()
725 static int s5c73m3_rom_boot(struct s5c73m3 *state, bool load_fw) s5c73m3_rom_boot() argument
737 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_rom_boot()
741 ret = s5c73m3_write(state, 0x30000004, 0xffff); s5c73m3_rom_boot()
747 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 4); s5c73m3_rom_boot()
754 ret = s5c73m3_write(state, boot_regs[i][0], boot_regs[i][1]); s5c73m3_rom_boot()
761 ret = s5c73m3_system_status_wait(state, 0x230e, 1000, 150); s5c73m3_rom_boot()
768 ret = s5c73m3_write(state, 0x30000004, 0xfffd); s5c73m3_rom_boot()
772 ret = s5c73m3_write(state, 0x301000a4, 0x0183); s5c73m3_rom_boot()
776 ret = s5c73m3_write(state, 0x30000004, 0xffff); s5c73m3_rom_boot()
780 state->isp_ready = 1; s5c73m3_rom_boot()
782 return s5c73m3_read_fw_version(state); s5c73m3_rom_boot()
785 static int s5c73m3_isp_init(struct s5c73m3 *state) s5c73m3_isp_init() argument
789 state->i2c_read_address = 0; s5c73m3_isp_init()
790 state->i2c_write_address = 0; s5c73m3_isp_init()
792 ret = s5c73m3_i2c_write(state->i2c_client, AHB_MSB_ADDR_PTR, 0x3310); s5c73m3_isp_init()
797 return s5c73m3_rom_boot(state, true); s5c73m3_isp_init()
799 return s5c73m3_spi_boot(state, true); s5c73m3_isp_init()
826 static void s5c73m3_oif_try_format(struct s5c73m3 *state, s5c73m3_oif_try_format() argument
831 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_oif_try_format()
851 *fs = state->oif_pix_size[RES_ISP]; s5c73m3_oif_try_format()
863 static void s5c73m3_try_format(struct s5c73m3 *state, s5c73m3_try_format() argument
884 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_g_frame_interval() local
889 mutex_lock(&state->lock); s5c73m3_oif_g_frame_interval()
890 fi->interval = state->fiv->interval; s5c73m3_oif_g_frame_interval()
891 mutex_unlock(&state->lock); s5c73m3_oif_g_frame_interval()
896 static int __s5c73m3_set_frame_interval(struct s5c73m3 *state, __s5c73m3_set_frame_interval() argument
900 state->sensor_pix_size[RES_ISP]; __s5c73m3_set_frame_interval()
923 state->fiv = fiv; __s5c73m3_set_frame_interval()
925 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, __s5c73m3_set_frame_interval()
933 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_s_frame_interval() local
942 mutex_lock(&state->lock); s5c73m3_oif_s_frame_interval()
944 ret = __s5c73m3_set_frame_interval(state, fi); s5c73m3_oif_s_frame_interval()
946 if (state->streaming) s5c73m3_oif_s_frame_interval()
947 ret = s5c73m3_set_frame_rate(state); s5c73m3_oif_s_frame_interval()
949 state->apply_fiv = 1; s5c73m3_oif_s_frame_interval()
951 mutex_unlock(&state->lock); s5c73m3_oif_s_frame_interval()
959 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_enum_frame_interval() local
968 mutex_lock(&state->lock); s5c73m3_oif_enum_frame_interval()
974 mutex_unlock(&state->lock); s5c73m3_oif_enum_frame_interval()
997 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); s5c73m3_get_fmt() local
1006 mutex_lock(&state->lock); s5c73m3_get_fmt()
1011 fs = state->sensor_pix_size[RES_ISP]; s5c73m3_get_fmt()
1015 fs = state->sensor_pix_size[RES_JPEG]; s5c73m3_get_fmt()
1018 mutex_unlock(&state->lock); s5c73m3_get_fmt()
1023 mutex_unlock(&state->lock); s5c73m3_get_fmt()
1031 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_get_fmt() local
1040 mutex_lock(&state->lock); s5c73m3_oif_get_fmt()
1045 fs = state->oif_pix_size[RES_ISP]; s5c73m3_oif_get_fmt()
1049 fs = state->oif_pix_size[RES_JPEG]; s5c73m3_oif_get_fmt()
1052 code = state->mbus_code; s5c73m3_oif_get_fmt()
1053 fs = state->oif_pix_size[RES_ISP]; s5c73m3_oif_get_fmt()
1056 mutex_unlock(&state->lock); s5c73m3_oif_get_fmt()
1061 mutex_unlock(&state->lock); s5c73m3_oif_get_fmt()
1070 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); s5c73m3_set_fmt() local
1074 mutex_lock(&state->lock); s5c73m3_set_fmt()
1076 s5c73m3_try_format(state, cfg, fmt, &frame_size); s5c73m3_set_fmt()
1084 state->sensor_pix_size[RES_ISP] = frame_size; s5c73m3_set_fmt()
1087 state->sensor_pix_size[RES_JPEG] = frame_size; s5c73m3_set_fmt()
1093 if (state->streaming) s5c73m3_set_fmt()
1096 state->apply_fmt = 1; s5c73m3_set_fmt()
1099 mutex_unlock(&state->lock); s5c73m3_set_fmt()
1109 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_set_fmt() local
1113 mutex_lock(&state->lock); s5c73m3_oif_set_fmt()
1115 s5c73m3_oif_try_format(state, cfg, fmt, &frame_size); s5c73m3_oif_set_fmt()
1128 state->oif_pix_size[RES_ISP] = frame_size; s5c73m3_oif_set_fmt()
1131 state->oif_pix_size[RES_JPEG] = frame_size; s5c73m3_oif_set_fmt()
1134 state->mbus_code = fmt->format.code; s5c73m3_oif_set_fmt()
1140 if (state->streaming) s5c73m3_oif_set_fmt()
1143 state->apply_fmt = 1; s5c73m3_oif_set_fmt()
1146 mutex_unlock(&state->lock); s5c73m3_oif_set_fmt()
1154 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_get_frame_desc() local
1160 mutex_lock(&state->lock); s5c73m3_oif_get_frame_desc()
1163 fd->entry[i] = state->frame_desc.entry[i]; s5c73m3_oif_get_frame_desc()
1164 mutex_unlock(&state->lock); s5c73m3_oif_get_frame_desc()
1172 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_set_frame_desc() local
1173 struct v4l2_mbus_frame_desc *frame_desc = &state->frame_desc; s5c73m3_oif_set_frame_desc()
1184 mutex_lock(&state->lock); s5c73m3_oif_set_frame_desc()
1187 mutex_unlock(&state->lock); s5c73m3_oif_set_frame_desc()
1254 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_enum_frame_size() local
1277 fs = state->oif_pix_size[RES_ISP]; s5c73m3_oif_enum_frame_size()
1311 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_log_status() local
1315 v4l2_info(sd, "power: %d, apply_fmt: %d\n", state->power, s5c73m3_oif_log_status()
1316 state->apply_fmt); s5c73m3_oif_log_status()
1372 static int __s5c73m3_power_on(struct s5c73m3 *state) __s5c73m3_power_on() argument
1377 ret = regulator_enable(state->supplies[i].consumer); __s5c73m3_power_on()
1382 ret = clk_set_rate(state->clock, state->mclk_frequency); __s5c73m3_power_on()
1386 ret = clk_prepare_enable(state->clock); __s5c73m3_power_on()
1390 v4l2_dbg(1, s5c73m3_dbg, &state->oif_sd, "clock frequency: %ld\n", __s5c73m3_power_on()
1391 clk_get_rate(state->clock)); __s5c73m3_power_on()
1393 s5c73m3_gpio_deassert(state, STBY); __s5c73m3_power_on()
1396 s5c73m3_gpio_deassert(state, RST); __s5c73m3_power_on()
1403 regulator_disable(state->supplies[i].consumer); __s5c73m3_power_on()
1407 static int __s5c73m3_power_off(struct s5c73m3 *state) __s5c73m3_power_off() argument
1411 if (s5c73m3_gpio_assert(state, RST)) __s5c73m3_power_off()
1414 if (s5c73m3_gpio_assert(state, STBY)) __s5c73m3_power_off()
1417 clk_disable_unprepare(state->clock); __s5c73m3_power_off()
1419 state->streaming = 0; __s5c73m3_power_off()
1420 state->isp_ready = 0; __s5c73m3_power_off()
1423 ret = regulator_disable(state->supplies[i].consumer); __s5c73m3_power_off()
1431 int r = regulator_enable(state->supplies[i].consumer); __s5c73m3_power_off()
1433 v4l2_err(&state->oif_sd, "Failed to reenable %s: %d\n", __s5c73m3_power_off()
1434 state->supplies[i].supply, r); __s5c73m3_power_off()
1437 clk_prepare_enable(state->clock); __s5c73m3_power_off()
1443 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_set_power() local
1446 mutex_lock(&state->lock); s5c73m3_oif_set_power()
1448 if (on && !state->power) { s5c73m3_oif_set_power()
1449 ret = __s5c73m3_power_on(state); s5c73m3_oif_set_power()
1451 ret = s5c73m3_isp_init(state); s5c73m3_oif_set_power()
1453 state->apply_fiv = 1; s5c73m3_oif_set_power()
1454 state->apply_fmt = 1; s5c73m3_oif_set_power()
1456 } else if (!on == state->power) { s5c73m3_oif_set_power()
1457 ret = s5c73m3_set_af_softlanding(state); s5c73m3_oif_set_power()
1459 ret = __s5c73m3_power_off(state); s5c73m3_oif_set_power()
1464 state->power += on ? 1 : -1; s5c73m3_oif_set_power()
1467 __func__, state->power); s5c73m3_oif_set_power()
1469 mutex_unlock(&state->lock); s5c73m3_oif_set_power()
1475 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_registered() local
1478 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->sensor_sd); s5c73m3_oif_registered()
1481 state->oif_sd.name); s5c73m3_oif_registered()
1485 ret = media_entity_create_link(&state->sensor_sd.entity, s5c73m3_oif_registered()
1486 S5C73M3_ISP_PAD, &state->oif_sd.entity, OIF_ISP_PAD, s5c73m3_oif_registered()
1489 ret = media_entity_create_link(&state->sensor_sd.entity, s5c73m3_oif_registered()
1490 S5C73M3_JPEG_PAD, &state->oif_sd.entity, OIF_JPEG_PAD, s5c73m3_oif_registered()
1498 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); s5c73m3_oif_unregistered() local
1499 v4l2_device_unregister_subdev(&state->sensor_sd); s5c73m3_oif_unregistered()
1550 static int s5c73m3_configure_gpios(struct s5c73m3 *state) s5c73m3_configure_gpios() argument
1555 struct i2c_client *c = state->i2c_client; s5c73m3_configure_gpios()
1556 struct s5c73m3_gpio *g = state->gpio; s5c73m3_configure_gpios()
1574 static int s5c73m3_parse_gpios(struct s5c73m3 *state) s5c73m3_parse_gpios() argument
1579 struct device *dev = &state->i2c_client->dev; s5c73m3_parse_gpios()
1593 state->gpio[i].gpio = ret; s5c73m3_parse_gpios()
1594 state->gpio[i].level = !(of_flags & OF_GPIO_ACTIVE_LOW); s5c73m3_parse_gpios()
1599 static int s5c73m3_get_platform_data(struct s5c73m3 *state) s5c73m3_get_platform_data() argument
1601 struct device *dev = &state->i2c_client->dev; s5c73m3_get_platform_data()
1614 state->mclk_frequency = pdata->mclk_frequency; s5c73m3_get_platform_data()
1615 state->gpio[STBY] = pdata->gpio_stby; s5c73m3_get_platform_data()
1616 state->gpio[RST] = pdata->gpio_reset; s5c73m3_get_platform_data()
1620 state->clock = devm_clk_get(dev, S5C73M3_CLK_NAME); s5c73m3_get_platform_data()
1621 if (IS_ERR(state->clock)) s5c73m3_get_platform_data()
1622 return PTR_ERR(state->clock); s5c73m3_get_platform_data()
1625 &state->mclk_frequency)) { s5c73m3_get_platform_data()
1626 state->mclk_frequency = S5C73M3_DEFAULT_MCLK_FREQ; s5c73m3_get_platform_data()
1628 state->mclk_frequency); s5c73m3_get_platform_data()
1631 ret = s5c73m3_parse_gpios(state); s5c73m3_get_platform_data()
1665 struct s5c73m3 *state; s5c73m3_probe() local
1668 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); s5c73m3_probe()
1669 if (!state) s5c73m3_probe()
1672 state->i2c_client = client; s5c73m3_probe()
1673 ret = s5c73m3_get_platform_data(state); s5c73m3_probe()
1677 mutex_init(&state->lock); s5c73m3_probe()
1678 sd = &state->sensor_sd; s5c73m3_probe()
1679 oif_sd = &state->oif_sd; s5c73m3_probe()
1683 v4l2_set_subdevdata(sd, state); s5c73m3_probe()
1689 state->sensor_pads[S5C73M3_JPEG_PAD].flags = MEDIA_PAD_FL_SOURCE; s5c73m3_probe()
1690 state->sensor_pads[S5C73M3_ISP_PAD].flags = MEDIA_PAD_FL_SOURCE; s5c73m3_probe()
1694 state->sensor_pads, 0); s5c73m3_probe()
1704 state->oif_pads[OIF_ISP_PAD].flags = MEDIA_PAD_FL_SINK; s5c73m3_probe()
1705 state->oif_pads[OIF_JPEG_PAD].flags = MEDIA_PAD_FL_SINK; s5c73m3_probe()
1706 state->oif_pads[OIF_SOURCE_PAD].flags = MEDIA_PAD_FL_SOURCE; s5c73m3_probe()
1710 state->oif_pads, 0); s5c73m3_probe()
1714 ret = s5c73m3_configure_gpios(state); s5c73m3_probe()
1719 state->supplies[i].supply = s5c73m3_supply_names[i]; s5c73m3_probe()
1722 state->supplies); s5c73m3_probe()
1728 ret = s5c73m3_init_controls(state); s5c73m3_probe()
1732 state->sensor_pix_size[RES_ISP] = &s5c73m3_isp_resolutions[1]; s5c73m3_probe()
1733 state->sensor_pix_size[RES_JPEG] = &s5c73m3_jpeg_resolutions[1]; s5c73m3_probe()
1734 state->oif_pix_size[RES_ISP] = state->sensor_pix_size[RES_ISP]; s5c73m3_probe()
1735 state->oif_pix_size[RES_JPEG] = state->sensor_pix_size[RES_JPEG]; s5c73m3_probe()
1737 state->mbus_code = S5C73M3_ISP_FMT; s5c73m3_probe()
1739 state->fiv = &s5c73m3_intervals[S5C73M3_DEFAULT_FRAME_INTERVAL]; s5c73m3_probe()
1741 state->fw_file_version[0] = 'G'; s5c73m3_probe()
1742 state->fw_file_version[1] = 'C'; s5c73m3_probe()
1744 ret = s5c73m3_register_spi_driver(state); s5c73m3_probe()
1750 ret = __s5c73m3_power_on(state); s5c73m3_probe()
1754 ret = s5c73m3_get_fw_version(state); s5c73m3_probe()
1755 __s5c73m3_power_off(state); s5c73m3_probe()
1770 s5c73m3_unregister_spi_driver(state); s5c73m3_probe()
1779 struct s5c73m3 *state = oif_sd_to_s5c73m3(oif_sd); s5c73m3_remove() local
1780 struct v4l2_subdev *sensor_sd = &state->sensor_sd; s5c73m3_remove()
1790 s5c73m3_unregister_spi_driver(state); s5c73m3_remove()
H A Ds5c73m3-ctrls.c39 static int s5c73m3_get_af_status(struct s5c73m3 *state, struct v4l2_ctrl *ctrl) s5c73m3_get_af_status() argument
43 int ret = s5c73m3_read(state, REG_AF_STATUS, &reg); s5c73m3_get_af_status()
56 v4l2_info(&state->sensor_sd, "Unknown AF status %#x\n", reg); s5c73m3_get_af_status()
71 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); s5c73m3_g_volatile_ctrl() local
74 if (state->power == 0) s5c73m3_g_volatile_ctrl()
79 ret = s5c73m3_get_af_status(state, state->ctrls.af_status); s5c73m3_g_volatile_ctrl()
88 static int s5c73m3_set_colorfx(struct s5c73m3 *state, int val) s5c73m3_set_colorfx() argument
103 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, s5c73m3_set_colorfx()
105 v4l2_ctrl_get_menu(state->ctrls.colorfx->id)[i]); s5c73m3_set_colorfx()
107 return s5c73m3_isp_command(state, COMM_IMAGE_EFFECT, s5c73m3_set_colorfx()
114 static int s5c73m3_set_exposure(struct s5c73m3 *state, int auto_exp) s5c73m3_set_exposure() argument
116 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_set_exposure()
117 struct s5c73m3_ctrls *ctrls = &state->ctrls; s5c73m3_set_exposure()
135 ret = s5c73m3_isp_command(state, COMM_METERING, metering); s5c73m3_set_exposure()
140 ret = s5c73m3_isp_command(state, COMM_EV, exp_bias); s5c73m3_set_exposure()
150 static int s5c73m3_set_white_balance(struct s5c73m3 *state, int val) s5c73m3_set_white_balance() argument
166 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, s5c73m3_set_white_balance()
168 v4l2_ctrl_get_menu(state->ctrls.auto_wb->id)[i]); s5c73m3_set_white_balance()
170 return s5c73m3_isp_command(state, COMM_AWB_MODE, wb[i][1]); s5c73m3_set_white_balance()
176 static int s5c73m3_af_run(struct s5c73m3 *state, bool on) s5c73m3_af_run() argument
178 struct s5c73m3_ctrls *c = &state->ctrls; s5c73m3_af_run()
181 return s5c73m3_isp_command(state, COMM_AF_CON, s5c73m3_af_run()
185 return s5c73m3_isp_command(state, COMM_AF_MODE, s5c73m3_af_run()
188 return s5c73m3_isp_command(state, COMM_AF_CON, COMM_AF_CON_START); s5c73m3_af_run()
191 static int s5c73m3_3a_lock(struct s5c73m3 *state, struct v4l2_ctrl *ctrl) s5c73m3_3a_lock() argument
199 ret = s5c73m3_isp_command(state, COMM_AE_CON, s5c73m3_3a_lock()
206 && state->ctrls.auto_wb->val) { s5c73m3_3a_lock()
207 ret = s5c73m3_isp_command(state, COMM_AWB_CON, s5c73m3_3a_lock()
214 ret = s5c73m3_af_run(state, ~af_lock); s5c73m3_3a_lock()
219 static int s5c73m3_set_auto_focus(struct s5c73m3 *state, int caf) s5c73m3_set_auto_focus() argument
221 struct s5c73m3_ctrls *c = &state->ctrls; s5c73m3_set_auto_focus()
227 ret = s5c73m3_isp_command(state, COMM_AF_MODE, mode); s5c73m3_set_auto_focus()
234 ret = s5c73m3_af_run(state, 1); s5c73m3_set_auto_focus()
237 ret = s5c73m3_af_run(state, 0); s5c73m3_set_auto_focus()
244 static int s5c73m3_set_contrast(struct s5c73m3 *state, int val) s5c73m3_set_contrast() argument
247 return s5c73m3_isp_command(state, COMM_CONTRAST, reg); s5c73m3_set_contrast()
250 static int s5c73m3_set_saturation(struct s5c73m3 *state, int val) s5c73m3_set_saturation() argument
253 return s5c73m3_isp_command(state, COMM_SATURATION, reg); s5c73m3_set_saturation()
256 static int s5c73m3_set_sharpness(struct s5c73m3 *state, int val) s5c73m3_set_sharpness() argument
259 return s5c73m3_isp_command(state, COMM_SHARPNESS, reg); s5c73m3_set_sharpness()
262 static int s5c73m3_set_iso(struct s5c73m3 *state, int val) s5c73m3_set_iso() argument
267 iso = state->ctrls.iso->val + 1; s5c73m3_set_iso()
271 return s5c73m3_isp_command(state, COMM_ISO, iso); s5c73m3_set_iso()
274 static int s5c73m3_set_stabilization(struct s5c73m3 *state, int val) s5c73m3_set_stabilization() argument
276 struct v4l2_subdev *sd = &state->sensor_sd; s5c73m3_set_stabilization()
280 return s5c73m3_isp_command(state, COMM_FRAME_RATE, val ? s5c73m3_set_stabilization()
284 static int s5c73m3_set_jpeg_quality(struct s5c73m3 *state, int quality) s5c73m3_set_jpeg_quality() argument
295 return s5c73m3_isp_command(state, COMM_IMAGE_QUALITY, reg); s5c73m3_set_jpeg_quality()
298 static int s5c73m3_set_scene_program(struct s5c73m3 *state, int val) s5c73m3_set_scene_program() argument
317 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, "Setting %s scene mode\n", s5c73m3_set_scene_program()
318 v4l2_ctrl_get_menu(state->ctrls.scene_mode->id)[val]); s5c73m3_set_scene_program()
320 return s5c73m3_isp_command(state, COMM_SCENE_MODE, scene_lookup[val]); s5c73m3_set_scene_program()
323 static int s5c73m3_set_power_line_freq(struct s5c73m3 *state, int val) s5c73m3_set_power_line_freq() argument
342 return s5c73m3_isp_command(state, COMM_FLICKER_MODE, pwr_line_freq); s5c73m3_set_power_line_freq()
348 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); s5c73m3_s_ctrl() local
354 mutex_lock(&state->lock); s5c73m3_s_ctrl()
360 if (state->power == 0) s5c73m3_s_ctrl()
370 ret = s5c73m3_3a_lock(state, ctrl); s5c73m3_s_ctrl()
374 ret = s5c73m3_set_white_balance(state, ctrl->val); s5c73m3_s_ctrl()
378 ret = s5c73m3_set_contrast(state, ctrl->val); s5c73m3_s_ctrl()
382 ret = s5c73m3_set_colorfx(state, ctrl->val); s5c73m3_s_ctrl()
386 ret = s5c73m3_set_exposure(state, ctrl->val); s5c73m3_s_ctrl()
390 ret = s5c73m3_set_auto_focus(state, ctrl->val); s5c73m3_s_ctrl()
394 ret = s5c73m3_set_stabilization(state, ctrl->val); s5c73m3_s_ctrl()
398 ret = s5c73m3_set_iso(state, ctrl->val); s5c73m3_s_ctrl()
402 ret = s5c73m3_set_jpeg_quality(state, ctrl->val); s5c73m3_s_ctrl()
406 ret = s5c73m3_set_power_line_freq(state, ctrl->val); s5c73m3_s_ctrl()
410 ret = s5c73m3_set_saturation(state, ctrl->val); s5c73m3_s_ctrl()
414 ret = s5c73m3_set_scene_program(state, ctrl->val); s5c73m3_s_ctrl()
418 ret = s5c73m3_set_sharpness(state, ctrl->val); s5c73m3_s_ctrl()
422 ret = s5c73m3_isp_command(state, COMM_WDR, !!ctrl->val); s5c73m3_s_ctrl()
426 ret = s5c73m3_isp_command(state, COMM_ZOOM_STEP, ctrl->val); s5c73m3_s_ctrl()
430 mutex_unlock(&state->lock); s5c73m3_s_ctrl()
451 int s5c73m3_init_controls(struct s5c73m3 *state) s5c73m3_init_controls() argument
454 struct s5c73m3_ctrls *ctrls = &state->ctrls; s5c73m3_init_controls()
560 state->sensor_sd.ctrl_handler = hdl; s5c73m3_init_controls()
/linux-4.1.27/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf-demod.c45 static int mxl111sf_demod_read_reg(struct mxl111sf_demod_state *state, mxl111sf_demod_read_reg() argument
48 return (state->cfg->read_reg) ? mxl111sf_demod_read_reg()
49 state->cfg->read_reg(state->mxl_state, addr, data) : mxl111sf_demod_read_reg()
53 static int mxl111sf_demod_write_reg(struct mxl111sf_demod_state *state, mxl111sf_demod_write_reg() argument
56 return (state->cfg->write_reg) ? mxl111sf_demod_write_reg()
57 state->cfg->write_reg(state->mxl_state, addr, data) : mxl111sf_demod_write_reg()
62 int mxl111sf_demod_program_regs(struct mxl111sf_demod_state *state, mxl111sf_demod_program_regs() argument
65 return (state->cfg->program_regs) ? mxl111sf_demod_program_regs()
66 state->cfg->program_regs(state->mxl_state, ctrl_reg_info) : mxl111sf_demod_program_regs()
74 int mxl1x1sf_demod_get_tps_code_rate(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_tps_code_rate() argument
78 int ret = mxl111sf_demod_read_reg(state, V6_CODE_RATE_TPS_REG, &val); mxl1x1sf_demod_get_tps_code_rate()
105 int mxl1x1sf_demod_get_tps_modulation(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_tps_modulation() argument
109 int ret = mxl111sf_demod_read_reg(state, V6_MODORDER_TPS_REG, &val); mxl1x1sf_demod_get_tps_modulation()
130 int mxl1x1sf_demod_get_tps_guard_fft_mode(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_tps_guard_fft_mode() argument
134 int ret = mxl111sf_demod_read_reg(state, V6_MODE_TPS_REG, &val); mxl1x1sf_demod_get_tps_guard_fft_mode()
155 int mxl1x1sf_demod_get_tps_guard_interval(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_tps_guard_interval() argument
159 int ret = mxl111sf_demod_read_reg(state, V6_CP_TPS_REG, &val); mxl1x1sf_demod_get_tps_guard_interval()
183 int mxl1x1sf_demod_get_tps_hierarchy(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_tps_hierarchy() argument
187 int ret = mxl111sf_demod_read_reg(state, V6_TPS_HIERACHY_REG, &val); mxl1x1sf_demod_get_tps_hierarchy()
214 int mxl1x1sf_demod_get_sync_lock_status(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_sync_lock_status() argument
218 int ret = mxl111sf_demod_read_reg(state, V6_SYNC_LOCK_REG, &val); mxl1x1sf_demod_get_sync_lock_status()
227 int mxl1x1sf_demod_get_rs_lock_status(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_rs_lock_status() argument
231 int ret = mxl111sf_demod_read_reg(state, V6_RS_LOCK_DET_REG, &val); mxl1x1sf_demod_get_rs_lock_status()
240 int mxl1x1sf_demod_get_tps_lock_status(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_tps_lock_status() argument
244 int ret = mxl111sf_demod_read_reg(state, V6_TPS_LOCK_REG, &val); mxl1x1sf_demod_get_tps_lock_status()
253 int mxl1x1sf_demod_get_fec_lock_status(struct mxl111sf_demod_state *state, mxl1x1sf_demod_get_fec_lock_status() argument
257 int ret = mxl111sf_demod_read_reg(state, V6_IRQ_STATUS_REG, &val); mxl1x1sf_demod_get_fec_lock_status()
267 int mxl1x1sf_demod_get_cp_lock_status(struct mxl111sf_demod_state *state,
271 int ret = mxl111sf_demod_read_reg(state, V6_CP_LOCK_DET_REG, &val);
280 static int mxl1x1sf_demod_reset_irq_status(struct mxl111sf_demod_state *state) mxl1x1sf_demod_reset_irq_status() argument
282 return mxl111sf_demod_write_reg(state, 0x0e, 0xff); mxl1x1sf_demod_reset_irq_status()
289 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_set_frontend() local
310 ret = mxl111sf_demod_program_regs(state, phy_pll_patch); mxl111sf_demod_set_frontend()
313 ret = mxl1x1sf_demod_reset_irq_status(state); mxl111sf_demod_set_frontend()
326 int mxl1x1sf_demod_reset_packet_error_count(struct mxl111sf_demod_state *state)
333 return mxl111sf_demod_program_regs(state, reset_per_count);
341 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_read_ucblocks() local
349 ret = mxl111sf_demod_read_reg(state, V6_FEC_PER_COUNT_REG, &val); mxl111sf_demod_read_ucblocks()
356 ret = mxl111sf_demod_read_reg(state, V6_FEC_PER_SCALE_REG, &val); mxl111sf_demod_read_ucblocks()
389 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_read_ber() local
395 ret = mxl111sf_demod_read_reg(state, V6_RS_AVG_ERRORS_LSB_REG, &val1); mxl111sf_demod_read_ber()
398 ret = mxl111sf_demod_read_reg(state, V6_RS_AVG_ERRORS_MSB_REG, &val2); mxl111sf_demod_read_ber()
401 ret = mxl111sf_demod_read_reg(state, V6_N_ACCUMULATE_REG, &val3); mxl111sf_demod_read_ber()
410 static int mxl111sf_demod_calc_snr(struct mxl111sf_demod_state *state, mxl111sf_demod_calc_snr() argument
418 ret = mxl111sf_demod_read_reg(state, V6_SNR_RB_LSB_REG, &val1); mxl111sf_demod_calc_snr()
421 ret = mxl111sf_demod_read_reg(state, V6_SNR_RB_MSB_REG, &val2); mxl111sf_demod_calc_snr()
432 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_read_snr() local
434 int ret = mxl111sf_demod_calc_snr(state, snr); mxl111sf_demod_read_snr()
446 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_read_status() local
451 ret = mxl1x1sf_demod_get_rs_lock_status(state, &locked); mxl111sf_demod_read_status()
454 ret = mxl1x1sf_demod_get_tps_lock_status(state, &cr_lock); mxl111sf_demod_read_status()
457 ret = mxl1x1sf_demod_get_sync_lock_status(state, &sync_lock); mxl111sf_demod_read_status()
460 ret = mxl1x1sf_demod_get_fec_lock_status(state, &fec_lock); mxl111sf_demod_read_status()
482 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_read_signal_strength() local
486 mxl111sf_demod_calc_snr(state, &snr); mxl111sf_demod_read_signal_strength()
487 mxl1x1sf_demod_get_tps_modulation(state, &modulation); mxl111sf_demod_read_signal_strength()
513 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_get_frontend() local
523 mxl1x1sf_demod_get_tps_code_rate(state, &p->code_rate_HP); mxl111sf_demod_get_frontend()
524 mxl1x1sf_demod_get_tps_code_rate(state, &p->code_rate_LP); mxl111sf_demod_get_frontend()
525 mxl1x1sf_demod_get_tps_modulation(state, &p->modulation); mxl111sf_demod_get_frontend()
526 mxl1x1sf_demod_get_tps_guard_fft_mode(state, mxl111sf_demod_get_frontend()
528 mxl1x1sf_demod_get_tps_guard_interval(state, mxl111sf_demod_get_frontend()
530 mxl1x1sf_demod_get_tps_hierarchy(state, mxl111sf_demod_get_frontend()
546 struct mxl111sf_demod_state *state = fe->demodulator_priv; mxl111sf_demod_release() local
548 kfree(state); mxl111sf_demod_release()
584 struct mxl111sf_demod_state *state = NULL; mxl111sf_demod_attach() local
588 state = kzalloc(sizeof(struct mxl111sf_demod_state), GFP_KERNEL); mxl111sf_demod_attach()
589 if (state == NULL) mxl111sf_demod_attach()
592 state->mxl_state = mxl_state; mxl111sf_demod_attach()
593 state->cfg = cfg; mxl111sf_demod_attach()
595 memcpy(&state->fe.ops, &mxl111sf_demod_ops, mxl111sf_demod_attach()
598 state->fe.demodulator_priv = state; mxl111sf_demod_attach()
599 return &state->fe; mxl111sf_demod_attach()
H A Dmxl111sf-tuner.c47 static int mxl111sf_tuner_read_reg(struct mxl111sf_tuner_state *state, mxl111sf_tuner_read_reg() argument
50 return (state->cfg->read_reg) ? mxl111sf_tuner_read_reg()
51 state->cfg->read_reg(state->mxl_state, addr, data) : mxl111sf_tuner_read_reg()
55 static int mxl111sf_tuner_write_reg(struct mxl111sf_tuner_state *state, mxl111sf_tuner_write_reg() argument
58 return (state->cfg->write_reg) ? mxl111sf_tuner_write_reg()
59 state->cfg->write_reg(state->mxl_state, addr, data) : mxl111sf_tuner_write_reg()
63 static int mxl111sf_tuner_program_regs(struct mxl111sf_tuner_state *state, mxl111sf_tuner_program_regs() argument
66 return (state->cfg->program_regs) ? mxl111sf_tuner_program_regs()
67 state->cfg->program_regs(state->mxl_state, ctrl_reg_info) : mxl111sf_tuner_program_regs()
71 static int mxl1x1sf_tuner_top_master_ctrl(struct mxl111sf_tuner_state *state, mxl1x1sf_tuner_top_master_ctrl() argument
74 return (state->cfg->top_master_ctrl) ? mxl1x1sf_tuner_top_master_ctrl()
75 state->cfg->top_master_ctrl(state->mxl_state, onoff) : mxl1x1sf_tuner_top_master_ctrl()
137 static int mxl1x1sf_tuner_set_if_output_freq(struct mxl111sf_tuner_state *state) mxl1x1sf_tuner_set_if_output_freq() argument
146 state->cfg->invert_spectrum, state->cfg->if_freq); mxl1x1sf_tuner_set_if_output_freq()
149 ctrl = state->cfg->invert_spectrum; mxl1x1sf_tuner_set_if_output_freq()
151 ctrl |= state->cfg->if_freq; mxl1x1sf_tuner_set_if_output_freq()
153 ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_SEL_REG, ctrl); mxl1x1sf_tuner_set_if_output_freq()
163 if (MXL_IF_LO == state->cfg->if_freq) { mxl1x1sf_tuner_set_if_output_freq()
166 } else if (MXL_IF_HI == state->cfg->if_freq) { mxl1x1sf_tuner_set_if_output_freq()
176 ret = mxl111sf_tuner_read_reg(state, V6_TUNER_IF_FCW_BYP_REG, &ctrl); mxl1x1sf_tuner_set_if_output_freq()
183 ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_BYP_REG, ctrl); mxl1x1sf_tuner_set_if_output_freq()
190 ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_REG, ctrl); mxl1x1sf_tuner_set_if_output_freq()
194 state->if_freq = state->cfg->if_freq; mxl1x1sf_tuner_set_if_output_freq()
201 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl1x1sf_tune_rf() local
209 ret = mxl111sf_tuner_write_reg(state, START_TUNE_REG, 0); mxl1x1sf_tune_rf()
214 ret = mxl111sf_tuner_read_reg(state, MXL_MODE_REG, &mxl_mode); mxl1x1sf_tune_rf()
223 ret = mxl111sf_tuner_program_regs(state, reg_ctrl_array); mxl1x1sf_tune_rf()
229 mxl1x1sf_tuner_top_master_ctrl(state, 0); mxl1x1sf_tune_rf()
230 mxl1x1sf_tuner_top_master_ctrl(state, 1); mxl1x1sf_tune_rf()
231 mxl1x1sf_tuner_set_if_output_freq(state); mxl1x1sf_tune_rf()
234 ret = mxl111sf_tuner_write_reg(state, START_TUNE_REG, 1); mxl1x1sf_tune_rf()
238 if (state->cfg->ant_hunt) mxl1x1sf_tune_rf()
239 state->cfg->ant_hunt(fe); mxl1x1sf_tune_rf()
244 static int mxl1x1sf_tuner_get_lock_status(struct mxl111sf_tuner_state *state, mxl1x1sf_tuner_get_lock_status() argument
254 ret = mxl111sf_tuner_read_reg(state, V6_RF_LOCK_STATUS_REG, &data); mxl1x1sf_tuner_get_lock_status()
265 static int mxl1x1sf_tuner_loop_thru_ctrl(struct mxl111sf_tuner_state *state,
268 return mxl111sf_tuner_write_reg(state, V6_TUNER_LOOP_THRU_CTRL_REG,
279 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl111sf_tuner_set_params() local
317 state->frequency = c->frequency; mxl111sf_tuner_set_params()
318 state->bandwidth = c->bandwidth_hz; mxl111sf_tuner_set_params()
328 struct mxl111sf_tuner_state *state = fe->tuner_priv;
338 struct mxl111sf_tuner_state *state = fe->tuner_priv;
351 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl111sf_tuner_get_status() local
356 ret = mxl1x1sf_tuner_get_lock_status(state, &rf_locked, &ref_locked); mxl111sf_tuner_get_status()
370 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl111sf_get_rf_strength() local
376 ret = mxl111sf_tuner_write_reg(state, 0x00, 0x02); mxl111sf_get_rf_strength()
379 ret = mxl111sf_tuner_read_reg(state, V6_DIG_RF_PWR_LSB_REG, &val1); mxl111sf_get_rf_strength()
382 ret = mxl111sf_tuner_read_reg(state, V6_DIG_RF_PWR_MSB_REG, &val2); mxl111sf_get_rf_strength()
388 ret = mxl111sf_tuner_write_reg(state, 0x00, 0x00); mxl111sf_get_rf_strength()
398 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl111sf_tuner_get_frequency() local
399 *frequency = state->frequency; mxl111sf_tuner_get_frequency()
405 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl111sf_tuner_get_bandwidth() local
406 *bandwidth = state->bandwidth; mxl111sf_tuner_get_bandwidth()
413 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl111sf_tuner_get_if_frequency() local
417 switch (state->if_freq) { mxl111sf_tuner_get_if_frequency()
460 struct mxl111sf_tuner_state *state = fe->tuner_priv; mxl111sf_tuner_release() local
462 kfree(state); mxl111sf_tuner_release()
495 struct mxl111sf_tuner_state *state = NULL; mxl111sf_tuner_attach() local
499 state = kzalloc(sizeof(struct mxl111sf_tuner_state), GFP_KERNEL); mxl111sf_tuner_attach()
500 if (state == NULL) mxl111sf_tuner_attach()
503 state->mxl_state = mxl_state; mxl111sf_tuner_attach()
504 state->cfg = cfg; mxl111sf_tuner_attach()
509 fe->tuner_priv = state; mxl111sf_tuner_attach()
H A Dmxl111sf-phy.h26 int mxl1x1sf_soft_reset(struct mxl111sf_state *state);
27 int mxl1x1sf_set_device_mode(struct mxl111sf_state *state, int mode);
28 int mxl1x1sf_top_master_ctrl(struct mxl111sf_state *state, int onoff);
29 int mxl111sf_disable_656_port(struct mxl111sf_state *state);
30 int mxl111sf_init_tuner_demod(struct mxl111sf_state *state);
31 int mxl111sf_enable_usb_output(struct mxl111sf_state *state);
32 int mxl111sf_config_mpeg_in(struct mxl111sf_state *state,
38 int mxl111sf_config_i2s(struct mxl111sf_state *state,
40 int mxl111sf_init_i2s_port(struct mxl111sf_state *state, u8 sample_size);
41 int mxl111sf_disable_i2s_port(struct mxl111sf_state *state);
42 int mxl111sf_config_spi(struct mxl111sf_state *state, int onoff);
43 int mxl111sf_idac_config(struct mxl111sf_state *state,
H A Dmxl111sf-gpio.c35 static int mxl111sf_set_gpo_state(struct mxl111sf_state *state, u8 pin, u8 val) mxl111sf_set_gpo_state() argument
43 ret = mxl111sf_read_reg(state, 0x19, &tmp); mxl111sf_set_gpo_state()
48 ret = mxl111sf_write_reg(state, 0x19, tmp); mxl111sf_set_gpo_state()
54 ret = mxl111sf_read_reg(state, 0x30, &tmp); mxl111sf_set_gpo_state()
59 ret = mxl111sf_write_reg(state, 0x30, tmp); mxl111sf_set_gpo_state()
68 static int mxl111sf_get_gpi_state(struct mxl111sf_state *state, u8 pin, u8 *val) mxl111sf_get_gpi_state() argument
82 ret = mxl111sf_read_reg(state, 0x23, &tmp); mxl111sf_get_gpi_state()
91 ret = mxl111sf_read_reg(state, 0x2f, &tmp); mxl111sf_get_gpi_state()
99 ret = mxl111sf_read_reg(state, 0x22, &tmp); mxl111sf_get_gpi_state()
117 static int mxl111sf_config_gpio_pins(struct mxl111sf_state *state, mxl111sf_config_gpio_pins() argument
130 ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_0, &tmp); mxl111sf_config_gpio_pins()
135 ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_0, tmp); mxl111sf_config_gpio_pins()
143 ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_1, &tmp); mxl111sf_config_gpio_pins()
148 ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_1, tmp); mxl111sf_config_gpio_pins()
155 ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_2, &tmp); mxl111sf_config_gpio_pins()
160 ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_2, tmp); mxl111sf_config_gpio_pins()
169 mxl111sf_set_gpo_state(state, mxl111sf_config_gpio_pins()
171 mxl111sf_get_gpi_state(state, mxl111sf_config_gpio_pins()
178 static int mxl111sf_hw_do_set_gpio(struct mxl111sf_state *state, mxl111sf_hw_do_set_gpio() argument
189 return mxl111sf_config_gpio_pins(state, &gpio_config); mxl111sf_hw_do_set_gpio()
214 int mxl111sf_config_pin_mux_modes(struct mxl111sf_state *state, mxl111sf_config_pin_mux_modes() argument
222 ret = mxl111sf_read_reg(state, 0x17, &r17); mxl111sf_config_pin_mux_modes()
225 ret = mxl111sf_read_reg(state, 0x18, &r18); mxl111sf_config_pin_mux_modes()
228 ret = mxl111sf_read_reg(state, 0x12, &r12); mxl111sf_config_pin_mux_modes()
231 ret = mxl111sf_read_reg(state, 0x15, &r15); mxl111sf_config_pin_mux_modes()
234 ret = mxl111sf_read_reg(state, 0x82, &r82); mxl111sf_config_pin_mux_modes()
237 ret = mxl111sf_read_reg(state, 0x84, &r84); mxl111sf_config_pin_mux_modes()
240 ret = mxl111sf_read_reg(state, 0x89, &r89); mxl111sf_config_pin_mux_modes()
243 ret = mxl111sf_read_reg(state, 0x3D, &r3D); mxl111sf_config_pin_mux_modes()
531 ret = mxl111sf_write_reg(state, 0x17, r17); mxl111sf_config_pin_mux_modes()
534 ret = mxl111sf_write_reg(state, 0x18, r18); mxl111sf_config_pin_mux_modes()
537 ret = mxl111sf_write_reg(state, 0x12, r12); mxl111sf_config_pin_mux_modes()
540 ret = mxl111sf_write_reg(state, 0x15, r15); mxl111sf_config_pin_mux_modes()
543 ret = mxl111sf_write_reg(state, 0x82, r82); mxl111sf_config_pin_mux_modes()
546 ret = mxl111sf_write_reg(state, 0x84, r84); mxl111sf_config_pin_mux_modes()
549 ret = mxl111sf_write_reg(state, 0x89, r89); mxl111sf_config_pin_mux_modes()
552 ret = mxl111sf_write_reg(state, 0x3D, r3D); mxl111sf_config_pin_mux_modes()
561 static int mxl111sf_hw_set_gpio(struct mxl111sf_state *state, int gpio, int val) mxl111sf_hw_set_gpio() argument
563 return mxl111sf_hw_do_set_gpio(state, gpio, MXL_GPIO_DIR_OUTPUT, val); mxl111sf_hw_set_gpio()
566 static int mxl111sf_hw_gpio_initialize(struct mxl111sf_state *state) mxl111sf_hw_gpio_initialize() argument
574 ret = mxl111sf_hw_set_gpio(state, i, (gpioval >> i) & 0x01); mxl111sf_hw_gpio_initialize()
583 static int pca9534_set_gpio(struct mxl111sf_state *state, int gpio, int val) pca9534_set_gpio() argument
597 i2c_transfer(&state->d->i2c_adap, msg, 2); pca9534_set_gpio()
613 i2c_transfer(&state->d->i2c_adap, &msg[0], 1); pca9534_set_gpio()
618 static int pca9534_init_port_expander(struct mxl111sf_state *state) pca9534_init_port_expander() argument
629 i2c_transfer(&state->d->i2c_adap, &msg, 1); pca9534_init_port_expander()
635 i2c_transfer(&state->d->i2c_adap, &msg, 1); pca9534_init_port_expander()
640 int mxl111sf_set_gpio(struct mxl111sf_state *state, int gpio, int val) mxl111sf_set_gpio() argument
644 switch (state->gpio_port_expander) { mxl111sf_set_gpio()
650 return pca9534_set_gpio(state, gpio, val); mxl111sf_set_gpio()
652 return mxl111sf_hw_set_gpio(state, gpio, val); mxl111sf_set_gpio()
656 static int mxl111sf_probe_port_expander(struct mxl111sf_state *state) mxl111sf_probe_port_expander() argument
672 ret = i2c_transfer(&state->d->i2c_adap, msg, 2); mxl111sf_probe_port_expander()
674 state->port_expander_addr = msg[0].addr; mxl111sf_probe_port_expander()
675 state->gpio_port_expander = mxl111sf_PCA9534; mxl111sf_probe_port_expander()
677 state->port_expander_addr); mxl111sf_probe_port_expander()
684 ret = i2c_transfer(&state->d->i2c_adap, msg, 2); mxl111sf_probe_port_expander()
686 state->port_expander_addr = msg[0].addr; mxl111sf_probe_port_expander()
687 state->gpio_port_expander = mxl111sf_PCA9534; mxl111sf_probe_port_expander()
689 state->port_expander_addr); mxl111sf_probe_port_expander()
692 state->port_expander_addr = 0xff; mxl111sf_probe_port_expander()
693 state->gpio_port_expander = mxl111sf_gpio_hw; mxl111sf_probe_port_expander()
698 int mxl111sf_init_port_expander(struct mxl111sf_state *state) mxl111sf_init_port_expander() argument
702 if (0x00 == state->port_expander_addr) mxl111sf_init_port_expander()
703 mxl111sf_probe_port_expander(state); mxl111sf_init_port_expander()
705 switch (state->gpio_port_expander) { mxl111sf_init_port_expander()
711 return pca9534_init_port_expander(state); mxl111sf_init_port_expander()
713 return mxl111sf_hw_gpio_initialize(state); mxl111sf_init_port_expander()
719 int mxl111sf_gpio_mode_switch(struct mxl111sf_state *state, unsigned int mode) mxl111sf_gpio_mode_switch() argument
732 mxl111sf_set_gpio(state, 4, 0); mxl111sf_gpio_mode_switch()
733 mxl111sf_set_gpio(state, 5, 0); mxl111sf_gpio_mode_switch()
735 mxl111sf_set_gpio(state, 7, 1); mxl111sf_gpio_mode_switch()
737 mxl111sf_set_gpio(state, 6, 1); mxl111sf_gpio_mode_switch()
740 mxl111sf_set_gpio(state, 3, 0); mxl111sf_gpio_mode_switch()
743 mxl111sf_set_gpio(state, 6, 0); mxl111sf_gpio_mode_switch()
744 mxl111sf_set_gpio(state, 7, 0); mxl111sf_gpio_mode_switch()
746 mxl111sf_set_gpio(state, 5, 1); mxl111sf_gpio_mode_switch()
748 mxl111sf_set_gpio(state, 4, 1); mxl111sf_gpio_mode_switch()
750 mxl111sf_set_gpio(state, 3, 1); mxl111sf_gpio_mode_switch()
753 mxl111sf_init_port_expander(state); mxl111sf_gpio_mode_switch()
H A Dmxl111sf.c89 int mxl111sf_read_reg(struct mxl111sf_state *state, u8 addr, u8 *data) mxl111sf_read_reg() argument
94 ret = mxl111sf_ctrl_msg(state->d, MXL_CMD_REG_READ, &addr, 1, buf, 2); mxl111sf_read_reg()
113 int mxl111sf_write_reg(struct mxl111sf_state *state, u8 addr, u8 data) mxl111sf_write_reg() argument
120 ret = mxl111sf_ctrl_msg(state->d, MXL_CMD_REG_WRITE, buf, 2, NULL, 0); mxl111sf_write_reg()
128 int mxl111sf_write_reg_mask(struct mxl111sf_state *state, mxl111sf_write_reg_mask() argument
135 ret = mxl111sf_read_reg(state, addr, &val); mxl111sf_write_reg_mask()
142 ret = mxl111sf_read_reg(state, addr, &val); mxl111sf_write_reg_mask()
150 ret = mxl111sf_write_reg(state, addr, val); mxl111sf_write_reg_mask()
158 int mxl111sf_ctrl_program_regs(struct mxl111sf_state *state, mxl111sf_ctrl_program_regs() argument
167 ret = mxl111sf_write_reg_mask(state, mxl111sf_ctrl_program_regs()
182 static int mxl1x1sf_get_chip_info(struct mxl111sf_state *state) mxl1x1sf_get_chip_info() argument
188 if ((state->chip_id) && (state->chip_ver)) mxl1x1sf_get_chip_info()
191 ret = mxl111sf_read_reg(state, CHIP_ID_REG, &id); mxl1x1sf_get_chip_info()
194 state->chip_id = id; mxl1x1sf_get_chip_info()
196 ret = mxl111sf_read_reg(state, TOP_CHIP_REV_ID_REG, &ver); mxl1x1sf_get_chip_info()
199 state->chip_ver = ver; mxl1x1sf_get_chip_info()
214 state->chip_rev = MXL111SF_V6; mxl1x1sf_get_chip_info()
218 state->chip_rev = MXL111SF_V8_100; mxl1x1sf_get_chip_info()
222 state->chip_rev = MXL111SF_V8_200; mxl1x1sf_get_chip_info()
226 state->chip_rev = 0; mxl1x1sf_get_chip_info()
235 #define get_chip_info(state) \
238 ___ret = mxl1x1sf_get_chip_info(state); \
242 ___ret = mxl1x1sf_get_chip_info(state); \
265 struct mxl111sf_state *state = fe_to_priv(fe); mxl111sf_adap_fe_init() local
266 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe->id]; mxl111sf_adap_fe_init()
270 if (!state->chip_id) { mxl111sf_adap_fe_init()
277 mutex_lock(&state->fe_lock); mxl111sf_adap_fe_init()
279 state->alt_mode = adap_state->alt_mode; mxl111sf_adap_fe_init()
281 if (usb_set_interface(d->udev, 0, state->alt_mode) < 0) mxl111sf_adap_fe_init()
284 err = mxl1x1sf_soft_reset(state); mxl111sf_adap_fe_init()
286 err = mxl111sf_init_tuner_demod(state); mxl111sf_adap_fe_init()
288 err = mxl1x1sf_set_device_mode(state, adap_state->device_mode); mxl111sf_adap_fe_init()
291 mxl111sf_enable_usb_output(state); mxl111sf_adap_fe_init()
293 mxl1x1sf_top_master_ctrl(state, 1); mxl111sf_adap_fe_init()
297 (state->chip_rev > MXL111SF_V6)) { mxl111sf_adap_fe_init()
298 mxl111sf_config_pin_mux_modes(state, mxl111sf_adap_fe_init()
302 err = mxl111sf_init_port_expander(state); mxl111sf_adap_fe_init()
304 state->gpio_mode = adap_state->gpio_mode; mxl111sf_adap_fe_init()
305 err = mxl111sf_gpio_mode_switch(state, state->gpio_mode); mxl111sf_adap_fe_init()
321 struct mxl111sf_state *state = fe_to_priv(fe); mxl111sf_adap_fe_sleep() local
322 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe->id]; mxl111sf_adap_fe_sleep()
326 if (!state->chip_id) { mxl111sf_adap_fe_sleep()
335 mutex_unlock(&state->fe_lock); mxl111sf_adap_fe_sleep()
345 struct mxl111sf_state *state = fe_to_priv(fe); mxl111sf_ep6_streaming_ctrl() local
346 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe->id]; mxl111sf_ep6_streaming_ctrl()
352 ret = mxl111sf_enable_usb_output(state); mxl111sf_ep6_streaming_ctrl()
354 ret = mxl111sf_config_mpeg_in(state, 1, 1, mxl111sf_ep6_streaming_ctrl()
360 ret = mxl111sf_disable_656_port(state); mxl111sf_ep6_streaming_ctrl()
370 struct mxl111sf_state *state = fe_to_priv(fe); mxl111sf_ep5_streaming_ctrl() local
376 ret = mxl111sf_enable_usb_output(state); mxl111sf_ep5_streaming_ctrl()
379 ret = mxl111sf_init_i2s_port(state, 200); mxl111sf_ep5_streaming_ctrl()
381 ret = mxl111sf_config_i2s(state, 0, 15); mxl111sf_ep5_streaming_ctrl()
384 ret = mxl111sf_disable_i2s_port(state); mxl111sf_ep5_streaming_ctrl()
387 if (state->chip_rev > MXL111SF_V6) mxl111sf_ep5_streaming_ctrl()
388 ret = mxl111sf_config_spi(state, onoff); mxl111sf_ep5_streaming_ctrl()
396 struct mxl111sf_state *state = fe_to_priv(fe); mxl111sf_ep4_streaming_ctrl() local
402 ret = mxl111sf_enable_usb_output(state); mxl111sf_ep4_streaming_ctrl()
425 struct mxl111sf_state *state = d_to_priv(d); mxl111sf_lgdt3305_frontend_attach() local
426 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe_id]; mxl111sf_lgdt3305_frontend_attach()
431 /* save a pointer to the dvb_usb_device in device state */ mxl111sf_lgdt3305_frontend_attach()
432 state->d = d; mxl111sf_lgdt3305_frontend_attach()
434 state->alt_mode = adap_state->alt_mode; mxl111sf_lgdt3305_frontend_attach()
436 if (usb_set_interface(d->udev, 0, state->alt_mode) < 0) mxl111sf_lgdt3305_frontend_attach()
439 state->gpio_mode = MXL111SF_GPIO_MOD_ATSC; mxl111sf_lgdt3305_frontend_attach()
440 adap_state->gpio_mode = state->gpio_mode; mxl111sf_lgdt3305_frontend_attach()
444 ret = mxl1x1sf_soft_reset(state); mxl111sf_lgdt3305_frontend_attach()
447 ret = mxl111sf_init_tuner_demod(state); mxl111sf_lgdt3305_frontend_attach()
451 ret = mxl1x1sf_set_device_mode(state, adap_state->device_mode); mxl111sf_lgdt3305_frontend_attach()
455 ret = mxl111sf_enable_usb_output(state); mxl111sf_lgdt3305_frontend_attach()
458 ret = mxl1x1sf_top_master_ctrl(state, 1); mxl111sf_lgdt3305_frontend_attach()
462 ret = mxl111sf_init_port_expander(state); mxl111sf_lgdt3305_frontend_attach()
465 ret = mxl111sf_gpio_mode_switch(state, state->gpio_mode); mxl111sf_lgdt3305_frontend_attach()
473 state->num_frontends++; mxl111sf_lgdt3305_frontend_attach()
496 struct mxl111sf_state *state = d_to_priv(d); mxl111sf_lg2160_frontend_attach() local
497 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe_id]; mxl111sf_lg2160_frontend_attach()
502 /* save a pointer to the dvb_usb_device in device state */ mxl111sf_lg2160_frontend_attach()
503 state->d = d; mxl111sf_lg2160_frontend_attach()
505 state->alt_mode = adap_state->alt_mode; mxl111sf_lg2160_frontend_attach()
507 if (usb_set_interface(d->udev, 0, state->alt_mode) < 0) mxl111sf_lg2160_frontend_attach()
510 state->gpio_mode = MXL111SF_GPIO_MOD_MH; mxl111sf_lg2160_frontend_attach()
511 adap_state->gpio_mode = state->gpio_mode; mxl111sf_lg2160_frontend_attach()
515 ret = mxl1x1sf_soft_reset(state); mxl111sf_lg2160_frontend_attach()
518 ret = mxl111sf_init_tuner_demod(state); mxl111sf_lg2160_frontend_attach()
522 ret = mxl1x1sf_set_device_mode(state, adap_state->device_mode); mxl111sf_lg2160_frontend_attach()
526 ret = mxl111sf_enable_usb_output(state); mxl111sf_lg2160_frontend_attach()
529 ret = mxl1x1sf_top_master_ctrl(state, 1); mxl111sf_lg2160_frontend_attach()
533 ret = mxl111sf_init_port_expander(state); mxl111sf_lg2160_frontend_attach()
536 ret = mxl111sf_gpio_mode_switch(state, state->gpio_mode); mxl111sf_lg2160_frontend_attach()
540 ret = get_chip_info(state); mxl111sf_lg2160_frontend_attach()
548 state->num_frontends++; mxl111sf_lg2160_frontend_attach()
581 struct mxl111sf_state *state = d_to_priv(d); mxl111sf_lg2161_frontend_attach() local
582 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe_id]; mxl111sf_lg2161_frontend_attach()
587 /* save a pointer to the dvb_usb_device in device state */ mxl111sf_lg2161_frontend_attach()
588 state->d = d; mxl111sf_lg2161_frontend_attach()
590 state->alt_mode = adap_state->alt_mode; mxl111sf_lg2161_frontend_attach()
592 if (usb_set_interface(d->udev, 0, state->alt_mode) < 0) mxl111sf_lg2161_frontend_attach()
595 state->gpio_mode = MXL111SF_GPIO_MOD_MH; mxl111sf_lg2161_frontend_attach()
596 adap_state->gpio_mode = state->gpio_mode; mxl111sf_lg2161_frontend_attach()
600 ret = mxl1x1sf_soft_reset(state); mxl111sf_lg2161_frontend_attach()
603 ret = mxl111sf_init_tuner_demod(state); mxl111sf_lg2161_frontend_attach()
607 ret = mxl1x1sf_set_device_mode(state, adap_state->device_mode); mxl111sf_lg2161_frontend_attach()
611 ret = mxl111sf_enable_usb_output(state); mxl111sf_lg2161_frontend_attach()
614 ret = mxl1x1sf_top_master_ctrl(state, 1); mxl111sf_lg2161_frontend_attach()
618 ret = mxl111sf_init_port_expander(state); mxl111sf_lg2161_frontend_attach()
621 ret = mxl111sf_gpio_mode_switch(state, state->gpio_mode); mxl111sf_lg2161_frontend_attach()
625 ret = get_chip_info(state); mxl111sf_lg2161_frontend_attach()
630 (MXL111SF_V8_200 == state->chip_rev) ? mxl111sf_lg2161_frontend_attach()
635 state->num_frontends++; mxl111sf_lg2161_frontend_attach()
668 struct mxl111sf_state *state = d_to_priv(d); mxl111sf_lg2161_ep6_frontend_attach() local
669 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe_id]; mxl111sf_lg2161_ep6_frontend_attach()
674 /* save a pointer to the dvb_usb_device in device state */ mxl111sf_lg2161_ep6_frontend_attach()
675 state->d = d; mxl111sf_lg2161_ep6_frontend_attach()
677 state->alt_mode = adap_state->alt_mode; mxl111sf_lg2161_ep6_frontend_attach()
679 if (usb_set_interface(d->udev, 0, state->alt_mode) < 0) mxl111sf_lg2161_ep6_frontend_attach()
682 state->gpio_mode = MXL111SF_GPIO_MOD_MH; mxl111sf_lg2161_ep6_frontend_attach()
683 adap_state->gpio_mode = state->gpio_mode; mxl111sf_lg2161_ep6_frontend_attach()
687 ret = mxl1x1sf_soft_reset(state); mxl111sf_lg2161_ep6_frontend_attach()
690 ret = mxl111sf_init_tuner_demod(state); mxl111sf_lg2161_ep6_frontend_attach()
694 ret = mxl1x1sf_set_device_mode(state, adap_state->device_mode); mxl111sf_lg2161_ep6_frontend_attach()
698 ret = mxl111sf_enable_usb_output(state); mxl111sf_lg2161_ep6_frontend_attach()
701 ret = mxl1x1sf_top_master_ctrl(state, 1); mxl111sf_lg2161_ep6_frontend_attach()
705 ret = mxl111sf_init_port_expander(state); mxl111sf_lg2161_ep6_frontend_attach()
708 ret = mxl111sf_gpio_mode_switch(state, state->gpio_mode); mxl111sf_lg2161_ep6_frontend_attach()
712 ret = get_chip_info(state); mxl111sf_lg2161_ep6_frontend_attach()
717 (MXL111SF_V8_200 == state->chip_rev) ? mxl111sf_lg2161_ep6_frontend_attach()
722 state->num_frontends++; mxl111sf_lg2161_ep6_frontend_attach()
743 struct mxl111sf_state *state = d_to_priv(d); mxl111sf_attach_demod() local
744 struct mxl111sf_adap_state *adap_state = &state->adap_state[fe_id]; mxl111sf_attach_demod()
749 /* save a pointer to the dvb_usb_device in device state */ mxl111sf_attach_demod()
750 state->d = d; mxl111sf_attach_demod()
752 state->alt_mode = adap_state->alt_mode; mxl111sf_attach_demod()
754 if (usb_set_interface(d->udev, 0, state->alt_mode) < 0) mxl111sf_attach_demod()
757 state->gpio_mode = MXL111SF_GPIO_MOD_DVBT; mxl111sf_attach_demod()
758 adap_state->gpio_mode = state->gpio_mode; mxl111sf_attach_demod()
762 ret = mxl1x1sf_soft_reset(state); mxl111sf_attach_demod()
765 ret = mxl111sf_init_tuner_demod(state); mxl111sf_attach_demod()
769 ret = mxl1x1sf_set_device_mode(state, adap_state->device_mode); mxl111sf_attach_demod()
773 ret = mxl111sf_enable_usb_output(state); mxl111sf_attach_demod()
776 ret = mxl1x1sf_top_master_ctrl(state, 1); mxl111sf_attach_demod()
781 mxl111sf_init_port_expander(state); mxl111sf_attach_demod()
783 adap->fe[fe_id] = dvb_attach(mxl111sf_demod_attach, state, mxl111sf_attach_demod()
786 state->num_frontends++; mxl111sf_attach_demod()
798 static inline int mxl111sf_set_ant_path(struct mxl111sf_state *state, mxl111sf_set_ant_path() argument
801 return mxl111sf_idac_config(state, 1, 1, mxl111sf_set_ant_path()
817 struct mxl111sf_state *state = fe_to_priv(fe); mxl111sf_ant_hunt() local
823 mxl111sf_set_ant_path(state, antctrl == ANT_PATH_AUTO ? mxl111sf_ant_hunt()
832 mxl111sf_set_ant_path(state, ANT_PATH_EXTERNAL); mxl111sf_ant_hunt()
836 mxl111sf_set_ant_path(state, ANT_PATH_EXTERNAL); mxl111sf_ant_hunt()
840 mxl111sf_set_ant_path(state, ANT_PATH_INTERNAL); mxl111sf_ant_hunt()
846 mxl111sf_set_ant_path(state, ANT_PATH_EXTERNAL); mxl111sf_ant_hunt()
870 struct mxl111sf_state *state = adap_to_priv(adap); mxl111sf_attach_tuner() local
875 for (i = 0; i < state->num_frontends; i++) { mxl111sf_attach_tuner()
876 if (dvb_attach(mxl111sf_tuner_attach, adap->fe[i], state, mxl111sf_attach_tuner()
900 struct mxl111sf_state *state = d_to_priv(d); mxl111sf_init() local
905 ret = get_chip_info(state); mxl111sf_init()
909 mutex_init(&state->fe_lock); mxl111sf_init()
911 if (state->chip_rev > MXL111SF_V6) mxl111sf_init()
912 mxl111sf_config_pin_mux_modes(state, PIN_MUX_TS_SPI_IN_MODE_1); mxl111sf_init()
920 tveeprom_hauppauge_analog(&c, &state->tv, (0x84 == eeprom[0xa0]) ? mxl111sf_init()
923 switch (state->tv.model) { mxl111sf_init()
931 __func__, state->tv.model); mxl111sf_init()
H A Dmxl111sf-phy.c24 int mxl111sf_init_tuner_demod(struct mxl111sf_state *state) mxl111sf_init_tuner_demod() argument
52 return mxl111sf_ctrl_program_regs(state, mxl_111_overwrite_default); mxl111sf_init_tuner_demod()
55 int mxl1x1sf_soft_reset(struct mxl111sf_state *state) mxl1x1sf_soft_reset() argument
60 ret = mxl111sf_write_reg(state, 0xff, 0x00); /* AIC */ mxl1x1sf_soft_reset()
63 ret = mxl111sf_write_reg(state, 0x02, 0x01); /* get out of reset */ mxl1x1sf_soft_reset()
69 int mxl1x1sf_set_device_mode(struct mxl111sf_state *state, int mode) mxl1x1sf_set_device_mode() argument
77 ret = mxl111sf_write_reg(state, 0x03, mxl1x1sf_set_device_mode()
82 ret = mxl111sf_write_reg_mask(state, mxl1x1sf_set_device_mode()
91 state->device_mode = mode; mxl1x1sf_set_device_mode()
97 int mxl1x1sf_top_master_ctrl(struct mxl111sf_state *state, int onoff) mxl1x1sf_top_master_ctrl() argument
101 return mxl111sf_write_reg(state, 0x01, onoff ? 0x01 : 0x00); mxl1x1sf_top_master_ctrl()
104 int mxl111sf_disable_656_port(struct mxl111sf_state *state) mxl111sf_disable_656_port() argument
108 return mxl111sf_write_reg_mask(state, 0x12, 0x04, 0x00); mxl111sf_disable_656_port()
111 int mxl111sf_enable_usb_output(struct mxl111sf_state *state) mxl111sf_enable_usb_output() argument
115 return mxl111sf_write_reg_mask(state, 0x17, 0x40, 0x00); mxl111sf_enable_usb_output()
119 int mxl111sf_config_mpeg_in(struct mxl111sf_state *state, mxl111sf_config_mpeg_in() argument
133 ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX); mxl111sf_config_mpeg_in()
137 mxl111sf_read_reg(state, V6_MPEG_IN_CLK_INV_REG, &mode); mxl111sf_config_mpeg_in()
144 ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode); mxl111sf_config_mpeg_in()
149 ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode); mxl111sf_config_mpeg_in()
168 ret = mxl111sf_read_reg(state, mxl111sf_config_mpeg_in()
178 ret = mxl111sf_write_reg(state, mxl111sf_config_mpeg_in()
196 ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode); mxl111sf_config_mpeg_in()
202 int mxl111sf_init_i2s_port(struct mxl111sf_state *state, u8 sample_size) mxl111sf_init_i2s_port() argument
222 ret = mxl111sf_ctrl_program_regs(state, init_i2s); mxl111sf_init_i2s_port()
226 ret = mxl111sf_write_reg(state, V6_I2S_NUM_SAMPLES_REG, sample_size); mxl111sf_init_i2s_port()
232 int mxl111sf_disable_i2s_port(struct mxl111sf_state *state) mxl111sf_disable_i2s_port() argument
241 return mxl111sf_ctrl_program_regs(state, disable_i2s); mxl111sf_disable_i2s_port()
244 int mxl111sf_config_i2s(struct mxl111sf_state *state, mxl111sf_config_i2s() argument
252 ret = mxl111sf_read_reg(state, V6_I2S_STREAM_START_BIT_REG, &tmp); mxl111sf_config_i2s()
258 ret = mxl111sf_write_reg(state, V6_I2S_STREAM_START_BIT_REG, tmp); mxl111sf_config_i2s()
262 ret = mxl111sf_read_reg(state, V6_I2S_STREAM_END_BIT_REG, &tmp); mxl111sf_config_i2s()
268 ret = mxl111sf_write_reg(state, V6_I2S_STREAM_END_BIT_REG, tmp); mxl111sf_config_i2s()
274 int mxl111sf_config_spi(struct mxl111sf_state *state, int onoff) mxl111sf_config_spi() argument
281 ret = mxl111sf_write_reg(state, 0x00, 0x02); mxl111sf_config_spi()
285 ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val); mxl111sf_config_spi()
294 ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val); mxl111sf_config_spi()
298 ret = mxl111sf_write_reg(state, 0x00, 0x00); mxl111sf_config_spi()
304 int mxl111sf_idac_config(struct mxl111sf_state *state, mxl111sf_idac_config() argument
328 ret = mxl111sf_write_reg(state, V6_IDAC_HYSTERESIS_REG, mxl111sf_idac_config()
333 ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val); mxl111sf_idac_config()
H A Daf9015.c35 struct af9015_state *state = d_to_priv(d); af9015_ctrl_msg() local
41 state->buf[0] = req->cmd; af9015_ctrl_msg()
42 state->buf[1] = state->seq++; af9015_ctrl_msg()
43 state->buf[2] = req->i2c_addr; af9015_ctrl_msg()
44 state->buf[3] = req->addr >> 8; af9015_ctrl_msg()
45 state->buf[4] = req->addr & 0xff; af9015_ctrl_msg()
46 state->buf[5] = req->mbox; af9015_ctrl_msg()
47 state->buf[6] = req->addr_len; af9015_ctrl_msg()
48 state->buf[7] = req->data_len; af9015_ctrl_msg()
58 state->buf[2] |= 0x01; /* set I2C direction */ af9015_ctrl_msg()
60 state->buf[0] = READ_WRITE_I2C; af9015_ctrl_msg()
65 state->buf[0] = WRITE_VIRTUAL_MEMORY; af9015_ctrl_msg()
93 memcpy(&state->buf[REQ_HDR_LEN], req->data, req->data_len); af9015_ctrl_msg()
103 state->buf, wlen, state->buf, rlen); af9015_ctrl_msg()
108 if (rlen && state->buf[1]) { af9015_ctrl_msg()
110 KBUILD_MODNAME, state->buf[1]); af9015_ctrl_msg()
117 memcpy(req->data, &state->buf[ACK_HDR_LEN], req->data_len); af9015_ctrl_msg()
152 struct af9015_state *state = d_to_priv(d); af9015_write_reg_i2c() local
155 if (addr == state->af9013_config[0].i2c_addr || af9015_write_reg_i2c()
156 addr == state->af9013_config[1].i2c_addr) af9015_write_reg_i2c()
165 struct af9015_state *state = d_to_priv(d); af9015_read_reg_i2c() local
168 if (addr == state->af9013_config[0].i2c_addr || af9015_read_reg_i2c()
169 addr == state->af9013_config[1].i2c_addr) af9015_read_reg_i2c()
211 struct af9015_state *state = d_to_priv(d); af9015_i2c_xfer() local
243 if (msg[i].addr == state->af9013_config[0].i2c_addr || af9015_i2c_xfer()
244 msg[i].addr == state->af9013_config[1].i2c_addr) { af9015_i2c_xfer()
260 if (msg[i].addr == state->af9013_config[0].i2c_addr) af9015_i2c_xfer()
277 if (msg[i].addr == state->af9013_config[0].i2c_addr) { af9015_i2c_xfer()
295 if (msg[i].addr == state->af9013_config[0].i2c_addr) af9015_i2c_xfer()
353 struct af9015_state *state = d_to_priv(d); af9015_download_firmware() local
363 state->firmware_size = fw->size; af9015_download_firmware()
364 state->firmware_checksum = checksum; af9015_download_firmware()
405 struct af9015_state *state = d_to_priv(d); af9015_eeprom_hash() local
421 state->eeprom_sum *= GOLDEN_RATIO_PRIME_32; af9015_eeprom_hash()
422 state->eeprom_sum += le32_to_cpu(((__le32 *)buf)[i]); af9015_eeprom_hash()
429 __func__, state->eeprom_sum); af9015_eeprom_hash()
438 struct af9015_state *state = d_to_priv(d); af9015_read_config() local
460 state->ir_mode = val; af9015_read_config()
469 state->dual_mode = val; af9015_read_config()
470 dev_dbg(&d->udev->dev, "%s: TS mode=%d\n", __func__, state->dual_mode); af9015_read_config()
474 state->dual_mode = 0; af9015_read_config()
476 if (state->dual_mode) { af9015_read_config()
483 state->af9013_config[1].i2c_addr = val; af9015_read_config()
486 for (i = 0; i < state->dual_mode + 1; i++) { af9015_read_config()
496 state->af9013_config[i].clock = 28800000; af9015_read_config()
499 state->af9013_config[i].clock = 20480000; af9015_read_config()
502 state->af9013_config[i].clock = 28000000; af9015_read_config()
505 state->af9013_config[i].clock = 25000000; af9015_read_config()
510 state->af9013_config[i].clock); af9015_read_config()
518 state->af9013_config[i].if_frequency = val << 8; af9015_read_config()
525 state->af9013_config[i].if_frequency += val; af9015_read_config()
526 state->af9013_config[i].if_frequency *= 1000; af9015_read_config()
528 i, state->af9013_config[i].if_frequency); af9015_read_config()
535 state->mt2060_if1[i] = val << 8; af9015_read_config()
540 state->mt2060_if1[i] += val; af9015_read_config()
542 state->mt2060_if1[i]); af9015_read_config()
558 state->af9013_config[i].spec_inv = 1; af9015_read_config()
564 state->af9013_config[i].spec_inv = 0; af9015_read_config()
567 state->af9013_config[i].gpio[1] = AF9013_GPIO_LO; af9015_read_config()
568 state->af9013_config[i].spec_inv = 1; af9015_read_config()
577 state->af9013_config[i].tuner = val; af9015_read_config()
599 state->dual_mode = 0; af9015_read_config()
602 state->af9013_config[0].if_frequency = 4570000; af9015_read_config()
622 struct af9015_state *state = d_to_priv(d); af9015_get_adapter_count() local
623 return state->dual_mode + 1; af9015_get_adapter_count()
630 struct af9015_state *state = fe_to_priv(fe); af9015_af9013_set_frontend() local
632 if (mutex_lock_interruptible(&state->fe_mutex)) af9015_af9013_set_frontend()
635 ret = state->set_frontend[fe_to_adap(fe)->id](fe); af9015_af9013_set_frontend()
637 mutex_unlock(&state->fe_mutex); af9015_af9013_set_frontend()
647 struct af9015_state *state = fe_to_priv(fe); af9015_af9013_read_status() local
649 if (mutex_lock_interruptible(&state->fe_mutex)) af9015_af9013_read_status()
652 ret = state->read_status[fe_to_adap(fe)->id](fe, status); af9015_af9013_read_status()
654 mutex_unlock(&state->fe_mutex); af9015_af9013_read_status()
663 struct af9015_state *state = fe_to_priv(fe); af9015_af9013_init() local
665 if (mutex_lock_interruptible(&state->fe_mutex)) af9015_af9013_init()
668 ret = state->init[fe_to_adap(fe)->id](fe); af9015_af9013_init()
670 mutex_unlock(&state->fe_mutex); af9015_af9013_init()
679 struct af9015_state *state = fe_to_priv(fe); af9015_af9013_sleep() local
681 if (mutex_lock_interruptible(&state->fe_mutex)) af9015_af9013_sleep()
684 ret = state->sleep[fe_to_adap(fe)->id](fe); af9015_af9013_sleep()
686 mutex_unlock(&state->fe_mutex); af9015_af9013_sleep()
695 struct af9015_state *state = fe_to_priv(fe); af9015_tuner_init() local
697 if (mutex_lock_interruptible(&state->fe_mutex)) af9015_tuner_init()
700 ret = state->tuner_init[fe_to_adap(fe)->id](fe); af9015_tuner_init()
702 mutex_unlock(&state->fe_mutex); af9015_tuner_init()
711 struct af9015_state *state = fe_to_priv(fe); af9015_tuner_sleep() local
713 if (mutex_lock_interruptible(&state->fe_mutex)) af9015_tuner_sleep()
716 ret = state->tuner_sleep[fe_to_adap(fe)->id](fe); af9015_tuner_sleep()
718 mutex_unlock(&state->fe_mutex); af9015_tuner_sleep()
725 struct af9015_state *state = d_to_priv(d); af9015_copy_firmware() local
733 fw_params[0] = state->firmware_size >> 8; af9015_copy_firmware()
734 fw_params[1] = state->firmware_size & 0xff; af9015_copy_firmware()
735 fw_params[2] = state->firmware_checksum >> 8; af9015_copy_firmware()
736 fw_params[3] = state->firmware_checksum & 0xff; af9015_copy_firmware()
741 ret = af9015_read_reg_i2c(d, state->af9013_config[1].i2c_addr, af9015_copy_firmware()
773 ret = af9015_write_reg_i2c(d, state->af9013_config[1].i2c_addr, af9015_copy_firmware()
784 ret = af9015_read_reg_i2c(d, state->af9013_config[1].i2c_addr, af9015_copy_firmware()
813 struct af9015_state *state = adap_to_priv(adap); af9015_af9013_frontend_attach() local
816 state->af9013_config[0].ts_mode = AF9013_TS_USB; af9015_af9013_frontend_attach()
817 memcpy(state->af9013_config[0].api_version, "\x0\x1\x9\x0", 4); af9015_af9013_frontend_attach()
818 state->af9013_config[0].gpio[0] = AF9013_GPIO_HI; af9015_af9013_frontend_attach()
819 state->af9013_config[0].gpio[3] = AF9013_GPIO_TUNER_ON; af9015_af9013_frontend_attach()
821 state->af9013_config[1].ts_mode = AF9013_TS_SERIAL; af9015_af9013_frontend_attach()
822 memcpy(state->af9013_config[1].api_version, "\x0\x1\x9\x0", 4); af9015_af9013_frontend_attach()
823 state->af9013_config[1].gpio[0] = AF9013_GPIO_TUNER_ON; af9015_af9013_frontend_attach()
824 state->af9013_config[1].gpio[1] = AF9013_GPIO_LO; af9015_af9013_frontend_attach()
827 if (state->dual_mode) { af9015_af9013_frontend_attach()
834 state->dual_mode = 0; af9015_af9013_frontend_attach()
844 &state->af9013_config[adap->id], &adap_to_d(adap)->i2c_adap); af9015_af9013_frontend_attach()
854 state->set_frontend[adap->id] = af9015_af9013_frontend_attach()
859 state->read_status[adap->id] = af9015_af9013_frontend_attach()
864 state->init[adap->id] = adap->fe[0]->ops.init; af9015_af9013_frontend_attach()
867 state->sleep[adap->id] = adap->fe[0]->ops.sleep; af9015_af9013_frontend_attach()
940 struct af9015_state *state = d_to_priv(d); af9015_tuner_attach() local
944 switch (state->af9013_config[adap->id].tuner) { af9015_tuner_attach()
949 state->mt2060_if1[adap->id]) af9015_tuner_attach()
998 state->af9013_config[adap->id].tuner); af9015_tuner_attach()
1003 state->tuner_init[adap->id] = af9015_tuner_attach()
1009 state->tuner_sleep[adap->id] = af9015_tuner_attach()
1057 struct af9015_state *state = d_to_priv(d); af9015_init_endpoint() local
1086 if (state->dual_mode) { af9015_init_endpoint()
1094 if (state->dual_mode) { af9015_init_endpoint()
1122 if (state->dual_mode) { af9015_init_endpoint()
1129 if (state->dual_mode) af9015_init_endpoint()
1144 struct af9015_state *state = d_to_priv(d); af9015_init() local
1148 mutex_init(&state->fe_mutex); af9015_init()
1197 struct af9015_state *state = d_to_priv(d); af9015_rc_query() local
1213 if ((state->rc_repeat != buf[6] || buf[0]) && af9015_rc_query()
1214 !memcmp(&buf[12], state->rc_last, 4)) { af9015_rc_query()
1217 state->rc_repeat = buf[6]; af9015_rc_query()
1232 memcpy(state->rc_last, &buf[12], 4); af9015_rc_query()
1236 state->rc_keycode = RC_SCANCODE_NEC(buf[12], af9015_rc_query()
1240 state->rc_keycode = RC_SCANCODE_NECX(buf[12] << 8 | af9015_rc_query()
1246 state->rc_keycode = RC_SCANCODE_NEC32(buf[12] << 24 | af9015_rc_query()
1251 rc_keydown(d->rc_dev, RC_TYPE_NEC, state->rc_keycode, 0); af9015_rc_query()
1256 state->rc_last[2] = state->rc_last[3]; af9015_rc_query()
1259 state->rc_repeat = buf[6]; af9015_rc_query()
1260 state->rc_failed = false; af9015_rc_query()
1268 if (!state->rc_failed) af9015_rc_query()
1271 state->rc_failed = true; af9015_rc_query()
1279 struct af9015_state *state = d_to_priv(d); af9015_get_rc_config() local
1282 if (state->ir_mode == AF9015_IR_MODE_DISABLED) af9015_get_rc_config()
1292 rc->map_name = af9015_rc_setup_match(state->eeprom_sum, af9015_get_rc_config()
H A Daf9035.c51 struct state *state = d_to_priv(d); af9035_ctrl_msg() local
66 state->buf[0] = REQ_HDR_LEN + req->wlen + CHECKSUM_LEN - 1; af9035_ctrl_msg()
67 state->buf[1] = req->mbox; af9035_ctrl_msg()
68 state->buf[2] = req->cmd; af9035_ctrl_msg()
69 state->buf[3] = state->seq++; af9035_ctrl_msg()
70 memcpy(&state->buf[REQ_HDR_LEN], req->wbuf, req->wlen); af9035_ctrl_msg()
76 checksum = af9035_checksum(state->buf, state->buf[0] - 1); af9035_ctrl_msg()
77 state->buf[state->buf[0] - 1] = (checksum >> 8); af9035_ctrl_msg()
78 state->buf[state->buf[0] - 0] = (checksum & 0xff); af9035_ctrl_msg()
85 state->buf, wlen, state->buf, rlen); af9035_ctrl_msg()
94 checksum = af9035_checksum(state->buf, rlen - 2); af9035_ctrl_msg()
95 tmp_checksum = (state->buf[rlen - 2] << 8) | state->buf[rlen - 1]; af9035_ctrl_msg()
106 if (state->buf[2]) { af9035_ctrl_msg()
108 if (req->cmd == CMD_IR_GET || state->buf[2] == 1) { af9035_ctrl_msg()
114 __func__, req->cmd, state->buf[2]); af9035_ctrl_msg()
121 memcpy(req->rbuf, &state->buf[ACK_HDR_LEN], req->rlen); af9035_ctrl_msg()
200 struct state *state = d_to_priv(d); af9035_add_i2c_dev() local
211 if (state->i2c_client[num] == NULL) af9035_add_i2c_dev()
240 state->i2c_client[num] = client; af9035_add_i2c_dev()
250 struct state *state = d_to_priv(d); af9035_del_i2c_dev() local
256 if (state->i2c_client[num] != NULL) af9035_del_i2c_dev()
268 client = state->i2c_client[num]; af9035_del_i2c_dev()
276 state->i2c_client[num] = NULL; af9035_del_i2c_dev()
286 struct state *state = d_to_priv(d); af9035_i2c_master_xfer() local
338 } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || af9035_i2c_master_xfer()
339 (msg[0].addr == state->af9033_i2c_addr[1]) || af9035_i2c_master_xfer()
340 (state->chip_type == 0x9135)) { af9035_i2c_master_xfer()
345 if (msg[0].addr == state->af9033_i2c_addr[1] || af9035_i2c_master_xfer()
346 msg[0].addr == (state->af9033_i2c_addr[1] >> 1)) af9035_i2c_master_xfer()
357 if (state->chip_type == 0x9306) { af9035_i2c_master_xfer()
364 if (state->chip_type == 0x9306) { af9035_i2c_master_xfer()
381 } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || af9035_i2c_master_xfer()
382 (msg[0].addr == state->af9033_i2c_addr[1]) || af9035_i2c_master_xfer()
383 (state->chip_type == 0x9135)) { af9035_i2c_master_xfer()
388 if (msg[0].addr == state->af9033_i2c_addr[1] || af9035_i2c_master_xfer()
389 msg[0].addr == (state->af9033_i2c_addr[1] >> 1)) af9035_i2c_master_xfer()
400 if (state->chip_type == 0x9306) { af9035_i2c_master_xfer()
407 if (state->chip_type == 0x9306) { af9035_i2c_master_xfer()
430 if (state->chip_type == 0x9306) { af9035_i2c_master_xfer()
436 if (state->chip_type == 0x9306) { af9035_i2c_master_xfer()
477 struct state *state = d_to_priv(d); af9035_identify_state() local
488 state->chip_version = rbuf[0]; af9035_identify_state()
489 state->chip_type = rbuf[2] << 8 | rbuf[1] << 0; af9035_identify_state()
491 ret = af9035_rd_reg(d, 0x384f, &state->prechip_version); af9035_identify_state()
497 KBUILD_MODNAME, state->prechip_version, af9035_identify_state()
498 state->chip_version, state->chip_type); af9035_identify_state()
500 if (state->chip_type == 0x9135) { af9035_identify_state()
501 if (state->chip_version == 0x02) af9035_identify_state()
505 state->eeprom_addr = EEPROM_BASE_IT9135; af9035_identify_state()
506 } else if (state->chip_type == 0x9306) { af9035_identify_state()
508 state->eeprom_addr = EEPROM_BASE_IT9135; af9035_identify_state()
511 state->eeprom_addr = EEPROM_BASE_AF9035; af9035_identify_state()
667 struct state *state = d_to_priv(d); af9035_download_firmware() local
683 ret = af9035_rd_reg(d, state->eeprom_addr + EEPROM_TS_MODE, &tmp); af9035_download_firmware()
709 state->eeprom_addr + EEPROM_2ND_DEMOD_ADDR, af9035_download_firmware()
718 if ((state->chip_type == 0x9135) || af9035_download_firmware()
719 (state->chip_type == 0x9306)) { af9035_download_firmware()
774 struct state *state = d_to_priv(d); af9035_read_config() local
780 state->af9033_i2c_addr[0] = 0x38; af9035_read_config()
781 state->af9033_i2c_addr[1] = 0x3a; af9035_read_config()
782 state->af9033_config[0].adc_multiplier = AF9033_ADC_MULTIPLIER_2X; af9035_read_config()
783 state->af9033_config[1].adc_multiplier = AF9033_ADC_MULTIPLIER_2X; af9035_read_config()
784 state->af9033_config[0].ts_mode = AF9033_TS_MODE_USB; af9035_read_config()
785 state->af9033_config[1].ts_mode = AF9033_TS_MODE_SERIAL; af9035_read_config()
787 if (state->chip_type == 0x9135) { af9035_read_config()
789 state->af9033_config[0].dyn0_clk = true; af9035_read_config()
790 state->af9033_config[1].dyn0_clk = true; af9035_read_config()
792 if (state->chip_version == 0x02) { af9035_read_config()
793 state->af9033_config[0].tuner = AF9033_TUNER_IT9135_60; af9035_read_config()
794 state->af9033_config[1].tuner = AF9033_TUNER_IT9135_60; af9035_read_config()
797 state->af9033_config[0].tuner = AF9033_TUNER_IT9135_38; af9035_read_config()
798 state->af9033_config[1].tuner = AF9033_TUNER_IT9135_38; af9035_read_config()
811 } else if (state->chip_type == 0x9306) { af9035_read_config()
822 ret = af9035_rd_reg(d, state->eeprom_addr + EEPROM_TS_MODE, &tmp); af9035_read_config()
827 state->dual_mode = true; af9035_read_config()
830 tmp, state->dual_mode); af9035_read_config()
832 if (state->dual_mode) { af9035_read_config()
835 state->eeprom_addr + EEPROM_2ND_DEMOD_ADDR, af9035_read_config()
841 state->af9033_i2c_addr[1] = tmp; af9035_read_config()
847 addr = state->eeprom_addr; af9035_read_config()
849 for (i = 0; i < state->dual_mode + 1; i++) { af9035_read_config()
859 if (state->chip_type == 0x9135) { af9035_read_config()
860 if (state->chip_version == 0x02) { af9035_read_config()
866 state->af9033_config[i].tuner = tmp; af9035_read_config()
875 state->af9033_config[i].tuner = tmp; af9035_read_config()
881 state->af9033_config[i].tuner = tmp; af9035_read_config()
884 if (state->af9033_config[i].tuner != tmp) { af9035_read_config()
888 state->af9033_config[i].tuner); af9035_read_config()
891 switch (state->af9033_config[i].tuner) { af9035_read_config()
898 state->af9033_config[i].spec_inv = 1; af9035_read_config()
915 switch (state->af9033_config[i].tuner) { af9035_read_config()
926 state->dual_mode = false; af9035_read_config()
958 for (i = 0; i < ARRAY_SIZE(state->af9033_config); i++) { af9035_read_config()
959 if (state->chip_type == 0x9135) af9035_read_config()
960 state->af9033_config[i].clock = clock_lut_it9135[tmp]; af9035_read_config()
962 state->af9033_config[i].clock = clock_lut_af9035[tmp]; af9035_read_config()
1086 struct state *state = d_to_priv(d); af9035_tuner_callback() local
1088 switch (state->af9033_config[0].tuner) { af9035_tuner_callback()
1121 struct state *state = d_to_priv(d); af9035_get_adapter_count() local
1123 return state->dual_mode + 1; af9035_get_adapter_count()
1128 struct state *state = adap_to_priv(adap); af9035_frontend_attach() local
1134 if (!state->af9033_config[adap->id].tuner) { af9035_frontend_attach()
1140 state->af9033_config[adap->id].fe = &adap->fe[0]; af9035_frontend_attach()
1141 state->af9033_config[adap->id].ops = &state->ops; af9035_frontend_attach()
1142 ret = af9035_add_i2c_dev(d, "af9033", state->af9033_i2c_addr[adap->id], af9035_frontend_attach()
1143 &state->af9033_config[adap->id], &d->i2c_adap); af9035_frontend_attach()
1166 struct state *state = adap_to_priv(adap); it930x_frontend_attach() local
1179 state->af9033_config[adap->id].fe = &adap->fe[0]; it930x_frontend_attach()
1180 state->af9033_config[adap->id].ops = &state->ops; it930x_frontend_attach()
1190 state->i2c_adapter_demod = adapter; it930x_frontend_attach()
1202 struct state *state = adap_to_priv(adap); af9035_frontend_detach() local
1213 switch (state->af9033_config[adap->id].tuner) { af9035_frontend_detach()
1227 if (state->i2c_client[demod2]) af9035_frontend_detach()
1230 if (state->i2c_client[0]) af9035_frontend_detach()
1289 struct state *state = adap_to_priv(adap); af9035_tuner_attach() local
1303 switch (state->af9033_config[adap->id].tuner) { af9035_tuner_attach()
1461 if (state->dual_mode) { af9035_tuner_attach()
1469 state->af9033_i2c_addr[adap->id] >> 1, af9035_tuner_attach()
1486 if (state->dual_mode) { af9035_tuner_attach()
1494 state->af9033_i2c_addr[adap->id] >> 1, af9035_tuner_attach()
1521 struct state *state = adap_to_priv(adap); it930x_tuner_attach() local
1573 &si2157_config, state->i2c_adapter_demod); it930x_tuner_attach()
1589 struct state *state = adap_to_priv(adap); it930x_tuner_detach() local
1595 if (state->i2c_client[3]) it930x_tuner_detach()
1598 if (state->i2c_client[1]) it930x_tuner_detach()
1608 struct state *state = adap_to_priv(adap); af9035_tuner_detach() local
1613 switch (state->af9033_config[adap->id].tuner) { af9035_tuner_detach()
1621 if (state->i2c_client[3]) af9035_tuner_detach()
1624 if (state->i2c_client[1]) af9035_tuner_detach()
1634 struct state *state = d_to_priv(d); af9035_init() local
1649 { 0x00dd11, state->dual_mode << 6, 0x40 }, af9035_init()
1653 { 0x80f9a3, state->dual_mode, 0x01 }, af9035_init()
1654 { 0x80f9cd, state->dual_mode, 0x01 }, af9035_init()
1681 struct state *state = d_to_priv(d); it930x_init() local
1696 { 0x00dd11, state->dual_mode << 6, 0x40 }, /* enable EP5 */ it930x_init()
1804 struct state *state = d_to_priv(d); af9035_get_rc_config() local
1808 ret = af9035_rd_reg(d, state->eeprom_addr + EEPROM_IR_MODE, &tmp); af9035_get_rc_config()
1816 ret = af9035_rd_reg(d, state->eeprom_addr + EEPROM_IR_TYPE, af9035_get_rc_config()
1867 struct state *state = adap_to_priv(adap); af9035_pid_filter_ctrl() local
1869 return state->ops.pid_filter_ctrl(adap->fe[0], onoff); af9035_pid_filter_ctrl()
1875 struct state *state = adap_to_priv(adap); af9035_pid_filter() local
1877 return state->ops.pid_filter(adap->fe[0], index, pid, onoff); af9035_pid_filter()
1923 .size_of_priv = sizeof(struct state),
1969 .size_of_priv = sizeof(struct state),
/linux-4.1.27/include/drm/
H A Ddrm_atomic.h35 void drm_atomic_state_clear(struct drm_atomic_state *state);
36 void drm_atomic_state_free(struct drm_atomic_state *state);
39 drm_atomic_get_crtc_state(struct drm_atomic_state *state,
42 struct drm_crtc_state *state, struct drm_property *property,
45 drm_atomic_get_plane_state(struct drm_atomic_state *state,
48 struct drm_plane_state *state, struct drm_property *property,
51 drm_atomic_get_connector_state(struct drm_atomic_state *state,
54 struct drm_connector_state *state, struct drm_property *property,
66 drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
69 drm_atomic_connectors_for_crtc(struct drm_atomic_state *state,
72 void drm_atomic_legacy_backoff(struct drm_atomic_state *state);
74 int __must_check drm_atomic_check_only(struct drm_atomic_state *state);
75 int __must_check drm_atomic_commit(struct drm_atomic_state *state);
76 int __must_check drm_atomic_async_commit(struct drm_atomic_state *state);
78 #define for_each_connector_in_state(state, connector, connector_state, __i) \
80 (__i) < (state)->num_connector && \
81 ((connector) = (state)->connectors[__i], \
82 (connector_state) = (state)->connector_states[__i], 1); \
86 #define for_each_crtc_in_state(state, crtc, crtc_state, __i) \
88 (__i) < (state)->dev->mode_config.num_crtc && \
89 ((crtc) = (state)->crtcs[__i], \
90 (crtc_state) = (state)->crtc_states[__i], 1); \
94 #define for_each_plane_in_state(state, plane, plane_state, __i) \
96 (__i) < (state)->dev->mode_config.num_total_plane && \
97 ((plane) = (state)->planes[__i], \
98 (plane_state) = (state)->plane_states[__i], 1); \
H A Ddrm_atomic_helper.h34 struct drm_atomic_state *state);
36 struct drm_atomic_state *state);
38 struct drm_atomic_state *state);
40 struct drm_atomic_state *state,
47 struct drm_atomic_state *state);
52 struct drm_atomic_state *state);
54 struct drm_atomic_state *state);
59 struct drm_atomic_state *state);
88 /* default implementations for state handling */
91 struct drm_crtc_state *state);
95 struct drm_crtc_state *state);
97 struct drm_crtc_state *state);
101 struct drm_plane_state *state);
105 struct drm_plane_state *state);
107 struct drm_plane_state *state);
112 struct drm_connector_state *state);
117 struct drm_connector_state *state);
119 struct drm_connector_state *state);
126 * This iterates over the current state, useful (for example) when applying
127 * atomic state after it has been checked and swapped. To iterate over the
132 drm_for_each_plane_mask(plane, (crtc)->dev, (crtc)->state->plane_mask)
135 * drm_crtc_atomic_state_for_each_plane - iterate over attached planes in new state
137 * @crtc_state: the incoming crtc-state
140 * attached if the specified state is applied. Useful during (for example)
141 * ->atomic_check() operations, to validate the incoming state
144 drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)
149 * @old_state: previous atomic state
151 * Checks the atomic state of a plane to determine whether it's being disabled
152 * or not. This also WARNs if it detects an invalid state (both CRTC and FB
167 WARN_ON((plane->state->crtc == NULL && plane->state->fb != NULL) || drm_atomic_plane_disabling()
168 (plane->state->crtc != NULL && plane->state->fb == NULL)); drm_atomic_plane_disabling()
172 * we know nothing about the current state and have to assume that it drm_atomic_plane_disabling()
177 * the correct state in ->reset() or that the driver will have taken drm_atomic_plane_disabling()
180 return (!old_state || old_state->crtc) && !plane->state->crtc; drm_atomic_plane_disabling()
/linux-4.1.27/drivers/media/platform/exynos4-is/
H A Dmipi-csis.c178 * struct csis_state - the driver's internal state data structure
191 * @flags: the state variable for power and streaming control
293 static void s5pcsis_enable_interrupts(struct csis_state *state, bool on) s5pcsis_enable_interrupts() argument
295 u32 val = s5pcsis_read(state, S5PCSIS_INTMSK); s5pcsis_enable_interrupts()
297 val |= state->interrupt_mask; s5pcsis_enable_interrupts()
299 val &= ~state->interrupt_mask; s5pcsis_enable_interrupts()
300 s5pcsis_write(state, S5PCSIS_INTMSK, val); s5pcsis_enable_interrupts()
303 static void s5pcsis_reset(struct csis_state *state) s5pcsis_reset() argument
305 u32 val = s5pcsis_read(state, S5PCSIS_CTRL); s5pcsis_reset()
307 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET); s5pcsis_reset()
311 static void s5pcsis_system_enable(struct csis_state *state, int on) s5pcsis_system_enable() argument
315 val = s5pcsis_read(state, S5PCSIS_CTRL); s5pcsis_system_enable()
320 s5pcsis_write(state, S5PCSIS_CTRL, val); s5pcsis_system_enable()
322 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); s5pcsis_system_enable()
325 mask = (1 << (state->num_lanes + 1)) - 1; s5pcsis_system_enable()
328 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); s5pcsis_system_enable()
331 /* Called with the state.lock mutex held */ __s5pcsis_set_format()
332 static void __s5pcsis_set_format(struct csis_state *state) __s5pcsis_set_format() argument
334 struct v4l2_mbus_framefmt *mf = &state->format; __s5pcsis_set_format()
337 v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n", __s5pcsis_set_format()
341 val = s5pcsis_read(state, S5PCSIS_CONFIG); __s5pcsis_set_format()
342 val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg; __s5pcsis_set_format()
343 s5pcsis_write(state, S5PCSIS_CONFIG, val); __s5pcsis_set_format()
347 s5pcsis_write(state, S5PCSIS_RESOL, val); __s5pcsis_set_format()
350 static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle) s5pcsis_set_hsync_settle() argument
352 u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); s5pcsis_set_hsync_settle()
355 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); s5pcsis_set_hsync_settle()
358 static void s5pcsis_set_params(struct csis_state *state) s5pcsis_set_params() argument
362 val = s5pcsis_read(state, S5PCSIS_CONFIG); s5pcsis_set_params()
363 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1); s5pcsis_set_params()
364 s5pcsis_write(state, S5PCSIS_CONFIG, val); s5pcsis_set_params()
366 __s5pcsis_set_format(state); s5pcsis_set_params()
367 s5pcsis_set_hsync_settle(state, state->hs_settle); s5pcsis_set_params()
369 val = s5pcsis_read(state, S5PCSIS_CTRL); s5pcsis_set_params()
370 if (state->csis_fmt->data_alignment == 32) s5pcsis_set_params()
376 if (state->wclk_ext) s5pcsis_set_params()
378 s5pcsis_write(state, S5PCSIS_CTRL, val); s5pcsis_set_params()
381 val = s5pcsis_read(state, S5PCSIS_CTRL); s5pcsis_set_params()
382 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW); s5pcsis_set_params()
385 static void s5pcsis_clk_put(struct csis_state *state) s5pcsis_clk_put() argument
390 if (IS_ERR(state->clock[i])) s5pcsis_clk_put()
392 clk_unprepare(state->clock[i]); s5pcsis_clk_put()
393 clk_put(state->clock[i]); s5pcsis_clk_put()
394 state->clock[i] = ERR_PTR(-EINVAL); s5pcsis_clk_put()
398 static int s5pcsis_clk_get(struct csis_state *state) s5pcsis_clk_get() argument
400 struct device *dev = &state->pdev->dev; s5pcsis_clk_get()
404 state->clock[i] = ERR_PTR(-EINVAL); s5pcsis_clk_get()
407 state->clock[i] = clk_get(dev, csi_clock_name[i]); s5pcsis_clk_get()
408 if (IS_ERR(state->clock[i])) { s5pcsis_clk_get()
409 ret = PTR_ERR(state->clock[i]); s5pcsis_clk_get()
412 ret = clk_prepare(state->clock[i]); s5pcsis_clk_get()
414 clk_put(state->clock[i]); s5pcsis_clk_get()
415 state->clock[i] = ERR_PTR(-EINVAL); s5pcsis_clk_get()
421 s5pcsis_clk_put(state); s5pcsis_clk_get()
426 static void dump_regs(struct csis_state *state, const char *label) dump_regs() argument
442 v4l2_info(&state->sd, "--- %s ---\n", label); dump_regs()
445 u32 cfg = s5pcsis_read(state, registers[i].offset); dump_regs()
446 v4l2_info(&state->sd, "%10s: 0x%08x\n", registers[i].name, cfg); dump_regs()
450 static void s5pcsis_start_stream(struct csis_state *state) s5pcsis_start_stream() argument
452 s5pcsis_reset(state); s5pcsis_start_stream()
453 s5pcsis_set_params(state); s5pcsis_start_stream()
454 s5pcsis_system_enable(state, true); s5pcsis_start_stream()
455 s5pcsis_enable_interrupts(state, true); s5pcsis_start_stream()
458 static void s5pcsis_stop_stream(struct csis_state *state) s5pcsis_stop_stream() argument
460 s5pcsis_enable_interrupts(state, false); s5pcsis_stop_stream()
461 s5pcsis_system_enable(state, false); s5pcsis_stop_stream()
464 static void s5pcsis_clear_counters(struct csis_state *state) s5pcsis_clear_counters() argument
469 spin_lock_irqsave(&state->slock, flags); s5pcsis_clear_counters()
471 state->events[i].counter = 0; s5pcsis_clear_counters()
472 spin_unlock_irqrestore(&state->slock, flags); s5pcsis_clear_counters()
475 static void s5pcsis_log_counters(struct csis_state *state, bool non_errors) s5pcsis_log_counters() argument
480 spin_lock_irqsave(&state->slock, flags); s5pcsis_log_counters()
483 if (state->events[i].counter > 0 || debug) s5pcsis_log_counters()
484 v4l2_info(&state->sd, "%s events: %d\n", s5pcsis_log_counters()
485 state->events[i].name, s5pcsis_log_counters()
486 state->events[i].counter); s5pcsis_log_counters()
488 spin_unlock_irqrestore(&state->slock, flags); s5pcsis_log_counters()
496 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_s_power() local
497 struct device *dev = &state->pdev->dev; s5pcsis_s_power()
507 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_s_stream() local
510 v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n", s5pcsis_s_stream()
511 __func__, enable, state->flags); s5pcsis_s_stream()
514 s5pcsis_clear_counters(state); s5pcsis_s_stream()
515 ret = pm_runtime_get_sync(&state->pdev->dev); s5pcsis_s_stream()
520 mutex_lock(&state->lock); s5pcsis_s_stream()
522 if (state->flags & ST_SUSPENDED) { s5pcsis_s_stream()
526 s5pcsis_start_stream(state); s5pcsis_s_stream()
527 state->flags |= ST_STREAMING; s5pcsis_s_stream()
529 s5pcsis_stop_stream(state); s5pcsis_s_stream()
530 state->flags &= ~ST_STREAMING; s5pcsis_s_stream()
532 s5pcsis_log_counters(state, true); s5pcsis_s_stream()
535 mutex_unlock(&state->lock); s5pcsis_s_stream()
537 pm_runtime_put(&state->pdev->dev); s5pcsis_s_stream()
571 struct csis_state *state, struct v4l2_subdev_pad_config *cfg, __s5pcsis_get_format()
575 return cfg ? v4l2_subdev_get_try_format(&state->sd, cfg, 0) : NULL; __s5pcsis_get_format()
577 return &state->format; __s5pcsis_get_format()
583 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_set_fmt() local
587 mf = __s5pcsis_get_format(state, cfg, fmt->which); s5pcsis_set_fmt()
591 mutex_lock(&state->lock); s5pcsis_set_fmt()
593 mutex_unlock(&state->lock); s5pcsis_set_fmt()
599 mutex_lock(&state->lock); s5pcsis_set_fmt()
602 state->csis_fmt = csis_fmt; s5pcsis_set_fmt()
603 mutex_unlock(&state->lock); s5pcsis_set_fmt()
611 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_get_fmt() local
614 mf = __s5pcsis_get_format(state, cfg, fmt->which); s5pcsis_get_fmt()
618 mutex_lock(&state->lock); s5pcsis_get_fmt()
620 mutex_unlock(&state->lock); s5pcsis_get_fmt()
627 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_s_rx_buffer() local
632 spin_lock_irqsave(&state->slock, flags); s5pcsis_s_rx_buffer()
633 state->pkt_buf.data = buf; s5pcsis_s_rx_buffer()
634 state->pkt_buf.len = *size; s5pcsis_s_rx_buffer()
635 spin_unlock_irqrestore(&state->slock, flags); s5pcsis_s_rx_buffer()
642 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_log_status() local
644 mutex_lock(&state->lock); s5pcsis_log_status()
645 s5pcsis_log_counters(state, true); s5pcsis_log_status()
646 if (debug && (state->flags & ST_POWERED)) s5pcsis_log_status()
647 dump_regs(state, __func__); s5pcsis_log_status()
648 mutex_unlock(&state->lock); s5pcsis_log_status()
693 struct csis_state *state = dev_id; s5pcsis_irq_handler() local
694 struct csis_pktbuf *pktbuf = &state->pkt_buf; s5pcsis_irq_handler()
698 status = s5pcsis_read(state, S5PCSIS_INTSRC); s5pcsis_irq_handler()
699 spin_lock_irqsave(&state->slock, flags); s5pcsis_irq_handler()
709 memcpy(pktbuf->data, state->regs + offset, pktbuf->len); s5pcsis_irq_handler()
718 if (!(status & state->events[i].mask)) s5pcsis_irq_handler()
720 state->events[i].counter++; s5pcsis_irq_handler()
721 v4l2_dbg(2, debug, &state->sd, "%s: %d\n", s5pcsis_irq_handler()
722 state->events[i].name, s5pcsis_irq_handler()
723 state->events[i].counter); s5pcsis_irq_handler()
725 v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status); s5pcsis_irq_handler()
727 spin_unlock_irqrestore(&state->slock, flags); s5pcsis_irq_handler()
729 s5pcsis_write(state, S5PCSIS_INTSRC, status); s5pcsis_irq_handler()
734 struct csis_state *state) s5pcsis_parse_dt()
740 &state->clk_frequency)) s5pcsis_parse_dt()
741 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; s5pcsis_parse_dt()
743 &state->max_num_lanes)) s5pcsis_parse_dt()
755 state->index = endpoint.base.port - FIMC_INPUT_MIPI_CSI2_0; s5pcsis_parse_dt()
756 if (state->index >= CSIS_MAX_ENTITIES) s5pcsis_parse_dt()
761 &state->hs_settle); s5pcsis_parse_dt()
762 state->wclk_ext = of_property_read_bool(node, s5pcsis_parse_dt()
765 state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes; s5pcsis_parse_dt()
780 struct csis_state *state; s5pcsis_probe() local
784 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); s5pcsis_probe()
785 if (!state) s5pcsis_probe()
788 mutex_init(&state->lock); s5pcsis_probe()
789 spin_lock_init(&state->slock); s5pcsis_probe()
790 state->pdev = pdev; s5pcsis_probe()
797 state->interrupt_mask = drv_data->interrupt_mask; s5pcsis_probe()
799 ret = s5pcsis_parse_dt(pdev, state); s5pcsis_probe()
803 if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { s5pcsis_probe()
805 state->num_lanes, state->max_num_lanes); s5pcsis_probe()
809 state->phy = devm_phy_get(dev, "csis"); s5pcsis_probe()
810 if (IS_ERR(state->phy)) s5pcsis_probe()
811 return PTR_ERR(state->phy); s5pcsis_probe()
814 state->regs = devm_ioremap_resource(dev, mem_res); s5pcsis_probe()
815 if (IS_ERR(state->regs)) s5pcsis_probe()
816 return PTR_ERR(state->regs); s5pcsis_probe()
818 state->irq = platform_get_irq(pdev, 0); s5pcsis_probe()
819 if (state->irq < 0) { s5pcsis_probe()
821 return state->irq; s5pcsis_probe()
825 state->supplies[i].supply = csis_supply_name[i]; s5pcsis_probe()
828 state->supplies); s5pcsis_probe()
832 ret = s5pcsis_clk_get(state); s5pcsis_probe()
836 if (state->clk_frequency) s5pcsis_probe()
837 ret = clk_set_rate(state->clock[CSIS_CLK_MUX], s5pcsis_probe()
838 state->clk_frequency); s5pcsis_probe()
844 ret = clk_enable(state->clock[CSIS_CLK_MUX]); s5pcsis_probe()
848 ret = devm_request_irq(dev, state->irq, s5pcsis_irq_handler, s5pcsis_probe()
849 0, dev_name(dev), state); s5pcsis_probe()
855 v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops); s5pcsis_probe()
856 state->sd.owner = THIS_MODULE; s5pcsis_probe()
857 snprintf(state->sd.name, sizeof(state->sd.name), "%s.%d", s5pcsis_probe()
858 CSIS_SUBDEV_NAME, state->index); s5pcsis_probe()
859 state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; s5pcsis_probe()
860 state->csis_fmt = &s5pcsis_formats[0]; s5pcsis_probe()
862 state->format.code = s5pcsis_formats[0].code; s5pcsis_probe()
863 state->format.width = S5PCSIS_DEF_PIX_WIDTH; s5pcsis_probe()
864 state->format.height = S5PCSIS_DEF_PIX_HEIGHT; s5pcsis_probe()
866 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK; s5pcsis_probe()
867 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; s5pcsis_probe()
868 ret = media_entity_init(&state->sd.entity, s5pcsis_probe()
869 CSIS_PADS_NUM, state->pads, 0); s5pcsis_probe()
874 v4l2_set_subdevdata(&state->sd, pdev); s5pcsis_probe()
877 platform_set_drvdata(pdev, &state->sd); s5pcsis_probe()
878 memcpy(state->events, s5pcsis_events, sizeof(state->events)); s5pcsis_probe()
888 state->num_lanes, state->hs_settle, state->wclk_ext, s5pcsis_probe()
889 state->clk_frequency); s5pcsis_probe()
893 media_entity_cleanup(&state->sd.entity); s5pcsis_probe()
895 clk_disable(state->clock[CSIS_CLK_MUX]); s5pcsis_probe()
897 s5pcsis_clk_put(state); s5pcsis_probe()
905 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_pm_suspend() local
909 __func__, state->flags); s5pcsis_pm_suspend()
911 mutex_lock(&state->lock); s5pcsis_pm_suspend()
912 if (state->flags & ST_POWERED) { s5pcsis_pm_suspend()
913 s5pcsis_stop_stream(state); s5pcsis_pm_suspend()
914 ret = phy_power_off(state->phy); s5pcsis_pm_suspend()
918 state->supplies); s5pcsis_pm_suspend()
921 clk_disable(state->clock[CSIS_CLK_GATE]); s5pcsis_pm_suspend()
922 state->flags &= ~ST_POWERED; s5pcsis_pm_suspend()
924 state->flags |= ST_SUSPENDED; s5pcsis_pm_suspend()
927 mutex_unlock(&state->lock); s5pcsis_pm_suspend()
935 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_pm_resume() local
939 __func__, state->flags); s5pcsis_pm_resume()
941 mutex_lock(&state->lock); s5pcsis_pm_resume()
942 if (!runtime && !(state->flags & ST_SUSPENDED)) s5pcsis_pm_resume()
945 if (!(state->flags & ST_POWERED)) { s5pcsis_pm_resume()
947 state->supplies); s5pcsis_pm_resume()
950 ret = phy_power_on(state->phy); s5pcsis_pm_resume()
952 state->flags |= ST_POWERED; s5pcsis_pm_resume()
955 state->supplies); s5pcsis_pm_resume()
958 clk_enable(state->clock[CSIS_CLK_GATE]); s5pcsis_pm_resume()
960 if (state->flags & ST_STREAMING) s5pcsis_pm_resume()
961 s5pcsis_start_stream(state); s5pcsis_pm_resume()
963 state->flags &= ~ST_SUSPENDED; s5pcsis_pm_resume()
965 mutex_unlock(&state->lock); s5pcsis_pm_resume()
996 struct csis_state *state = sd_to_csis_state(sd); s5pcsis_remove() local
1000 clk_disable(state->clock[CSIS_CLK_MUX]); s5pcsis_remove()
1002 s5pcsis_clk_put(state); s5pcsis_remove()
1004 media_entity_cleanup(&state->sd.entity); s5pcsis_remove()
570 __s5pcsis_get_format( struct csis_state *state, struct v4l2_subdev_pad_config *cfg, enum v4l2_subdev_format_whence which) __s5pcsis_get_format() argument
733 s5pcsis_parse_dt(struct platform_device *pdev, struct csis_state *state) s5pcsis_parse_dt() argument
/linux-4.1.27/include/linux/pinctrl/
H A Dpinctrl-state.h2 * Standard pin control state definitions
6 * @PINCTRL_STATE_DEFAULT: the state the pinctrl handle shall be put
8 * be used by the device driver. This state is commonly used by
9 * hogs to configure muxing and pins at boot, and also as a state
12 * @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into
13 * when the pins are idle. This is a state where the system is relaxed
17 * @PINCTRL_STATE_SLEEP: the state the pinctrl handle shall be put into
18 * when the pins are sleeping. This is a state where the system is in
19 * its lowest sleep state. Could typically be set from an
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_atomic_plane.c30 * atomic state infrastructure and perform plane updates as separate
40 * intel_create_plane_state - create plane state object
43 * Allocates a fresh plane state for the given plane and sets some of
44 * the state values to sensible initial values.
46 * Returns: A newly allocated plane state, or NULL on failure
51 struct intel_plane_state *state; intel_create_plane_state() local
53 state = kzalloc(sizeof(*state), GFP_KERNEL); intel_create_plane_state()
54 if (!state) intel_create_plane_state()
57 state->base.plane = plane; intel_create_plane_state()
58 state->base.rotation = BIT(DRM_ROTATE_0); intel_create_plane_state()
60 return state; intel_create_plane_state()
64 * intel_plane_duplicate_state - duplicate plane state
67 * Allocates and returns a copy of the plane state (both common and
70 * Returns: The newly allocated plane state, or NULL on failure.
75 struct drm_plane_state *state; intel_plane_duplicate_state() local
78 if (WARN_ON(!plane->state)) intel_plane_duplicate_state()
81 intel_state = kmemdup(plane->state, sizeof(*intel_state), intel_plane_duplicate_state()
87 state = &intel_state->base; intel_plane_duplicate_state()
88 if (state->fb) intel_plane_duplicate_state()
89 drm_framebuffer_reference(state->fb); intel_plane_duplicate_state()
91 return state; intel_plane_duplicate_state()
95 * intel_plane_destroy_state - destroy plane state
97 * @state: state object to destroy
99 * Destroys the plane state (both common and Intel-specific) for the
104 struct drm_plane_state *state) intel_plane_destroy_state()
106 drm_atomic_helper_plane_destroy_state(plane, state); intel_plane_destroy_state()
110 struct drm_plane_state *state) intel_plane_atomic_check()
112 struct drm_crtc *crtc = state->crtc; intel_plane_atomic_check()
115 struct intel_plane_state *intel_state = to_intel_plane_state(state); intel_plane_atomic_check()
130 * The original src/dest coordinates are stored in state->base, but intel_plane_atomic_check()
134 intel_state->src.x1 = state->src_x; intel_plane_atomic_check()
135 intel_state->src.y1 = state->src_y; intel_plane_atomic_check()
136 intel_state->src.x2 = state->src_x + state->src_w; intel_plane_atomic_check()
137 intel_state->src.y2 = state->src_y + state->src_h; intel_plane_atomic_check()
138 intel_state->dst.x1 = state->crtc_x; intel_plane_atomic_check()
139 intel_state->dst.y1 = state->crtc_y; intel_plane_atomic_check()
140 intel_state->dst.x2 = state->crtc_x + state->crtc_w; intel_plane_atomic_check()
141 intel_state->dst.y2 = state->crtc_y + state->crtc_h; intel_plane_atomic_check()
156 if (state->fb == NULL && plane->state->fb != NULL) { intel_plane_atomic_check()
173 to_intel_plane_state(plane->state); intel_plane_atomic_update()
176 if (!plane->state->fb && !old_state->fb) intel_plane_atomic_update()
192 * @state: state containing the property value
202 const struct drm_plane_state *state, intel_plane_atomic_get_property()
213 * @state: state to update property value in
218 * state object.
224 struct drm_plane_state *state, intel_plane_atomic_set_property()
103 intel_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) intel_plane_destroy_state() argument
109 intel_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) intel_plane_atomic_check() argument
201 intel_plane_atomic_get_property(struct drm_plane *plane, const struct drm_plane_state *state, struct drm_property *property, uint64_t *val) intel_plane_atomic_get_property() argument
223 intel_plane_atomic_set_property(struct drm_plane *plane, struct drm_plane_state *state, struct drm_property *property, uint64_t val) intel_plane_atomic_set_property() argument
H A Dintel_atomic.c27 * The functions here implement the state management and hardware programming
40 * intel_atomic_check - validate state object
42 * @state: state to validate
45 struct drm_atomic_state *state) intel_atomic_check()
60 struct intel_plane *plane = to_intel_plane(state->planes[i]); intel_atomic_check()
76 state->allow_modeset = false; intel_atomic_check()
78 struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]); intel_atomic_check()
83 if (state->connectors[i] != NULL) intel_atomic_check()
91 ret = drm_atomic_helper_check_planes(dev, state); intel_atomic_check()
100 * intel_atomic_commit - commit validated state object
102 * @state: the top-level driver state object
105 * This function commits a top-level state object that has been validated
116 struct drm_atomic_state *state, intel_atomic_commit()
127 ret = drm_atomic_helper_prepare_planes(dev, state); intel_atomic_commit()
136 * drm_atomic_helper_swap_state(dev, state) intel_atomic_commit()
137 * drm_atomic_helper_commit_modeset_disables(dev, state); intel_atomic_commit()
138 * drm_atomic_helper_commit_planes(dev, state); intel_atomic_commit()
139 * drm_atomic_helper_commit_modeset_enables(dev, state); intel_atomic_commit()
140 * drm_atomic_helper_wait_for_vblanks(dev, state); intel_atomic_commit()
141 * drm_atomic_helper_cleanup_planes(dev, state); intel_atomic_commit()
142 * drm_atomic_state_free(state); intel_atomic_commit()
149 struct drm_plane *plane = state->planes[i]; intel_atomic_commit()
154 plane->state->state = state; intel_atomic_commit()
155 swap(state->plane_states[i], plane->state); intel_atomic_commit()
156 plane->state->state = NULL; intel_atomic_commit()
158 drm_atomic_helper_commit_planes(dev, state); intel_atomic_commit()
159 drm_atomic_helper_wait_for_vblanks(dev, state); intel_atomic_commit()
160 drm_atomic_helper_cleanup_planes(dev, state); intel_atomic_commit()
161 drm_atomic_state_free(state); intel_atomic_commit()
169 * @state: state containing the property value
179 const struct drm_connector_state *state, intel_connector_atomic_get_property()
191 * When the crtc/connector state work matures, this function should intel_connector_atomic_get_property()
192 * be updated to read the values out of the state structure instead. intel_connector_atomic_get_property()
205 * intel_crtc_duplicate_state - duplicate crtc state
208 * Allocates and returns a copy of the crtc state (both common and
211 * Returns: The newly allocated crtc state, or NULL on failure.
232 * intel_crtc_destroy_state - destroy crtc state
235 * Destroys the crtc state (both common and Intel-specific) for the
240 struct drm_crtc_state *state) intel_crtc_destroy_state()
242 drm_atomic_helper_crtc_destroy_state(crtc, state); intel_crtc_destroy_state()
44 intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) intel_atomic_check() argument
115 intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, bool async) intel_atomic_commit() argument
178 intel_connector_atomic_get_property(struct drm_connector *connector, const struct drm_connector_state *state, struct drm_property *property, uint64_t *val) intel_connector_atomic_get_property() argument
239 intel_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) intel_crtc_destroy_state() argument
/linux-4.1.27/drivers/media/pci/pt1/
H A Dva1j5jf8007s.c53 struct va1j5jf8007s_state *state; va1j5jf8007s_read_snr() local
60 state = fe->demodulator_priv; va1j5jf8007s_read_snr()
61 addr = state->config->demod_address; va1j5jf8007s_read_snr()
77 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007s_read_snr()
113 struct va1j5jf8007s_state *state; va1j5jf8007s_read_status() local
115 state = fe->demodulator_priv; va1j5jf8007s_read_status()
117 switch (state->tune_state) { va1j5jf8007s_read_status()
174 static int va1j5jf8007s_set_frequency_1(struct va1j5jf8007s_state *state) va1j5jf8007s_set_frequency_1() argument
181 frequency = state->fe.dtv_property_cache.frequency; va1j5jf8007s_set_frequency_1()
194 msg.addr = state->config->demod_address; va1j5jf8007s_set_frequency_1()
199 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_set_frequency_1()
205 static int va1j5jf8007s_set_frequency_2(struct va1j5jf8007s_state *state) va1j5jf8007s_set_frequency_2() argument
214 msg.addr = state->config->demod_address; va1j5jf8007s_set_frequency_2()
219 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_set_frequency_2()
225 static int va1j5jf8007s_set_frequency_3(struct va1j5jf8007s_state *state) va1j5jf8007s_set_frequency_3() argument
231 frequency = state->fe.dtv_property_cache.frequency; va1j5jf8007s_set_frequency_3()
238 msg.addr = state->config->demod_address; va1j5jf8007s_set_frequency_3()
243 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_set_frequency_3()
250 va1j5jf8007s_check_frequency(struct va1j5jf8007s_state *state, int *lock) va1j5jf8007s_check_frequency() argument
256 addr = state->config->demod_address; va1j5jf8007s_check_frequency()
271 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007s_check_frequency()
278 static int va1j5jf8007s_set_modulation(struct va1j5jf8007s_state *state) va1j5jf8007s_set_modulation() argument
286 msg.addr = state->config->demod_address; va1j5jf8007s_set_modulation()
291 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_set_modulation()
298 va1j5jf8007s_check_modulation(struct va1j5jf8007s_state *state, int *lock) va1j5jf8007s_check_modulation() argument
304 addr = state->config->demod_address; va1j5jf8007s_check_modulation()
318 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007s_check_modulation()
326 va1j5jf8007s_set_ts_id(struct va1j5jf8007s_state *state) va1j5jf8007s_set_ts_id() argument
332 ts_id = state->fe.dtv_property_cache.stream_id; va1j5jf8007s_set_ts_id()
340 msg.addr = state->config->demod_address; va1j5jf8007s_set_ts_id()
345 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_set_ts_id()
352 va1j5jf8007s_check_ts_id(struct va1j5jf8007s_state *state, int *lock) va1j5jf8007s_check_ts_id() argument
359 ts_id = state->fe.dtv_property_cache.stream_id; va1j5jf8007s_check_ts_id()
365 addr = state->config->demod_address; va1j5jf8007s_check_ts_id()
379 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007s_check_ts_id()
392 struct va1j5jf8007s_state *state; va1j5jf8007s_tune() local
396 state = fe->demodulator_priv; va1j5jf8007s_tune()
399 state->tune_state = VA1J5JF8007S_SET_FREQUENCY_1; va1j5jf8007s_tune()
401 switch (state->tune_state) { va1j5jf8007s_tune()
408 ret = va1j5jf8007s_set_frequency_1(state); va1j5jf8007s_tune()
412 state->tune_state = VA1J5JF8007S_SET_FREQUENCY_2; va1j5jf8007s_tune()
418 ret = va1j5jf8007s_set_frequency_2(state); va1j5jf8007s_tune()
422 state->tune_state = VA1J5JF8007S_SET_FREQUENCY_3; va1j5jf8007s_tune()
428 ret = va1j5jf8007s_set_frequency_3(state); va1j5jf8007s_tune()
432 state->tune_state = VA1J5JF8007S_CHECK_FREQUENCY; va1j5jf8007s_tune()
438 ret = va1j5jf8007s_check_frequency(state, &lock); va1j5jf8007s_tune()
448 state->tune_state = VA1J5JF8007S_SET_MODULATION; va1j5jf8007s_tune()
454 ret = va1j5jf8007s_set_modulation(state); va1j5jf8007s_tune()
458 state->tune_state = VA1J5JF8007S_CHECK_MODULATION; va1j5jf8007s_tune()
464 ret = va1j5jf8007s_check_modulation(state, &lock); va1j5jf8007s_tune()
474 state->tune_state = VA1J5JF8007S_SET_TS_ID; va1j5jf8007s_tune()
480 ret = va1j5jf8007s_set_ts_id(state); va1j5jf8007s_tune()
484 state->tune_state = VA1J5JF8007S_CHECK_TS_ID; va1j5jf8007s_tune()
488 ret = va1j5jf8007s_check_ts_id(state, &lock); va1j5jf8007s_tune()
498 state->tune_state = VA1J5JF8007S_TRACK; va1j5jf8007s_tune()
510 static int va1j5jf8007s_init_frequency(struct va1j5jf8007s_state *state) va1j5jf8007s_init_frequency() argument
520 msg.addr = state->config->demod_address; va1j5jf8007s_init_frequency()
525 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_init_frequency()
531 static int va1j5jf8007s_set_sleep(struct va1j5jf8007s_state *state, int sleep) va1j5jf8007s_set_sleep() argument
539 msg.addr = state->config->demod_address; va1j5jf8007s_set_sleep()
544 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_set_sleep()
552 struct va1j5jf8007s_state *state; va1j5jf8007s_sleep() local
555 state = fe->demodulator_priv; va1j5jf8007s_sleep()
557 ret = va1j5jf8007s_init_frequency(state); va1j5jf8007s_sleep()
561 return va1j5jf8007s_set_sleep(state, 1); va1j5jf8007s_sleep()
566 struct va1j5jf8007s_state *state; va1j5jf8007s_init() local
568 state = fe->demodulator_priv; va1j5jf8007s_init()
569 state->tune_state = VA1J5JF8007S_IDLE; va1j5jf8007s_init()
571 return va1j5jf8007s_set_sleep(state, 0); va1j5jf8007s_init()
576 struct va1j5jf8007s_state *state; va1j5jf8007s_release() local
577 state = fe->demodulator_priv; va1j5jf8007s_release()
578 kfree(state); va1j5jf8007s_release()
603 static int va1j5jf8007s_prepare_1(struct va1j5jf8007s_state *state) va1j5jf8007s_prepare_1() argument
609 addr = state->config->demod_address; va1j5jf8007s_prepare_1()
623 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007s_prepare_1()
646 static int va1j5jf8007s_prepare_2(struct va1j5jf8007s_state *state) va1j5jf8007s_prepare_2() argument
655 switch (state->config->frequency) { va1j5jf8007s_prepare_2()
668 addr = state->config->demod_address; va1j5jf8007s_prepare_2()
676 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007s_prepare_2()
686 struct va1j5jf8007s_state *state; va1j5jf8007s_prepare() local
689 state = fe->demodulator_priv; va1j5jf8007s_prepare()
691 ret = va1j5jf8007s_prepare_1(state); va1j5jf8007s_prepare()
695 ret = va1j5jf8007s_prepare_2(state); va1j5jf8007s_prepare()
699 return va1j5jf8007s_init_frequency(state); va1j5jf8007s_prepare()
706 struct va1j5jf8007s_state *state; va1j5jf8007s_attach() local
711 state = kzalloc(sizeof(struct va1j5jf8007s_state), GFP_KERNEL); va1j5jf8007s_attach()
712 if (!state) va1j5jf8007s_attach()
715 state->config = config; va1j5jf8007s_attach()
716 state->adap = adap; va1j5jf8007s_attach()
718 fe = &state->fe; va1j5jf8007s_attach()
720 fe->demodulator_priv = state; va1j5jf8007s_attach()
725 msg.addr = state->config->demod_address; va1j5jf8007s_attach()
730 if (i2c_transfer(state->adap, &msg, 1) != 1) { va1j5jf8007s_attach()
731 kfree(state); va1j5jf8007s_attach()
H A Dva1j5jf8007t.c51 struct va1j5jf8007t_state *state; va1j5jf8007t_read_snr() local
58 state = fe->demodulator_priv; va1j5jf8007t_read_snr()
59 addr = state->config->demod_address; va1j5jf8007t_read_snr()
75 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007t_read_snr()
103 struct va1j5jf8007t_state *state; va1j5jf8007t_read_status() local
105 state = fe->demodulator_priv; va1j5jf8007t_read_status()
107 switch (state->tune_state) { va1j5jf8007t_read_status()
160 static int va1j5jf8007t_set_frequency(struct va1j5jf8007t_state *state) va1j5jf8007t_set_frequency() argument
167 frequency = state->fe.dtv_property_cache.frequency; va1j5jf8007t_set_frequency()
177 msg.addr = state->config->demod_address; va1j5jf8007t_set_frequency()
182 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007t_set_frequency()
189 va1j5jf8007t_check_frequency(struct va1j5jf8007t_state *state, int *lock) va1j5jf8007t_check_frequency() argument
195 addr = state->config->demod_address; va1j5jf8007t_check_frequency()
210 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007t_check_frequency()
217 static int va1j5jf8007t_set_modulation(struct va1j5jf8007t_state *state) va1j5jf8007t_set_modulation() argument
225 msg.addr = state->config->demod_address; va1j5jf8007t_set_modulation()
230 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007t_set_modulation()
236 static int va1j5jf8007t_check_modulation(struct va1j5jf8007t_state *state, va1j5jf8007t_check_modulation() argument
243 addr = state->config->demod_address; va1j5jf8007t_check_modulation()
257 if (i2c_transfer(state->adap, msgs, 2) != 2) va1j5jf8007t_check_modulation()
271 struct va1j5jf8007t_state *state; va1j5jf8007t_tune() local
275 state = fe->demodulator_priv; va1j5jf8007t_tune()
278 state->tune_state = VA1J5JF8007T_SET_FREQUENCY; va1j5jf8007t_tune()
280 switch (state->tune_state) { va1j5jf8007t_tune()
287 ret = va1j5jf8007t_set_frequency(state); va1j5jf8007t_tune()
291 state->tune_state = VA1J5JF8007T_CHECK_FREQUENCY; va1j5jf8007t_tune()
297 ret = va1j5jf8007t_check_frequency(state, &lock); va1j5jf8007t_tune()
307 state->tune_state = VA1J5JF8007T_SET_MODULATION; va1j5jf8007t_tune()
313 ret = va1j5jf8007t_set_modulation(state); va1j5jf8007t_tune()
317 state->tune_state = VA1J5JF8007T_CHECK_MODULATION; va1j5jf8007t_tune()
323 ret = va1j5jf8007t_check_modulation(state, &lock, &retry); va1j5jf8007t_tune()
329 state->tune_state = VA1J5JF8007T_ABORT; va1j5jf8007t_tune()
339 state->tune_state = VA1J5JF8007T_TRACK; va1j5jf8007t_tune()
356 static int va1j5jf8007t_init_frequency(struct va1j5jf8007t_state *state) va1j5jf8007t_init_frequency() argument
369 msg.addr = state->config->demod_address; va1j5jf8007t_init_frequency()
374 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007t_init_frequency()
380 static int va1j5jf8007t_set_sleep(struct va1j5jf8007t_state *state, int sleep) va1j5jf8007t_set_sleep() argument
388 msg.addr = state->config->demod_address; va1j5jf8007t_set_sleep()
393 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007t_set_sleep()
401 struct va1j5jf8007t_state *state; va1j5jf8007t_sleep() local
404 state = fe->demodulator_priv; va1j5jf8007t_sleep()
406 ret = va1j5jf8007t_init_frequency(state); va1j5jf8007t_sleep()
410 return va1j5jf8007t_set_sleep(state, 1); va1j5jf8007t_sleep()
415 struct va1j5jf8007t_state *state; va1j5jf8007t_init() local
417 state = fe->demodulator_priv; va1j5jf8007t_init()
418 state->tune_state = VA1J5JF8007T_IDLE; va1j5jf8007t_init()
420 return va1j5jf8007t_set_sleep(state, 0); va1j5jf8007t_init()
425 struct va1j5jf8007t_state *state; va1j5jf8007t_release() local
426 state = fe->demodulator_priv; va1j5jf8007t_release()
427 kfree(state); va1j5jf8007t_release()
466 struct va1j5jf8007t_state *state; va1j5jf8007t_prepare() local
473 state = fe->demodulator_priv; va1j5jf8007t_prepare()
475 switch (state->config->frequency) { va1j5jf8007t_prepare()
488 msg.addr = state->config->demod_address; va1j5jf8007t_prepare()
495 if (i2c_transfer(state->adap, &msg, 1) != 1) va1j5jf8007t_prepare()
499 return va1j5jf8007t_init_frequency(state); va1j5jf8007t_prepare()
506 struct va1j5jf8007t_state *state; va1j5jf8007t_attach() local
511 state = kzalloc(sizeof(struct va1j5jf8007t_state), GFP_KERNEL); va1j5jf8007t_attach()
512 if (!state) va1j5jf8007t_attach()
515 state->config = config; va1j5jf8007t_attach()
516 state->adap = adap; va1j5jf8007t_attach()
518 fe = &state->fe; va1j5jf8007t_attach()
520 fe->demodulator_priv = state; va1j5jf8007t_attach()
525 msg.addr = state->config->demod_address; va1j5jf8007t_attach()
530 if (i2c_transfer(state->adap, &msg, 1) != 1) { va1j5jf8007t_attach()
531 kfree(state); va1j5jf8007t_attach()
/linux-4.1.27/include/crypto/
H A Dsha256_base.h25 sctx->state[0] = SHA224_H0; sha224_base_init()
26 sctx->state[1] = SHA224_H1; sha224_base_init()
27 sctx->state[2] = SHA224_H2; sha224_base_init()
28 sctx->state[3] = SHA224_H3; sha224_base_init()
29 sctx->state[4] = SHA224_H4; sha224_base_init()
30 sctx->state[5] = SHA224_H5; sha224_base_init()
31 sctx->state[6] = SHA224_H6; sha224_base_init()
32 sctx->state[7] = SHA224_H7; sha224_base_init()
42 sctx->state[0] = SHA256_H0; sha256_base_init()
43 sctx->state[1] = SHA256_H1; sha256_base_init()
44 sctx->state[2] = SHA256_H2; sha256_base_init()
45 sctx->state[3] = SHA256_H3; sha256_base_init()
46 sctx->state[4] = SHA256_H4; sha256_base_init()
47 sctx->state[5] = SHA256_H5; sha256_base_init()
48 sctx->state[6] = SHA256_H6; sha256_base_init()
49 sctx->state[7] = SHA256_H7; sha256_base_init()
124 put_unaligned_be32(sctx->state[i], digest++); sha256_base_finish()
H A Dsha512_base.h25 sctx->state[0] = SHA384_H0; sha384_base_init()
26 sctx->state[1] = SHA384_H1; sha384_base_init()
27 sctx->state[2] = SHA384_H2; sha384_base_init()
28 sctx->state[3] = SHA384_H3; sha384_base_init()
29 sctx->state[4] = SHA384_H4; sha384_base_init()
30 sctx->state[5] = SHA384_H5; sha384_base_init()
31 sctx->state[6] = SHA384_H6; sha384_base_init()
32 sctx->state[7] = SHA384_H7; sha384_base_init()
42 sctx->state[0] = SHA512_H0; sha512_base_init()
43 sctx->state[1] = SHA512_H1; sha512_base_init()
44 sctx->state[2] = SHA512_H2; sha512_base_init()
45 sctx->state[3] = SHA512_H3; sha512_base_init()
46 sctx->state[4] = SHA512_H4; sha512_base_init()
47 sctx->state[5] = SHA512_H5; sha512_base_init()
48 sctx->state[6] = SHA512_H6; sha512_base_init()
49 sctx->state[7] = SHA512_H7; sha512_base_init()
127 put_unaligned_be64(sctx->state[i], digest++); sha512_base_finish()
/linux-4.1.27/net/802/
H A Dgarp.c30 u8 state; member in struct:garp_state_trans
34 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_AA,
36 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_AA },
37 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VA },
38 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VA },
39 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VA },
40 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VP },
41 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_INVALID },
42 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_LA },
45 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_QA,
47 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_QA },
48 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VA },
49 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VA },
50 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VA },
51 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VP },
52 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_INVALID },
53 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_LA },
56 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_INVALID },
57 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_QA },
58 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VA },
59 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VA },
60 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VP },
61 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VP },
62 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_INVALID },
63 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_LA },
66 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_VO,
68 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_LA },
69 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VO },
70 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_LA },
71 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_LA },
72 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VO },
73 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_VA },
74 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_INVALID },
77 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_AA,
79 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_AP },
80 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VP },
81 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VP },
82 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VP },
83 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VP },
84 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_INVALID },
85 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_VO },
88 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_QA,
90 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_QP },
91 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VP },
92 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VP },
93 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VP },
94 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VP },
95 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_INVALID },
96 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_AO },
99 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_INVALID },
100 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_QP },
101 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VP },
102 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VP },
103 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VP },
104 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VP },
105 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_INVALID },
106 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_QO },
109 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_INVALID },
110 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_AO },
111 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VO },
112 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VO },
113 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VO },
114 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VO },
115 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_VP },
116 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_INVALID },
119 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_INVALID },
120 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_QO },
121 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VO },
122 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VO },
123 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VO },
124 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VO },
125 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_AP },
126 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_INVALID },
129 [GARP_EVENT_TRANSMIT_PDU] = { .state = GARP_APPLICANT_INVALID },
130 [GARP_EVENT_R_JOIN_IN] = { .state = GARP_APPLICANT_QO },
131 [GARP_EVENT_R_JOIN_EMPTY] = { .state = GARP_APPLICANT_VO },
132 [GARP_EVENT_R_EMPTY] = { .state = GARP_APPLICANT_VO },
133 [GARP_EVENT_R_LEAVE_IN] = { .state = GARP_APPLICANT_VO },
134 [GARP_EVENT_R_LEAVE_EMPTY] = { .state = GARP_APPLICANT_VO },
135 [GARP_EVENT_REQ_JOIN] = { .state = GARP_APPLICANT_QP },
136 [GARP_EVENT_REQ_LEAVE] = { .state = GARP_APPLICANT_INVALID },
193 attr->state = GARP_APPLICANT_VO; garp_attr_create()
316 enum garp_applicant_state state; garp_attr_event() local
318 state = garp_applicant_state_table[attr->state][event].state; garp_attr_event()
319 if (state == GARP_APPLICANT_INVALID) garp_attr_event()
322 switch (garp_applicant_state_table[attr->state][event].action) { garp_attr_event()
326 /* When appending the attribute fails, don't update state in garp_attr_event()
341 attr->state = state; garp_attr_event()
/linux-4.1.27/tools/usb/ffs-aio-example/simple/host_app/
H A Dtest.c39 * struct test_state - describes test program state
59 int test_init(struct test_state *state) test_init() argument
65 state->found = NULL; test_init()
66 state->ctx = NULL; test_init()
67 state->handle = NULL; test_init()
68 state->attached = 0; test_init()
70 ret = libusb_init(&state->ctx); test_init()
76 cnt = libusb_get_device_list(state->ctx, &list); test_init()
92 state->found = dev; test_init()
97 if (!state->found) { test_init()
102 ret = libusb_open(state->found, &state->handle); test_init()
108 if (libusb_claim_interface(state->handle, 0)) { test_init()
109 ret = libusb_detach_kernel_driver(state->handle, 0); test_init()
115 state->attached = 1; test_init()
116 ret = libusb_claim_interface(state->handle, 0); test_init()
127 if (state->attached == 1) test_init()
128 libusb_attach_kernel_driver(state->handle, 0); test_init()
131 libusb_close(state->handle); test_init()
137 libusb_exit(state->ctx); test_init()
145 void test_exit(struct test_state *state) test_exit() argument
147 libusb_release_interface(state->handle, 0); test_exit()
148 if (state->attached == 1) test_exit()
149 libusb_attach_kernel_driver(state->handle, 0); test_exit()
150 libusb_close(state->handle); test_exit()
151 libusb_exit(state->ctx); test_exit()
156 struct test_state state; main() local
161 if (test_init(&state)) main()
164 libusb_get_config_descriptor(state.found, 0, &conf); main()
172 libusb_bulk_transfer(state.handle, in_addr, buffer, BUF_LEN, main()
174 libusb_bulk_transfer(state.handle, out_addr, buffer, BUF_LEN, main()
177 test_exit(&state); main()
/linux-4.1.27/drivers/scsi/
H A Dmac53c94.c71 struct fsc_state *state; mac53c94_queue_lck() local
88 state = (struct fsc_state *) cmd->device->host->hostdata; mac53c94_queue_lck()
90 if (state->request_q == NULL) mac53c94_queue_lck()
91 state->request_q = cmd; mac53c94_queue_lck()
93 state->request_qtail->host_scribble = (void *) cmd; mac53c94_queue_lck()
94 state->request_qtail = cmd; mac53c94_queue_lck()
96 if (state->phase == idle) mac53c94_queue_lck()
97 mac53c94_start(state); mac53c94_queue_lck()
106 struct fsc_state *state = (struct fsc_state *) cmd->device->host->hostdata; mac53c94_host_reset() local
107 struct mac53c94_regs __iomem *regs = state->regs; mac53c94_host_reset()
108 struct dbdma_regs __iomem *dma = state->dma; mac53c94_host_reset()
118 mac53c94_init(state); mac53c94_host_reset()
125 static void mac53c94_init(struct fsc_state *state) mac53c94_init() argument
127 struct mac53c94_regs __iomem *regs = state->regs; mac53c94_init()
128 struct dbdma_regs __iomem *dma = state->dma; mac53c94_init()
131 writeb(state->host->this_id | CF1_PAR_ENABLE, &regs->config1); mac53c94_init()
133 writeb(CLKF_VAL(state->clk_freq), &regs->clk_factor); mac53c94_init()
146 static void mac53c94_start(struct fsc_state *state) mac53c94_start() argument
149 struct mac53c94_regs __iomem *regs = state->regs; mac53c94_start()
152 if (state->phase != idle || state->current_req != NULL) mac53c94_start()
153 panic("inappropriate mac53c94_start (state=%p)", state); mac53c94_start()
154 if (state->request_q == NULL) mac53c94_start()
156 state->current_req = cmd = state->request_q; mac53c94_start()
157 state->request_q = (struct scsi_cmnd *) cmd->host_scribble; mac53c94_start()
177 state->phase = selecting; mac53c94_start()
179 set_dma_cmds(state, cmd); mac53c94_start()
195 struct fsc_state *state = (struct fsc_state *) dev_id; mac53c94_interrupt() local
196 struct mac53c94_regs __iomem *regs = state->regs; mac53c94_interrupt()
197 struct dbdma_regs __iomem *dma = state->dma; mac53c94_interrupt()
198 struct scsi_cmnd *cmd = state->current_req; mac53c94_interrupt()
212 intr, stat, seq, state->phase); mac53c94_interrupt()
220 cmd_done(state, DID_RESET << 16); mac53c94_interrupt()
225 intr, stat, seq, state->phase); mac53c94_interrupt()
226 cmd_done(state, DID_ERROR << 16); mac53c94_interrupt()
233 intr, stat, seq, state->phase); mac53c94_interrupt()
244 cmd_done(state, DID_PARITY << 16); mac53c94_interrupt()
247 switch (state->phase) { mac53c94_interrupt()
251 cmd_done(state, DID_BAD_TARGET << 16); mac53c94_interrupt()
256 cmd_done(state, DID_ERROR << 16); mac53c94_interrupt()
261 cmd_done(state, DID_ERROR << 16); mac53c94_interrupt()
275 writel(virt_to_phys(state->dma_cmds), &dma->cmdptr); mac53c94_interrupt()
278 state->phase = dataing; mac53c94_interrupt()
283 state->phase = completing; mac53c94_interrupt()
287 cmd_done(state, DID_ERROR << 16); mac53c94_interrupt()
295 cmd_done(state, DID_ERROR << 16); mac53c94_interrupt()
318 state->phase = completing; mac53c94_interrupt()
323 cmd_done(state, DID_ERROR << 16); mac53c94_interrupt()
330 state->phase = busfreeing; mac53c94_interrupt()
336 cmd_done(state, (DID_OK << 16) + (cmd->SCp.Message << 8) mac53c94_interrupt()
340 printk(KERN_DEBUG "don't know about phase %d\n", state->phase); mac53c94_interrupt()
344 static void cmd_done(struct fsc_state *state, int result) cmd_done() argument
348 cmd = state->current_req; cmd_done()
352 state->current_req = NULL; cmd_done()
354 state->phase = idle; cmd_done()
355 mac53c94_start(state); cmd_done()
361 static void set_dma_cmds(struct fsc_state *state, struct scsi_cmnd *cmd) set_dma_cmds() argument
376 dcmds = state->dma_cmds; set_dma_cmds()
414 struct fsc_state *state; mac53c94_probe() local
439 state = (struct fsc_state *) host->hostdata; mac53c94_probe()
440 macio_set_drvdata(mdev, state); mac53c94_probe()
441 state->host = host; mac53c94_probe()
442 state->pdev = pdev; mac53c94_probe()
443 state->mdev = mdev; mac53c94_probe()
445 state->regs = (struct mac53c94_regs __iomem *) mac53c94_probe()
447 state->intr = macio_irq(mdev, 0); mac53c94_probe()
448 state->dma = (struct dbdma_regs __iomem *) mac53c94_probe()
450 state->dmaintr = macio_irq(mdev, 1); mac53c94_probe()
451 if (state->regs == NULL || state->dma == NULL) { mac53c94_probe()
461 state->clk_freq = 25000000; mac53c94_probe()
463 state->clk_freq = *(int *)clkprop; mac53c94_probe()
477 state->dma_cmds = (struct dbdma_cmd *)DBDMA_ALIGN(dma_cmd_space); mac53c94_probe()
478 memset(state->dma_cmds, 0, (host->sg_tablesize + 1) mac53c94_probe()
480 state->dma_cmd_space = dma_cmd_space; mac53c94_probe()
482 mac53c94_init(state); mac53c94_probe()
484 if (request_irq(state->intr, do_mac53c94_interrupt, 0, "53C94",state)) { mac53c94_probe()
486 state->intr, node->full_name); mac53c94_probe()
498 free_irq(state->intr, state); mac53c94_probe()
500 kfree(state->dma_cmd_space); mac53c94_probe()
502 if (state->dma != NULL) mac53c94_probe()
503 iounmap(state->dma); mac53c94_probe()
504 if (state->regs != NULL) mac53c94_probe()
505 iounmap(state->regs); mac53c94_probe()
/linux-4.1.27/arch/s390/crypto/
H A Dsha256_s390.c28 sctx->state[0] = SHA256_H0; sha256_init()
29 sctx->state[1] = SHA256_H1; sha256_init()
30 sctx->state[2] = SHA256_H2; sha256_init()
31 sctx->state[3] = SHA256_H3; sha256_init()
32 sctx->state[4] = SHA256_H4; sha256_init()
33 sctx->state[5] = SHA256_H5; sha256_init()
34 sctx->state[6] = SHA256_H6; sha256_init()
35 sctx->state[7] = SHA256_H7; sha256_init()
48 memcpy(octx->state, sctx->state, sizeof(octx->state)); sha256_export()
59 memcpy(sctx->state, ictx->state, sizeof(ictx->state)); sha256_import()
88 sctx->state[0] = SHA224_H0; sha224_init()
89 sctx->state[1] = SHA224_H1; sha224_init()
90 sctx->state[2] = SHA224_H2; sha224_init()
91 sctx->state[3] = SHA224_H3; sha224_init()
92 sctx->state[4] = SHA224_H4; sha224_init()
93 sctx->state[5] = SHA224_H5; sha224_init()
94 sctx->state[6] = SHA224_H6; sha224_init()
95 sctx->state[7] = SHA224_H7; sha224_init()
H A Dsha512_s390.c29 *(__u64 *)&ctx->state[0] = 0x6a09e667f3bcc908ULL; sha512_init()
30 *(__u64 *)&ctx->state[2] = 0xbb67ae8584caa73bULL; sha512_init()
31 *(__u64 *)&ctx->state[4] = 0x3c6ef372fe94f82bULL; sha512_init()
32 *(__u64 *)&ctx->state[6] = 0xa54ff53a5f1d36f1ULL; sha512_init()
33 *(__u64 *)&ctx->state[8] = 0x510e527fade682d1ULL; sha512_init()
34 *(__u64 *)&ctx->state[10] = 0x9b05688c2b3e6c1fULL; sha512_init()
35 *(__u64 *)&ctx->state[12] = 0x1f83d9abfb41bd6bULL; sha512_init()
36 *(__u64 *)&ctx->state[14] = 0x5be0cd19137e2179ULL; sha512_init()
50 memcpy(octx->state, sctx->state, sizeof(octx->state)); sha512_export()
64 memcpy(sctx->state, ictx->state, sizeof(ictx->state)); sha512_import()
95 *(__u64 *)&ctx->state[0] = 0xcbbb9d5dc1059ed8ULL; sha384_init()
96 *(__u64 *)&ctx->state[2] = 0x629a292a367cd507ULL; sha384_init()
97 *(__u64 *)&ctx->state[4] = 0x9159015a3070dd17ULL; sha384_init()
98 *(__u64 *)&ctx->state[6] = 0x152fecd8f70e5939ULL; sha384_init()
99 *(__u64 *)&ctx->state[8] = 0x67332667ffc00b31ULL; sha384_init()
100 *(__u64 *)&ctx->state[10] = 0x8eb44a8768581511ULL; sha384_init()
101 *(__u64 *)&ctx->state[12] = 0xdb0c2e0d64f98fa7ULL; sha384_init()
102 *(__u64 *)&ctx->state[14] = 0x47b5481dbefa4fa4ULL; sha384_init()
H A Dsha1_s390.c38 sctx->state[0] = SHA1_H0; sha1_init()
39 sctx->state[1] = SHA1_H1; sha1_init()
40 sctx->state[2] = SHA1_H2; sha1_init()
41 sctx->state[3] = SHA1_H3; sha1_init()
42 sctx->state[4] = SHA1_H4; sha1_init()
55 memcpy(octx->state, sctx->state, sizeof(octx->state)); sha1_export()
66 memcpy(sctx->state, ictx->state, sizeof(ictx->state)); sha1_import()
/linux-4.1.27/include/trace/events/
H A Dpower.h16 TP_PROTO(unsigned int state, unsigned int cpu_id),
18 TP_ARGS(state, cpu_id),
21 __field( u32, state )
26 __entry->state = state;
30 TP_printk("state=%lu cpu_id=%lu", (unsigned long)__entry->state,
36 TP_PROTO(unsigned int state, unsigned int cpu_id),
38 TP_ARGS(state, cpu_id)
45 u32 state,
53 state,
62 __field(u32, state)
72 __entry->state = state;
78 TP_printk("core_busy=%lu scaled=%lu state=%lu mperf=%llu aperf=%llu freq=%lu ",
81 (unsigned long)__entry->state,
188 TP_PROTO(const char *name, unsigned int state),
190 TP_ARGS(name, state),
194 __field( u64, state )
199 __entry->state = state;
202 TP_printk("%s state=0x%lx", __get_str(name),
203 (unsigned long)__entry->state)
208 TP_PROTO(const char *name, unsigned int state),
210 TP_ARGS(name, state)
215 TP_PROTO(const char *name, unsigned int state),
217 TP_ARGS(name, state)
226 TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
228 TP_ARGS(name, state, cpu_id),
232 __field( u64, state )
238 __entry->state = state;
242 TP_printk("%s state=%lu cpu_id=%lu", __get_str(name),
243 (unsigned long)__entry->state, (unsigned long)__entry->cpu_id)
248 TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
250 TP_ARGS(name, state, cpu_id)
255 TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
257 TP_ARGS(name, state, cpu_id)
262 TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
264 TP_ARGS(name, state, cpu_id)
272 TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
274 TP_ARGS(name, state, cpu_id),
278 __field( u64, state )
284 __entry->state = state;
288 TP_printk("%s state=%lu cpu_id=%lu", __get_str(name),
289 (unsigned long)__entry->state, (unsigned long)__entry->cpu_id)
294 TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
296 TP_ARGS(name, state, cpu_id)
/linux-4.1.27/include/linux/platform_data/
H A Domap1_bl.h8 int (*set_power)(struct device *dev, int state);
H A Dpcmcia-pxa2xx_viper.h8 void (*reset)(int state);
/linux-4.1.27/net/wimax/
H A DMakefile9 op-state-get.o \
H A Dop-rfkill.c37 * initial state and then every time it changes. See wimax.h:struct
53 * wimax_report_rfkill_sw() Driver reports state change
56 * wimax_report_rfkill_hw() Driver reports state change
79 * @state: New state of the RF Kill switch. %WIMAX_RF_ON radio on,
82 * When the device detects a change in the state of thehardware RF
84 * know that the state has changed so it can be properly propagated.
86 * The WiMAX stack caches the state (the driver doesn't need to). As
88 * change the software state to mirror the hardware state.
94 enum wimax_rf_state state) wimax_report_rfkill_hw()
100 d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state); wimax_report_rfkill_hw()
101 BUG_ON(state == WIMAX_RF_QUERY); wimax_report_rfkill_hw()
102 BUG_ON(state != WIMAX_RF_ON && state != WIMAX_RF_OFF); wimax_report_rfkill_hw()
109 if (state != wimax_dev->rf_hw) { wimax_report_rfkill_hw()
110 wimax_dev->rf_hw = state; wimax_report_rfkill_hw()
118 state == WIMAX_RF_OFF); wimax_report_rfkill_hw()
124 d_fnend(3, dev, "(wimax_dev %p state %u) = void [%d]\n", wimax_report_rfkill_hw()
125 wimax_dev, state, result); wimax_report_rfkill_hw()
135 * @state: New state of the RF kill switch. %WIMAX_RF_ON radio on,
138 * Reports changes in the software RF switch state to the the WiMAX
142 * device for its current software radio kill switch state and feed it
145 * On the side, the device does not change the software state by
150 enum wimax_rf_state state) wimax_report_rfkill_sw()
156 d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state); wimax_report_rfkill_sw()
157 BUG_ON(state == WIMAX_RF_QUERY); wimax_report_rfkill_sw()
158 BUG_ON(state != WIMAX_RF_ON && state != WIMAX_RF_OFF); wimax_report_rfkill_sw()
165 if (state != wimax_dev->rf_sw) { wimax_report_rfkill_sw()
166 wimax_dev->rf_sw = state; wimax_report_rfkill_sw()
173 rfkill_set_sw_state(wimax_dev->rfkill, state == WIMAX_RF_OFF); wimax_report_rfkill_sw()
177 d_fnend(3, dev, "(wimax_dev %p state %u) = void [%d]\n", wimax_report_rfkill_sw()
178 wimax_dev, state, result); wimax_report_rfkill_sw()
191 * here so the software RF Kill switch state is changed to reflect
192 * the hardware switch state.
194 * - When the user sets the state through sysfs' rfkill/state file
201 * state 0!
207 enum wimax_rf_state state) __wimax_rf_toggle_radio()
214 d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state); __wimax_rf_toggle_radio()
215 if (wimax_dev->rf_sw == state) __wimax_rf_toggle_radio()
218 result = wimax_dev->op_rfkill_sw_toggle(wimax_dev, state); __wimax_rf_toggle_radio()
219 else if (state == WIMAX_RF_OFF) /* No op? can't turn off */ __wimax_rf_toggle_radio()
225 wimax_dev->rf_sw = state; __wimax_rf_toggle_radio()
226 wimax_state = state == WIMAX_RF_ON ? __wimax_rf_toggle_radio()
231 d_fnend(3, dev, "(wimax_dev %p state %u) = %d\n", __wimax_rf_toggle_radio()
232 wimax_dev, state, result); __wimax_rf_toggle_radio()
238 * Translate from rfkill state to wimax state
240 * NOTE: Special state handling rules here
242 * Just pretend the call didn't happen if we are in a state where
261 if (wimax_dev->state <= __WIMAX_ST_QUIESCING) wimax_rfkill_set_radio_block()
276 * wimax_rfkill - Set the software RF switch state for a WiMAX device
280 * @state: New RF state.
284 * >= 0 toggle state if ok, < 0 errno code on error. The toggle state
285 * is returned as a bitmap, bit 0 being the hardware RF state, bit 1
286 * the software RF state.
295 * %WIMAX_RF_QUERY, just the current state is returned.
301 int wimax_rfkill(struct wimax_dev *wimax_dev, enum wimax_rf_state state) wimax_rfkill() argument
306 d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state); wimax_rfkill()
314 if (result == -ENOMEDIUM && state == WIMAX_RF_QUERY) wimax_rfkill()
318 switch (state) { wimax_rfkill()
321 result = __wimax_rf_toggle_radio(wimax_dev, state); wimax_rfkill()
324 rfkill_set_sw_state(wimax_dev->rfkill, state == WIMAX_RF_OFF); wimax_rfkill()
336 d_fnend(3, dev, "(wimax_dev %p state %u) = %d\n", wimax_rfkill()
337 wimax_dev, state, result); wimax_rfkill()
410 * Only one attribute: the new state requested (on, off or no change,
93 wimax_report_rfkill_hw(struct wimax_dev *wimax_dev, enum wimax_rf_state state) wimax_report_rfkill_hw() argument
149 wimax_report_rfkill_sw(struct wimax_dev *wimax_dev, enum wimax_rf_state state) wimax_report_rfkill_sw() argument
206 __wimax_rf_toggle_radio(struct wimax_dev *wimax_dev, enum wimax_rf_state state) __wimax_rf_toggle_radio() argument
/linux-4.1.27/tools/usb/ffs-aio-example/multibuff/host_app/
H A Dtest.c39 * struct test_state - describes test program state
59 int test_init(struct test_state *state) test_init() argument
65 state->found = NULL; test_init()
66 state->ctx = NULL; test_init()
67 state->handle = NULL; test_init()
68 state->attached = 0; test_init()
70 ret = libusb_init(&state->ctx); test_init()
76 cnt = libusb_get_device_list(state->ctx, &list); test_init()
92 state->found = dev; test_init()
97 if (!state->found) { test_init()
102 ret = libusb_open(state->found, &state->handle); test_init()
108 if (libusb_claim_interface(state->handle, 0)) { test_init()
109 ret = libusb_detach_kernel_driver(state->handle, 0); test_init()
115 state->attached = 1; test_init()
116 ret = libusb_claim_interface(state->handle, 0); test_init()
127 if (state->attached == 1) test_init()
128 libusb_attach_kernel_driver(state->handle, 0); test_init()
131 libusb_close(state->handle); test_init()
137 libusb_exit(state->ctx); test_init()
145 void test_exit(struct test_state *state) test_exit() argument
147 libusb_release_interface(state->handle, 0); test_exit()
148 if (state->attached == 1) test_exit()
149 libusb_attach_kernel_driver(state->handle, 0); test_exit()
150 libusb_close(state->handle); test_exit()
151 libusb_exit(state->ctx); test_exit()
156 struct test_state state; main() local
161 if (test_init(&state)) main()
164 libusb_get_config_descriptor(state.found, 0, &conf); main()
171 libusb_bulk_transfer(state.handle, addr, buffer, BUF_LEN, main()
174 test_exit(&state); main()
/linux-4.1.27/drivers/pcmcia/
H A Dsa1100_shannon.c44 struct pcmcia_state *state) shannon_pcmcia_socket_state()
48 state->bvd1 = 1; shannon_pcmcia_socket_state()
49 state->bvd2 = 1; shannon_pcmcia_socket_state()
50 state->vs_3v = 1; /* FIXME Can only apply 3.3V on Shannon. */ shannon_pcmcia_socket_state()
51 state->vs_Xv = 0; shannon_pcmcia_socket_state()
55 state->bvd1 = 1; shannon_pcmcia_socket_state()
56 state->bvd2 = 1; shannon_pcmcia_socket_state()
57 state->vs_3v = 1; /* FIXME Can only apply 3.3V on Shannon. */ shannon_pcmcia_socket_state()
58 state->vs_Xv = 0; shannon_pcmcia_socket_state()
65 const socket_state_t *state) shannon_pcmcia_configure_socket()
67 switch (state->Vcc) { shannon_pcmcia_configure_socket()
77 __func__, state->Vcc); shannon_pcmcia_configure_socket()
43 shannon_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) shannon_pcmcia_socket_state() argument
64 shannon_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) shannon_pcmcia_configure_socket() argument
H A Dsa1100_simpad.c40 struct pcmcia_state *state) simpad_pcmcia_socket_state()
45 state->detect = !state->detect; simpad_pcmcia_socket_state()
47 state->bvd1 = 1; /* Might be cs3reg & PCMCIA_BVD1 */ simpad_pcmcia_socket_state()
48 state->bvd2 = 1; /* Might be cs3reg & PCMCIA_BVD2 */ simpad_pcmcia_socket_state()
52 state->vs_3v=0; simpad_pcmcia_socket_state()
53 state->vs_Xv=0; simpad_pcmcia_socket_state()
55 state->vs_3v=1; simpad_pcmcia_socket_state()
56 state->vs_Xv=0; simpad_pcmcia_socket_state()
62 const socket_state_t *state) simpad_pcmcia_configure_socket()
69 switch (state->Vcc) { simpad_pcmcia_configure_socket()
86 __func__, state->Vcc); simpad_pcmcia_configure_socket()
39 simpad_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) simpad_pcmcia_socket_state() argument
61 simpad_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) simpad_pcmcia_configure_socket() argument
H A Dpxa2xx_trizeps4.c56 struct pcmcia_state *state) trizeps_pcmcia_socket_state()
74 state->bvd1 = (status & ConXS_CFSR_BVD1) ? 1 : 0; trizeps_pcmcia_socket_state()
75 state->bvd2 = (status & ConXS_CFSR_BVD2) ? 1 : 0; trizeps_pcmcia_socket_state()
76 state->vs_3v = (status & ConXS_CFSR_VS1) ? 0 : 1; trizeps_pcmcia_socket_state()
77 state->vs_Xv = (status & ConXS_CFSR_VS2) ? 0 : 1; trizeps_pcmcia_socket_state()
83 state->detect = 0; trizeps_pcmcia_socket_state()
84 state->ready = 0; trizeps_pcmcia_socket_state()
85 state->bvd1 = 0; trizeps_pcmcia_socket_state()
86 state->bvd2 = 0; trizeps_pcmcia_socket_state()
87 state->vs_3v = 0; trizeps_pcmcia_socket_state()
88 state->vs_Xv = 0; trizeps_pcmcia_socket_state()
96 const socket_state_t *state) trizeps_pcmcia_configure_socket()
102 switch (state->Vcc) { trizeps_pcmcia_configure_socket()
109 pr_err("%s(): bad Vcc %u\n", __func__, state->Vcc); trizeps_pcmcia_configure_socket()
113 switch (state->Vpp) { trizeps_pcmcia_configure_socket()
120 if (state->Vpp != state->Vcc) { trizeps_pcmcia_configure_socket()
121 pr_err("%s(): bad Vpp %u\n", __func__, state->Vpp); trizeps_pcmcia_configure_socket()
55 trizeps_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) trizeps_pcmcia_socket_state() argument
95 trizeps_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) trizeps_pcmcia_configure_socket() argument
H A Dsa1111_jornada720.c27 jornada720_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) jornada720_pcmcia_configure_socket() argument
34 skt->nr, state->Vcc, state->Vpp); jornada720_pcmcia_configure_socket()
40 switch (state->Vcc) { jornada720_pcmcia_configure_socket()
57 switch (state->Vcc) { jornada720_pcmcia_configure_socket()
75 if (state->Vpp != state->Vcc && state->Vpp != 0) { jornada720_pcmcia_configure_socket()
77 __func__, state->Vpp); jornada720_pcmcia_configure_socket()
81 ret = sa1111_pcmcia_configure_socket(skt, state); jornada720_pcmcia_configure_socket()
H A Dsa1111_neponset.c44 neponset_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) neponset_pcmcia_configure_socket() argument
55 if (state->Vpp == 0) neponset_pcmcia_configure_socket()
57 else if (state->Vpp == 120) neponset_pcmcia_configure_socket()
59 else if (state->Vpp == state->Vcc) neponset_pcmcia_configure_socket()
63 __func__, state->Vpp); neponset_pcmcia_configure_socket()
73 if (state->Vpp != state->Vcc && state->Vpp != 0) { neponset_pcmcia_configure_socket()
75 __func__, state->Vpp); neponset_pcmcia_configure_socket()
88 switch (state->Vcc) { neponset_pcmcia_configure_socket()
95 ret = sa1111_pcmcia_configure_socket(skt, state); neponset_pcmcia_configure_socket()
H A Dpxa2xx_mainstone.c36 * Setup default state of GPIO outputs mst_pcmcia_hw_init()
58 struct pcmcia_state *state) mst_pcmcia_socket_state()
80 state->detect = (status & MST_PCMCIA_nCD) ? 0 : 1; mst_pcmcia_socket_state()
81 state->ready = (status & MST_PCMCIA_nIRQ) ? 1 : 0; mst_pcmcia_socket_state()
82 state->bvd1 = (status & MST_PCMCIA_nSTSCHG_BVD1) ? 1 : 0; mst_pcmcia_socket_state()
83 state->bvd2 = (status & MST_PCMCIA_nSPKR_BVD2) ? 1 : 0; mst_pcmcia_socket_state()
84 state->vs_3v = (status & MST_PCMCIA_nVS1) ? 0 : 1; mst_pcmcia_socket_state()
85 state->vs_Xv = (status & MST_PCMCIA_nVS2) ? 0 : 1; mst_pcmcia_socket_state()
89 const socket_state_t *state) mst_pcmcia_configure_socket()
94 switch (state->Vcc) { mst_pcmcia_configure_socket()
100 __func__, state->Vcc); mst_pcmcia_configure_socket()
104 switch (state->Vpp) { mst_pcmcia_configure_socket()
108 if(state->Vpp == state->Vcc) { mst_pcmcia_configure_socket()
112 __func__, state->Vpp); mst_pcmcia_configure_socket()
117 if (state->flags & SS_RESET) mst_pcmcia_configure_socket()
57 mst_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) mst_pcmcia_socket_state() argument
88 mst_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) mst_pcmcia_configure_socket() argument
H A Dsa1111_generic.c66 void sa1111_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) sa1111_pcmcia_socket_state() argument
73 state->detect = status & PCSR_S0_DETECT ? 0 : 1; sa1111_pcmcia_socket_state()
74 state->ready = status & PCSR_S0_READY ? 1 : 0; sa1111_pcmcia_socket_state()
75 state->bvd1 = status & PCSR_S0_BVD1 ? 1 : 0; sa1111_pcmcia_socket_state()
76 state->bvd2 = status & PCSR_S0_BVD2 ? 1 : 0; sa1111_pcmcia_socket_state()
77 state->wrprot = status & PCSR_S0_WP ? 1 : 0; sa1111_pcmcia_socket_state()
78 state->vs_3v = status & PCSR_S0_VS1 ? 0 : 1; sa1111_pcmcia_socket_state()
79 state->vs_Xv = status & PCSR_S0_VS2 ? 0 : 1; sa1111_pcmcia_socket_state()
83 state->detect = status & PCSR_S1_DETECT ? 0 : 1; sa1111_pcmcia_socket_state()
84 state->ready = status & PCSR_S1_READY ? 1 : 0; sa1111_pcmcia_socket_state()
85 state->bvd1 = status & PCSR_S1_BVD1 ? 1 : 0; sa1111_pcmcia_socket_state()
86 state->bvd2 = status & PCSR_S1_BVD2 ? 1 : 0; sa1111_pcmcia_socket_state()
87 state->wrprot = status & PCSR_S1_WP ? 1 : 0; sa1111_pcmcia_socket_state()
88 state->vs_3v = status & PCSR_S1_VS1 ? 0 : 1; sa1111_pcmcia_socket_state()
89 state->vs_Xv = status & PCSR_S1_VS2 ? 0 : 1; sa1111_pcmcia_socket_state()
94 int sa1111_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) sa1111_pcmcia_configure_socket() argument
115 if (state->Vcc != 0) sa1111_pcmcia_configure_socket()
117 if (state->Vcc == 50) sa1111_pcmcia_configure_socket()
119 if (state->flags & SS_RESET) sa1111_pcmcia_configure_socket()
121 if (state->flags & SS_OUTPUT_ENA) sa1111_pcmcia_configure_socket()
200 * Initialise the suspend state. pcmcia_probe()
H A Dsa1100_assabet.c35 assabet_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) assabet_pcmcia_socket_state() argument
37 state->vs_3v = 1; /* Can only apply 3.3V on Assabet. */ assabet_pcmcia_socket_state()
38 state->vs_Xv = 0; assabet_pcmcia_socket_state()
42 assabet_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) assabet_pcmcia_configure_socket() argument
46 switch (state->Vcc) { assabet_pcmcia_configure_socket()
61 state->Vcc); assabet_pcmcia_configure_socket()
67 if (state->flags & SS_RESET) assabet_pcmcia_configure_socket()
69 if (!(state->flags & SS_OUTPUT_ENA)) assabet_pcmcia_configure_socket()
/linux-4.1.27/arch/powerpc/boot/
H A Dgunzip_util.c25 * @state: decompressor state structure to be initialized
31 * state in @state. The other functions in this file can then be used
36 * in @state and the other functions in this file will simply copy
42 void gunzip_start(struct gunzip_state *state, void *src, int srclen) gunzip_start() argument
47 memset(state, 0, sizeof(*state)); gunzip_start()
54 state->s.workspace = state->scratch; gunzip_start()
55 if (zlib_inflate_workspacesize() > sizeof(state->scratch)) gunzip_start()
76 r = zlib_inflateInit2(&state->s, -MAX_WBITS); gunzip_start()
81 state->s.total_in = hdrlen; gunzip_start()
82 state->s.next_in = src + hdrlen; gunzip_start()
83 state->s.avail_in = srclen - hdrlen; gunzip_start()
88 * @state: gzip state structure previously initialized by gunzip_start()
93 * previously associated with @state by gunzip_start(), decompressing
102 int gunzip_partial(struct gunzip_state *state, void *dst, int dstlen) gunzip_partial() argument
106 if (state->s.workspace) { gunzip_partial()
110 state->s.next_out = dst; gunzip_partial()
111 state->s.avail_out = dstlen; gunzip_partial()
112 r = zlib_inflate(&state->s, Z_FULL_FLUSH); gunzip_partial()
114 fatal("inflate returned %d msg: %s\n\r", r, state->s.msg); gunzip_partial()
115 len = state->s.next_out - (Byte *)dst; gunzip_partial()
118 len = min(state->s.avail_in, (uLong)dstlen); gunzip_partial()
119 memcpy(dst, state->s.next_in, len); gunzip_partial()
120 state->s.next_in += len; gunzip_partial()
121 state->s.avail_in -= len; gunzip_partial()
128 * @state: gzip state structure previously initialized by gunzip_start()
133 * previously associated with @state by gunzip_start(), decompressing
140 void gunzip_exactly(struct gunzip_state *state, void *dst, int dstlen) gunzip_exactly() argument
144 len = gunzip_partial(state, dst, dstlen); gunzip_exactly()
152 * @state: gzip state structure previously initialized by gunzip_start()
156 * data stream previously associated with @state by gunzip_start().
165 void gunzip_discard(struct gunzip_state *state, int len) gunzip_discard() argument
170 gunzip_exactly(state, discard_buf, sizeof(discard_buf)); gunzip_discard()
175 gunzip_exactly(state, discard_buf, len); gunzip_discard()
180 * @state: gzip state structure previously initialized by gunzip_start()
185 * bytes, from the stream previously associated with @state by
187 * any of the functions in this file on @state until it is
193 int gunzip_finish(struct gunzip_state *state, void *dst, int dstlen) gunzip_finish() argument
197 len = gunzip_partial(state, dst, dstlen); gunzip_finish()
199 if (state->s.workspace) { gunzip_finish()
200 zlib_inflateEnd(&state->s); gunzip_finish()
/linux-4.1.27/drivers/gpu/drm/i2c/
H A Dch7006_mode.c198 /* Some common HW state calculation code */
204 uint8_t *regs = priv->state.regs; ch7006_setup_levels()
235 struct ch7006_state *state = &priv->state; ch7006_setup_subcarrier() local
243 setbitf(state, CH7006_SUBC_INC0, 28, subc_inc); ch7006_setup_subcarrier()
244 setbitf(state, CH7006_SUBC_INC1, 24, subc_inc); ch7006_setup_subcarrier()
245 setbitf(state, CH7006_SUBC_INC2, 20, subc_inc); ch7006_setup_subcarrier()
246 setbitf(state, CH7006_SUBC_INC3, 16, subc_inc); ch7006_setup_subcarrier()
247 setbitf(state, CH7006_SUBC_INC4, 12, subc_inc); ch7006_setup_subcarrier()
248 setbitf(state, CH7006_SUBC_INC5, 8, subc_inc); ch7006_setup_subcarrier()
249 setbitf(state, CH7006_SUBC_INC6, 4, subc_inc); ch7006_setup_subcarrier()
250 setbitf(state, CH7006_SUBC_INC7, 0, subc_inc); ch7006_setup_subcarrier()
259 uint8_t *regs = priv->state.regs; ch7006_setup_pll()
296 uint8_t *power = &priv->state.regs[CH7006_POWER]; ch7006_setup_power_state()
330 struct ch7006_state *state = &priv->state; ch7006_setup_properties() local
334 uint8_t *regs = state->regs; ch7006_setup_properties()
355 setbitf(state, CH7006_POV, HPOS_8, hpos); ch7006_setup_properties()
356 setbitf(state, CH7006_HPOS, 0, hpos); ch7006_setup_properties()
361 setbitf(state, CH7006_POV, VPOS_8, vpos); ch7006_setup_properties()
362 setbitf(state, CH7006_VPOS, 0, vpos); ch7006_setup_properties()
402 struct ch7006_state *state) ch7006_state_load()
404 ch7006_load_reg(client, state, CH7006_POWER); ch7006_state_load()
406 ch7006_load_reg(client, state, CH7006_DISPMODE); ch7006_state_load()
407 ch7006_load_reg(client, state, CH7006_FFILTER); ch7006_state_load()
408 ch7006_load_reg(client, state, CH7006_BWIDTH); ch7006_state_load()
409 ch7006_load_reg(client, state, CH7006_INPUT_FORMAT); ch7006_state_load()
410 ch7006_load_reg(client, state, CH7006_CLKMODE); ch7006_state_load()
411 ch7006_load_reg(client, state, CH7006_START_ACTIVE); ch7006_state_load()
412 ch7006_load_reg(client, state, CH7006_POV); ch7006_state_load()
413 ch7006_load_reg(client, state, CH7006_BLACK_LEVEL); ch7006_state_load()
414 ch7006_load_reg(client, state, CH7006_HPOS); ch7006_state_load()
415 ch7006_load_reg(client, state, CH7006_VPOS); ch7006_state_load()
416 ch7006_load_reg(client, state, CH7006_INPUT_SYNC); ch7006_state_load()
417 ch7006_load_reg(client, state, CH7006_DETECT); ch7006_state_load()
418 ch7006_load_reg(client, state, CH7006_CONTRAST); ch7006_state_load()
419 ch7006_load_reg(client, state, CH7006_PLLOV); ch7006_state_load()
420 ch7006_load_reg(client, state, CH7006_PLLM); ch7006_state_load()
421 ch7006_load_reg(client, state, CH7006_PLLN); ch7006_state_load()
422 ch7006_load_reg(client, state, CH7006_BCLKOUT); ch7006_state_load()
423 ch7006_load_reg(client, state, CH7006_SUBC_INC0); ch7006_state_load()
424 ch7006_load_reg(client, state, CH7006_SUBC_INC1); ch7006_state_load()
425 ch7006_load_reg(client, state, CH7006_SUBC_INC2); ch7006_state_load()
426 ch7006_load_reg(client, state, CH7006_SUBC_INC3); ch7006_state_load()
427 ch7006_load_reg(client, state, CH7006_SUBC_INC4); ch7006_state_load()
428 ch7006_load_reg(client, state, CH7006_SUBC_INC5); ch7006_state_load()
429 ch7006_load_reg(client, state, CH7006_SUBC_INC6); ch7006_state_load()
430 ch7006_load_reg(client, state, CH7006_SUBC_INC7); ch7006_state_load()
431 ch7006_load_reg(client, state, CH7006_PLL_CONTROL); ch7006_state_load()
432 ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0); ch7006_state_load()
436 struct ch7006_state *state) ch7006_state_save()
438 ch7006_save_reg(client, state, CH7006_POWER); ch7006_state_save()
440 ch7006_save_reg(client, state, CH7006_DISPMODE); ch7006_state_save()
441 ch7006_save_reg(client, state, CH7006_FFILTER); ch7006_state_save()
442 ch7006_save_reg(client, state, CH7006_BWIDTH); ch7006_state_save()
443 ch7006_save_reg(client, state, CH7006_INPUT_FORMAT); ch7006_state_save()
444 ch7006_save_reg(client, state, CH7006_CLKMODE); ch7006_state_save()
445 ch7006_save_reg(client, state, CH7006_START_ACTIVE); ch7006_state_save()
446 ch7006_save_reg(client, state, CH7006_POV); ch7006_state_save()
447 ch7006_save_reg(client, state, CH7006_BLACK_LEVEL); ch7006_state_save()
448 ch7006_save_reg(client, state, CH7006_HPOS); ch7006_state_save()
449 ch7006_save_reg(client, state, CH7006_VPOS); ch7006_state_save()
450 ch7006_save_reg(client, state, CH7006_INPUT_SYNC); ch7006_state_save()
451 ch7006_save_reg(client, state, CH7006_DETECT); ch7006_state_save()
452 ch7006_save_reg(client, state, CH7006_CONTRAST); ch7006_state_save()
453 ch7006_save_reg(client, state, CH7006_PLLOV); ch7006_state_save()
454 ch7006_save_reg(client, state, CH7006_PLLM); ch7006_state_save()
455 ch7006_save_reg(client, state, CH7006_PLLN); ch7006_state_save()
456 ch7006_save_reg(client, state, CH7006_BCLKOUT); ch7006_state_save()
457 ch7006_save_reg(client, state, CH7006_SUBC_INC0); ch7006_state_save()
458 ch7006_save_reg(client, state, CH7006_SUBC_INC1); ch7006_state_save()
459 ch7006_save_reg(client, state, CH7006_SUBC_INC2); ch7006_state_save()
460 ch7006_save_reg(client, state, CH7006_SUBC_INC3); ch7006_state_save()
461 ch7006_save_reg(client, state, CH7006_SUBC_INC4); ch7006_state_save()
462 ch7006_save_reg(client, state, CH7006_SUBC_INC5); ch7006_state_save()
463 ch7006_save_reg(client, state, CH7006_SUBC_INC6); ch7006_state_save()
464 ch7006_save_reg(client, state, CH7006_SUBC_INC7); ch7006_state_save()
465 ch7006_save_reg(client, state, CH7006_PLL_CONTROL); ch7006_state_save()
466 ch7006_save_reg(client, state, CH7006_CALC_SUBC_INC0); ch7006_state_save()
468 state->regs[CH7006_FFILTER] = (state->regs[CH7006_FFILTER] & 0xf0) | ch7006_state_save()
469 (state->regs[CH7006_FFILTER] & 0x0c) >> 2 | ch7006_state_save()
470 (state->regs[CH7006_FFILTER] & 0x03) << 2; ch7006_state_save()
401 ch7006_state_load(struct i2c_client *client, struct ch7006_state *state) ch7006_state_load() argument
435 ch7006_state_save(struct i2c_client *client, struct ch7006_state *state) ch7006_state_save() argument
/linux-4.1.27/drivers/phy/
H A Dphy-exynos-dp-video.c35 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); exynos_dp_video_phy_power_on() local
38 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, exynos_dp_video_phy_power_on()
44 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); exynos_dp_video_phy_power_off() local
47 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, exynos_dp_video_phy_power_off()
79 struct exynos_dp_video_phy *state; exynos_dp_video_phy_probe() local
85 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); exynos_dp_video_phy_probe()
86 if (!state) exynos_dp_video_phy_probe()
89 state->regs = syscon_regmap_lookup_by_phandle(dev->of_node, exynos_dp_video_phy_probe()
91 if (IS_ERR(state->regs)) { exynos_dp_video_phy_probe()
93 return PTR_ERR(state->regs); exynos_dp_video_phy_probe()
97 state->drvdata = match->data; exynos_dp_video_phy_probe()
104 phy_set_drvdata(phy, state); exynos_dp_video_phy_probe()
H A Dphy-exynos-mipi-video.c49 static int __set_phy_state(struct exynos_mipi_video_phy *state, __set_phy_state() argument
61 spin_lock(&state->slock); __set_phy_state()
63 if (!IS_ERR(state->regmap)) { __set_phy_state()
64 regmap_read(state->regmap, offset, &val); __set_phy_state()
69 regmap_write(state->regmap, offset, val); __set_phy_state()
74 regmap_write(state->regmap, offset, val); __set_phy_state()
76 addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2); __set_phy_state()
93 spin_unlock(&state->slock); __set_phy_state()
103 struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc); exynos_mipi_video_phy_power_on() local
105 return __set_phy_state(state, phy_desc->index, 1); exynos_mipi_video_phy_power_on()
111 struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc); exynos_mipi_video_phy_power_off() local
113 return __set_phy_state(state, phy_desc->index, 0); exynos_mipi_video_phy_power_off()
119 struct exynos_mipi_video_phy *state = dev_get_drvdata(dev); exynos_mipi_video_phy_xlate() local
124 return state->phys[args->args[0]].phy; exynos_mipi_video_phy_xlate()
135 struct exynos_mipi_video_phy *state; exynos_mipi_video_phy_probe() local
140 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); exynos_mipi_video_phy_probe()
141 if (!state) exynos_mipi_video_phy_probe()
144 state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon"); exynos_mipi_video_phy_probe()
145 if (IS_ERR(state->regmap)) { exynos_mipi_video_phy_probe()
149 PTR_ERR(state->regmap)); exynos_mipi_video_phy_probe()
152 state->regs = devm_ioremap_resource(dev, res); exynos_mipi_video_phy_probe()
153 if (IS_ERR(state->regs)) exynos_mipi_video_phy_probe()
154 return PTR_ERR(state->regs); exynos_mipi_video_phy_probe()
157 dev_set_drvdata(dev, state); exynos_mipi_video_phy_probe()
158 spin_lock_init(&state->slock); exynos_mipi_video_phy_probe()
168 state->phys[i].phy = phy; exynos_mipi_video_phy_probe()
169 state->phys[i].index = i; exynos_mipi_video_phy_probe()
170 phy_set_drvdata(phy, &state->phys[i]); exynos_mipi_video_phy_probe()
/linux-4.1.27/drivers/media/pci/cx88/
H A Dcx88-vp3054-i2c.c40 static void vp3054_bit_setscl(void *data, int state) vp3054_bit_setscl() argument
46 if (state) { vp3054_bit_setscl()
47 vp3054_i2c->state |= 0x0001; /* SCL high */ vp3054_bit_setscl()
48 vp3054_i2c->state &= ~0x0100; /* external pullup */ vp3054_bit_setscl()
50 vp3054_i2c->state &= ~0x0001; /* SCL low */ vp3054_bit_setscl()
51 vp3054_i2c->state |= 0x0100; /* drive pin */ vp3054_bit_setscl()
53 cx_write(MO_GP0_IO, 0x010000 | vp3054_i2c->state); vp3054_bit_setscl()
57 static void vp3054_bit_setsda(void *data, int state) vp3054_bit_setsda() argument
63 if (state) { vp3054_bit_setsda()
64 vp3054_i2c->state |= 0x0002; /* SDA high */ vp3054_bit_setsda()
65 vp3054_i2c->state &= ~0x0200; /* tristate pin */ vp3054_bit_setsda()
67 vp3054_i2c->state &= ~0x0002; /* SDA low */ vp3054_bit_setsda()
68 vp3054_i2c->state |= 0x0200; /* drive pin */ vp3054_bit_setsda()
70 cx_write(MO_GP0_IO, 0x020000 | vp3054_i2c->state); vp3054_bit_setsda()
78 u32 state; vp3054_bit_getscl() local
80 state = cx_read(MO_GP0_IO); vp3054_bit_getscl()
81 return (state & 0x01) ? 1 : 0; vp3054_bit_getscl()
88 u32 state; vp3054_bit_getsda() local
90 state = cx_read(MO_GP0_IO); vp3054_bit_getsda()
91 return (state & 0x02) ? 1 : 0; vp3054_bit_getsda()
/linux-4.1.27/drivers/media/usb/dvb-usb/
H A Dvp7045-fe.c31 struct vp7045_fe_state *state = fe->demodulator_priv; vp7045_fe_read_status() local
32 u8 s0 = vp7045_read_reg(state->d,0x00), vp7045_fe_read_status()
33 s1 = vp7045_read_reg(state->d,0x01), vp7045_fe_read_status()
34 s3 = vp7045_read_reg(state->d,0x03); vp7045_fe_read_status()
57 struct vp7045_fe_state *state = fe->demodulator_priv; vp7045_fe_read_ber() local
58 *ber = (vp7045_read_reg(state->d, 0x0D) << 16) | vp7045_fe_read_ber()
59 (vp7045_read_reg(state->d, 0x0E) << 8) | vp7045_fe_read_ber()
60 vp7045_read_reg(state->d, 0x0F); vp7045_fe_read_ber()
66 struct vp7045_fe_state *state = fe->demodulator_priv; vp7045_fe_read_unc_blocks() local
67 *unc = (vp7045_read_reg(state->d, 0x10) << 8) | vp7045_fe_read_unc_blocks()
68 vp7045_read_reg(state->d, 0x11); vp7045_fe_read_unc_blocks()
74 struct vp7045_fe_state *state = fe->demodulator_priv; vp7045_fe_read_signal_strength() local
75 u16 signal = (vp7045_read_reg(state->d, 0x14) << 8) | vp7045_fe_read_signal_strength()
76 vp7045_read_reg(state->d, 0x15); vp7045_fe_read_signal_strength()
84 struct vp7045_fe_state *state = fe->demodulator_priv; vp7045_fe_read_snr() local
85 u8 _snr = vp7045_read_reg(state->d, 0x09); vp7045_fe_read_snr()
109 struct vp7045_fe_state *state = fe->demodulator_priv; vp7045_fe_set_frontend() local
132 vp7045_usb_op(state->d,LOCK_TUNER_COMMAND,buf,5,NULL,0,200); vp7045_fe_set_frontend()
138 struct vp7045_fe_state *state = fe->demodulator_priv; vp7045_fe_release() local
139 kfree(state); vp7045_fe_release()
H A Ddtt200u-fe.c25 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_read_status() local
28 dvb_usb_generic_rw(state->d,&st,1,b,3,0); dtt200u_fe_read_status()
48 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_read_ber() local
50 dvb_usb_generic_rw(state->d,&bw,1,b,3,0); dtt200u_fe_read_ber()
57 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_read_unc_blocks() local
60 dvb_usb_generic_rw(state->d,&bw,1,b,2,0); dtt200u_fe_read_unc_blocks()
67 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_read_signal_strength() local
69 dvb_usb_generic_rw(state->d,&bw,1,&b,1,0); dtt200u_fe_read_signal_strength()
76 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_read_snr() local
78 dvb_usb_generic_rw(state->d,&bw,1,&br,1,0); dtt200u_fe_read_snr()
85 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_init() local
87 return dvb_usb_generic_write(state->d,&b,1); dtt200u_fe_init()
106 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_set_frontend() local
126 dvb_usb_generic_write(state->d,bwbuf,2); dtt200u_fe_set_frontend()
130 dvb_usb_generic_write(state->d,freqbuf,3); dtt200u_fe_set_frontend()
145 struct dtt200u_fe_state *state = fe->demodulator_priv; dtt200u_fe_get_frontend() local
146 memcpy(fep, &state->fep, sizeof(struct dtv_frontend_properties)); dtt200u_fe_get_frontend()
152 struct dtt200u_fe_state *state = (struct dtt200u_fe_state*) fe->demodulator_priv; dtt200u_fe_release() local
153 kfree(state); dtt200u_fe_release()
160 struct dtt200u_fe_state* state = NULL; dtt200u_fe_attach() local
162 /* allocate memory for the internal state */ dtt200u_fe_attach()
163 state = kzalloc(sizeof(struct dtt200u_fe_state), GFP_KERNEL); dtt200u_fe_attach()
164 if (state == NULL) dtt200u_fe_attach()
169 state->d = d; dtt200u_fe_attach()
171 memcpy(&state->frontend.ops,&dtt200u_fe_ops,sizeof(struct dvb_frontend_ops)); dtt200u_fe_attach()
172 state->frontend.demodulator_priv = state; dtt200u_fe_attach()
174 return &state->frontend; dtt200u_fe_attach()
H A Daf9005-fe.c106 struct af9005_fe_state *state = fe->demodulator_priv; af9005_is_fecmon_available() local
112 ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en, af9005_is_fecmon_available()
119 af9005_read_register_bits(state->d, af9005_is_fecmon_available()
137 struct af9005_fe_state *state = fe->demodulator_priv; af9005_get_post_vit_err_cw_count() local
149 af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy, af9005_get_post_vit_err_cw_count()
160 af9005_read_ofdm_register(state->d, af9005_get_post_vit_err_cw_count()
166 af9005_read_ofdm_register(state->d, af9005_get_post_vit_err_cw_count()
175 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0, af9005_get_post_vit_err_cw_count()
180 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8, af9005_get_post_vit_err_cw_count()
185 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16, af9005_get_post_vit_err_cw_count()
194 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0, af9005_get_post_vit_err_cw_count()
199 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8, af9005_get_post_vit_err_cw_count()
240 struct af9005_fe_state *state = fe->demodulator_priv; af9005_get_pre_vit_err_bit_count() local
246 af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy, af9005_get_pre_vit_err_bit_count()
256 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0, af9005_get_pre_vit_err_bit_count()
261 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8, af9005_get_pre_vit_err_bit_count()
266 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16, af9005_get_pre_vit_err_bit_count()
273 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0, af9005_get_pre_vit_err_bit_count()
278 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8, af9005_get_pre_vit_err_bit_count()
290 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod, af9005_get_pre_vit_err_bit_count()
308 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const, af9005_get_pre_vit_err_bit_count()
335 struct af9005_fe_state *state = fe->demodulator_priv; af9005_reset_pre_viterbi() local
340 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0, af9005_reset_pre_viterbi()
344 ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8, af9005_reset_pre_viterbi()
350 af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst, af9005_reset_pre_viterbi()
359 struct af9005_fe_state *state = fe->demodulator_priv; af9005_reset_post_viterbi() local
364 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0, af9005_reset_post_viterbi()
369 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8, af9005_reset_post_viterbi()
375 af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst, af9005_reset_post_viterbi()
384 struct af9005_fe_state *state = fe->demodulator_priv; af9005_get_statistic() local
397 ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count, af9005_get_statistic()
398 &state->pre_vit_bit_count); af9005_get_statistic()
401 if (state->pre_vit_bit_count > 0) { af9005_get_statistic()
406 (u64) state->pre_vit_error_count * (u64) 1000000000; af9005_get_statistic()
407 denominator = (u64) state->pre_vit_bit_count; af9005_get_statistic()
408 state->ber = do_div(numerator, denominator); af9005_get_statistic()
410 state->ber = 0xffffffff; af9005_get_statistic()
414 ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count, af9005_get_statistic()
415 &state->post_vit_bit_count, af9005_get_statistic()
416 &state->abort_count); af9005_get_statistic()
419 state->unc += state->abort_count; af9005_get_statistic()
428 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_refresh_state() local
429 if (time_after(jiffies, state->next_status_check)) { af9005_fe_refresh_state()
435 state->next_status_check = jiffies + 250 * HZ / 1000; af9005_fe_refresh_state()
442 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_read_status() local
450 ret = af9005_read_register_bits(state->d, xd_p_agc_lock, af9005_fe_read_status()
457 ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock, af9005_fe_read_status()
465 ret = af9005_read_register_bits(state->d, af9005_fe_read_status()
473 if (state->opened) af9005_fe_read_status()
474 af9005_led_control(state->d, *stat & FE_HAS_LOCK); af9005_fe_read_status()
477 af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected, af9005_fe_read_status()
482 if (temp != state->strong) { af9005_fe_read_status()
484 state->strong = temp; af9005_fe_read_status()
491 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_read_ber() local
495 *ber = state->ber; af9005_fe_read_ber()
501 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_read_unc_blocks() local
505 *unc = state->unc; af9005_fe_read_unc_blocks()
512 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_read_signal_strength() local
519 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain, af9005_fe_read_signal_strength()
524 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain, af9005_fe_read_signal_strength()
799 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_power() local
803 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0); af9005_fe_power()
817 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_init() local
829 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en, af9005_fe_init()
832 if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0))) af9005_fe_init()
838 af9005_read_ofdm_register(state->d, af9005_fe_init()
858 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9); af9005_fe_init()
861 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07); af9005_fe_init()
865 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0); af9005_fe_init()
868 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00); af9005_fe_init()
871 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1); af9005_fe_init()
877 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst, af9005_fe_init()
880 ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst, af9005_fe_init()
886 ret = af9005_write_ofdm_register(state->d, 0xaefc, 0); af9005_fe_init()
893 af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone, af9005_fe_init()
901 af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip, af9005_fe_init()
906 af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip, af9005_fe_init()
914 af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14))) af9005_fe_init()
920 af9005_write_register_bits(state->d, xd_p_reg_dca_en, af9005_fe_init()
924 ret = af9005_write_ofdm_register(state->d, 0xa16c, 1); af9005_fe_init()
927 ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0); af9005_fe_init()
933 ret = af9005_fe_program_cfoe(state->d, 6000000); af9005_fe_init()
939 af9005_write_register_bits(state->d, xd_p_reg_feq_read_update, af9005_fe_init()
950 af9005_write_register_bits(state->d, xd_p_reg_dca_read_update, af9005_fe_init()
958 af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en, af9005_fe_init()
964 ret = af9005_write_ofdm_register(state->d, 0xa601, 0); af9005_fe_init()
968 if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01))) af9005_fe_init()
976 af9005_write_register_bits(state->d, script[i].reg, af9005_fe_init()
990 state->original_if_unplug_th = script[i].val; af9005_fe_init()
992 state->original_rf_unplug_th = script[i].val; af9005_fe_init()
994 state->original_dtop_if_unplug_th = script[i].val; af9005_fe_init()
996 state->original_dtop_rf_unplug_th = script[i].val; af9005_fe_init()
999 state->original_fcw = af9005_fe_init()
1008 af9005_read_word_agc(state->d, af9005_fe_init()
1011 &state->original_rf_top); af9005_fe_init()
1017 af9005_read_word_agc(state->d, af9005_fe_init()
1020 &state->original_if_top); af9005_fe_init()
1026 af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2, af9005_fe_init()
1027 &state->original_aci0_if_top); af9005_fe_init()
1033 af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2, af9005_fe_init()
1034 &state->original_aci1_if_top); af9005_fe_init()
1090 struct af9005_fe_state *state = fe->demodulator_priv; af9005_ts_bus_ctrl() local
1093 state->opened++; af9005_ts_bus_ctrl()
1096 state->opened--; af9005_ts_bus_ctrl()
1097 if (!state->opened) af9005_ts_bus_ctrl()
1098 af9005_led_control(state->d, 0); af9005_ts_bus_ctrl()
1106 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_set_frontend() local
1119 ret = af9005_led_control(state->d, 0); af9005_fe_set_frontend()
1123 ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0); af9005_fe_set_frontend()
1129 temp0 = (u8) (state->original_fcw & 0x000000ff); af9005_fe_set_frontend()
1130 temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8); af9005_fe_set_frontend()
1131 temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16); af9005_fe_set_frontend()
1132 ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0); af9005_fe_set_frontend()
1135 ret = af9005_write_ofdm_register(state->d, 0xae19, temp1); af9005_fe_set_frontend()
1138 ret = af9005_write_ofdm_register(state->d, 0xae18, temp2); af9005_fe_set_frontend()
1145 af9005_write_word_agc(state->d, af9005_fe_set_frontend()
1148 state->original_rf_top); af9005_fe_set_frontend()
1152 af9005_write_word_agc(state->d, af9005_fe_set_frontend()
1155 state->original_if_top); af9005_fe_set_frontend()
1159 af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2, af9005_fe_set_frontend()
1160 state->original_aci0_if_top); af9005_fe_set_frontend()
1164 af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2, af9005_fe_set_frontend()
1165 state->original_aci1_if_top); af9005_fe_set_frontend()
1171 ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz); af9005_fe_set_frontend()
1174 ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz); af9005_fe_set_frontend()
1180 ret = af9005_write_ofdm_register(state->d, 0xaefd, 0); af9005_fe_set_frontend()
1187 af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th, af9005_fe_set_frontend()
1188 state->original_if_unplug_th); af9005_fe_set_frontend()
1200 ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1); af9005_fe_set_frontend()
1207 af9005_write_register_bits(state->d, af9005_fe_set_frontend()
1216 state->pre_vit_error_count = 0; af9005_fe_set_frontend()
1217 state->pre_vit_bit_count = 0; af9005_fe_set_frontend()
1218 state->ber = 0; af9005_fe_set_frontend()
1219 state->post_vit_error_count = 0; af9005_fe_set_frontend()
1220 /* state->unc = 0; commented out since it should be ever increasing */ af9005_fe_set_frontend()
1221 state->abort_count = 0; af9005_fe_set_frontend()
1223 state->next_status_check = jiffies; af9005_fe_set_frontend()
1224 state->strong = -1; af9005_fe_set_frontend()
1232 struct af9005_fe_state *state = fe->demodulator_priv; af9005_fe_get_frontend() local
1238 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const, af9005_fe_get_frontend()
1262 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier, af9005_fe_get_frontend()
1289 af9005_read_register_bits(state->d, xd_g_reg_dec_pri, af9005_fe_get_frontend()
1298 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr, af9005_fe_get_frontend()
1329 af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr, af9005_fe_get_frontend()
1360 af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi, af9005_fe_get_frontend()
1386 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod, af9005_fe_get_frontend()
1405 af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos, af9005_fe_get_frontend()
1427 struct af9005_fe_state *state = af9005_fe_release() local
1429 kfree(state); af9005_fe_release()
1436 struct af9005_fe_state *state = NULL; af9005_fe_attach() local
1438 /* allocate memory for the internal state */ af9005_fe_attach()
1439 state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL); af9005_fe_attach()
1440 if (state == NULL) af9005_fe_attach()
1445 state->d = d; af9005_fe_attach()
1446 state->opened = 0; af9005_fe_attach()
1448 memcpy(&state->frontend.ops, &af9005_fe_ops, af9005_fe_attach()
1450 state->frontend.demodulator_priv = state; af9005_fe_attach()
1452 return &state->frontend; af9005_fe_attach()
H A Dfriio-fe.c27 static int jdvbt90502_reg_read(struct jdvbt90502_state *state, jdvbt90502_reg_read() argument
38 msg[0].addr = state->config.demod_address; jdvbt90502_reg_read()
48 ret = i2c_transfer(state->i2c, msg, 2); jdvbt90502_reg_read()
57 static int jdvbt90502_single_reg_write(struct jdvbt90502_state *state, jdvbt90502_single_reg_write() argument
66 msg.addr = state->config.demod_address; jdvbt90502_single_reg_write()
71 if (i2c_transfer(state->i2c, &msg, 1) != 1) { jdvbt90502_single_reg_write()
80 struct jdvbt90502_state *state = fe->demodulator_priv; _jdvbt90502_write() local
83 err = jdvbt90502_single_reg_write(state, _jdvbt90502_write()
94 static int jdvbt90502_pll_read(struct jdvbt90502_state *state, u8 *result) jdvbt90502_pll_read() argument
99 u8 pll_addr_byte = (state->config.pll_address << 1) + 1; jdvbt90502_pll_read()
103 ret = jdvbt90502_single_reg_write(state, JDVBT90502_2ND_I2C_REG, jdvbt90502_pll_read()
108 ret = jdvbt90502_reg_read(state, 0x0100, result, 1); jdvbt90502_pll_read()
122 static int jdvbt90502_pll_set_freq(struct jdvbt90502_state *state, u32 freq) jdvbt90502_pll_set_freq() argument
135 state->frontend.ops.info.frequency_stepsize); jdvbt90502_pll_set_freq()
138 f = freq / state->frontend.ops.info.frequency_stepsize; jdvbt90502_pll_set_freq()
145 pll_freq_cmd[ADDRESS_BYTE] = state->config.pll_address << 1; jdvbt90502_pll_set_freq()
151 msg[0].addr = state->config.demod_address; jdvbt90502_pll_set_freq()
156 ret = i2c_transfer(state->i2c, &msg[0], 1); jdvbt90502_pll_set_freq()
175 ret = i2c_transfer(state->i2c, &msg[1], 1); jdvbt90502_pll_set_freq()
181 ret = jdvbt90502_single_reg_write(state, 0x01, 0x40); jdvbt90502_pll_set_freq()
182 ret |= jdvbt90502_single_reg_write(state, 0x01, 0x00); jdvbt90502_pll_set_freq()
190 ret = jdvbt90502_reg_read(state, 0x0096, &res1, 1); jdvbt90502_pll_set_freq()
194 ret = jdvbt90502_reg_read(state, 0x00B0, res2, sizeof(res2)); jdvbt90502_pll_set_freq()
213 static int jdvbt90502_read_status(struct dvb_frontend *fe, fe_status_t *state) jdvbt90502_read_status() argument
218 *state = FE_HAS_SIGNAL; jdvbt90502_read_status()
226 *state = FE_HAS_SIGNAL jdvbt90502_read_status()
232 *state |= FE_HAS_LOCK; jdvbt90502_read_status()
309 struct jdvbt90502_state *state = fe->demodulator_priv; jdvbt90502_set_frontend() local
317 ret = jdvbt90502_pll_set_freq(state, p->frequency); jdvbt90502_set_frontend()
378 struct jdvbt90502_state *state = fe->demodulator_priv; jdvbt90502_init() local
382 msg.addr = state->config.demod_address; jdvbt90502_init()
387 ret = i2c_transfer(state->i2c, &msg, 1); jdvbt90502_init()
404 struct jdvbt90502_state *state = fe->demodulator_priv; jdvbt90502_release() local
405 kfree(state); jdvbt90502_release()
413 struct jdvbt90502_state *state = NULL; jdvbt90502_attach() local
417 /* allocate memory for the internal state */ jdvbt90502_attach()
418 state = kzalloc(sizeof(struct jdvbt90502_state), GFP_KERNEL); jdvbt90502_attach()
419 if (state == NULL) jdvbt90502_attach()
422 /* setup the state */ jdvbt90502_attach()
423 state->i2c = &d->i2c_adap; jdvbt90502_attach()
424 state->config = friio_fe_config; jdvbt90502_attach()
427 state->frontend.ops = jdvbt90502_ops; jdvbt90502_attach()
428 state->frontend.demodulator_priv = state; jdvbt90502_attach()
430 if (jdvbt90502_init(&state->frontend) < 0) jdvbt90502_attach()
433 return &state->frontend; jdvbt90502_attach()
436 kfree(state); jdvbt90502_attach()
/linux-4.1.27/drivers/input/misc/
H A Dsparcspkr.c67 struct sparcspkr_state *state = dev_get_drvdata(dev->dev.parent); bbc_spkr_event() local
68 struct bbc_beep_info *info = &state->u.bbc; bbc_spkr_event()
86 spin_lock_irqsave(&state->lock, flags); bbc_spkr_event()
98 spin_unlock_irqrestore(&state->lock, flags); bbc_spkr_event()
105 struct sparcspkr_state *state = dev_get_drvdata(dev->dev.parent); grover_spkr_event() local
106 struct grover_beep_info *info = &state->u.grover; grover_spkr_event()
122 spin_lock_irqsave(&state->lock, flags); grover_spkr_event()
137 spin_unlock_irqrestore(&state->lock, flags); grover_spkr_event()
144 struct sparcspkr_state *state = dev_get_drvdata(dev); sparcspkr_probe() local
152 input_dev->name = state->name; sparcspkr_probe()
163 input_dev->event = state->event; sparcspkr_probe()
171 state->input_dev = input_dev; sparcspkr_probe()
178 struct sparcspkr_state *state = platform_get_drvdata(dev); sparcspkr_shutdown() local
179 struct input_dev *input_dev = state->input_dev; sparcspkr_shutdown()
182 state->event(input_dev, EV_SND, SND_BELL, 0); sparcspkr_shutdown()
187 struct sparcspkr_state *state; bbc_beep_probe() local
192 state = kzalloc(sizeof(*state), GFP_KERNEL); bbc_beep_probe()
193 if (!state) bbc_beep_probe()
196 state->name = "Sparc BBC Speaker"; bbc_beep_probe()
197 state->event = bbc_spkr_event; bbc_beep_probe()
198 spin_lock_init(&state->lock); bbc_beep_probe()
205 info = &state->u.bbc; bbc_beep_probe()
214 platform_set_drvdata(op, state); bbc_beep_probe()
226 kfree(state); bbc_beep_probe()
233 struct sparcspkr_state *state = platform_get_drvdata(op); bbc_remove() local
234 struct input_dev *input_dev = state->input_dev; bbc_remove()
235 struct bbc_beep_info *info = &state->u.bbc; bbc_remove()
238 state->event(input_dev, EV_SND, SND_BELL, 0); bbc_remove()
244 kfree(state); bbc_remove()
269 struct sparcspkr_state *state; grover_beep_probe() local
273 state = kzalloc(sizeof(*state), GFP_KERNEL); grover_beep_probe()
274 if (!state) grover_beep_probe()
277 state->name = "Sparc Grover Speaker"; grover_beep_probe()
278 state->event = grover_spkr_event; grover_beep_probe()
279 spin_lock_init(&state->lock); grover_beep_probe()
281 info = &state->u.grover; grover_beep_probe()
290 platform_set_drvdata(op, state); grover_beep_probe()
304 kfree(state); grover_beep_probe()
311 struct sparcspkr_state *state = platform_get_drvdata(op); grover_remove() local
312 struct grover_beep_info *info = &state->u.grover; grover_remove()
313 struct input_dev *input_dev = state->input_dev; grover_remove()
316 state->event(input_dev, EV_SND, SND_BELL, 0); grover_remove()
323 kfree(state); grover_remove()
/linux-4.1.27/arch/mips/cavium-octeon/crypto/
H A Docteon-crypto.c18 * sure the state of COP2 isn't corrupted if userspace is also performing
19 * hardware crypto operations. Allocate the state parameter on the stack.
22 * @state: Pointer to state structure to store current COP2 state in.
26 unsigned long octeon_crypto_enable(struct octeon_cop2_state *state) octeon_crypto_enable() argument
40 octeon_cop2_save(state); octeon_crypto_enable()
52 * @state: Pointer to COP2 state to restore
55 void octeon_crypto_disable(struct octeon_cop2_state *state, octeon_crypto_disable() argument
62 octeon_cop2_restore(state); octeon_crypto_disable()
H A Docteon-sha512.c37 write_octeon_64bit_hash_sha512(sctx->state[0], 0); octeon_sha512_store_hash()
38 write_octeon_64bit_hash_sha512(sctx->state[1], 1); octeon_sha512_store_hash()
39 write_octeon_64bit_hash_sha512(sctx->state[2], 2); octeon_sha512_store_hash()
40 write_octeon_64bit_hash_sha512(sctx->state[3], 3); octeon_sha512_store_hash()
41 write_octeon_64bit_hash_sha512(sctx->state[4], 4); octeon_sha512_store_hash()
42 write_octeon_64bit_hash_sha512(sctx->state[5], 5); octeon_sha512_store_hash()
43 write_octeon_64bit_hash_sha512(sctx->state[6], 6); octeon_sha512_store_hash()
44 write_octeon_64bit_hash_sha512(sctx->state[7], 7); octeon_sha512_store_hash()
49 sctx->state[0] = read_octeon_64bit_hash_sha512(0); octeon_sha512_read_hash()
50 sctx->state[1] = read_octeon_64bit_hash_sha512(1); octeon_sha512_read_hash()
51 sctx->state[2] = read_octeon_64bit_hash_sha512(2); octeon_sha512_read_hash()
52 sctx->state[3] = read_octeon_64bit_hash_sha512(3); octeon_sha512_read_hash()
53 sctx->state[4] = read_octeon_64bit_hash_sha512(4); octeon_sha512_read_hash()
54 sctx->state[5] = read_octeon_64bit_hash_sha512(5); octeon_sha512_read_hash()
55 sctx->state[6] = read_octeon_64bit_hash_sha512(6); octeon_sha512_read_hash()
56 sctx->state[7] = read_octeon_64bit_hash_sha512(7); octeon_sha512_read_hash()
85 sctx->state[0] = SHA512_H0; octeon_sha512_init()
86 sctx->state[1] = SHA512_H1; octeon_sha512_init()
87 sctx->state[2] = SHA512_H2; octeon_sha512_init()
88 sctx->state[3] = SHA512_H3; octeon_sha512_init()
89 sctx->state[4] = SHA512_H4; octeon_sha512_init()
90 sctx->state[5] = SHA512_H5; octeon_sha512_init()
91 sctx->state[6] = SHA512_H6; octeon_sha512_init()
92 sctx->state[7] = SHA512_H7; octeon_sha512_init()
102 sctx->state[0] = SHA384_H0; octeon_sha384_init()
103 sctx->state[1] = SHA384_H1; octeon_sha384_init()
104 sctx->state[2] = SHA384_H2; octeon_sha384_init()
105 sctx->state[3] = SHA384_H3; octeon_sha384_init()
106 sctx->state[4] = SHA384_H4; octeon_sha384_init()
107 sctx->state[5] = SHA384_H5; octeon_sha384_init()
108 sctx->state[6] = SHA384_H6; octeon_sha384_init()
109 sctx->state[7] = SHA384_H7; octeon_sha384_init()
153 struct octeon_cop2_state state; octeon_sha512_update() local
164 flags = octeon_crypto_enable(&state); octeon_sha512_update()
170 octeon_crypto_disable(&state, flags); octeon_sha512_update()
179 struct octeon_cop2_state state; octeon_sha512_final() local
195 flags = octeon_crypto_enable(&state); octeon_sha512_final()
204 octeon_crypto_disable(&state, flags); octeon_sha512_final()
206 /* Store state in digest. */ octeon_sha512_final()
208 dst[i] = cpu_to_be64(sctx->state[i]); octeon_sha512_final()
/linux-4.1.27/arch/mips/include/asm/mach-malta/
H A Dmalta-pm.h19 * mips_pm_suspend - enter a suspend state
20 * @state: the state to enter, one of PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_*
22 * Enters a suspend state via the Malta's PIIX4. If the state to be entered
26 extern int mips_pm_suspend(unsigned state);
30 static inline int mips_pm_suspend(unsigned state) mips_pm_suspend() argument
/linux-4.1.27/net/netfilter/
H A Dnf_queue.c51 struct nf_hook_state *state = &entry->state; nf_queue_entry_release_refs() local
54 if (state->in) nf_queue_entry_release_refs()
55 dev_put(state->in); nf_queue_entry_release_refs()
56 if (state->out) nf_queue_entry_release_refs()
57 dev_put(state->out); nf_queue_entry_release_refs()
58 if (state->sk) nf_queue_entry_release_refs()
59 sock_put(state->sk); nf_queue_entry_release_refs()
80 struct nf_hook_state *state = &entry->state; nf_queue_entry_get_refs() local
85 if (state->in) nf_queue_entry_get_refs()
86 dev_hold(state->in); nf_queue_entry_get_refs()
87 if (state->out) nf_queue_entry_get_refs()
88 dev_hold(state->out); nf_queue_entry_get_refs()
89 if (state->sk) nf_queue_entry_get_refs()
90 sock_hold(state->sk); nf_queue_entry_get_refs()
131 struct nf_hook_state *state, nf_queue()
148 afinfo = nf_get_afinfo(state->pf); nf_queue()
161 .state = *state, nf_queue()
207 afinfo = nf_get_afinfo(entry->state.pf); nf_reinject()
212 entry->state.thresh = INT_MIN; nf_reinject()
216 verdict = nf_iterate(&nf_hooks[entry->state.pf][entry->state.hook], nf_reinject()
217 skb, &entry->state, &elem); nf_reinject()
224 entry->state.okfn(entry->state.sk, skb); nf_reinject()
228 err = nf_queue(skb, elem, &entry->state, nf_reinject()
129 nf_queue(struct sk_buff *skb, struct nf_hook_ops *elem, struct nf_hook_state *state, unsigned int queuenum) nf_queue() argument
/linux-4.1.27/drivers/leds/trigger/
H A Dledtrig-transient.c32 int state; member in struct:transient_trig_data
61 unsigned long state; transient_activate_store() local
64 ret = kstrtoul(buf, 10, &state); transient_activate_store()
68 if (state != 1 && state != 0) transient_activate_store()
72 if (state == 0 && transient_data->activate == 1) { transient_activate_store()
74 transient_data->activate = state; transient_activate_store()
81 if (state == 1 && transient_data->activate == 0 && transient_activate_store()
83 transient_data->activate = state; transient_activate_store()
84 led_set_brightness_async(led_cdev, transient_data->state); transient_activate_store()
86 (transient_data->state == LED_FULL) ? LED_OFF : LED_FULL; transient_activate_store()
91 /* state == 0 && transient_data->activate == 0 transient_activate_store()
93 /* state == 1 && transient_data->activate == 1 transient_activate_store()
113 unsigned long state; transient_duration_store() local
116 ret = kstrtoul(buf, 10, &state); transient_duration_store()
120 transient_data->duration = state; transient_duration_store()
129 int state; transient_state_show() local
131 state = (transient_data->state == LED_FULL) ? 1 : 0; transient_state_show()
132 return sprintf(buf, "%d\n", state); transient_state_show()
140 unsigned long state; transient_state_store() local
143 ret = kstrtoul(buf, 10, &state); transient_state_store()
147 if (state != 1 && state != 0) transient_state_store()
150 transient_data->state = (state == 1) ? LED_FULL : LED_OFF; transient_state_store()
158 static DEVICE_ATTR(state, 0644, transient_state_show, transient_state_store);
/linux-4.1.27/drivers/iio/dac/
H A Dmcp4922.c60 static int mcp4922_spi_write(struct mcp4922_state *state, u8 addr, u32 val) mcp4922_spi_write() argument
62 state->mosi[1] = val & 0xff; mcp4922_spi_write()
63 state->mosi[0] = (addr == 0) ? 0x00 : 0x80; mcp4922_spi_write()
64 state->mosi[0] |= 0x30 | ((val >> 8) & 0x0f); mcp4922_spi_write()
66 return spi_write(state->spi, state->mosi, 2); mcp4922_spi_write()
75 struct mcp4922_state *state = iio_priv(indio_dev); mcp4922_read_raw() local
79 *val = state->value[chan->channel]; mcp4922_read_raw()
82 *val = state->vref_mv; mcp4922_read_raw()
96 struct mcp4922_state *state = iio_priv(indio_dev); mcp4922_write_raw() local
106 state->value[chan->channel] = val; mcp4922_write_raw()
107 return mcp4922_spi_write(state, chan->channel, val); mcp4922_write_raw()
128 struct mcp4922_state *state; mcp4922_probe() local
132 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state)); mcp4922_probe()
136 state = iio_priv(indio_dev); mcp4922_probe()
137 state->spi = spi; mcp4922_probe()
138 state->vref_reg = devm_regulator_get(&spi->dev, "vref"); mcp4922_probe()
139 if (IS_ERR(state->vref_reg)) { mcp4922_probe()
141 return PTR_ERR(state->vref_reg); mcp4922_probe()
144 ret = regulator_enable(state->vref_reg); mcp4922_probe()
151 ret = regulator_get_voltage(state->vref_reg); mcp4922_probe()
157 state->vref_mv = ret / 1000; mcp4922_probe()
178 regulator_disable(state->vref_reg); mcp4922_probe()
186 struct mcp4922_state *state; mcp4922_remove() local
189 state = iio_priv(indio_dev); mcp4922_remove()
190 regulator_disable(state->vref_reg); mcp4922_remove()
/linux-4.1.27/drivers/net/ethernet/qualcomm/
H A Dqca_framing.c62 * following a simple state machine.
78 switch (handle->state) { qcafrm_fsm_decode()
81 /* by default, just go to next state */ qcafrm_fsm_decode()
82 handle->state--; qcafrm_fsm_decode()
86 handle->state = QCAFRM_HW_LEN0; qcafrm_fsm_decode()
91 handle->state--; qcafrm_fsm_decode()
100 handle->state = QCAFRM_HW_LEN0; qcafrm_fsm_decode()
102 handle->state--; qcafrm_fsm_decode()
109 handle->state = QCAFRM_WAIT_LEN_BYTE1; qcafrm_fsm_decode()
113 handle->state = QCAFRM_WAIT_RSVD_BYTE1; qcafrm_fsm_decode()
116 handle->state = QCAFRM_WAIT_RSVD_BYTE2; qcafrm_fsm_decode()
122 handle->state = QCAFRM_HW_LEN0; qcafrm_fsm_decode()
124 handle->state = (enum qcafrm_state)(len + 1); qcafrm_fsm_decode()
133 handle->state--; qcafrm_fsm_decode()
138 handle->state = QCAFRM_HW_LEN0; qcafrm_fsm_decode()
140 handle->state = QCAFRM_WAIT_552; qcafrm_fsm_decode()
146 handle->state = QCAFRM_HW_LEN0; qcafrm_fsm_decode()
150 handle->state = QCAFRM_HW_LEN0; qcafrm_fsm_decode()
/linux-4.1.27/drivers/media/usb/ttusb-dec/
H A Dttusbdecfe.c53 struct ttusbdecfe_state* state = fe->demodulator_priv; ttusbdecfe_dvbt_read_status() local
61 ret=state->config->send_command(fe, 0x73, sizeof(b), b, &len, result); ttusbdecfe_dvbt_read_status()
93 struct ttusbdecfe_state* state = (struct ttusbdecfe_state*) fe->demodulator_priv; ttusbdecfe_dvbt_set_frontend() local
102 state->config->send_command(fe, 0x71, sizeof(b), b, NULL, NULL); ttusbdecfe_dvbt_set_frontend()
120 struct ttusbdecfe_state* state = (struct ttusbdecfe_state*) fe->demodulator_priv; ttusbdecfe_dvbs_set_frontend() local
138 (state->hi_band ? LOF_HI : LOF_LO)); ttusbdecfe_dvbs_set_frontend()
142 band = htonl(state->hi_band ? LOF_HI : LOF_LO); ttusbdecfe_dvbs_set_frontend()
144 lnb_voltage = htonl(state->voltage); ttusbdecfe_dvbs_set_frontend()
147 state->config->send_command(fe, 0x71, sizeof(b), b, NULL, NULL); ttusbdecfe_dvbs_set_frontend()
154 struct ttusbdecfe_state* state = (struct ttusbdecfe_state*) fe->demodulator_priv; ttusbdecfe_dvbs_diseqc_send_master_cmd() local
164 state->config->send_command(fe, 0x72, ttusbdecfe_dvbs_diseqc_send_master_cmd()
174 struct ttusbdecfe_state* state = (struct ttusbdecfe_state*) fe->demodulator_priv; ttusbdecfe_dvbs_set_tone() local
176 state->hi_band = (SEC_TONE_ON == tone); ttusbdecfe_dvbs_set_tone()
184 struct ttusbdecfe_state* state = (struct ttusbdecfe_state*) fe->demodulator_priv; ttusbdecfe_dvbs_set_voltage() local
188 state->voltage = 13; ttusbdecfe_dvbs_set_voltage()
191 state->voltage = 18; ttusbdecfe_dvbs_set_voltage()
202 struct ttusbdecfe_state* state = (struct ttusbdecfe_state*) fe->demodulator_priv; ttusbdecfe_release() local
203 kfree(state); ttusbdecfe_release()
210 struct ttusbdecfe_state* state = NULL; ttusbdecfe_dvbt_attach() local
212 /* allocate memory for the internal state */ ttusbdecfe_dvbt_attach()
213 state = kmalloc(sizeof(struct ttusbdecfe_state), GFP_KERNEL); ttusbdecfe_dvbt_attach()
214 if (state == NULL) ttusbdecfe_dvbt_attach()
217 /* setup the state */ ttusbdecfe_dvbt_attach()
218 state->config = config; ttusbdecfe_dvbt_attach()
221 memcpy(&state->frontend.ops, &ttusbdecfe_dvbt_ops, sizeof(struct dvb_frontend_ops)); ttusbdecfe_dvbt_attach()
222 state->frontend.demodulator_priv = state; ttusbdecfe_dvbt_attach()
223 return &state->frontend; ttusbdecfe_dvbt_attach()
230 struct ttusbdecfe_state* state = NULL; ttusbdecfe_dvbs_attach() local
232 /* allocate memory for the internal state */ ttusbdecfe_dvbs_attach()
233 state = kmalloc(sizeof(struct ttusbdecfe_state), GFP_KERNEL); ttusbdecfe_dvbs_attach()
234 if (state == NULL) ttusbdecfe_dvbs_attach()
237 /* setup the state */ ttusbdecfe_dvbs_attach()
238 state->config = config; ttusbdecfe_dvbs_attach()
239 state->voltage = 0; ttusbdecfe_dvbs_attach()
240 state->hi_band = 0; ttusbdecfe_dvbs_attach()
243 memcpy(&state->frontend.ops, &ttusbdecfe_dvbs_ops, sizeof(struct dvb_frontend_ops)); ttusbdecfe_dvbs_attach()
244 state->frontend.demodulator_priv = state; ttusbdecfe_dvbs_attach()
245 return &state->frontend; ttusbdecfe_dvbs_attach()
/linux-4.1.27/arch/mips/include/asm/
H A Dpm-cps.h34 * cps_pm_support_state - determine whether the system supports a PM state
35 * @state: the state to test for support
37 * Returns true if the system supports the given state, otherwise false.
39 extern bool cps_pm_support_state(enum cps_pm_state state);
42 * cps_pm_enter_state - enter a PM state
43 * @state: the state to enter
45 * Enter the given PM state. If coupled_coherence is non-zero then it is
49 extern int cps_pm_enter_state(enum cps_pm_state state);
/linux-4.1.27/drivers/input/
H A Dff-memless.c52 unsigned long flags; /* effect state (STARTED, PLAYING, etc) */
89 static unsigned long calculate_next_time(struct ml_effect_state *state) calculate_next_time() argument
91 const struct ff_envelope *envelope = get_envelope(state->effect); calculate_next_time()
95 attack_stop = state->play_at + calculate_next_time()
97 if (time_before(state->adj_at, attack_stop)) calculate_next_time()
98 return state->adj_at + calculate_next_time()
102 if (state->effect->replay.length) { calculate_next_time()
105 fade_start = state->stop_at - calculate_next_time()
108 if (time_before(state->adj_at, fade_start)) calculate_next_time()
112 next_fade = state->adj_at + calculate_next_time()
114 if (time_before(next_fade, state->stop_at)) calculate_next_time()
118 return state->stop_at; calculate_next_time()
121 return state->play_at; calculate_next_time()
126 struct ml_effect_state *state; ml_schedule_timer() local
137 state = &ml->states[i]; ml_schedule_timer()
139 if (!test_bit(FF_EFFECT_STARTED, &state->flags)) ml_schedule_timer()
142 if (test_bit(FF_EFFECT_PLAYING, &state->flags)) ml_schedule_timer()
143 next_at = calculate_next_time(state); ml_schedule_timer()
145 next_at = state->play_at; ml_schedule_timer()
164 static int apply_envelope(struct ml_effect_state *state, int value, apply_envelope() argument
167 struct ff_effect *effect = state->effect; apply_envelope()
176 state->play_at + msecs_to_jiffies(envelope->attack_length))) { apply_envelope()
179 time_from_level = jiffies_to_msecs(now - state->play_at); apply_envelope()
185 state->stop_at - msecs_to_jiffies(envelope->fade_length)) && apply_envelope()
186 time_before(now, state->stop_at)) { apply_envelope()
187 time_from_level = jiffies_to_msecs(state->stop_at - now); apply_envelope()
256 struct ml_effect_state *state, ml_combine_effects()
259 struct ff_effect *new = state->effect; ml_combine_effects()
267 level = fixp_new16(apply_envelope(state, ml_combine_effects()
307 i = apply_envelope(state, abs(new->u.periodic.magnitude), ml_combine_effects()
343 struct ml_effect_state *state; ml_get_combo_effect() local
353 state = &ml->states[i]; ml_get_combo_effect()
354 effect = state->effect; ml_get_combo_effect()
356 if (!test_bit(FF_EFFECT_STARTED, &state->flags)) ml_get_combo_effect()
359 if (time_before(jiffies, state->play_at)) ml_get_combo_effect()
376 if (__test_and_clear_bit(FF_EFFECT_ABORTING, &state->flags)) { ml_get_combo_effect()
377 __clear_bit(FF_EFFECT_PLAYING, &state->flags); ml_get_combo_effect()
378 __clear_bit(FF_EFFECT_STARTED, &state->flags); ml_get_combo_effect()
380 time_after_eq(jiffies, state->stop_at)) { ml_get_combo_effect()
382 __clear_bit(FF_EFFECT_PLAYING, &state->flags); ml_get_combo_effect()
384 if (--state->count <= 0) { ml_get_combo_effect()
385 __clear_bit(FF_EFFECT_STARTED, &state->flags); ml_get_combo_effect()
387 state->play_at = jiffies + ml_get_combo_effect()
389 state->stop_at = state->play_at + ml_get_combo_effect()
393 __set_bit(FF_EFFECT_PLAYING, &state->flags); ml_get_combo_effect()
394 state->adj_at = jiffies; ml_get_combo_effect()
395 ml_combine_effects(combo_effect, state, ml->gain); ml_get_combo_effect()
450 struct ml_effect_state *state = &ml->states[effect_id]; ml_ff_playback() local
455 __set_bit(FF_EFFECT_STARTED, &state->flags); ml_ff_playback()
456 state->count = value; ml_ff_playback()
457 state->play_at = jiffies + ml_ff_playback()
458 msecs_to_jiffies(state->effect->replay.delay); ml_ff_playback()
459 state->stop_at = state->play_at + ml_ff_playback()
460 msecs_to_jiffies(state->effect->replay.length); ml_ff_playback()
461 state->adj_at = state->play_at; ml_ff_playback()
466 if (test_bit(FF_EFFECT_PLAYING, &state->flags)) ml_ff_playback()
467 __set_bit(FF_EFFECT_ABORTING, &state->flags); ml_ff_playback()
469 __clear_bit(FF_EFFECT_STARTED, &state->flags); ml_ff_playback()
481 struct ml_effect_state *state = &ml->states[effect->id]; ml_ff_upload() local
485 if (test_bit(FF_EFFECT_STARTED, &state->flags)) { ml_ff_upload()
486 __clear_bit(FF_EFFECT_PLAYING, &state->flags); ml_ff_upload()
487 state->play_at = jiffies + ml_ff_upload()
488 msecs_to_jiffies(state->effect->replay.delay); ml_ff_upload()
489 state->stop_at = state->play_at + ml_ff_upload()
490 msecs_to_jiffies(state->effect->replay.length); ml_ff_upload()
491 state->adj_at = state->play_at; ml_ff_upload()
255 ml_combine_effects(struct ff_effect *effect, struct ml_effect_state *state, int gain) ml_combine_effects() argument
/linux-4.1.27/drivers/acpi/
H A Ddevice_pm.c37 * acpi_power_state_string - String representation of ACPI device power state.
38 * @state: ACPI device power state to return the string representation of.
40 const char *acpi_power_state_string(int state) acpi_power_state_string() argument
42 switch (state) { acpi_power_state_string()
59 * acpi_device_get_power - Get power state of an ACPI device.
60 * @device: Device to get the power state of.
61 * @state: Place to store the power state of the device.
63 * This function does not update the device's power.state field, but it may
64 * update its parent's power.state field (when the parent's power state is
65 * unknown and the device's power state turns out to be D0).
67 int acpi_device_get_power(struct acpi_device *device, int *state) acpi_device_get_power() argument
71 if (!device || !state) acpi_device_get_power()
76 *state = device->parent ? acpi_device_get_power()
77 device->parent->power.state : ACPI_STATE_D0; acpi_device_get_power()
82 * Get the device's power state from power resources settings and _PSC, acpi_device_get_power()
100 * The power resources settings may indicate a power state acpi_device_get_power()
101 * shallower than the actual power state of the device. acpi_device_get_power()
115 * If we were unsure about the device parent's power state up to this acpi_device_get_power()
120 && device->parent->power.state == ACPI_STATE_UNKNOWN acpi_device_get_power()
122 device->parent->power.state = ACPI_STATE_D0; acpi_device_get_power()
124 *state = result; acpi_device_get_power()
127 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] power state is %s\n", acpi_device_get_power()
128 device->pnp.bus_id, acpi_power_state_string(*state))); acpi_device_get_power()
133 static int acpi_dev_pm_explicit_set(struct acpi_device *adev, int state) acpi_dev_pm_explicit_set() argument
135 if (adev->power.states[state].flags.explicit_set) { acpi_dev_pm_explicit_set()
136 char method[5] = { '_', 'P', 'S', '0' + state, '\0' }; acpi_dev_pm_explicit_set()
147 * acpi_device_set_power - Set power state of an ACPI device.
148 * @device: Device to set the power state of.
149 * @state: New power state to set.
154 int acpi_device_set_power(struct acpi_device *device, int state) acpi_device_set_power() argument
160 || (state < ACPI_STATE_D0) || (state > ACPI_STATE_D3_COLD)) acpi_device_set_power()
163 /* Make sure this is a valid target state */ acpi_device_set_power()
165 if (state == device->power.state) { acpi_device_set_power()
168 acpi_power_state_string(state))); acpi_device_set_power()
172 if (!device->power.states[state].flags.valid) { acpi_device_set_power()
173 dev_warn(&device->dev, "Power state %s not supported\n", acpi_device_set_power()
174 acpi_power_state_string(state)); acpi_device_set_power()
178 device->parent && (state < device->parent->power.state)) { acpi_device_set_power()
180 "Cannot transition to power state %s for parent in %s\n", acpi_device_set_power()
181 acpi_power_state_string(state), acpi_device_set_power()
182 acpi_power_state_string(device->parent->power.state)); acpi_device_set_power()
187 if (state == ACPI_STATE_D3_COLD acpi_device_set_power()
189 state = ACPI_STATE_D3_HOT; acpi_device_set_power()
193 if (state < device->power.state && state != ACPI_STATE_D0 acpi_device_set_power()
194 && device->power.state >= ACPI_STATE_D3_HOT) { acpi_device_set_power()
196 "Cannot transition to non-D0 state from D3\n"); acpi_device_set_power()
207 result = acpi_power_transition(device, state); acpi_device_set_power()
211 result = acpi_dev_pm_explicit_set(device, state); acpi_device_set_power()
216 device->power.state = state; acpi_device_set_power()
217 state = ACPI_STATE_D3_COLD; acpi_device_set_power()
218 result = acpi_power_transition(device, state); acpi_device_set_power()
223 dev_warn(&device->dev, "Failed to change power state to %s\n", acpi_device_set_power()
224 acpi_power_state_string(state)); acpi_device_set_power()
226 device->power.state = state; acpi_device_set_power()
230 acpi_power_state_string(state))); acpi_device_set_power()
237 int acpi_bus_set_power(acpi_handle handle, int state) acpi_bus_set_power() argument
246 return acpi_device_set_power(device, state); acpi_bus_set_power()
252 int state; acpi_bus_init_power() local
258 device->power.state = ACPI_STATE_UNKNOWN; acpi_bus_init_power()
262 result = acpi_device_get_power(device, &state); acpi_bus_init_power()
266 if (state < ACPI_STATE_D3_COLD && device->power.flags.power_resources) { acpi_bus_init_power()
267 result = acpi_power_on_resources(device, state); acpi_bus_init_power()
271 result = acpi_dev_pm_explicit_set(device, state); acpi_bus_init_power()
274 } else if (state == ACPI_STATE_UNKNOWN) { acpi_bus_init_power()
281 state = ACPI_STATE_D0; acpi_bus_init_power()
283 device->power.state = state; acpi_bus_init_power()
289 * @device: Device object whose power state is to be fixed up.
301 && device->power.state == ACPI_STATE_D0) acpi_device_fix_up_power()
309 int state; acpi_device_update_power() local
312 if (device->power.state == ACPI_STATE_UNKNOWN) { acpi_device_update_power()
315 *state_p = device->power.state; acpi_device_update_power()
320 result = acpi_device_get_power(device, &state); acpi_device_update_power()
324 if (state == ACPI_STATE_UNKNOWN) { acpi_device_update_power()
325 state = ACPI_STATE_D0; acpi_device_update_power()
326 result = acpi_device_set_power(device, state); acpi_device_update_power()
332 * We don't need to really switch the state, bu we need acpi_device_update_power()
335 result = acpi_power_transition(device, state); acpi_device_update_power()
339 device->power.state = state; acpi_device_update_power()
342 *state_p = state; acpi_device_update_power()
480 * acpi_dev_pm_get_state - Get preferred power state of ACPI device.
481 * @dev: Device whose preferred target power state to return.
483 * @target_state: System state to match the resultant device state.
484 * @d_min_p: Location to store the highest power state available to the device.
485 * @d_max_p: Location to store the lowest power state available to the device.
489 * state represented by @target_state. Store the integer numbers representing
511 * If the system state is S0, the lowest power state the device can be acpi_dev_pm_get_state()
514 * lowest power state available to the device. acpi_dev_pm_get_state()
520 * If present, _SxD methods return the minimum D-state (highest power acpi_dev_pm_get_state()
521 * state) we can use for the corresponding S-states. Otherwise, the acpi_dev_pm_get_state()
522 * minimum D-state is D0 (ACPI 3.x). acpi_dev_pm_get_state()
538 * D3cold if D3hot is not a valid state. acpi_dev_pm_get_state()
555 * If _PRW says we can wake up the system from the target sleep state, acpi_dev_pm_get_state()
556 * the D-state returned by _SxD is sufficient for that (we assume a acpi_dev_pm_get_state()
558 * (ACPI 3.x), it should return the maximum (lowest power) D-state that acpi_dev_pm_get_state()
568 /* Fall back to D3cold if ret is not a valid state. */ acpi_dev_pm_get_state()
588 * acpi_pm_device_sleep_state - Get preferred power state of ACPI device.
589 * @dev: Device whose preferred target power state to return.
591 * @d_max_in: Deepest low-power state to take into consideration.
592 * Return value: Preferred power state of the device on success, -ENODEV
755 * acpi_dev_pm_low_power - Put ACPI device into a low-power state.
756 * @dev: Device to put into a low-power state.
758 * @system_state: System state to choose the device state for.
763 int ret, state; acpi_dev_pm_low_power() local
768 ret = acpi_dev_pm_get_state(dev, adev, system_state, NULL, &state); acpi_dev_pm_low_power()
769 return ret ? ret : acpi_device_set_power(adev, state); acpi_dev_pm_low_power()
773 * acpi_dev_pm_full_power - Put ACPI device into the full-power state.
774 * @adev: ACPI device node to put into the full-power state.
783 * acpi_dev_runtime_suspend - Put device into a low-power state using ACPI.
784 * @dev: Device to put into a low-power state.
786 * Put the given device into a runtime low-power state using the standard ACPI
787 * mechanism. Set up remote wakeup if desired, choose the state to put the
789 * the power state of the device.
815 * acpi_dev_runtime_resume - Put device into the full-power state using ACPI.
816 * @dev: Device to put into the full-power state.
818 * Put the given device into the full-power state using the standard ACPI
819 * mechanism at run time. Set the power state of the device to ACPI D0 and
841 * it into a runtime low-power state.
854 * Use ACPI to put the given device into the full-power state and carry out the
866 * acpi_dev_suspend_late - Put device into a low-power state using ACPI.
867 * @dev: Device to put into a low-power state.
869 * Put the given device into a low-power state during system transition to a
870 * sleep state using the standard ACPI mechanism. Set up system wakeup if
871 * desired, choose the state to put the device into (this checks if system
872 * wakeup is expected to work too), and set the power state of the device.
899 * acpi_dev_resume_early - Put device into the full-power state using ACPI.
900 * @dev: Device to put into the full-power state.
902 * Put the given device into the full-power state using the standard ACPI
903 * mechanism during system transition to the working state. Set the power
904 * state of the device to ACPI D0 and disable remote wakeup.
921 * acpi_subsys_prepare - Prepare device for system transition to a sleep state.
928 int ret, state; acpi_subsys_prepare() local
945 ret = acpi_dev_pm_get_state(dev, adev, sys_target, NULL, &state); acpi_subsys_prepare()
946 return !ret && state == adev->power.state; acpi_subsys_prepare()
959 * the sleep state it is going out of and it has never been resumed till acpi_subsys_complete()
986 * it into a low-power state during system transition into a sleep state.
999 * Use ACPI to put the given device into the full-power state and carry out the
1001 * working state.
1071 * choice of the low-power state to put the device into. acpi_dev_pm_detach()
1089 * be put into the ACPI D0 state before the function returns.
/linux-4.1.27/drivers/ata/
H A Dpata_icside.c62 struct pata_icside_state *state; member in struct:pata_icside_info
87 struct pata_icside_state *state = ec->irq_data; pata_icside_irqenable_arcin_v5() local
89 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); pata_icside_irqenable_arcin_v5()
97 struct pata_icside_state *state = ec->irq_data; pata_icside_irqdisable_arcin_v5() local
99 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); pata_icside_irqdisable_arcin_v5()
114 struct pata_icside_state *state = ec->irq_data; pata_icside_irqenable_arcin_v6() local
115 void __iomem *base = state->irq_port; pata_icside_irqenable_arcin_v6()
117 if (!state->port[0].disabled) pata_icside_irqenable_arcin_v6()
119 if (!state->port[1].disabled) pata_icside_irqenable_arcin_v6()
128 struct pata_icside_state *state = ec->irq_data; pata_icside_irqdisable_arcin_v6() local
130 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); pata_icside_irqdisable_arcin_v6()
131 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); pata_icside_irqdisable_arcin_v6()
139 struct pata_icside_state *state = ec->irq_data; pata_icside_irqpending_arcin_v6() local
141 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || pata_icside_irqpending_arcin_v6()
142 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; pata_icside_irqpending_arcin_v6()
189 struct pata_icside_state *state = ap->host->private_data; pata_icside_set_dmamode() local
216 state->port[ap->port_no].speed[adev->devno] = cycle; pata_icside_set_dmamode()
222 struct pata_icside_state *state = ap->host->private_data; pata_icside_bmdma_setup() local
229 BUG_ON(dma_channel_active(state->dma)); pata_icside_bmdma_setup()
234 writeb(state->port[ap->port_no].port_sel, state->ioc_base); pata_icside_bmdma_setup()
236 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); pata_icside_bmdma_setup()
237 set_dma_sg(state->dma, qc->sg, qc->n_elem); pata_icside_bmdma_setup()
238 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); pata_icside_bmdma_setup()
247 struct pata_icside_state *state = ap->host->private_data; pata_icside_bmdma_start() local
249 BUG_ON(dma_channel_active(state->dma)); pata_icside_bmdma_start()
250 enable_dma(state->dma); pata_icside_bmdma_start()
256 struct pata_icside_state *state = ap->host->private_data; pata_icside_bmdma_stop() local
258 disable_dma(state->dma); pata_icside_bmdma_stop()
266 struct pata_icside_state *state = ap->host->private_data; pata_icside_bmdma_status() local
269 irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 : pata_icside_bmdma_status()
277 struct pata_icside_state *state = info->state; icside_dma_init() local
282 state->port[0].speed[i] = 480; icside_dma_init()
283 state->port[1].speed[i] = 480; icside_dma_init()
287 state->dma = ec->dma; icside_dma_init()
304 struct pata_icside_state *state = ap->host->private_data; pata_icside_postreset() local
309 state->port[ap->port_no].disabled = 1; pata_icside_postreset()
311 if (state->type == ICS_TYPE_V6) { pata_icside_postreset()
317 void __iomem *irq_port = state->irq_port + pata_icside_postreset()
372 struct pata_icside_state *state = info->state; pata_icside_register_v5() local
379 state->irq_port = base; pata_icside_register_v5()
395 struct pata_icside_state *state = info->state; pata_icside_register_v6() local
419 state->irq_port = easi_base; pata_icside_register_v6()
420 state->ioc_base = ioc_base; pata_icside_register_v6()
421 state->port[0].port_sel = sel; pata_icside_register_v6()
422 state->port[1].port_sel = sel | 1; pata_icside_register_v6()
447 ecard_setirq(ec, info->irqops, info->state); pata_icside_add_ports()
458 host->private_data = info->state; pata_icside_add_ports()
479 struct pata_icside_state *state; pata_icside_probe() local
488 state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL); pata_icside_probe()
489 if (!state) { pata_icside_probe()
494 state->type = ICS_TYPE_NOTYPE; pata_icside_probe()
495 state->dma = NO_DMA; pata_icside_probe()
507 state->type = type; pata_icside_probe()
511 info.state = state; pata_icside_probe()
514 switch (state->type) { pata_icside_probe()
571 struct pata_icside_state *state = host->private_data; pata_icside_shutdown() local
572 if (state->ioc_base) pata_icside_shutdown()
573 writeb(0, state->ioc_base); pata_icside_shutdown()
580 struct pata_icside_state *state = host->private_data; pata_icside_remove() local
590 if (state->dma != NO_DMA) pata_icside_remove()
591 free_dma(state->dma); pata_icside_remove()
/linux-4.1.27/tools/power/cpupower/utils/idle_monitor/
H A Dcpuidle_sysfs.c48 int cpu, state; cpuidle_start() local
51 for (state = 0; state < cpuidle_sysfs_monitor.hw_states_num; cpuidle_start()
52 state++) { cpuidle_start()
53 previous_count[cpu][state] = cpuidle_start()
54 sysfs_get_idlestate_time(cpu, state); cpuidle_start()
56 cpu, state, previous_count[cpu][state]); cpuidle_start()
64 int cpu, state; cpuidle_stop() local
70 for (state = 0; state < cpuidle_sysfs_monitor.hw_states_num; cpuidle_stop()
71 state++) { cpuidle_stop()
72 current_count[cpu][state] = cpuidle_stop()
73 sysfs_get_idlestate_time(cpu, state); cpuidle_stop()
75 cpu, state, previous_count[cpu][state]); cpuidle_stop()
134 /* Assume idle state count is the same for all CPUs */ cpuidle_register()
/linux-4.1.27/drivers/net/wan/
H A Dhdlc_fr.c12 Theory of PVC state
134 }state; member in struct:pvc_device
171 static inline struct frad_state* state(hdlc_device *hdlc) state() function
173 return(struct frad_state *)(hdlc->state); state()
179 struct pvc_device *pvc = state(hdlc)->first_pvc; find_pvc()
196 struct pvc_device *pvc, **pvc_p = &state(hdlc)->first_pvc; add_pvc()
249 struct pvc_device **pvc_p = &state(hdlc)->first_pvc; delete_unused_pvcs()
353 if (state(hdlc)->settings.lmi == LMI_NONE) pvc_open()
354 pvc->state.active = netif_carrier_ok(pvc->frad); pvc_open()
356 pvc_carrier(pvc->state.active, pvc); pvc_open()
357 state(hdlc)->dce_changed = 1; pvc_open()
370 if (state(hdlc)->settings.lmi == LMI_NONE) pvc_close()
371 pvc->state.active = 0; pvc_close()
373 if (state(hdlc)->settings.dce) { pvc_close()
374 state(hdlc)->dce_changed = 1; pvc_close()
375 pvc->state.active = 0; pvc_close()
415 if (pvc->state.active) { pvc_xmit()
435 if (pvc->state.fecn) /* TX Congestion counter */ pvc_xmit()
455 pvc->state.new ? " new" : "", fr_log_dlci_active()
456 !pvc->state.exist ? "deleted" : fr_log_dlci_active()
457 pvc->state.active ? "active" : "inactive"); fr_log_dlci_active()
473 struct pvc_device *pvc = state(hdlc)->first_pvc; fr_lmi_send()
474 int lmi = state(hdlc)->settings.lmi; fr_lmi_send()
475 int dce = state(hdlc)->settings.dce; fr_lmi_send()
482 len += state(hdlc)->dce_pvc_count * (2 + stat_len); fr_lmi_send()
514 data[i++] = state(hdlc)->txseq = fr_lmi_send()
515 fr_lmi_nextseq(state(hdlc)->txseq); fr_lmi_send()
516 data[i++] = state(hdlc)->rxseq; fr_lmi_send()
525 if (state(hdlc)->reliable && !pvc->state.exist) { fr_lmi_send()
526 pvc->state.exist = pvc->state.new = 1; fr_lmi_send()
531 if (pvc->open_count && !pvc->state.active && fr_lmi_send()
532 pvc->state.exist && !pvc->state.new) { fr_lmi_send()
534 pvc->state.active = 1; fr_lmi_send()
547 if (pvc->state.new) fr_lmi_send()
549 else if (pvc->state.active) fr_lmi_send()
570 struct pvc_device *pvc = state(hdlc)->first_pvc; fr_set_link_state()
572 state(hdlc)->reliable = reliable; fr_set_link_state()
575 state(hdlc)->n391cnt = 0; /* Request full status */ fr_set_link_state()
576 state(hdlc)->dce_changed = 1; fr_set_link_state()
578 if (state(hdlc)->settings.lmi == LMI_NONE) { fr_set_link_state()
581 pvc->state.exist = pvc->state.active = 1; fr_set_link_state()
582 pvc->state.new = 0; fr_set_link_state()
590 pvc->state.exist = pvc->state.active = 0; fr_set_link_state()
591 pvc->state.new = 0; fr_set_link_state()
592 if (!state(hdlc)->settings.dce) fr_set_link_state()
593 pvc->state.bandwidth = 0; fr_set_link_state()
607 if (state(hdlc)->settings.dce) { fr_timer()
608 reliable = state(hdlc)->request && fr_timer()
609 time_before(jiffies, state(hdlc)->last_poll + fr_timer()
610 state(hdlc)->settings.t392 * HZ); fr_timer()
611 state(hdlc)->request = 0; fr_timer()
613 state(hdlc)->last_errors <<= 1; /* Shift the list */ fr_timer()
614 if (state(hdlc)->request) { fr_timer()
615 if (state(hdlc)->reliable) fr_timer()
617 state(hdlc)->last_errors |= 1; fr_timer()
620 list = state(hdlc)->last_errors; fr_timer()
621 for (i = 0; i < state(hdlc)->settings.n393; i++, list >>= 1) fr_timer()
624 reliable = (cnt < state(hdlc)->settings.n392); fr_timer()
627 if (state(hdlc)->reliable != reliable) { fr_timer()
632 if (state(hdlc)->settings.dce) fr_timer()
633 state(hdlc)->timer.expires = jiffies + fr_timer()
634 state(hdlc)->settings.t392 * HZ; fr_timer()
636 if (state(hdlc)->n391cnt) fr_timer()
637 state(hdlc)->n391cnt--; fr_timer()
639 fr_lmi_send(dev, state(hdlc)->n391cnt == 0); fr_timer()
641 state(hdlc)->last_poll = jiffies; fr_timer()
642 state(hdlc)->request = 1; fr_timer()
643 state(hdlc)->timer.expires = jiffies + fr_timer()
644 state(hdlc)->settings.t391 * HZ; fr_timer()
647 state(hdlc)->timer.function = fr_timer; fr_timer()
648 state(hdlc)->timer.data = arg; fr_timer()
649 add_timer(&state(hdlc)->timer); fr_timer()
658 int lmi = state(hdlc)->settings.lmi; fr_lmi_recv()
659 int dce = state(hdlc)->settings.dce; fr_lmi_recv()
730 state(hdlc)->rxseq = skb->data[i++]; /* TX sequence from peer */ fr_lmi_recv()
733 txseq = state(hdlc)->txseq; fr_lmi_recv()
736 state(hdlc)->last_poll = jiffies; fr_lmi_recv()
739 if (!state(hdlc)->reliable) fr_lmi_recv()
743 state(hdlc)->n391cnt = 0; fr_lmi_recv()
748 if (state(hdlc)->fullrep_sent && !error) { fr_lmi_recv()
750 state(hdlc)->fullrep_sent = 0; fr_lmi_recv()
751 pvc = state(hdlc)->first_pvc; fr_lmi_recv()
753 if (pvc->state.new) { fr_lmi_recv()
754 pvc->state.new = 0; fr_lmi_recv()
757 state(hdlc)->dce_changed = 1; fr_lmi_recv()
763 if (state(hdlc)->dce_changed) { fr_lmi_recv()
765 state(hdlc)->fullrep_sent = 1; fr_lmi_recv()
766 state(hdlc)->dce_changed = 0; fr_lmi_recv()
769 state(hdlc)->request = 1; /* got request */ fr_lmi_recv()
776 state(hdlc)->request = 0; /* got response, no request pending */ fr_lmi_recv()
784 pvc = state(hdlc)->first_pvc; fr_lmi_recv()
787 pvc->state.deleted = 1; fr_lmi_recv()
832 pvc->state.exist = 1; fr_lmi_recv()
833 pvc->state.deleted = 0; fr_lmi_recv()
834 if (active != pvc->state.active || fr_lmi_recv()
835 new != pvc->state.new || fr_lmi_recv()
836 bw != pvc->state.bandwidth || fr_lmi_recv()
837 !pvc->state.exist) { fr_lmi_recv()
838 pvc->state.new = new; fr_lmi_recv()
839 pvc->state.active = active; fr_lmi_recv()
840 pvc->state.bandwidth = bw; fr_lmi_recv()
849 pvc = state(hdlc)->first_pvc; fr_lmi_recv()
852 if (pvc->state.deleted && pvc->state.exist) { fr_lmi_recv()
854 pvc->state.active = pvc->state.new = 0; fr_lmi_recv()
855 pvc->state.exist = 0; fr_lmi_recv()
856 pvc->state.bandwidth = 0; fr_lmi_recv()
863 state(hdlc)->n391cnt = state(hdlc)->settings.n391; fr_lmi_recv()
885 (state(hdlc)->settings.lmi == LMI_ANSI || fr_rx()
886 state(hdlc)->settings.lmi == LMI_CCITT)) || fr_rx()
888 state(hdlc)->settings.lmi == LMI_CISCO)) { fr_rx()
905 if (pvc->state.fecn != fh->fecn) { fr_rx()
910 pvc->state.fecn ^= 1; fr_rx()
913 if (pvc->state.becn != fh->becn) { fr_rx()
918 pvc->state.becn ^= 1; fr_rx()
973 if (pvc->state.becn) fr_rx()
997 if (state(hdlc)->settings.lmi != LMI_NONE) { fr_start()
998 state(hdlc)->reliable = 0; fr_start()
999 state(hdlc)->dce_changed = 1; fr_start()
1000 state(hdlc)->request = 0; fr_start()
1001 state(hdlc)->fullrep_sent = 0; fr_start()
1002 state(hdlc)->last_errors = 0xFFFFFFFF; fr_start()
1003 state(hdlc)->n391cnt = 0; fr_start()
1004 state(hdlc)->txseq = state(hdlc)->rxseq = 0; fr_start()
1006 init_timer(&state(hdlc)->timer); fr_start()
1008 state(hdlc)->timer.expires = jiffies + HZ; fr_start()
1009 state(hdlc)->timer.function = fr_timer; fr_start()
1010 state(hdlc)->timer.data = (unsigned long)dev; fr_start()
1011 add_timer(&state(hdlc)->timer); fr_start()
1023 if (state(hdlc)->settings.lmi != LMI_NONE) fr_stop()
1024 del_timer_sync(&state(hdlc)->timer); fr_stop()
1032 struct pvc_device *pvc = state(hdlc)->first_pvc; fr_close()
1111 state(hdlc)->dce_changed = 1; fr_add_pvc()
1112 state(hdlc)->dce_pvc_count++; fr_add_pvc()
1137 state(hdlc)->dce_pvc_count--; fr_del_pvc()
1138 state(hdlc)->dce_changed = 1; fr_del_pvc()
1149 struct pvc_device *pvc = state(hdlc)->first_pvc; fr_destroy()
1150 state(hdlc)->first_pvc = NULL; /* All PVCs destroyed */ fr_destroy()
1151 state(hdlc)->dce_pvc_count = 0; fr_destroy()
1152 state(hdlc)->dce_changed = 1; fr_destroy()
1198 if (copy_to_user(fr_s, &state(hdlc)->settings, size)) fr_ioctl()
1238 state(hdlc)->first_pvc = NULL; fr_ioctl()
1239 state(hdlc)->dce_pvc_count = 0; fr_ioctl()
1241 memcpy(&state(hdlc)->settings, &new_settings, size); fr_ioctl()
/linux-4.1.27/include/linux/
H A Dratelimit.h11 raw_spinlock_t lock; /* protect the state */
48 #define __ratelimit(state) ___ratelimit(state, __func__)
52 #define WARN_ON_RATELIMIT(condition, state) \
53 WARN_ON((condition) && __ratelimit(state))
70 #define WARN_ON_RATELIMIT(condition, state) \
H A Dnfs_fs_i.h10 u32 state; member in struct:nfs_lock_info
/linux-4.1.27/drivers/hid/
H A Dhid-wiimote-core.c61 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_queue_worker()
63 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_queue_worker()
129 if (wdata->state.flags & WIIPROTO_FLAG_RUMBLE) wiiproto_keep_rumble()
138 if (rumble == !!(wdata->state.flags & WIIPROTO_FLAG_RUMBLE)) wiiproto_req_rumble()
142 wdata->state.flags |= WIIPROTO_FLAG_RUMBLE; wiiproto_req_rumble()
144 wdata->state.flags &= ~WIIPROTO_FLAG_RUMBLE; wiiproto_req_rumble()
158 if ((wdata->state.flags & WIIPROTO_FLAGS_LEDS) == leds) wiiproto_req_leds()
160 wdata->state.flags = (wdata->state.flags & ~WIIPROTO_FLAGS_LEDS) | leds; wiiproto_req_leds()
199 __u8 ir = wdata->state.flags & WIIPROTO_FLAGS_IR; select_drm()
202 ext = (wdata->state.flags & WIIPROTO_FLAG_EXT_USED) || select_drm()
203 (wdata->state.flags & WIIPROTO_FLAG_MP_USED); select_drm()
206 if (wdata->state.devtype == WIIMOTE_DEV_BALANCE_BOARD) { select_drm()
214 if (wdata->state.flags & WIIPROTO_FLAG_ACCEL) { select_drm()
229 if (wdata->state.flags & WIIPROTO_FLAG_ACCEL) { select_drm()
247 if (wdata->state.flags & WIIPROTO_FLAG_DRM_LOCKED) wiiproto_req_drm()
248 drm = wdata->state.drm; wiiproto_req_drm()
256 wdata->state.drm = drm; wiiproto_req_drm()
275 if (accel == !!(wdata->state.flags & WIIPROTO_FLAG_ACCEL)) wiiproto_req_accel()
279 wdata->state.flags |= WIIPROTO_FLAG_ACCEL; wiiproto_req_accel()
281 wdata->state.flags &= ~WIIPROTO_FLAG_ACCEL; wiiproto_req_accel()
371 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_cmd_write()
374 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_cmd_write()
377 if (!ret && wdata->state.cmd_err) wiimote_cmd_write()
390 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_cmd_read()
391 wdata->state.cmd_read_size = size; wiimote_cmd_read()
392 wdata->state.cmd_read_buf = rmem; wiimote_cmd_read()
395 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_cmd_read()
399 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_cmd_read()
400 wdata->state.cmd_read_buf = NULL; wiimote_cmd_read()
401 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_cmd_read()
404 if (wdata->state.cmd_read_size == 0) wiimote_cmd_read()
407 ret = wdata->state.cmd_read_size; wiimote_cmd_read()
662 spin_lock_irq(&wdata->state.lock); wiimote_modules_load()
663 wdata->state.devtype = devtype; wiimote_modules_load()
664 spin_unlock_irq(&wdata->state.lock); wiimote_modules_load()
686 mods = wiimote_devtype_mods[wdata->state.devtype]; wiimote_modules_unload()
688 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_modules_unload()
689 wdata->state.devtype = WIIMOTE_DEV_UNKNOWN; wiimote_modules_unload()
690 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_modules_unload()
729 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_ext_load()
730 wdata->state.exttype = ext; wiimote_ext_load()
731 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_ext_load()
739 ops = wiimod_ext_table[wdata->state.exttype]; wiimote_ext_unload()
741 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_ext_unload()
742 wdata->state.exttype = WIIMOTE_EXT_UNKNOWN; wiimote_ext_unload()
743 wdata->state.flags &= ~WIIPROTO_FLAG_EXT_USED; wiimote_ext_unload()
744 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_ext_unload()
764 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_mp_load()
765 wdata->state.mp = mode; wiimote_mp_load()
766 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_mp_load()
774 if (wdata->state.mp < 2) wiimote_mp_unload()
779 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_mp_unload()
780 wdata->state.mp = 0; wiimote_mp_unload()
781 wdata->state.flags &= ~WIIPROTO_FLAG_MP_USED; wiimote_mp_unload()
782 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_mp_unload()
866 spin_lock_irq(&wdata->state.lock); wiimote_init_detect()
867 wdata->state.devtype = WIIMOTE_DEV_UNKNOWN; wiimote_init_detect()
870 spin_unlock_irq(&wdata->state.lock); wiimote_init_detect()
876 spin_lock_irq(&wdata->state.lock); wiimote_init_detect()
877 ext = wdata->state.flags & WIIPROTO_FLAG_EXT_PLUGGED; wiimote_init_detect()
878 spin_unlock_irq(&wdata->state.lock); wiimote_init_detect()
891 spin_lock_irq(&wdata->state.lock); wiimote_init_detect()
892 if (!(wdata->state.flags & WIIPROTO_FLAG_BUILTIN_MP) && wiimote_init_detect()
893 !(wdata->state.flags & WIIPROTO_FLAG_NO_MP)) wiimote_init_detect()
895 spin_unlock_irq(&wdata->state.lock); wiimote_init_detect()
916 if (!wdata->state.mp) { wiimote_init_poll_mp()
920 } else if (wdata->state.mp) { wiimote_init_poll_mp()
928 * Check whether the wiimote is in the expected state. The extension registers
932 * expected state, we can ignore the hotplug event.
934 * Returns "true" if the device is in expected state, "false" if we should
943 spin_lock_irq(&wdata->state.lock); wiimote_init_check()
944 flags = wdata->state.flags; wiimote_init_check()
945 spin_unlock_irq(&wdata->state.lock); wiimote_init_check()
951 * state.flags == !EXT_ACTIVE && !MP_PLUGGED && MP_ACTIVE wiimote_init_check()
956 if (wdata->state.exttype == WIIMOTE_EXT_NONE && wiimote_init_check()
957 wdata->state.mp > 0 && (flags & WIIPROTO_FLAG_MP_USED)) { wiimote_init_check()
961 spin_lock_irq(&wdata->state.lock); wiimote_init_check()
962 ret = ret && !(wdata->state.flags & WIIPROTO_FLAG_EXT_ACTIVE); wiimote_init_check()
963 ret = ret && !(wdata->state.flags & WIIPROTO_FLAG_MP_PLUGGED); wiimote_init_check()
964 ret = ret && (wdata->state.flags & WIIPROTO_FLAG_MP_ACTIVE); wiimote_init_check()
965 spin_unlock_irq(&wdata->state.lock); wiimote_init_check()
968 hid_dbg(wdata->hdev, "state left: !EXT && MP\n"); wiimote_init_check()
977 * read_ext == state.exttype wiimote_init_check()
978 * state.flags == !MP_ACTIVE && EXT_ACTIVE wiimote_init_check()
982 wdata->state.exttype != WIIMOTE_EXT_NONE) { wiimote_init_check()
984 ret = type == wdata->state.exttype; wiimote_init_check()
986 spin_lock_irq(&wdata->state.lock); wiimote_init_check()
987 ret = ret && !(wdata->state.flags & WIIPROTO_FLAG_MP_ACTIVE); wiimote_init_check()
988 ret = ret && (wdata->state.flags & WIIPROTO_FLAG_EXT_ACTIVE); wiimote_init_check()
989 spin_unlock_irq(&wdata->state.lock); wiimote_init_check()
992 hid_dbg(wdata->hdev, "state left: EXT && !MP\n"); wiimote_init_check()
1002 * state.flags == !MP_ACTIVE && !EXT_ACTIVE && !EXT_PLUGGED wiimote_init_check()
1008 wdata->state.exttype == WIIMOTE_EXT_NONE) { wiimote_init_check()
1010 ret = type == wdata->state.exttype; wiimote_init_check()
1012 spin_lock_irq(&wdata->state.lock); wiimote_init_check()
1013 ret = ret && !(wdata->state.flags & WIIPROTO_FLAG_EXT_ACTIVE); wiimote_init_check()
1014 ret = ret && !(wdata->state.flags & WIIPROTO_FLAG_MP_ACTIVE); wiimote_init_check()
1015 ret = ret && !(wdata->state.flags & WIIPROTO_FLAG_EXT_PLUGGED); wiimote_init_check()
1016 spin_unlock_irq(&wdata->state.lock); wiimote_init_check()
1019 hid_dbg(wdata->hdev, "state left: !EXT && !MP\n"); wiimote_init_check()
1035 if (wdata->state.exttype != WIIMOTE_EXT_NONE && wiimote_init_check()
1036 wdata->state.mp > 0 && (flags & WIIPROTO_FLAG_MP_USED)) { wiimote_init_check()
1042 spin_lock_irq(&wdata->state.lock); wiimote_init_check()
1043 ret = ret && (wdata->state.flags & WIIPROTO_FLAG_EXT_PLUGGED); wiimote_init_check()
1044 ret = ret && (wdata->state.flags & WIIPROTO_FLAG_EXT_ACTIVE); wiimote_init_check()
1045 ret = ret && (wdata->state.flags & WIIPROTO_FLAG_MP_ACTIVE); wiimote_init_check()
1046 spin_unlock_irq(&wdata->state.lock); wiimote_init_check()
1049 hid_dbg(wdata->hdev, "state left: EXT && MP\n"); wiimote_init_check()
1057 /* unknown state */ wiimote_init_check()
1063 /* only poll for MP if requested and if state didn't change */ wiimote_init_check()
1084 * the desired state. This involves mapping MP into the main extension
1098 spin_lock_irq(&wdata->state.lock); wiimote_init_hotplug()
1100 /* get state snapshot that we will then work on */ wiimote_init_hotplug()
1101 flags = wdata->state.flags; wiimote_init_hotplug()
1104 wdata->state.flags &= ~WIIPROTO_FLAG_EXT_ACTIVE; wiimote_init_hotplug()
1105 wdata->state.flags &= ~WIIPROTO_FLAG_MP_ACTIVE; wiimote_init_hotplug()
1107 spin_unlock_irq(&wdata->state.lock); wiimote_init_hotplug()
1122 if (exttype != wdata->state.exttype) { wiimote_init_hotplug()
1130 spin_lock_irq(&wdata->state.lock); wiimote_init_hotplug()
1131 wdata->state.exttype = WIIMOTE_EXT_NONE; wiimote_init_hotplug()
1132 spin_unlock_irq(&wdata->state.lock); wiimote_init_hotplug()
1143 if (!wdata->state.mp) { wiimote_init_hotplug()
1147 } else if (wdata->state.mp) { wiimote_init_hotplug()
1170 spin_lock_irq(&wdata->state.lock); wiimote_init_hotplug()
1172 /* enable data forwarding again and set expected hotplug state */ wiimote_init_hotplug()
1174 wdata->state.flags |= WIIPROTO_FLAG_MP_ACTIVE; wiimote_init_hotplug()
1175 if (wdata->state.exttype == WIIMOTE_EXT_NONE) { wiimote_init_hotplug()
1176 wdata->state.flags &= ~WIIPROTO_FLAG_EXT_PLUGGED; wiimote_init_hotplug()
1177 wdata->state.flags &= ~WIIPROTO_FLAG_MP_PLUGGED; wiimote_init_hotplug()
1179 wdata->state.flags &= ~WIIPROTO_FLAG_EXT_PLUGGED; wiimote_init_hotplug()
1180 wdata->state.flags |= WIIPROTO_FLAG_MP_PLUGGED; wiimote_init_hotplug()
1181 wdata->state.flags |= WIIPROTO_FLAG_EXT_ACTIVE; wiimote_init_hotplug()
1183 } else if (wdata->state.exttype != WIIMOTE_EXT_NONE) { wiimote_init_hotplug()
1184 wdata->state.flags |= WIIPROTO_FLAG_EXT_ACTIVE; wiimote_init_hotplug()
1187 /* request status report for hotplug state updates */ wiimote_init_hotplug()
1190 spin_unlock_irq(&wdata->state.lock); wiimote_init_hotplug()
1193 wdata->state.mp, wdata->state.exttype); wiimote_init_hotplug()
1202 if (wdata->state.devtype == WIIMOTE_DEV_PENDING) { wiimote_init_worker()
1216 if (!(wdata->state.flags & WIIPROTO_FLAG_EXITING)) __wiimote_schedule()
1224 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_schedule()
1226 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_schedule()
1243 ops = wiimod_ext_table[wdata->state.exttype]; handler_keys()
1249 mods = wiimote_devtype_mods[wdata->state.devtype]; handler_keys()
1264 ops = wiimod_ext_table[wdata->state.exttype]; handler_accel()
1270 mods = wiimote_devtype_mods[wdata->state.devtype]; handler_accel()
1311 if (wdata->state.flags & WIIPROTO_FLAG_MP_ACTIVE) { handler_ext()
1317 if (!(wdata->state.flags & WIIPROTO_FLAG_MP_PLUGGED)) { handler_ext()
1319 wdata->state.flags |= WIIPROTO_FLAG_MP_PLUGGED; handler_ext()
1323 if (wdata->state.flags & WIIPROTO_FLAG_MP_PLUGGED) { handler_ext()
1325 wdata->state.flags &= ~WIIPROTO_FLAG_MP_PLUGGED; handler_ext()
1326 wdata->state.flags &= ~WIIPROTO_FLAG_EXT_ACTIVE; handler_ext()
1338 if (!(wdata->state.flags & WIIPROTO_FLAG_EXT_ACTIVE) && !is_mp) handler_ext()
1342 ops = wiimod_ext_table[wdata->state.exttype]; handler_ext()
1362 mods = wiimote_devtype_mods[wdata->state.devtype]; handler_ext()
1386 ops = wiimod_ext_table[wdata->state.exttype]; handler_ir()
1392 mods = wiimote_devtype_mods[wdata->state.devtype]; handler_ir()
1419 if (!(wdata->state.flags & WIIPROTO_FLAG_EXT_PLUGGED)) { handler_status()
1421 wdata->state.flags |= WIIPROTO_FLAG_EXT_PLUGGED; handler_status()
1425 if (wdata->state.flags & WIIPROTO_FLAG_EXT_PLUGGED) { handler_status()
1427 wdata->state.flags &= ~WIIPROTO_FLAG_EXT_PLUGGED; handler_status()
1428 wdata->state.flags &= ~WIIPROTO_FLAG_MP_PLUGGED; handler_status()
1429 wdata->state.flags &= ~WIIPROTO_FLAG_EXT_ACTIVE; handler_status()
1430 wdata->state.flags &= ~WIIPROTO_FLAG_MP_ACTIVE; handler_status()
1435 wdata->state.cmd_battery = payload[5]; handler_status()
1457 else if (size > wdata->state.cmd_read_size) handler_data()
1458 size = wdata->state.cmd_read_size; handler_data()
1460 wdata->state.cmd_read_size = size; handler_data()
1461 if (wdata->state.cmd_read_buf) handler_data()
1462 memcpy(wdata->state.cmd_read_buf, &payload[5], size); handler_data()
1475 wdata->state.cmd_err = err; handler_return()
1548 wdata->state.accel_split[0] = payload[2]; handler_drm_SKAI1()
1549 wdata->state.accel_split[1] = (payload[0] >> 1) & (0x10 | 0x20); handler_drm_SKAI1()
1550 wdata->state.accel_split[1] |= (payload[1] << 1) & (0x40 | 0x80); handler_drm_SKAI1()
1562 wdata->state.accel_split[1] |= (payload[0] >> 5) & (0x01 | 0x02); handler_drm_SKAI2()
1563 wdata->state.accel_split[1] |= (payload[1] >> 3) & (0x04 | 0x08); handler_drm_SKAI2()
1567 buf[2] = wdata->state.accel_split[0]; handler_drm_SKAI2()
1569 buf[4] = wdata->state.accel_split[1]; handler_drm_SKAI2()
1621 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_hid_event()
1635 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_hid_event()
1648 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_ext_show()
1649 type = wdata->state.exttype; wiimote_ext_show()
1650 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_ext_show()
1696 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_dev_show()
1697 type = wdata->state.devtype; wiimote_dev_show()
1698 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_dev_show()
1736 spin_lock_init(&wdata->state.lock); wiimote_create()
1737 init_completion(&wdata->state.ready); wiimote_create()
1738 mutex_init(&wdata->state.sync); wiimote_create()
1739 wdata->state.drm = WIIPROTO_REQ_DRM_K; wiimote_create()
1740 wdata->state.cmd_battery = 0xff; wiimote_create()
1755 spin_lock_irqsave(&wdata->state.lock, flags); wiimote_destroy()
1756 wdata->state.flags |= WIIPROTO_FLAG_EXITING; wiimote_destroy()
1757 spin_unlock_irqrestore(&wdata->state.lock, flags); wiimote_destroy()
/linux-4.1.27/security/apparmor/
H A Dmatch.c285 * aa_dfa_match_len - traverse @dfa to find state @str stops at
287 * @start: the state of the dfa to start matching in
291 * aa_dfa_match_len will match @str against the dfa and return the state it
292 * finished matching in. The final state can be used to look up the accepting
293 * label, or as the start state of a continuing match.
298 * Returns: final state reached after input is consumed
307 unsigned int state = start, pos; aa_dfa_match_len() local
309 if (state == 0) aa_dfa_match_len()
312 /* current state is <state>, matching character *str */ aa_dfa_match_len()
316 /* default is direct to next state */ aa_dfa_match_len()
318 pos = base_idx(base[state]) + equiv[(u8) *str++]; aa_dfa_match_len()
319 if (check[pos] == state) aa_dfa_match_len()
320 state = next[pos]; aa_dfa_match_len()
322 state = def[state]; aa_dfa_match_len()
325 /* default is direct to next state */ aa_dfa_match_len()
327 pos = base_idx(base[state]) + (u8) *str++; aa_dfa_match_len()
328 if (check[pos] == state) aa_dfa_match_len()
329 state = next[pos]; aa_dfa_match_len()
331 state = def[state]; aa_dfa_match_len()
335 return state; aa_dfa_match_len()
339 * aa_dfa_match - traverse @dfa to find state @str stops at
341 * @start: the state of the dfa to start matching in
344 * aa_dfa_match will match @str against the dfa and return the state it
345 * finished matching in. The final state can be used to look up the accepting
346 * label, or as the start state of a continuing match.
348 * Returns: final state reached after input is consumed
357 unsigned int state = start, pos; aa_dfa_match() local
359 if (state == 0) aa_dfa_match()
362 /* current state is <state>, matching character *str */ aa_dfa_match()
366 /* default is direct to next state */ aa_dfa_match()
368 pos = base_idx(base[state]) + equiv[(u8) *str++]; aa_dfa_match()
369 if (check[pos] == state) aa_dfa_match()
370 state = next[pos]; aa_dfa_match()
372 state = def[state]; aa_dfa_match()
375 /* default is direct to next state */ aa_dfa_match()
377 pos = base_idx(base[state]) + (u8) *str++; aa_dfa_match()
378 if (check[pos] == state) aa_dfa_match()
379 state = next[pos]; aa_dfa_match()
381 state = def[state]; aa_dfa_match()
385 return state; aa_dfa_match()
389 * aa_dfa_next - step one character to the next state in the dfa
391 * @state: the state to start in
396 * Returns: state reach after input @c
398 unsigned int aa_dfa_next(struct aa_dfa *dfa, unsigned int state, aa_dfa_next() argument
407 /* current state is <state>, matching character *str */ aa_dfa_next()
411 /* default is direct to next state */ aa_dfa_next()
413 pos = base_idx(base[state]) + equiv[(u8) c]; aa_dfa_next()
414 if (check[pos] == state) aa_dfa_next()
415 state = next[pos]; aa_dfa_next()
417 state = def[state]; aa_dfa_next()
419 /* default is direct to next state */ aa_dfa_next()
420 pos = base_idx(base[state]) + (u8) c; aa_dfa_next()
421 if (check[pos] == state) aa_dfa_next()
422 state = next[pos]; aa_dfa_next()
424 state = def[state]; aa_dfa_next()
427 return state; aa_dfa_next()
/linux-4.1.27/include/net/netfilter/
H A Dnf_nat_l3proto.h47 const struct nf_hook_state *state,
50 const struct nf_hook_state *state,
54 const struct nf_hook_state *state,
57 const struct nf_hook_state *state,
62 const struct nf_hook_state *state,
65 const struct nf_hook_state *state,
69 const struct nf_hook_state *state,
72 const struct nf_hook_state *state,
80 const struct nf_hook_state *state,
83 const struct nf_hook_state *state,
87 const struct nf_hook_state *state,
90 const struct nf_hook_state *state,
95 const struct nf_hook_state *state,
98 const struct nf_hook_state *state,
102 const struct nf_hook_state *state,
105 const struct nf_hook_state *state,
H A Dnf_tables_ipv4.h11 const struct nf_hook_state *state) nft_set_pktinfo_ipv4()
15 nft_set_pktinfo(pkt, ops, skb, state); nft_set_pktinfo_ipv4()
8 nft_set_pktinfo_ipv4(struct nft_pktinfo *pkt, const struct nf_hook_ops *ops, struct sk_buff *skb, const struct nf_hook_state *state) nft_set_pktinfo_ipv4() argument
/linux-4.1.27/arch/powerpc/platforms/pseries/
H A Doffline_states.h14 extern void set_cpu_current_state(int cpu, enum cpu_state_vals state);
15 extern void set_preferred_offline_state(int cpu, enum cpu_state_vals state);
23 static inline void set_cpu_current_state(int cpu, enum cpu_state_vals state) set_cpu_current_state() argument
27 static inline void set_preferred_offline_state(int cpu, enum cpu_state_vals state) set_preferred_offline_state() argument
/linux-4.1.27/arch/sh/include/asm/
H A Dspi.h10 void (*chip_select)(struct sh_spi_info *spi, int cs, int state);
/linux-4.1.27/arch/frv/include/asm/
H A Dfpu.h6 * MAX floating point unit state size (FSAVE/FRESTORE)
/linux-4.1.27/include/linux/mfd/
H A Dqcom_rpm.h11 int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count);
/linux-4.1.27/drivers/gpu/drm/msm/
H A Dmsm_atomic.c24 struct drm_atomic_state *state; member in struct:msm_commit
62 static struct msm_commit *commit_init(struct drm_atomic_state *state) commit_init() argument
69 c->dev = state->dev; commit_init()
70 c->state = state; commit_init()
92 struct drm_atomic_state *state = c->state; complete_commit() local
93 struct drm_device *dev = state->dev; complete_commit()
97 kms->funcs->prepare_commit(kms, state); complete_commit()
99 drm_atomic_helper_commit_modeset_disables(dev, state); complete_commit()
101 drm_atomic_helper_commit_planes(dev, state); complete_commit()
103 drm_atomic_helper_commit_modeset_enables(dev, state); complete_commit()
118 drm_atomic_helper_wait_for_vblanks(dev, state); complete_commit()
120 drm_atomic_helper_cleanup_planes(dev, state); complete_commit()
122 kms->funcs->complete_commit(kms, state); complete_commit()
124 drm_atomic_state_free(state); complete_commit()
144 struct drm_atomic_state *state) msm_atomic_check()
152 ret = drm_atomic_helper_check_planes(dev, state); msm_atomic_check()
156 ret = drm_atomic_helper_check_modeset(dev, state); msm_atomic_check()
164 * drm_atomic_helper_commit - commit validated state object
166 * @state: the driver state object
169 * This function commits a with drm_atomic_helper_check() pre-validated state
177 struct drm_atomic_state *state, bool async) msm_atomic_commit()
185 ret = drm_atomic_helper_prepare_planes(dev, state); msm_atomic_commit()
189 c = commit_init(state); msm_atomic_commit()
197 struct drm_crtc *crtc = state->crtcs[i]; msm_atomic_commit()
207 struct drm_plane *plane = state->planes[i]; msm_atomic_commit()
208 struct drm_plane_state *new_state = state->plane_states[i]; msm_atomic_commit()
213 if ((plane->state->fb != new_state->fb) && new_state->fb) msm_atomic_commit()
229 * when the hw goes bonghits. Which means we can commit the new state on msm_atomic_commit()
233 drm_atomic_helper_swap_state(dev, state); msm_atomic_commit()
241 * before the new state gets committed on the software side with msm_atomic_commit()
244 * This scheme allows new atomic state updates to be prepared and msm_atomic_commit()
260 WARN_ON(ret); // TODO unswap state back? or?? msm_atomic_commit()
143 msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) msm_atomic_check() argument
176 msm_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, bool async) msm_atomic_commit() argument
/linux-4.1.27/net/llc/
H A Dllc_s_st.c2 * llc_s_st.c - Defines SAP component state machine transitions.
4 * The followed transitions are SAP component state machine transitions
23 /* dummy last-transition indicator; common to all state transition groups
24 * last entry for this state
29 /* state LLC_SAP_STATE_INACTIVE transition for
49 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_RX_UI event */
61 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_UNITDATA_REQ event */
73 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_XID_REQ event */
85 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_RX_XID_C event */
97 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_RX_XID_R event */
109 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_TEST_REQ event */
121 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_RX_TEST_C event */
133 /* state LLC_SAP_STATE_ACTIVE transition for LLC_SAP_EV_RX_TEST_R event */
145 /* state LLC_SAP_STATE_ACTIVE transition for
173 /* SAP state transition table */
/linux-4.1.27/drivers/video/fbdev/riva/
H A Driva_hw.c242 static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) nv3_iterate() argument
273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; nv3_iterate()
277 if (state->enable_mp) nv3_iterate()
285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; nv3_iterate()
290 if (!state->gr_during_vid && ainfo->vid_en) nv3_iterate()
340 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; nv3_iterate()
344 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; nv3_iterate()
356 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; nv3_iterate()
360 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; nv3_iterate()
370 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; nv3_iterate()
381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; nv3_iterate()
388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; nv3_iterate()
427 static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) nv3_arb() argument
433 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; nv3_arb()
435 if (state->mem_aligned) gmisses = 2; nv3_arb()
438 eburst_size = state->memory_width * 1; nv3_arb()
440 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; nv3_arb()
451 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; nv3_arb()
452 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; nv3_arb()
459 nv3_iterate(res_info, state,ainfo); nv3_arb()
461 if (state->enable_mp) nv3_arb()
463 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; nv3_arb()
464 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; nv3_arb()
471 nv3_iterate(res_info, state,ainfo); nv3_arb()
478 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; nv3_arb()
481 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; nv3_arb()
483 nv3_iterate(res_info, state,ainfo); nv3_arb()
490 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; nv3_arb()
493 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; nv3_arb()
495 nv3_iterate(res_info, state, ainfo); nv3_arb()
533 static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) nv3_get_param() argument
547 done = nv3_arb(res_info, state,ainfo); nv3_get_param()
563 nv3_sim_state * state nv3CalcArbitration()
571 ainfo.vid_en = state->enable_video; nv3CalcArbitration()
574 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); nv3CalcArbitration()
575 ainfo.vdrain_rate = (int) state->pclk_khz * 2; nv3CalcArbitration()
576 if (state->video_scale != 0) nv3CalcArbitration()
577 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; nv3CalcArbitration()
580 if (!state->gr_during_vid && state->enable_video) nv3CalcArbitration()
585 res_vid = nv3_get_param(res_info, state, &ainfo); nv3CalcArbitration()
592 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); nv3CalcArbitration()
594 res_gr = nv3_get_param(res_info, state, &ainfo); nv3CalcArbitration()
604 res_gr = nv3_get_param(res_info, state, &ainfo); nv3CalcArbitration()
1231 * mode state structure.
1236 RIVA_HW_STATE *state, CalcStateExt()
1251 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ CalcStateExt()
1252 state->width = width; CalcStateExt()
1253 state->height = height; CalcStateExt()
1266 &(state->arbitration0), CalcStateExt()
1267 &(state->arbitration1), CalcStateExt()
1269 state->cursor0 = 0x00; CalcStateExt()
1270 state->cursor1 = 0x78; CalcStateExt()
1271 state->cursor2 = 0x00000000; CalcStateExt()
1272 state->pllsel = 0x10010100; CalcStateExt()
1273 state->config = ((width + 31)/32) CalcStateExt()
1276 state->general = 0x00100100; CalcStateExt()
1277 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; CalcStateExt()
1282 &(state->arbitration0), CalcStateExt()
1283 &(state->arbitration1), CalcStateExt()
1285 state->cursor0 = 0x00; CalcStateExt()
1286 state->cursor1 = 0xFC; CalcStateExt()
1287 state->cursor2 = 0x00000000; CalcStateExt()
1288 state->pllsel = 0x10000700; CalcStateExt()
1289 state->config = 0x00001114; CalcStateExt()
1290 state->general = bpp == 16 ? 0x00101100 : 0x00100100; CalcStateExt()
1291 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; CalcStateExt()
1301 &(state->arbitration0), CalcStateExt()
1302 &(state->arbitration1), CalcStateExt()
1307 &(state->arbitration0), CalcStateExt()
1308 &(state->arbitration1), CalcStateExt()
1311 state->cursor0 = 0x80 | (chip->CursorStart >> 17); CalcStateExt()
1312 state->cursor1 = (chip->CursorStart >> 11) << 2; CalcStateExt()
1313 state->cursor2 = chip->CursorStart >> 24; CalcStateExt()
1314 state->pllsel = 0x10000700; CalcStateExt()
1315 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); CalcStateExt()
1316 state->general = bpp == 16 ? 0x00101100 : 0x00100100; CalcStateExt()
1317 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; CalcStateExt()
1324 state->general |= 0x00000030; CalcStateExt()
1326 state->vpll = (p << 16) | (n << 8) | m; CalcStateExt()
1327 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; CalcStateExt()
1328 state->pixel = pixelDepth > 2 ? 3 : pixelDepth; CalcStateExt()
1329 state->offset0 = CalcStateExt()
1330 state->offset1 = CalcStateExt()
1331 state->offset2 = CalcStateExt()
1332 state->offset3 = 0; CalcStateExt()
1333 state->pitch0 = CalcStateExt()
1334 state->pitch1 = CalcStateExt()
1335 state->pitch2 = CalcStateExt()
1336 state->pitch3 = pixelDepth * width; CalcStateExt()
1341 * Load fixed function state and pre-calculated/stored state.
1395 * Initialize state for the RivaTriangle3D05 routines. UpdateFifoState()
1407 RIVA_HW_STATE *state LoadStateExt()
1413 * Load HW fixed function state. LoadStateExt()
1423 NV_WR32(chip->PFB, 0x00000200, state->config); LoadStateExt()
1427 switch (state->bpp) LoadStateExt()
1450 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); LoadStateExt()
1451 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); LoadStateExt()
1452 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); LoadStateExt()
1453 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); LoadStateExt()
1454 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); LoadStateExt()
1455 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); LoadStateExt()
1456 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); LoadStateExt()
1457 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); LoadStateExt()
1463 NV_WR32(chip->PFB, 0x00000200, state->config); LoadStateExt()
1467 switch (state->bpp) LoadStateExt()
1492 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); LoadStateExt()
1493 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); LoadStateExt()
1494 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); LoadStateExt()
1495 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); LoadStateExt()
1496 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); LoadStateExt()
1497 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); LoadStateExt()
1498 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); LoadStateExt()
1499 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); LoadStateExt()
1506 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); LoadStateExt()
1513 switch (state->bpp) LoadStateExt()
1540 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); LoadStateExt()
1541 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); LoadStateExt()
1542 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); LoadStateExt()
1543 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); LoadStateExt()
1544 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); LoadStateExt()
1545 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); LoadStateExt()
1546 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); LoadStateExt()
1547 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); LoadStateExt()
1548 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); LoadStateExt()
1550 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); LoadStateExt()
1551 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); LoadStateExt()
1552 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); LoadStateExt()
1553 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); LoadStateExt()
1554 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); LoadStateExt()
1555 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); LoadStateExt()
1556 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); LoadStateExt()
1557 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); LoadStateExt()
1558 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); LoadStateExt()
1559 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); LoadStateExt()
1564 NV_WR32(chip->PCRTC0, 0x00000860, state->head); LoadStateExt()
1565 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); LoadStateExt()
1660 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); LoadStateExt()
1664 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); LoadStateExt()
1667 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); LoadStateExt()
1679 VGA_WR08(chip->PCIO, 0x03D5, state->extra); LoadStateExt()
1684 * Load HW mode state. LoadStateExt()
1687 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); LoadStateExt()
1689 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); LoadStateExt()
1691 VGA_WR08(chip->PCIO, 0x03D5, state->screen); LoadStateExt()
1693 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); LoadStateExt()
1695 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); LoadStateExt()
1697 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); LoadStateExt()
1699 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); LoadStateExt()
1701 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); LoadStateExt()
1703 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); LoadStateExt()
1705 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); LoadStateExt()
1707 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); LoadStateExt()
1710 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); LoadStateExt()
1711 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); LoadStateExt()
1713 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); LoadStateExt()
1715 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); LoadStateExt()
1717 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); LoadStateExt()
1729 * Set current state pointer. LoadStateExt()
1731 chip->CurrentState = state; LoadStateExt()
1742 RIVA_HW_STATE *state UnloadStateExt()
1746 * Save current HW state. UnloadStateExt()
1749 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1751 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1753 state->screen = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1755 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1757 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1759 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1761 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1763 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1765 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1767 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1769 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1770 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); UnloadStateExt()
1771 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); UnloadStateExt()
1772 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); UnloadStateExt()
1773 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); UnloadStateExt()
1774 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); UnloadStateExt()
1775 state->config = NV_RD32(chip->PFB, 0x00000200); UnloadStateExt()
1779 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); UnloadStateExt()
1780 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); UnloadStateExt()
1781 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); UnloadStateExt()
1782 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); UnloadStateExt()
1783 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); UnloadStateExt()
1784 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); UnloadStateExt()
1785 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); UnloadStateExt()
1786 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); UnloadStateExt()
1789 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); UnloadStateExt()
1790 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); UnloadStateExt()
1791 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); UnloadStateExt()
1792 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); UnloadStateExt()
1793 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); UnloadStateExt()
1794 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); UnloadStateExt()
1795 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); UnloadStateExt()
1796 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); UnloadStateExt()
1801 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); UnloadStateExt()
1802 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); UnloadStateExt()
1803 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); UnloadStateExt()
1804 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); UnloadStateExt()
1805 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); UnloadStateExt()
1806 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); UnloadStateExt()
1807 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); UnloadStateExt()
1808 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); UnloadStateExt()
1810 state->head = NV_RD32(chip->PCRTC0, 0x00000860); UnloadStateExt()
1811 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); UnloadStateExt()
1813 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1816 state->extra = VGA_RD08(chip->PCIO, 0x03D5); UnloadStateExt()
1817 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); UnloadStateExt()
1820 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); UnloadStateExt()
1823 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); UnloadStateExt()
1233 CalcStateExt( RIVA_HW_INST *chip, RIVA_HW_STATE *state, int bpp, int width, int hDisplaySize, int height, int dotClock ) CalcStateExt() argument
/linux-4.1.27/arch/x86/crypto/sha-mb/
H A Dsha1_mb_mgr_flush_avx2.S65 #define state arg1 define
113 # JOB* sha1_mb_mgr_flush_avx2(MB_MGR *state)
114 # arg 1 : rcx : state
128 mov _unused_lanes(state), unused_lanes
135 cmpq $0, offset(state)
138 cmpq $0, offset(state)
141 cmpq $0, offset(state)
144 cmpq $0, offset(state)
147 cmpq $0, offset(state)
150 cmpq $0, offset(state)
153 cmpq $0, offset(state)
159 mov offset(state,idx,8), tmp
164 cmpq $0, offset(state)
168 mov tmp, offset(state)
170 movl $0xFFFFFFFF, offset(state)
177 vmovdqa _lens+0*16(state), %xmm0
178 vmovdqa _lens+1*16(state), %xmm1
198 vmovdqa %xmm0, _lens+0*16(state)
199 vmovdqa %xmm1, _lens+1*16(state)
201 # "state" and "args" are the same address, arg1
204 # state and idx are intact
210 lea _ldata(state, lane_data), lane_data
215 mov _unused_lanes(state), unused_lanes
218 mov unused_lanes, _unused_lanes(state)
220 movl $0xFFFFFFFF, _lens(state, idx, 4)
222 vmovd _args_digest(state , idx, 4) , %xmm0
223 vpinsrd $1, _args_digest+1*32(state, idx, 4), %xmm0, %xmm0
224 vpinsrd $2, _args_digest+2*32(state, idx, 4), %xmm0, %xmm0
225 vpinsrd $3, _args_digest+3*32(state, idx, 4), %xmm0, %xmm0
226 movl _args_digest+4*32(state, idx, 4), tmp2_w
258 mov _unused_lanes(state), unused_lanes
263 vmovdqa _lens(state), %xmm0
264 vmovdqa _lens+1*16(state), %xmm1
278 lea _ldata(state, lane_data), lane_data
283 mov _unused_lanes(state), unused_lanes
286 mov unused_lanes, _unused_lanes(state)
288 movl $0xFFFFFFFF, _lens(state, idx, 4)
290 vmovd _args_digest(state, idx, 4), %xmm0
291 vpinsrd $1, _args_digest+1*32(state, idx, 4), %xmm0, %xmm0
292 vpinsrd $2, _args_digest+2*32(state, idx, 4), %xmm0, %xmm0
293 vpinsrd $3, _args_digest+3*32(state, idx, 4), %xmm0, %xmm0
294 movl _args_digest+4*32(state, idx, 4), tmp2_w
/linux-4.1.27/drivers/ide/
H A Dicside.c89 struct icside_state *state = ec->irq_data; icside_irqenable_arcin_v5() local
91 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); icside_irqenable_arcin_v5()
99 struct icside_state *state = ec->irq_data; icside_irqdisable_arcin_v5() local
101 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); icside_irqdisable_arcin_v5()
116 struct icside_state *state = ec->irq_data; icside_irqenable_arcin_v6() local
117 void __iomem *base = state->irq_port; icside_irqenable_arcin_v6()
119 state->enabled = 1; icside_irqenable_arcin_v6()
121 switch (state->channel) { icside_irqenable_arcin_v6()
138 struct icside_state *state = ec->irq_data; icside_irqdisable_arcin_v6() local
140 state->enabled = 0; icside_irqdisable_arcin_v6()
142 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); icside_irqdisable_arcin_v6()
143 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); icside_irqdisable_arcin_v6()
151 struct icside_state *state = ec->irq_data; icside_irqpending_arcin_v6() local
153 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || icside_irqpending_arcin_v6()
154 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; icside_irqpending_arcin_v6()
171 struct icside_state *state = ecard_get_drvdata(ec); icside_maskproc() local
176 state->channel = hwif->channel; icside_maskproc()
178 if (state->enabled && !mask) { icside_maskproc()
181 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); icside_maskproc()
182 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); icside_maskproc()
185 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); icside_maskproc()
186 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); icside_maskproc()
190 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); icside_maskproc()
191 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); icside_maskproc()
312 struct icside_state *state = ecard_get_drvdata(ec); icside_dma_setup() local
333 writeb(state->sel | hwif->channel, state->ioc_base); icside_dma_setup()
354 struct icside_state *state = ecard_get_drvdata(ec); icside_dma_test_irq() local
356 return readb(state->irq_port + icside_dma_test_irq()
409 static int icside_register_v5(struct icside_state *state, icside_register_v5() argument
421 state->irq_port = base; icside_register_v5()
426 ecard_setirq(ec, &icside_ops_arcin_v5, state); icside_register_v5()
439 state->host = host; icside_register_v5()
441 ecard_set_drvdata(ec, state); icside_register_v5()
463 static int icside_register_v6(struct icside_state *state, icside_register_v6() argument
496 ecard_setirq(ec, &icside_ops_arcin_v6, state); icside_register_v6()
498 state->irq_port = easi_base; icside_register_v6()
499 state->ioc_base = ioc_base; icside_register_v6()
500 state->sel = sel; icside_register_v6()
514 state->host = host; icside_register_v6()
516 ecard_set_drvdata(ec, state); icside_register_v6()
542 struct icside_state *state; icside_probe() local
550 state = kzalloc(sizeof(struct icside_state), GFP_KERNEL); icside_probe()
551 if (!state) { icside_probe()
556 state->type = ICS_TYPE_NOTYPE; icside_probe()
568 state->type = type; icside_probe()
571 switch (state->type) { icside_probe()
583 ret = icside_register_v5(state, ec); icside_probe()
587 ret = icside_register_v6(state, ec); icside_probe()
599 kfree(state); icside_probe()
608 struct icside_state *state = ecard_get_drvdata(ec); icside_remove() local
610 switch (state->type) { icside_remove()
627 writeb(0, state->ioc_base); icside_remove()
633 kfree(state); icside_remove()
639 struct icside_state *state = ecard_get_drvdata(ec); icside_shutdown() local
656 if (state->ioc_base) icside_shutdown()
657 writeb(0, state->ioc_base); icside_shutdown()
/linux-4.1.27/arch/blackfin/include/asm/
H A Dpm.h17 int (*valid)(suspend_state_t state);
18 void (*enter)(suspend_state_t state);

Completed in 3814 milliseconds

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