Lines Matching refs:state
241 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) in Read16() argument
243 u8 adr = state->config.demod_address; in Read16()
248 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) in Read16()
255 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) in Read32() argument
257 u8 adr = state->config.demod_address; in Read32()
263 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) in Read32()
271 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) in Write16() argument
273 u8 adr = state->config.demod_address; in Write16()
279 if (i2c_write(state->i2c, adr, mm, 6) < 0) in Write16()
284 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) in Write32() argument
286 u8 adr = state->config.demod_address; in Write32()
293 if (i2c_write(state->i2c, adr, mm, 8) < 0) in Write32()
298 static int write_chunk(struct drxd_state *state, in write_chunk() argument
301 u8 adr = state->config.demod_address; in write_chunk()
309 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { in write_chunk()
316 static int WriteBlock(struct drxd_state *state, in WriteBlock() argument
322 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) in WriteBlock()
331 static int WriteTable(struct drxd_state *state, u8 * pTable) in WriteTable() argument
351 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
361 static int ResetCEFR(struct drxd_state *state) in ResetCEFR() argument
363 return WriteTable(state, state->m_ResetCEFR); in ResetCEFR()
366 static int InitCP(struct drxd_state *state) in InitCP() argument
368 return WriteTable(state, state->m_InitCP); in InitCP()
371 static int InitCE(struct drxd_state *state) in InitCE() argument
374 enum app_env AppEnv = state->app_env_default; in InitCE()
377 status = WriteTable(state, state->m_InitCE); in InitCE()
381 if (state->operation_mode == OM_DVBT_Diversity_Front || in InitCE()
382 state->operation_mode == OM_DVBT_Diversity_End) { in InitCE()
383 AppEnv = state->app_env_diversity; in InitCE()
386 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
390 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
393 } else if (AppEnv == APPENV_MOBILE && state->type_A) { in InitCE()
394 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
397 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { in InitCE()
398 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
404 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
411 static int StopOC(struct drxd_state *state) in StopOC() argument
415 u16 ocModeLop = state->m_EcOcRegOcModeLop; in StopOC()
421 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
425 state->m_EcOcRegSncSncLvl = ocSyncLvl; in StopOC()
429 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
432 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
435 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
438 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
443 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
446 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
452 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
458 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
464 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
467 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
470 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
478 static int StartOC(struct drxd_state *state) in StartOC() argument
484 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
489 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
492 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
497 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
502 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
509 static int InitEQ(struct drxd_state *state) in InitEQ() argument
511 return WriteTable(state, state->m_InitEQ); in InitEQ()
514 static int InitEC(struct drxd_state *state) in InitEC() argument
516 return WriteTable(state, state->m_InitEC); in InitEC()
519 static int InitSC(struct drxd_state *state) in InitSC() argument
521 return WriteTable(state, state->m_InitSC); in InitSC()
524 static int InitAtomicRead(struct drxd_state *state) in InitAtomicRead() argument
526 return WriteTable(state, state->m_InitAtomicRead); in InitAtomicRead()
529 static int CorrectSysClockDeviation(struct drxd_state *state);
531 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) in DRX_GetLockStatus() argument
545 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
551 if (state->drxd_state != DRXD_STARTED) in DRX_GetLockStatus()
556 CorrectSysClockDeviation(state); in DRX_GetLockStatus()
569 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgIfAgc() argument
581 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
586 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
592 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
610 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
616 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
624 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
635 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
638 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
686 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
689 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
692 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
695 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
698 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
712 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgRfAgc() argument
727 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
734 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); in SetCfgRfAgc()
735 state->m_FeAgRegAgPwd |= in SetCfgRfAgc()
737 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
741 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
748 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
755 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
762 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
775 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
777 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
779 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
783 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
790 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
796 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
807 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
814 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
826 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
828 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
830 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
834 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
841 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
848 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
855 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
864 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) in ReadIFAgc() argument
869 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { in ReadIFAgc()
871 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
884 u32 R1 = state->if_agc_cfg.R1; in ReadIFAgc()
885 u32 R2 = state->if_agc_cfg.R2; in ReadIFAgc()
886 u32 R3 = state->if_agc_cfg.R3; in ReadIFAgc()
904 static int load_firmware(struct drxd_state *state, const char *fw_name) in load_firmware() argument
908 if (request_firmware(&fw, fw_name, state->dev) < 0) { in load_firmware()
913 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); in load_firmware()
914 if (state->microcode == NULL) { in load_firmware()
920 state->microcode_length = fw->size; in load_firmware()
925 static int DownloadMicrocode(struct drxd_state *state, in DownloadMicrocode() argument
964 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
975 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) in HI_Command() argument
981 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
991 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); in HI_Command()
995 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
999 static int HI_CfgCommand(struct drxd_state *state) in HI_CfgCommand() argument
1003 mutex_lock(&state->mutex); in HI_CfgCommand()
1004 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
1005 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); in HI_CfgCommand()
1006 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); in HI_CfgCommand()
1007 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); in HI_CfgCommand()
1008 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); in HI_CfgCommand()
1010 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
1012 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == in HI_CfgCommand()
1014 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
1017 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); in HI_CfgCommand()
1018 mutex_unlock(&state->mutex); in HI_CfgCommand()
1022 static int InitHI(struct drxd_state *state) in InitHI() argument
1024 state->hi_cfg_wakeup_key = (state->chip_adr); in InitHI()
1026 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; in InitHI()
1027 return HI_CfgCommand(state); in InitHI()
1030 static int HI_ResetCommand(struct drxd_state *state) in HI_ResetCommand() argument
1034 mutex_lock(&state->mutex); in HI_ResetCommand()
1035 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1038 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); in HI_ResetCommand()
1039 mutex_unlock(&state->mutex); in HI_ResetCommand()
1044 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) in DRX_ConfigureI2CBridge() argument
1046 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); in DRX_ConfigureI2CBridge()
1048 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; in DRX_ConfigureI2CBridge()
1050 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; in DRX_ConfigureI2CBridge()
1052 return HI_CfgCommand(state); in DRX_ConfigureI2CBridge()
1061 static int AtomicReadBlock(struct drxd_state *state,
1071 mutex_lock(&state->mutex);
1076 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1079 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1082 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1085 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1088 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1092 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1102 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1110 mutex_unlock(&state->mutex);
1114 static int AtomicReadReg32(struct drxd_state *state,
1122 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1130 static int StopAllProcessors(struct drxd_state *state) in StopAllProcessors() argument
1132 return Write16(state, HI_COMM_EXEC__A, in StopAllProcessors()
1136 static int EnableAndResetMB(struct drxd_state *state) in EnableAndResetMB() argument
1138 if (state->type_A) { in EnableAndResetMB()
1140 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); in EnableAndResetMB()
1144 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); in EnableAndResetMB()
1145 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); in EnableAndResetMB()
1149 static int InitCC(struct drxd_state *state) in InitCC() argument
1151 if (state->osc_clock_freq == 0 || in InitCC()
1152 state->osc_clock_freq > 20000 || in InitCC()
1153 (state->osc_clock_freq % 4000) != 0) { in InitCC()
1154 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); in InitCC()
1158 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); in InitCC()
1159 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | in InitCC()
1161 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); in InitCC()
1162 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); in InitCC()
1163 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); in InitCC()
1168 static int ResetECOD(struct drxd_state *state) in ResetECOD() argument
1172 if (state->type_A) in ResetECOD()
1173 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1175 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1178 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1180 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1186 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) in SetCfgPga() argument
1195 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1200 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1205 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1210 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1216 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1223 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1228 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1233 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1238 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1244 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1252 static int InitFE(struct drxd_state *state) in InitFE() argument
1257 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1261 if (state->type_A) { in InitFE()
1262 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1266 if (state->PGA) in InitFE()
1267 status = SetCfgPga(state, 0); in InitFE()
1270 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1277 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1280 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1284 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1293 static int InitFT(struct drxd_state *state) in InitFT() argument
1299 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); in InitFT()
1302 static int SC_WaitForReady(struct drxd_state *state) in SC_WaitForReady() argument
1308 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); in SC_WaitForReady()
1315 static int SC_SendCommand(struct drxd_state *state, u16 cmd) in SC_SendCommand() argument
1320 Write16(state, SC_RA_RAM_CMD__A, cmd, 0); in SC_SendCommand()
1321 SC_WaitForReady(state); in SC_SendCommand()
1323 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); in SC_SendCommand()
1333 static int SC_ProcStartCommand(struct drxd_state *state, in SC_ProcStartCommand() argument
1339 mutex_lock(&state->mutex); in SC_ProcStartCommand()
1341 Read16(state, SC_COMM_EXEC__A, &scExec, 0); in SC_ProcStartCommand()
1346 SC_WaitForReady(state); in SC_ProcStartCommand()
1347 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_ProcStartCommand()
1348 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_ProcStartCommand()
1349 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_ProcStartCommand()
1351 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); in SC_ProcStartCommand()
1353 mutex_unlock(&state->mutex); in SC_ProcStartCommand()
1357 static int SC_SetPrefParamCommand(struct drxd_state *state, in SC_SetPrefParamCommand() argument
1362 mutex_lock(&state->mutex); in SC_SetPrefParamCommand()
1364 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1367 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1370 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1373 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1377 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1381 mutex_unlock(&state->mutex); in SC_SetPrefParamCommand()
1386 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1390 mutex_lock(&state->mutex);
1392 status = SC_WaitForReady(state);
1395 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1398 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1402 mutex_unlock(&state->mutex);
1407 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) in ConfigureMPEGOutput() argument
1419 if (state->operation_mode == OM_DVBT_Diversity_Front) { in ConfigureMPEGOutput()
1428 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; in ConfigureMPEGOutput()
1436 if (state->insert_rs_byte) { in ConfigureMPEGOutput()
1453 if (state->enable_parallel) in ConfigureMPEGOutput()
1481 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1484 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1487 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1490 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1497 static int SetDeviceTypeId(struct drxd_state *state) in SetDeviceTypeId() argument
1503 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1507 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1512 state->type_A = 0; in SetDeviceTypeId()
1513 state->PGA = 0; in SetDeviceTypeId()
1514 state->diversity = 0; in SetDeviceTypeId()
1516 state->type_A = 1; in SetDeviceTypeId()
1523 state->diversity = 1; in SetDeviceTypeId()
1526 state->PGA = 1; in SetDeviceTypeId()
1529 state->diversity = 1; in SetDeviceTypeId()
1544 state->m_InitAtomicRead = DRXD_InitAtomicRead; in SetDeviceTypeId()
1545 state->m_InitSC = DRXD_InitSC; in SetDeviceTypeId()
1546 state->m_ResetECRAM = DRXD_ResetECRAM; in SetDeviceTypeId()
1547 if (state->type_A) { in SetDeviceTypeId()
1548 state->m_ResetCEFR = DRXD_ResetCEFR; in SetDeviceTypeId()
1549 state->m_InitFE_1 = DRXD_InitFEA2_1; in SetDeviceTypeId()
1550 state->m_InitFE_2 = DRXD_InitFEA2_2; in SetDeviceTypeId()
1551 state->m_InitCP = DRXD_InitCPA2; in SetDeviceTypeId()
1552 state->m_InitCE = DRXD_InitCEA2; in SetDeviceTypeId()
1553 state->m_InitEQ = DRXD_InitEQA2; in SetDeviceTypeId()
1554 state->m_InitEC = DRXD_InitECA2; in SetDeviceTypeId()
1555 if (load_firmware(state, DRX_FW_FILENAME_A2)) in SetDeviceTypeId()
1558 state->m_ResetCEFR = NULL; in SetDeviceTypeId()
1559 state->m_InitFE_1 = DRXD_InitFEB1_1; in SetDeviceTypeId()
1560 state->m_InitFE_2 = DRXD_InitFEB1_2; in SetDeviceTypeId()
1561 state->m_InitCP = DRXD_InitCPB1; in SetDeviceTypeId()
1562 state->m_InitCE = DRXD_InitCEB1; in SetDeviceTypeId()
1563 state->m_InitEQ = DRXD_InitEQB1; in SetDeviceTypeId()
1564 state->m_InitEC = DRXD_InitECB1; in SetDeviceTypeId()
1565 if (load_firmware(state, DRX_FW_FILENAME_B1)) in SetDeviceTypeId()
1568 if (state->diversity) { in SetDeviceTypeId()
1569 state->m_InitDiversityFront = DRXD_InitDiversityFront; in SetDeviceTypeId()
1570 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; in SetDeviceTypeId()
1571 state->m_DisableDiversity = DRXD_DisableDiversity; in SetDeviceTypeId()
1572 state->m_StartDiversityFront = DRXD_StartDiversityFront; in SetDeviceTypeId()
1573 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; in SetDeviceTypeId()
1574 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; in SetDeviceTypeId()
1575 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; in SetDeviceTypeId()
1577 state->m_InitDiversityFront = NULL; in SetDeviceTypeId()
1578 state->m_InitDiversityEnd = NULL; in SetDeviceTypeId()
1579 state->m_DisableDiversity = NULL; in SetDeviceTypeId()
1580 state->m_StartDiversityFront = NULL; in SetDeviceTypeId()
1581 state->m_StartDiversityEnd = NULL; in SetDeviceTypeId()
1582 state->m_DiversityDelay8MHZ = NULL; in SetDeviceTypeId()
1583 state->m_DiversityDelay6MHZ = NULL; in SetDeviceTypeId()
1589 static int CorrectSysClockDeviation(struct drxd_state *state) in CorrectSysClockDeviation() argument
1605 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1608 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1612 if (state->type_A) { in CorrectSysClockDeviation()
1620 switch (state->props.bandwidth_hz) { in CorrectSysClockDeviation()
1647 (state->expected_sys_clock_freq)) * in CorrectSysClockDeviation()
1650 (state->expected_sys_clock_freq)); in CorrectSysClockDeviation()
1652 Diff = oscClockDeviation - state->osc_clock_deviation; in CorrectSysClockDeviation()
1655 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()
1656 if (oscClockDeviation != state->osc_clock_deviation) { in CorrectSysClockDeviation()
1657 if (state->config.osc_deviation) { in CorrectSysClockDeviation()
1658 state->config.osc_deviation(state->priv, in CorrectSysClockDeviation()
1661 state->osc_clock_deviation = in CorrectSysClockDeviation()
1666 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1671 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1674 state->cscd_state = CSCD_SAVED; in CorrectSysClockDeviation()
1681 static int DRX_Stop(struct drxd_state *state) in DRX_Stop() argument
1685 if (state->drxd_state != DRXD_STARTED) in DRX_Stop()
1689 if (state->cscd_state != CSCD_SAVED) { in DRX_Stop()
1691 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1696 status = StopOC(state); in DRX_Stop()
1700 state->drxd_state = DRXD_STOPPED; in DRX_Stop()
1702 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1706 if (state->type_A) { in DRX_Stop()
1708 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1712 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1715 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1720 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1723 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1726 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1729 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1732 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1735 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1738 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1748 static int SetOperationMode(struct drxd_state *state, int oMode)
1753 if (state->drxd_state != DRXD_STOPPED) {
1758 if (oMode == state->operation_mode) {
1763 if (oMode != OM_Default && !state->diversity) {
1770 status = WriteTable(state, state->m_InitDiversityFront);
1773 status = WriteTable(state, state->m_InitDiversityEnd);
1779 status = WriteTable(state, state->m_DisableDiversity);
1785 state->operation_mode = oMode;
1790 static int StartDiversity(struct drxd_state *state) in StartDiversity() argument
1796 if (state->operation_mode == OM_DVBT_Diversity_Front) { in StartDiversity()
1797 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1800 } else if (state->operation_mode == OM_DVBT_Diversity_End) { in StartDiversity()
1801 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1804 if (state->props.bandwidth_hz == 8000000) { in StartDiversity()
1805 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1809 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1814 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1823 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1831 static int SetFrequencyShift(struct drxd_state *state, in SetFrequencyShift() argument
1834 int negativeShift = (state->tuner_mirrors == channelMirrored); in SetFrequencyShift()
1847 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + in SetFrequencyShift()
1849 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1851 state->fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1853 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); in SetFrequencyShift()
1857 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, in SetFrequencyShift()
1858 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1860 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1862 state->org_fe_fs_add_incr = ((1L << 28) - in SetFrequencyShift()
1863 state->org_fe_fs_add_incr); in SetFrequencyShift()
1865 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, in SetFrequencyShift()
1866 state->fe_fs_add_incr, 0); in SetFrequencyShift()
1869 static int SetCfgNoiseCalibration(struct drxd_state *state, in SetCfgNoiseCalibration() argument
1876 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1883 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1887 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1891 if (!state->type_A) { in SetCfgNoiseCalibration()
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1895 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1904 static int DRX_Start(struct drxd_state *state, s32 off) in DRX_Start() argument
1906 struct dtv_frontend_properties *p = &state->props; in DRX_Start()
1935 if (state->drxd_state != DRXD_STOPPED) in DRX_Start()
1937 status = ResetECOD(state); in DRX_Start()
1940 if (state->type_A) { in DRX_Start()
1941 status = InitSC(state); in DRX_Start()
1945 status = InitFT(state); in DRX_Start()
1948 status = InitCP(state); in DRX_Start()
1951 status = InitCE(state); in DRX_Start()
1954 status = InitEQ(state); in DRX_Start()
1957 status = InitSC(state); in DRX_Start()
1964 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1967 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1971 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); in DRX_Start()
1979 if (state->type_A) { in DRX_Start()
1980 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1990 if (state->type_A) { in DRX_Start()
1991 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
2024 if (state->type_A) { in DRX_Start()
2025 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2028 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2054 if (state->type_A) { in DRX_Start()
2055 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2058 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2083 if (state->type_A) { in DRX_Start()
2084 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2087 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2115 if (state->type_A) { in DRX_Start()
2116 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2119 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2154 if (state->type_A) { in DRX_Start()
2155 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2158 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2161 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2164 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2167 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2171 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2174 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2177 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2180 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2187 if (state->type_A) { in DRX_Start()
2188 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2191 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2194 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2197 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2200 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2204 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2207 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2210 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2213 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2221 if (state->type_A) { in DRX_Start()
2222 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2225 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2228 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2231 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2234 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2238 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2241 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2244 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2247 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2269 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2279 if (state->type_A) { in DRX_Start()
2280 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2289 if (state->type_A) { in DRX_Start()
2290 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2297 if (state->type_A) { in DRX_Start()
2298 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2305 if (state->type_A) { in DRX_Start()
2306 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2313 if (state->type_A) { in DRX_Start()
2314 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2340 status = Write16(state, in DRX_Start()
2347 status = Write16(state, in DRX_Start()
2354 status = Write16(state, in DRX_Start()
2363 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2369 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2383 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2388 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2392 if (state->cscd_state == CSCD_INIT) { in DRX_Start()
2394 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2398 state->cscd_state = CSCD_SET; in DRX_Start()
2404 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, in DRX_Start()
2406 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2409 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2415 SetFrequencyShift(state, off, mirrorFreqSpect); in DRX_Start()
2420 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2423 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2435 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2440 …status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2444 status = StartOC(state); in DRX_Start()
2448 if (state->operation_mode != OM_Default) { in DRX_Start()
2449 status = StartDiversity(state); in DRX_Start()
2454 state->drxd_state = DRXD_STARTED; in DRX_Start()
2460 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) in CDRXD() argument
2480 u32 ulClock = state->config.clock; in CDRXD()
2490 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2491 state->if_agc_cfg.outputLevel = 0; in CDRXD()
2492 state->if_agc_cfg.settleLevel = 140; in CDRXD()
2493 state->if_agc_cfg.minOutputLevel = 0; in CDRXD()
2494 state->if_agc_cfg.maxOutputLevel = 1023; in CDRXD()
2495 state->if_agc_cfg.speed = 904; in CDRXD()
2498 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2499 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); in CDRXD()
2507 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2508 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); in CDRXD()
2509 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); in CDRXD()
2510 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); in CDRXD()
2511 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); in CDRXD()
2514 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); in CDRXD()
2515 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); in CDRXD()
2516 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); in CDRXD()
2518 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); in CDRXD()
2519 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); in CDRXD()
2520 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); in CDRXD()
2522 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2525 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2526 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); in CDRXD()
2534 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2535 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); in CDRXD()
2536 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); in CDRXD()
2537 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); in CDRXD()
2538 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); in CDRXD()
2542 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; in CDRXD()
2545 state->app_env_default = (enum app_env) in CDRXD()
2548 state->app_env_diversity = (enum app_env) in CDRXD()
2553 state->noise_cal.cpOpt = 0; in CDRXD()
2554 state->noise_cal.cpNexpOfs = 40; in CDRXD()
2555 state->noise_cal.tdCal2k = -40; in CDRXD()
2556 state->noise_cal.tdCal8k = -24; in CDRXD()
2559 state->noise_cal.cpOpt = 1; in CDRXD()
2560 state->noise_cal.cpNexpOfs = 0; in CDRXD()
2561 state->noise_cal.tdCal2k = -21; in CDRXD()
2562 state->noise_cal.tdCal8k = -24; in CDRXD()
2564 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); in CDRXD()
2566 state->chip_adr = (state->config.demod_address << 1) | 1; in CDRXD()
2569 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; in CDRXD()
2572 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; in CDRXD()
2575 state->m_HiI2cPatch = NULL; in CDRXD()
2579 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); in CDRXD()
2581 state->expected_sys_clock_freq = 48000; in CDRXD()
2583 state->sys_clock_freq = 48000; in CDRXD()
2584 state->osc_clock_freq = (u16) ulClock; in CDRXD()
2585 state->osc_clock_deviation = 0; in CDRXD()
2586 state->cscd_state = CSCD_INIT; in CDRXD()
2587 state->drxd_state = DRXD_UNINITIALIZED; in CDRXD()
2589 state->PGA = 0; in CDRXD()
2590 state->type_A = 0; in CDRXD()
2591 state->tuner_mirrors = 0; in CDRXD()
2594 state->insert_rs_byte = state->config.insert_rs_byte; in CDRXD()
2595 state->enable_parallel = (ulSerialMode != 1); in CDRXD()
2600 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()
2604 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * in CDRXD()
2607 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in CDRXD()
2609 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in CDRXD()
2613 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) in DRXD_init() argument
2618 if (state->init_done) in DRXD_init()
2621 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in DRXD_init()
2624 state->operation_mode = OM_Default; in DRXD_init()
2626 status = SetDeviceTypeId(state); in DRXD_init()
2631 if (!state->type_A && state->m_HiI2cPatch != NULL) { in DRXD_init()
2632 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2637 if (state->type_A) { in DRXD_init()
2640 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2645 status = HI_ResetCommand(state); in DRXD_init()
2649 status = StopAllProcessors(state); in DRXD_init()
2652 status = InitCC(state); in DRXD_init()
2656 state->osc_clock_deviation = 0; in DRXD_init()
2658 if (state->config.osc_deviation) in DRXD_init()
2659 state->osc_clock_deviation = in DRXD_init()
2660 state->config.osc_deviation(state->priv, 0, 0); in DRXD_init()
2664 s32 devA = (s32) (state->osc_clock_deviation) * in DRXD_init()
2665 (s32) (state->expected_sys_clock_freq); in DRXD_init()
2678 state->sys_clock_freq = in DRXD_init()
2679 (u16) ((state->expected_sys_clock_freq) + in DRXD_init()
2682 status = InitHI(state); in DRXD_init()
2685 status = InitAtomicRead(state); in DRXD_init()
2689 status = EnableAndResetMB(state); in DRXD_init()
2692 if (state->type_A) { in DRXD_init()
2693 status = ResetCEFR(state); in DRXD_init()
2698 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2702 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2707 if (state->PGA) { in DRXD_init()
2708 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; in DRXD_init()
2709 SetCfgPga(state, 0); /* PGA = 0 dB */ in DRXD_init()
2711 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in DRXD_init()
2714 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in DRXD_init()
2716 status = InitFE(state); in DRXD_init()
2719 status = InitFT(state); in DRXD_init()
2722 status = InitCP(state); in DRXD_init()
2725 status = InitCE(state); in DRXD_init()
2728 status = InitEQ(state); in DRXD_init()
2731 status = InitEC(state); in DRXD_init()
2734 status = InitSC(state); in DRXD_init()
2738 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2741 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2745 state->cscd_state = CSCD_INIT; in DRXD_init()
2746 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2749 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2761 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2765 status = StopOC(state); in DRXD_init()
2769 state->drxd_state = DRXD_STOPPED; in DRXD_init()
2770 state->init_done = 1; in DRXD_init()
2776 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) in DRXD_status() argument
2778 DRX_GetLockStatus(state, pLockStatus); in DRXD_status()
2782 ConfigureMPEGOutput(state, 1); in DRXD_status()
2796 struct drxd_state *state = fe->demodulator_priv; in drxd_read_signal_strength() local
2800 res = ReadIFAgc(state, &value); in drxd_read_signal_strength()
2810 struct drxd_state *state = fe->demodulator_priv; in drxd_read_status() local
2813 DRXD_status(state, &lock); in drxd_read_status()
2833 struct drxd_state *state = fe->demodulator_priv; in drxd_init() local
2835 return DRXD_init(state, NULL, 0); in drxd_init()
2840 struct drxd_state *state = fe->demodulator_priv; in drxd_config_i2c() local
2842 if (state->config.disable_i2c_gate_ctrl == 1) in drxd_config_i2c()
2845 return DRX_ConfigureI2CBridge(state, onoff); in drxd_config_i2c()
2877 struct drxd_state *state = fe->demodulator_priv; in drxd_sleep() local
2879 ConfigureMPEGOutput(state, 0); in drxd_sleep()
2891 struct drxd_state *state = fe->demodulator_priv; in drxd_set_frontend() local
2894 state->props = *p; in drxd_set_frontend()
2895 DRX_Stop(state); in drxd_set_frontend()
2905 return DRX_Start(state, off); in drxd_set_frontend()
2910 struct drxd_state *state = fe->demodulator_priv; in drxd_release() local
2912 kfree(state); in drxd_release()
2951 struct drxd_state *state = NULL; in drxd_attach() local
2953 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL); in drxd_attach()
2954 if (!state) in drxd_attach()
2956 memset(state, 0, sizeof(*state)); in drxd_attach()
2958 state->ops = drxd_ops; in drxd_attach()
2959 state->dev = dev; in drxd_attach()
2960 state->config = *config; in drxd_attach()
2961 state->i2c = i2c; in drxd_attach()
2962 state->priv = priv; in drxd_attach()
2964 mutex_init(&state->mutex); in drxd_attach()
2966 if (Read16(state, 0, NULL, 0) < 0) in drxd_attach()
2969 state->frontend.ops = drxd_ops; in drxd_attach()
2970 state->frontend.demodulator_priv = state; in drxd_attach()
2971 ConfigureMPEGOutput(state, 0); in drxd_attach()
2973 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in drxd_attach()
2974 InitHI(state); in drxd_attach()
2976 return &state->frontend; in drxd_attach()
2980 kfree(state); in drxd_attach()