Lines Matching refs:state
55 static int s5h1432_writereg(struct s5h1432_state *state, in s5h1432_writereg() argument
63 ret = i2c_transfer(state->i2c, &msg, 1); in s5h1432_writereg()
72 static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg) in s5h1432_readreg() argument
83 ret = i2c_transfer(state->i2c, msg, 2); in s5h1432_readreg()
99 struct s5h1432_state *state = fe->demodulator_priv; in s5h1432_set_channel_bandwidth() local
104 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E); in s5h1432_set_channel_bandwidth()
119 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg); in s5h1432_set_channel_bandwidth()
125 struct s5h1432_state *state = fe->demodulator_priv; in s5h1432_set_IF() local
129 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55); in s5h1432_set_IF()
130 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55); in s5h1432_set_IF()
131 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15); in s5h1432_set_IF()
134 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00); in s5h1432_set_IF()
135 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00); in s5h1432_set_IF()
136 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40); in s5h1432_set_IF()
139 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00); in s5h1432_set_IF()
140 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00); in s5h1432_set_IF()
141 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0); in s5h1432_set_IF()
144 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66); in s5h1432_set_IF()
145 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66); in s5h1432_set_IF()
146 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE); in s5h1432_set_IF()
149 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55); in s5h1432_set_IF()
150 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55); in s5h1432_set_IF()
151 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED); in s5h1432_set_IF()
154 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA); in s5h1432_set_IF()
155 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA); in s5h1432_set_IF()
156 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA); in s5h1432_set_IF()
166 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, in s5h1432_set_IF()
168 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, in s5h1432_set_IF()
170 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, in s5h1432_set_IF()
185 struct s5h1432_state *state = fe->demodulator_priv; in s5h1432_set_frontend() local
187 if (p->frequency == state->current_frequency) { in s5h1432_set_frontend()
213 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); in s5h1432_set_frontend()
215 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); in s5h1432_set_frontend()
237 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); in s5h1432_set_frontend()
239 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); in s5h1432_set_frontend()
243 state->current_frequency = p->frequency; in s5h1432_set_frontend()
250 struct s5h1432_state *state = fe->demodulator_priv; in s5h1432_init() local
253 state->current_frequency = 0; in s5h1432_init()
259 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8); in s5h1432_init()
260 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01); in s5h1432_init()
261 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70); in s5h1432_init()
262 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80); in s5h1432_init()
263 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D); in s5h1432_init()
264 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30); in s5h1432_init()
265 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20); in s5h1432_init()
266 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B); in s5h1432_init()
267 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40); in s5h1432_init()
268 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84); in s5h1432_init()
269 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a); in s5h1432_init()
270 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3); in s5h1432_init()
271 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50); in s5h1432_init()
272 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c); in s5h1432_init()
273 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10); in s5h1432_init()
274 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c); in s5h1432_init()
275 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00); in s5h1432_init()
276 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94); in s5h1432_init()
278 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00); in s5h1432_init()
283 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66); in s5h1432_init()
284 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66); in s5h1432_init()
285 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE); in s5h1432_init()
287 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31); in s5h1432_init()
290 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42); in s5h1432_init()
292 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg); in s5h1432_init()
297 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); in s5h1432_init()
299 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); in s5h1432_init()
340 struct s5h1432_state *state = fe->demodulator_priv; in s5h1432_release() local
341 kfree(state); in s5h1432_release()
349 struct s5h1432_state *state = NULL; in s5h1432_attach() local
353 state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL); in s5h1432_attach()
354 if (!state) in s5h1432_attach()
358 state->config = config; in s5h1432_attach()
359 state->i2c = i2c; in s5h1432_attach()
360 state->current_modulation = QAM_16; in s5h1432_attach()
361 state->inversion = state->config->inversion; in s5h1432_attach()
364 memcpy(&state->frontend.ops, &s5h1432_ops, in s5h1432_attach()
367 state->frontend.demodulator_priv = state; in s5h1432_attach()
369 return &state->frontend; in s5h1432_attach()